[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2015035725A1 - 像素单元以及阵列基板、液晶显示装置 - Google Patents

像素单元以及阵列基板、液晶显示装置 Download PDF

Info

Publication number
WO2015035725A1
WO2015035725A1 PCT/CN2013/089304 CN2013089304W WO2015035725A1 WO 2015035725 A1 WO2015035725 A1 WO 2015035725A1 CN 2013089304 W CN2013089304 W CN 2013089304W WO 2015035725 A1 WO2015035725 A1 WO 2015035725A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
pixel unit
electrode
electrodes
signal line
Prior art date
Application number
PCT/CN2013/089304
Other languages
English (en)
French (fr)
Inventor
蔡佩芝
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/361,950 priority Critical patent/US9773816B2/en
Publication of WO2015035725A1 publication Critical patent/WO2015035725A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • Pixel unit and array substrate liquid crystal display device
  • Embodiments of the present invention relate to a liquid crystal display technology, and in particular, to a pixel unit, an array substrate, and a liquid crystal display device. Background technique
  • the pixel unit of a thin film transistor liquid crystal display device can improve the color shift by self-compensation of the liquid crystal, but the effect of expanding the viewing angle is limited, and the viewing angle of different directions cannot be effectively expanded.
  • the gate/source parasitic power is easily changed with the deviation of the process, which causes the jump voltages of different display areas to be different, and the screen may have flicker or residual image, etc.
  • a pixel unit includes a scan line, a signal line, a slit electrode, a coupling electrode that can form an electric field with the slit electrode, and a thin film transistor, and the slit electrode is formed with a plurality of narrow lines
  • the scan line and the signal line are overlapped and define at least two sub-regions
  • the coupling electrode includes at least two sub-electrodes respectively located in one of the sub-regions; the slit electrode corresponds to all sub-segments The slits in the regions and in the different sub-regions extend in different directions.
  • the thin film transistor includes an active layer above the scan line and insulated from the scan line, and further includes a drain located above the scan line and orthographically all located within the scan line; the signal line is located at the Above the source layer and connected to the active layer, the signal line serves as a source.
  • the scan line is widened to one side or both sides corresponding to a portion of the thin film transistor.
  • two of the sub-electrodes are located on the same side of the signal line, and the two sub-electrodes are connected by a connection bridge of the same layer; the drain is connected to the connection bridge.
  • both sides of the signal line include two sub-electrodes connected by a connection bridge and one of the thin film transistors, and the drains of the thin film transistors are all connected to the connection bridge.
  • the pixel unit is symmetrical with respect to the scan line and the signal line.
  • the coupling electrode is a pixel electrode
  • the slit electrode is a common electrode.
  • an array substrate comprising the pixel unit as described above.
  • a liquid crystal display device comprising the array substrate as described above.
  • a color film substrate is further included, the color film substrate includes a black matrix layer, the black matrix layer covers an area between the pixel units, and further covers the scan lines and the Said signal line.
  • FIG. 1 is a diagram of a pixel unit according to an embodiment of the present invention.
  • FIG. 2 is a partial perspective enlarged view of the intersection of the scanning line and the signal line in FIG. 1;
  • Figure 3 is a cross-sectional view of the pixel unit of Figure 1 taken along line A-A;
  • Embodiments of the present invention provide a pixel unit including a scan line 6, a signal line 1, a slit electrode 4, a coupling electrode 3 that can form an electric field with the slit electrode 4, and a TFT, the slit electrode 4 is formed with a plurality of slits; wherein the scan line 6 and the signal line 1 are superposed on each other and define at least two sub-regions (for example, four sub-regions I, II, III, IV shown in FIG.
  • the coupling electrode 3 includes at least two sub-electrodes respectively located in one of the sub-regions; the slit electrode has different extension directions of slits corresponding to all sub-regions (ie, covering all sub-regions) and located in different sub-regions (For example, if the scanning line 6 is the X-axis, then the angle between the extending direction of the four I, II, III, and IV regions of the slit in FIG. 1 and the X-axis is, for example, +45°, +135°, + 225° (or -135°) and +315° (or -45").
  • the coupling electrode and the slit electrode are interchangeable.
  • the embodiment of the present invention is described by taking the coupling electrode 3 and the slit electrode 4 as pixel electrodes and a common electrode, respectively.
  • the thin film transistor includes an active layer 2 over the scan line 6 and insulated from the scan line 6, and further includes a source 5 located above the scan line 6 and orthographically all located within the scan line 6; the signal line is located at the Above the active layer 2 and connected to the active layer 2, at this time, the signal line 1 serves as a drain.
  • the problem of the coupling capacitance (Cgs) offset between the gate and the source 5 is brought about by the process deviation.
  • the source 5 can be deposited over the scan line 6, that is, the portion of the scan line 6 serves as a gate.
  • the pixel unit with Cgs self-compensation function stabilizes the Cgs value of different regions, thereby ensuring the uniformity of the hopping voltage and effectively improving the product quality.
  • the coupling electrode 3 can be directly connected to the source 5 by the bridge 10 without connecting through via holes to improve the yield of the product.
  • the TFT may include an active layer 2 over the scan line 6 and insulated from the scan line 6, and further includes a scan line 6 and an orthographic projection all located within the scan line 6.
  • the drain of the signal line 1 is located above the active layer 2 and is connected to the active layer 2, at which time the signal line 1 serves as a source.
  • the manufacturing variation of the drain position generally does not affect the overlap area of the drain and the gate, thereby ensuring the gate and drain of the different TFTs.
  • the parasitic capacitance between the poles is consistent, which ultimately ensures the consistency of the display quality of each pixel.
  • the scanning line 6 is widened to one side or both sides corresponding to the portion of the TFT.
  • the aspect ratio of the TFT can be increased while the channel width is constant to improve the TFT charging performance.
  • two sub-electrodes driven by the same TFT may be electrically connected through a connection bridge 10 of the same layer; the drain is electrically connected to the connection bridge.
  • the two sub-electrodes located on the signal line 1 On the same side, the two sub-electrodes are electrically connected by a connecting bridge 10 of the same layer.
  • both sides of the signal line 1 may include two sub-electrodes and one TFT electrically connected through the connection bridge 10, and the drain of the TFT is electrically connected to the connection bridge 10.
  • the width of the bridge 10 may be smaller than the width of the coupling electrode 3 as shown in Fig. 2 or the same as the width of the coupling electrode 3.
  • different sub-electrodes of the coupling electrode 3 may be separately arranged instead of all the different sub-electrodes as one unit; for different sub-electrodes, the same or different TFTs may be provided, so that one TFT can drive one or At least two sub-electrodes; this allows the viewing angles in different directions to be enlarged, the color shift can be effectively eliminated, and the aperture ratio can be effectively provided, and the display quality is remarkably improved.
  • the pixel unit in Fig. 1 is symmetrical with respect to the scanning line 6 and the signal line 1, so that the picture display quality is better.
  • the coupling electrode 3 is usually a pixel electrode, and the slit electrode 4 is usually a common electrode. Of course, the coupling electrode 3 and the slit electrode 4 can also be reversed.
  • An embodiment of the present invention further provides an array substrate, including the above pixel unit.
  • the above-described pixel unit of the present invention can be designed on a glass substrate to form an array substrate, but the substrate of the present invention is not limited to a glass substrate.
  • the embodiment of the invention further provides a liquid crystal display device comprising the above array substrate.
  • the deflection direction of the liquid crystal is in a chaotic state at the boundary of the different sub-electrodes, so the following occlusion settings can be made:
  • a black matrix layer covering a different sub-electrode junction of the coupling electrode 3 is disposed on the color filter substrate of the pair of array substrates to which the pixel unit of the present invention is designed, for example: the black matrix layer covers the pixel unit Scan line 6 and signal line 1 inside.
  • the above occlusion arrangement method can effectively optimize the disorder of the liquid crystal molecules in the deflection direction at the junction of the different sub-electrodes of the coupling electrode 3, thereby improving the display quality.
  • the black matrix layer also covers an area between the pixel units.
  • the overlapping portion of the slit electrode 4 and the scanning line 6 or the signal line 1 can be removed to reduce the overlapping area between the slit electrode 4 and the scanning line 6 and the signal line 1, thereby effectively reducing the coupling capacitance. , reduce power consumption.
  • FIG. 1 the scanning line 6 and the signal line 1 are superimposed and define four sub-areas, and the coupling electrode 3 includes four sub-electrodes respectively located in the four sub-areas.
  • the scan line 6 or the signal line 1 is located at the edge of the pixel unit shown in FIG. 1, the scan line 6 and the signal line 1 are superimposed and define two sub-areas.
  • the pixel unit in Fig. 1 is symmetrical with respect to the scanning line 6 and the signal line 1, so that the picture display quality is better.
  • the coupling electrode 3 includes four sub-electrodes that are symmetric in center, so that the coupling electrode 3 is symmetric in both the X and Y directions, that is, for one side (left or right side) of the longitudinal center line of the coupling electrode 3, the coupling electrode 3 is at the lateral center Line symmetry; for one side (upper or lower side) of the lateral center line of the coupling electrode 3, the coupling electrode 3 is symmetrical with respect to the longitudinal center line. This expands the viewing angle in four directions, effectively eliminating color shift and significantly improving display quality.
  • the signal line 1 and the scanning line 6 are disposed at different sub-electrode junctions of the coupling electrode 3, such as: the signal line 1 is longitudinally disposed on the longitudinal center line of the coupling electrode 3, and the scanning line 6 is laterally disposed at the coupling electrode 3.
  • the horizontal centerline is disposed at different sub-electrode junctions of the coupling electrode 3, such as: the signal line 1 is longitudinally disposed on the longitudinal center line of the coupling electrode 3, and the scanning line 6 is laterally disposed at the coupling electrode 3.
  • the horizontal centerline is disposed at different sub-electrode junctions of the coupling electrode 3, such as: the signal line 1 is longitudinally disposed on the longitudinal center line of the coupling electrode 3, and the scanning line 6 is laterally disposed at the coupling electrode 3. The horizontal centerline.
  • one TFT may be provided for two of the sub-electrodes, and one TFT is provided for the other two sub-electrodes so that each of the TFTs can drive the two sub-electrodes to increase the aperture ratio.
  • one TFT may be disposed for the two sub-electrodes on the left side of the signal line 1, and one TFT is provided for the two sub-electrodes on the right side of the signal line 1;
  • the upper two sub-electrodes and the lower two sub-electrodes divided by the scanning line 6 of the coupling electrode 3 may be provided with one TFT for the two sub-electrodes on the scanning line 6, and one TFT for the two sub-electrodes below the scanning line 6.
  • Fig. 2 The specific connection relationship between the sub-electrode and the TFT is shown in Fig. 2.
  • the process for forming the structure shown in Fig. 2 can be a commonly used mask mask process, which mainly includes the following processes:
  • the pixel unit and the array substrate and the liquid crystal display device including the pixel unit of the present invention include a scan line, a signal line, a slit electrode, and a coupling electrode that can form an electric field with the slit electrode.
  • the scan line and the signal line are overlapped and define at least two sub-regions
  • the coupling electrode includes at least two sub-regions respectively
  • the sub-electrodes; the slit electrodes have different slit directions in all sub-regions and in different sub-regions. Therefore, the viewing angles in different directions are expanded, and the color shift can be effectively eliminated compared with the prior art, and the aperture ratio can be effectively provided, and the display quality is remarkably improved.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)

Abstract

提供了一种像素单元以及包含该像素单元的阵列基板、液晶显示装置，其中像素单元包括扫描线（6）、信号线（1）、狭缝电极（4）、可与狭缝电极（4）配合形成电场的耦合电极（3）和薄膜晶体管，狭缝电极（4）上形成有多条狭缝，扫描线（6）和信号线（1）交叉叠置并限定出至少两个子区域（I，II，III，IV），耦合电极（3）包括至少两个分别位于一子区域（I，II，III，IV）的子电极，狭缝电极（4）对应所有子区域（I，II，III，IV）且位于不同子区域（I，II，III，IV）的狭缝延伸方向不同。因此，不同方向的视角得到扩大，能够有效消除色偏，并且能够有效提供开口率，明显提高显示质量。

Description

像素单元以及阵列基板、 液晶显示装置 技术领域
本发明实施例涉及液晶显示技术，具体涉及一种像素单元以及阵列基板、 液晶显示装置。 背景技术
目前， 薄膜晶体管液晶显示装置（TFT-LCD ) 的像素单元可以通过液晶 的自补偿来改善色偏， 但是这样做扩大视角的作用有限， 仍然无法使不同方 向的视角得到有效扩大。 并且， 在传统的像素单元中， 栅 /源寄生电 艮容易 随着工艺的偏差而发生变化， 这导致不同显示区域的跳变电压有所不同， 画 面可能会出现闪烁或残影等不良， 影响产品品 。 发明内容
本发明的目的在于提供一种像素单元以及阵列基板、 液晶显示装置， 以 消除色偏， 提高显示品质。
为达到上述目的， 本发明的技术方案是这样实现的：
根据本发明第一方面， 提供一种像素单元， 包括扫描线、 信号线、 狭缝 电极、 可与狭缝电极配合形成电场的耦合电极和薄膜晶体管， 所述狭缝电极 上形成有多条狭缝； 其中所述扫描线和所述信号线交叉叠置并限定出至少两 个子区域， 所述耦合电极包括至少两个分别位于一所述子区域的子电极； 所 述狭缝电极对应所有子区域且位于不同子区域的狭缝延伸方向不同。
在一个示例中， 所述薄膜晶体管包括位于扫描线上方并与扫描线绝缘的 有源层， 还包括位于扫描线上方且正投影全部位于扫描线内的漏极； 所述信 号线位于所述有源层上方并与所述有源层连接， 所述信号线作为源极。
在一个示例中， 所述扫描线对应于所述薄膜晶体管的部分向一侧或两侧 加宽。
在一个示例中，所述子电极中，有两个子电极位于所述信号线的同一侧， 这两个子电极通过同层的连接桥连接； 所述漏极与所述连接桥连接。 在一个示例中， 所述信号线两侧均包括通过连接桥连接的两个子电极和 一个所述薄膜晶体管， 所述薄膜晶体管的漏极均与所述连接桥连接。
在一个示例中， 所述像素单元相对于所述扫描线和所述信号线均对称。 在一个示例中， 所述耦合电极为像素电极， 所述狭缝电极为公共电极。 根据本发明第二方面，还提供一种阵列基板， 包括如上所述的像素单元。 根据本发明第三方面， 还提供一种液晶显示装置， 包括如上所述的阵列 基板。
在一个示例中， 还包括彩膜基板， 所述彩膜基板包括黑矩阵层， 所述黑 矩阵层覆盖所述像素单元之间的区域， 还覆盖所述像素单元内的所述扫描线 和所述信号线。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例的像素单元图；
图 2为图 1中扫描线与信号线交汇处的局部透祯放大图；
图 3为图 1的像素单元沿 A-A， 线的截面图；
附图标记说明：
1、 信号线； 2、 有源层； 3、 耦合电极； 4、 狭缝电极； 5、 源极； 6、 扫 描线； 7、 绝缘层； 8、 钝化层； 9、 玻璃基板； 10、 连接桥。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
附图中各层薄膜厚度和形状不反映阵列基板的真实比例， 目的只是示意 说明本发明内容。 本发明实施例提供了一种像素单元，该像素单元包括扫描线 6、信号线 1、 狭缝电极 4、 可与狭缝电极 4配合形成电场的耦合电极 3、 和 TFT, 所述狭 缝电极 4上形成有多条狭缝； 其中， 所述扫描线 6和所述信号线 1交叉叠置 并限定出至少两个子区域（例如图 1所示的四个子区域 I、 II、 III、 IV ), 所 述耦合电极 3包括至少两个分别位于一所述子区域的子电极； 所述狭缝电极 对应所有子区域（即覆盖于所有子区域）且位于不同子区域的狭缝的延伸方 向不同 （例如， 以扫描线 6为 X轴， 那么图 1中的狭缝在四个 I、 II、 III、 IV 区域的延伸方向与该 X轴的夹角例如为 +45°、 +135°、 +225° (或 -135° )和+315° (或 -45" )。
通常， 耦合电极、 狭缝电极可以互换， 本发明实施例以耦合电极 3、 狭 缝电极 4分别为像素电极、 公共电极为例进行描述。
所述薄膜晶体管包括位于扫描线 6上方并与扫描线 6绝缘的有源层 2, 还包括位于扫描线 6上方且正投影全部位于扫描线 6内的源极 5; 所述信号 线位于所述有源层 2上方并与所述有源层 2连接，此时，信号线 1作为漏极。
参见图 2, 对工艺偏差带来栅极和源极 5之间的耦合电容（ Cgs )偏移的 问题， 可以将源极 5沉积在扫描线 6上方， 即扫描线 6部分充当栅极， 这种 具有 Cgs自补偿功能的像素单元稳定了不同区域的 Cgs数值， 从而保证了跳 变电压的均一性， 有效改善产品品质。 并且， 耦合电极 3 可以由连接桥 10 直接与源极 5电连接， 无需通过过孔相连， 以便提升产品良率。
在将源极与漏极对调的情况下，所述 TFT可以包括位于扫描线 6上方并 与扫描线 6绝缘的有源层 2, 还包括位于扫描线 6上方且正投影全部位于扫 描线 6内的漏极； 信号线 1位于有源层 2上方并与有源层 2连接， 此时， 信 号线 1作为源极。
可见， 由于所述漏极完全制作在扫描线 6的上方， 从而漏极位置的制造 偏差通常不会对漏极与栅极的交叠面积产生影响，从而可保证各不同 TFT的 栅极与漏极之间的寄生电容一致， 最终保证各像素显示品质的一致性。
由图 2还可见， 扫描线 6对应于 TFT的部分向一侧或两侧加宽。 这样， 在沟道宽度不变的情况下可以增加 TFT的宽长比， 以提高 TFT充电性能。
另夕卜， 由同一个 TFT驱动的两个子电极， 可以通过同层的连接桥 10电 连接； 所述漏极与所述连接桥电连接。 例如可以有两个子电极位于信号线 1 的同一侧， 这两个子电极通过同层的连接桥 10电连接。 当然，信号线 1两侧 可以均包括通过连接桥 10电连接的两个子电极和一个 TFT , 该 TFT的漏极 与连接桥 10电连接。
连接桥 10的宽度可以如图 2所示小于耦合电极 3的宽度,也可以与耦合 电极 3的宽度相同。
在实际应用中， 可以将耦合电极 3的不同子电极分开设置， 而不是将所 有不同子电极设置为一个整体； 针对不同子电极， 可以设置同一个或不同的 TFT, 使得一个 TFT能够驱动一个或至少两个子电极； 这使得不同方向的视 角得到扩大， 能够有效消除色偏， 并且能够有效提供开口率， 明显提高显示 品质。
图 1中的像素单元相对于扫描线 6和信号线 1均对称， 使得画面显示品 质更好。
耦合电极 3通常为像素电极， 狭缝电极 4通常为公共电极。 当然， 耦合 电极 3与狭缝电极 4也可以对调。
本发明实施例还提供了一种阵列基板， 包括上述的像素单元。 例如， 可 以在玻璃基板上设计本发明上述的像素单元以形成阵列基板， 但是本发明的 基板不限于玻璃基板。
本发明实施例还提供了一种液晶显示装置， 包括上述的阵列基板。 另外， 由于液晶的相互作用导致液晶的偏转方向在不同子电极的交界处 处于混乱状态， 因此， 可以进行以下遮挡设置：
在将与设计有本发明的像素单元的阵列基板对盒的彩膜基板上， 设置覆 盖在耦合电极 3的不同子电极交界处的黑矩阵层， 比如： 所述黑矩阵层覆盖 所述像素单元内的扫描线 6和信号线 1。
上述遮挡设置方式能够有效地对耦合电极 3的不同子电极交界处的液晶 分子偏转方向混乱现象进行优化， 提高显示品质。
所述黑矩阵层还要覆盖所述像素单元之间的区域。
另外， 可以将狭缝电极 4与扫描线 6或信号线 1的交叠部分去掉， 以减 小狭缝电极 4与扫描线 6和信号线 1之间的交叠面积， 进而有效减小耦合电 容， 降低功耗。
在实际应用中， 基于上述内容可以进行多种设置， 如图 1所示的设置。 由于被覆盖， 因此图 1中没有标出图 2中的有源层 2、 源极 5。 图 1中， 扫描 线 6和信号线 1交叉叠置并限定出四个子区域， 耦合电极 3包括四个分别位 于所述四个子区域的子电极。 当然， 如果扫描线 6或信号线 1位于图 1所示 像素单元的边缘,那么扫描线 6和信号线 1则交叉叠置并限定出两个子区域。
图 1中的像素单元相对于扫描线 6和信号线 1均对称， 使得画面显示品 质更好。耦合电极 3包括中心对称的四个子电极，使耦合电极 3在 X和 Y方 向均对称， 即： 针对耦合电极 3的纵向中心线的一侧（左侧或右侧）， 耦合电 极 3以横向中心线对称；针对耦合电极 3的横向中心线的一侧（上侧或下侧 ), 耦合电极 3以纵向中心线对称。 这使得四个方向的视角得到扩大， 能够有效 消除色偏， 明显提高显示品质。
另外， 将信号线 1和扫描线 6设置在耦合电极 3的不同子电极交界处， 如： 将信号线 1纵向设置在耦合电极 3的纵向中心线上， 将扫描线 6横向设 置在耦合电极 3的横向中心线上。
在耦合电极 3包含的四个子电极中， 可以为其中的两个子电极设置一个 TFT, 再为另外两个子电极设置一个 TFT, 以使每个 TFT能够驱动两个子电 极， 提高开口率。 比如： 针对耦合电极 3被信号线 1划分出的左边两个子电 极以及右边两个子电极， 可以为信号线 1左边两个子电极设置一个 TFT, 再 为信号线 1右边两个子电极设置一个 TFT; 或者， 针对耦合电极 3被扫描线 6划分出的上边两个子电极以及下边两个子电极， 可以为扫描线 6上边两个 子电极设置一个 TFT, 再为扫描线 6下边两个子电极设置一个 TFT。
通常， 上述两个 TFT的状态是一致的。 子电极与 TFT之间的具体连接 关系如图 2所示， 用于形成图 2所示结构的工艺可以是常用的 5掩膜 Mask 工艺， 主要包括以下工艺流程：
( 1 )在玻璃基板 9上沉积栅极金属， 形成栅线；
( 2 )连续沉积 GI, a-Si, n+a-Si 多层膜；
( 3 )沉积 SD金属， 形成信号线 1及 TFT 沟道；
( 4 )沉积第一层 ITO, 形成耦合电极 3;
( 5 )沉积 PVX层；
( 6 )沉积第二层 ITO, 形成狭缝电极 4。
需要说明的是， 形成图 2所示结构所需的工艺可以有多种， 上述内容只 是以图 3为例进行描述。另夕卜， 源极 5与作为漏极的信号线 1通常可以对调。 综上所述可见， 本发明实施例的像素单元以及包含该像素单元的阵列基 板、 液晶显示装置中， 包括扫描线、 信号线、 狭缝电极、 可与狭缝电极配合 形成电场的耦合电极和 TFT, 所述狭缝电极上形成有多条狭缝； 所述扫描线 和所述信号线交叉叠置并限定出至少两个子区域， 所述耦合电极包括至少两 个分别位于一所述子区域的子电极； 所述狭缝电极对应所有子区域且位于不 同子区域的狭缝延伸方向不同。 因此不同方向的视角得到扩大， 相对现有技 术能够有效消除色偏， 并且能够有效提供开口率， 明显提高显示品质。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种像素单元， 包括扫描线、 信号线、 狭缝电极、 可与狭缝电极配合 形成电场的耦合电极和薄膜晶体管， 所述狭缝电极上形成有多条狭缝； 其中 所述扫描线和所述信号线交叉叠置并限定出至少两个子区域， 所述耦合电极 包括至少两个分别位于一所述子区域的子电极； 所述狭缝电极对应所有子区 域且位于不同子区域的狭缝延伸方向不同。
2、根据权利要求 1所述的像素单元，其中所述薄膜晶体管包括位于扫描 线上方并与扫描线绝缘的有源层， 还包括位于扫描线上方且正投影全部位于 扫描线内的漏极； 所述信号线位于所述有源层上方并与所述有源层连接， 所 述信号线作为源极。
3、根据权利要求 1或 2所述的像素单元，其中所述扫描线对应于所述薄 膜晶体管的部分向一侧或两侧加宽。
4、 根据权利要求 1-3任一项所述的像素单元， 其中所述子电极中， 有两 个子电极位于所述信号线的同一侧， 这两个子电极通过同层的连接桥连接； 所述漏极与所述连接桥连接。
5、根据权利要求 1-3任一项所述的像素单元， 其中所述信号线两侧均包 括通过连接桥连接的两个子电极和一个所述薄膜晶体管， 所述薄膜晶体管的 漏极均与所述连接桥连接。
6、根据权利要求 1-5任一项所述的像素单元， 其中所述像素单元相对于 所述扫描线和所述信号线均对称。
7、根据权利要求 1-6任一项所述的像素单元， 其中所述耦合电极为像素 电极， 所述狭缝电极为公共电极。
8、 一种阵列基板， 包括如权利要求 1-7任一项所述的像素单元。
9、 一种液晶显示装置， 包括如权利要求 8所述的阵列基板。
10、 根据权利要求 9所述的液晶显示装置， 还包括彩膜基板， 所述彩膜 基板包括黑矩阵层， 所述黑矩阵层覆盖所述像素单元之间的区域， 还覆盖所 述像素单元内的所述扫描线和所述信号线。
PCT/CN2013/089304 2013-09-10 2013-12-12 像素单元以及阵列基板、液晶显示装置 WO2015035725A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/361,950 US9773816B2 (en) 2013-09-10 2013-12-12 Pixel unit, array substrate and liquid crystal display

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310410129.5 2013-09-10
CN201310410129.5A CN104423111B (zh) 2013-09-10 2013-09-10 一种像素结构以及阵列基板、液晶显示装置

Publications (1)

Publication Number Publication Date
WO2015035725A1 true WO2015035725A1 (zh) 2015-03-19

Family

ID=52664996

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/089304 WO2015035725A1 (zh) 2013-09-10 2013-12-12 像素单元以及阵列基板、液晶显示装置

Country Status (2)

Country Link
CN (1) CN104423111B (zh)
WO (1) WO2015035725A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10670923B2 (en) * 2015-10-30 2020-06-02 Sharp Kabushiki Kaisha Liquid crystal display panel
WO2018176462A1 (en) * 2017-04-01 2018-10-04 Boe Technology Group Co., Ltd. Liquid crystal array substrate, liquid crystal display panel, and liquid crystal display apparatus
TWI699751B (zh) * 2019-03-22 2020-07-21 友達光電股份有限公司 畫素結構、畫素矩陣、以及相關的驅動方法
CN112083605B (zh) * 2020-08-26 2022-11-29 成都中电熊猫显示科技有限公司 液晶面板、显示装置及液晶面板的配向方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6839117B1 (en) * 2003-12-11 2005-01-04 Hannstar Display Corp. Compensating electrode structure of a display device
CN101398587A (zh) * 2007-09-29 2009-04-01 北京京东方光电科技有限公司 水平电场型液晶显示装置的像素结构
US20100128192A1 (en) * 2008-11-25 2010-05-27 Hee-Joon Kim Liquid crystal display and method of manufacturing the same
CN102156367A (zh) * 2010-08-04 2011-08-17 京东方科技集团股份有限公司 阵列基板、液晶面板和液晶显示器
US20120194776A1 (en) * 2008-05-30 2012-08-02 Sony Corporation Display device
CN203519984U (zh) * 2013-09-10 2014-04-02 北京京东方光电科技有限公司 一种像素结构以及阵列基板、液晶显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6839117B1 (en) * 2003-12-11 2005-01-04 Hannstar Display Corp. Compensating electrode structure of a display device
CN101398587A (zh) * 2007-09-29 2009-04-01 北京京东方光电科技有限公司 水平电场型液晶显示装置的像素结构
US20120194776A1 (en) * 2008-05-30 2012-08-02 Sony Corporation Display device
US20100128192A1 (en) * 2008-11-25 2010-05-27 Hee-Joon Kim Liquid crystal display and method of manufacturing the same
CN102156367A (zh) * 2010-08-04 2011-08-17 京东方科技集团股份有限公司 阵列基板、液晶面板和液晶显示器
CN203519984U (zh) * 2013-09-10 2014-04-02 北京京东方光电科技有限公司 一种像素结构以及阵列基板、液晶显示装置

Also Published As

Publication number Publication date
CN104423111A (zh) 2015-03-18
CN104423111B (zh) 2018-04-10

Similar Documents

Publication Publication Date Title
US10048559B2 (en) Array substrate and semiconductor device containing the same, and method for fabricating the same
TWI358586B (en) Liquid crystal driving electrode, liquid crystal d
US8767158B2 (en) Array substrate, liquid crystal panel, liquid crystal display and driving method thereof
US10488714B2 (en) Array substrate and display device
US9188799B2 (en) Liquid crystal display device having minimized bezel
US20150187810A1 (en) Display device
US10790306B2 (en) Display substrate, manufacturing method thereof and display device
US20150070644A1 (en) Pixel structure
US10197870B2 (en) Array substrate and display device
TWI460512B (zh) 高透光率平面內切換型液晶顯示裝置
JP2004348130A5 (zh)
US20190384124A1 (en) Pixel structure and lcd panel
WO2015010422A1 (zh) 液晶显示面板和显示装置
WO2013078921A1 (zh) 薄膜晶体管液晶显示器的亚像素结构及液晶显示器
US8115878B2 (en) Thin film transistor array substrate and liquid crystal display
WO2016065798A1 (zh) 阵列基板及其制造方法、显示装置
WO2019161688A1 (zh) 一种像素结构及阵列基板
WO2015035725A1 (zh) 像素单元以及阵列基板、液晶显示装置
US20170287421A1 (en) Array Substrate and Manufacturing Method Thereof, Display Panel and Driving Method Thereof
WO2017177764A1 (zh) 显示基板及液晶显示装置
US9875717B2 (en) Liquid crystal display device having improved side visibility
US20160148951A1 (en) Array substrate and method of manufacturing the same, and liquid crystal display screen
KR102098161B1 (ko) 액정표시장치용 어레이 기판
US8502947B2 (en) Liquid crystal display device
RU2664286C1 (ru) Подложка матрицы и жидкокристаллическое устройство отображения

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14361950

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13893376

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 11.07.2016)

122 Ep: pct application non-entry in european phase

Ref document number: 13893376

Country of ref document: EP

Kind code of ref document: A1