WO2015083259A1 - Solar cell manufacturing method - Google Patents
Solar cell manufacturing method Download PDFInfo
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- WO2015083259A1 WO2015083259A1 PCT/JP2013/082624 JP2013082624W WO2015083259A1 WO 2015083259 A1 WO2015083259 A1 WO 2015083259A1 JP 2013082624 W JP2013082624 W JP 2013082624W WO 2015083259 A1 WO2015083259 A1 WO 2015083259A1
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- semiconductor substrate
- mask pattern
- passivation film
- surface side
- film
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
Definitions
- the present invention relates to a method for manufacturing a solar battery cell.
- solar cells Conventional bulk silicon solar cells (hereinafter sometimes referred to as solar cells) are generally manufactured by the following method.
- a p-type silicon substrate is prepared as a first conductivity type substrate.
- the damaged layer on the silicon surface generated when the silicon substrate is sliced from the cast ingot is removed with a thickness of 10 ⁇ m to 20 ⁇ m with an alkaline solution such as sodium hydroxide or potassium hydroxide of several wt% to 20 wt%, for example.
- a surface uneven structure called texture is formed on the surface from which the damage layer has been removed.
- a texture is usually formed in order to suppress light reflection and capture as much sunlight as possible onto the p-type silicon substrate.
- an alkali texture method As a method for producing the texture, for example, there is a method called an alkali texture method.
- anisotropic etching is performed with a solution in which an additive that promotes anisotropic etching such as IPA (isopropyl alcohol) is added to a low concentration alkali solution such as sodium hydroxide or potassium hydroxide of several wt%. Then, the texture is formed so that the silicon (111) surface appears.
- IPA isopropyl alcohol
- the p-type silicon substrate is treated for several tens of minutes at, for example, 800 ° C. to 900 ° C. in a mixed gas atmosphere of, for example, phosphorus oxychloride (POCl 3 ), nitrogen, and oxygen, and the second surface is uniformly applied to the entire surface.
- An n-type layer is formed as a conductive impurity layer.
- the end face region of the p-type silicon substrate is etched by dry etching, for example.
- end face separation of the p-type silicon substrate may be performed by a laser. Thereafter, the p-type silicon substrate is immersed in a hydrofluoric acid aqueous solution, and the glassy material (PSG) deposited on the surface during the diffusion treatment is removed by etching.
- PSG glassy material
- an insulating film such as a silicon oxide film, a silicon nitride film, or a titanium oxide film is formed with a uniform thickness on the surface of the n-type layer as an insulating film (antireflection film) for the purpose of preventing reflection.
- an insulating film such as a silicon oxide film, a silicon nitride film, or a titanium oxide film is formed with a uniform thickness on the surface of the n-type layer as an insulating film (antireflection film) for the purpose of preventing reflection.
- a silicon nitride film as the antireflection film, for example, it is formed by plasma CVD using silane (SiH 4 ) gas and ammonia (NH 3 ) gas as raw materials under conditions of 300 ° C. or higher and reduced pressure.
- the refractive index of the antireflection film is about 2.0 to 2.2, and the optimum film thickness is about 70 nm to 90 nm. It should be noted that the antireflection film formed
- a silver paste to be a surface side electrode is applied to the shape of the grid electrode and the bus electrode on the antireflection film by a screen printing method and dried.
- the silver paste for the surface-side electrode is formed on an insulating film for the purpose of preventing reflection.
- the back aluminum electrode paste containing aluminum, glass, etc., which becomes the back aluminum electrode, and the back silver paste which becomes the back silver bus electrode are screen-printed into the shape of the back aluminum electrode and the shape of the back silver bus electrode on the back surface of the substrate, respectively. Apply and dry.
- the electrode paste applied to the front and back surfaces of the silicon substrate is simultaneously fired at about 600 ° C. to 900 ° C. for several minutes to several tens of seconds.
- a grid electrode and a bus electrode are formed on the front surface side of the silicon substrate as surface side electrodes
- a back aluminum electrode and a back silver bus electrode are formed on the back surface side of the silicon substrate as back surface side electrodes.
- the silver material comes into contact with silicon and re-solidifies while the antireflection film is melted with the glass material contained in the silver paste. Thereby, electrical connection between the surface side electrode and the silicon substrate (n-type layer) is ensured.
- Such a process is called a fire-through method.
- the back aluminum electrode paste also reacts with the back surface of the silicon substrate to compensate for the n-type layer formed by diffusion immediately below the back aluminum electrode, thereby forming a p + layer.
- a silicon nitride film (SiN) is entirely formed except for an electrode region for taking out electricity on the back surface (surface opposite to the light receiving surface) of the solar cell.
- Film or an oxide film may be formed as a back surface passivation film (see, for example, Non-Patent Document 1 and Non-Patent Document 2).
- the back surface passivation film when a silicon nitride film (SiN film) or an oxide film is used as the back surface passivation film, there is a step of drilling a part of the back surface passivation film, which is an insulating film, for conduction with the back surface of the solar cell substrate. It is necessary separately. This process of drilling is an obstacle to mass production.
- SiN film silicon nitride film
- oxide film oxide film
- the insulating film was drilled by an expensive and laborious process using photolithography technology.
- a technique for directly drilling with a laser having a small number of processes has been established.
- laser drilling has a low processing capability and is not suitable for mass production.
- This invention is made in view of the above, Comprising: Obtaining the manufacturing method of the photovoltaic cell which can manufacture the photovoltaic cell which was provided with the back surface passivation film and was excellent in photoelectric conversion efficiency with a simple process with sufficient productivity. With the goal.
- a method for manufacturing a solar battery cell according to the present invention includes a second conductivity type impurity diffusion layer on one surface side that is a light receiving surface side in a first conductivity type semiconductor substrate.
- a second step of forming a mask pattern on the other side of the semiconductor substrate, and a passivation film having a thickness smaller than the thickness of the mask pattern is formed on the other side of the semiconductor substrate.
- FIG. 1 is a diagram schematically illustrating the configuration of a solar battery cell according to an embodiment of the present invention, and is a top view of the solar battery cell viewed from the light receiving surface side.
- FIG. 2 is a diagram schematically showing the configuration of the solar cell according to the embodiment of the present invention, and is a bottom view of the solar cell viewed from the side opposite to the light receiving surface (back surface).
- FIG. 3 is a cross-sectional view of the main part of the solar battery cell according to the embodiment of the present invention, and is a cross-sectional view of the main part in the AA direction of FIG. FIG.
- FIG. 4 is a cross-sectional view of the main part of the solar battery cell according to the embodiment of the present invention, and is a cross-sectional view of the main part in the BB direction of FIG.
- FIG. 5 is a bottom view of the solar battery cell showing the shape of the comb-shaped opening formed in the back surface passivation film of the solar battery cell according to the embodiment of the present invention.
- FIG. 6 is a flowchart for explaining a manufacturing process of the solar battery cell according to the embodiment of the present invention.
- FIG. 7 is a process diagram schematically showing an example of a manufacturing process of the solar battery cell according to the embodiment of the present invention.
- FIG. 8: is process drawing which shows typically an example of the manufacturing process of the photovoltaic cell concerning embodiment of this invention.
- FIG. 9 is a process diagram schematically showing an example of the manufacturing process of the solar battery cell according to the embodiment of the present invention.
- FIG. 10 is a process diagram schematically showing an example of the manufacturing process of the solar battery cell according to the embodiment of the present invention.
- FIG. 11 is process drawing which shows typically an example of the manufacturing process of the photovoltaic cell concerning embodiment of this invention.
- FIG. 12 is process drawing which shows typically an example of the manufacturing process of the photovoltaic cell concerning embodiment of this invention.
- FIG. 13 is process drawing which shows typically an example of the manufacturing process of the photovoltaic cell concerning embodiment of this invention.
- FIG. 14 is a process diagram schematically showing an example of a manufacturing process of the solar battery cell according to the embodiment of the present invention.
- FIG. 11 is process drawing which shows typically an example of the manufacturing process of the photovoltaic cell concerning embodiment of this invention.
- FIG. 12 is process drawing which shows typically an example of the manufacturing process of the photovoltaic cell concerning embodiment of this invention.
- FIG. 13 is
- FIG. 15 is process drawing which shows typically an example of the manufacturing process of the photovoltaic cell concerning embodiment of this invention.
- FIG. 16 is process drawing which shows typically an example of the manufacturing process of the photovoltaic cell concerning embodiment of this invention.
- FIG. 17 is process drawing which shows typically the manufacturing process of a back surface side electrode among the manufacturing processes of the photovoltaic cell concerning embodiment of this invention.
- FIG. 18 is process drawing which shows typically the manufacturing process of a back surface side electrode among the manufacturing processes of the photovoltaic cell concerning embodiment of this invention.
- FIG. 19 is process drawing which shows typically the manufacturing process of a back surface side electrode among the manufacturing processes of the photovoltaic cell concerning embodiment of this invention.
- FIG. 20 is process drawing which shows typically the manufacturing process of a back surface side electrode among the manufacturing processes of the photovoltaic cell concerning embodiment of this invention.
- FIG. 21 is process drawing which shows typically the manufacturing process of a back surface side electrode among the manufacturing processes of the photovoltaic cell concerning embodiment of this invention.
- FIG. 22 is a process diagram schematically illustrating a manufacturing process of the back-side electrode among the manufacturing processes of the solar battery cell according to the embodiment of the present invention.
- Embodiment. 1 to 5 are diagrams schematically showing a configuration of a solar battery cell 1 according to an embodiment of the present invention.
- FIG. 1 is a top view of the solar battery cell 1 viewed from the light receiving surface side.
- FIG. 2 is a bottom view of the solar battery cell 1 viewed from the side opposite to the light receiving surface (back surface).
- FIG. 3 is a cross-sectional view of the main part of the solar battery cell 1, and is a cross-sectional view of the main part in the AA direction of FIG. 4 is a cross-sectional view of main parts of the solar battery cell 1, and is a cross-sectional view of main parts in the BB direction of FIG.
- FIG. 5 is a bottom view of the solar cell 1 showing the shape of the comb-shaped opening formed in the back surface passivation film provided on the back surface side of the solar cell 1.
- n-type impurity diffusion layer 3 is formed by phosphorous diffusion on the light-receiving surface side of semiconductor substrate 2 made of p-type single crystal silicon, and semiconductor substrate 11 having a pn junction is formed.
- an antireflection film 4 made of a silicon nitride film (SiN film) is formed on the n-type impurity diffusion layer 3.
- the semiconductor substrate 2 is not limited to a p-type single crystal silicon substrate, and an n-type single crystal silicon substrate may be used.
- a texture structure constituted by minute irregularities 2a is formed on the light receiving surface side (n-type impurity diffusion layer 3) and the back surface side of the semiconductor substrate 11.
- the texture structure increases the area that absorbs light from the outside on the light receiving surface, suppresses the light reflectance on the light receiving surface, and confines light.
- the antireflection film 4 is made of an insulating film for the purpose of preventing reflection, such as a silicon nitride film (SiN film), a silicon oxide film (SiO 2 film), or a titanium oxide film (TiO 2 film).
- a plurality of long and narrow surface silver grid electrodes 5 are arranged side by side on the light receiving surface side of the semiconductor substrate 11, and a surface silver bus electrode 6 electrically connected to the surface silver grid electrode 5 is substantially the same as the surface silver grid electrode 5. They are provided so as to be orthogonal to each other, and are electrically connected to the n-type impurity diffusion layer 3 at the bottom portions.
- the front silver grid electrode 5 and the front silver bus electrode 6 are made of a silver material.
- the front silver grid electrode 5 has a width of about 100 ⁇ m to 200 ⁇ m, for example, and is arranged substantially in parallel at intervals of about 2 mm, and collects electricity generated inside the semiconductor substrate 11. Further, the front silver bus electrodes 6 have a width of, for example, about 1 mm to 3 mm and are arranged in a number of 2 to 4 per solar battery cell, and the electricity collected by the front silver grid electrode 5 is taken out to the outside.
- the front silver grid electrode 5 and the front silver bus electrode 6 constitute a light receiving surface side electrode 12 as a first electrode. Since the light receiving surface side electrode 12 blocks sunlight incident on the semiconductor substrate 11, it is desirable to reduce the area as much as possible from the viewpoint of improving the power generation efficiency, and a comb-shaped surface silver grid as shown in FIG. Generally, the electrodes 5 and the bar-shaped surface silver bus electrodes 6 are arranged.
- a silver paste is usually used, for example, lead boron glass is added.
- This glass has a frit shape and is composed of, for example, lead (Pb) 5 to 30 wt%, boron (B) 5 to 10 wt%, silicon (Si) 5 to 15 wt%, and oxygen (O) 30 to 60 wt%.
- lead (Pb) 5 to 30 wt% boron (B) 5 to 10 wt%
- silicon (Si) 5 to 15 wt% silicon
- oxygen (O) 30 to 60 wt% oxygen
- zinc (Zn), cadmium (Cd), etc. may be mixed by several wt%.
- Such lead boron glass has a property of melting by heating at several hundred degrees C. (for example, 800.degree. C.) and eroding silicon at that time.
- a method of obtaining electrical contact between a silicon substrate and a silver paste by using the characteristics of the glass frit is used.
- a back surface passivation film 7 which is a back surface insulating film made of a silicon nitride film (SiN film) is formed on the entire back surface (surface opposite to the light receiving surface) of the semiconductor substrate 11.
- the back surface passivation film 7 is provided with comb-shaped openings 7a extending in the vertical and horizontal directions in the figure.
- attention is paid to the shape of the opening 7 a in the back surface passivation film 7, and the description of some members is omitted.
- a back silver electrode 8 including a silver material and a back aluminum electrode 9 including an aluminum material are embedded in the opening 7a.
- the intersection portion between the line-shaped region extending in the vertical direction and the line-shaped region extending in the horizontal direction in the comb-shaped opening 7a is formed in a square shape.
- the intersections are arranged in substantially the same direction as the front silver bus electrode 6.
- a back silver electrode 8 is embedded in this square intersection portion of the opening 7 a in a state in which a part protrudes from the surface of the back surface passivation film 7.
- a back aluminum electrode 9 is embedded in a region where the back silver electrode 8 is not embedded in the opening 7a.
- the back aluminum electrode 9 is embedded in a comb shape in the opening 7a, like the electrode on the light receiving surface side of the semiconductor substrate 11, so that current collection from the back surface of the semiconductor substrate 11 can be efficiently performed. Further, the back aluminum electrode 9 is also formed on the back surface passivation film 7 so as to surround the back silver electrode 8 on the back surface of the semiconductor substrate 11, and is formed on almost the entire back surface of the semiconductor substrate 11 surrounding the back silver electrode 8. Has been.
- the back silver electrode 8 and the back aluminum electrode 9 constitute a back electrode 13 that is a second electrode.
- a p + layer (BSF (Back Surface Field) layer) 10 containing a high concentration impurity is formed in the lower region of the back aluminum electrode 9 in the surface layer portion on the back surface (surface opposite to the light receiving surface) of the semiconductor substrate 11. Is formed.
- the p + layer 10 is provided to obtain the BSF effect, and the electron concentration of the p-type layer (semiconductor substrate 2) is increased by an electric field having a band structure so that electrons in the p-type layer (semiconductor substrate 2) do not disappear. .
- the solar cell 1 configured as described above, sunlight is irradiated from the light receiving surface side of the solar cell 1 to the pn junction surface of the semiconductor substrate 11 (the junction surface between the semiconductor substrate 2 and the n-type impurity diffusion layer 3). As a result, holes and electrons are generated. Due to the electric field of the pn junction, the generated electrons move toward the n-type impurity diffusion layer 3 and the holes move toward the p + layer 10. As a result, electrons are excessive in the n-type impurity diffusion layer 3 and holes are excessive in the p + layer 10. As a result, a photovoltaic force is generated.
- This photovoltaic force is generated in the direction of biasing the pn junction in the forward direction, the light receiving surface side electrode 12 connected to the n-type impurity diffusion layer 3 becomes a negative pole, and the back aluminum electrode 9 connected to the p + layer 10 becomes a positive pole. Thus, a current flows through an external circuit (not shown).
- the reason for the presence of the back silver electrode 8 is that it is necessary to tab-connect the solar cells 1 when connecting a plurality of solar cells 1 to produce a module.
- FIG. 6 is a flowchart for explaining a manufacturing process of the solar battery cell 1 according to the embodiment of the present invention.
- 7 to 16 are process diagrams schematically showing an example of the manufacturing process of the solar battery cell 1 according to the embodiment of the present invention, and are sectional views corresponding to FIG. 17 to 22 are process diagrams schematically showing a manufacturing process of the back surface side electrode 13 among the manufacturing processes of the solar battery cell 1 according to the embodiment of the present invention.
- FIG. 17A to FIG. 22A are bottom views of the semiconductor substrate 11 as viewed from the side opposite to the light receiving surface (back surface).
- (B) in FIGS. 17 to 19 is a cross-sectional view of the main part in the CC direction of (a) in each figure.
- 20B to 22B are cross-sectional views of the main part in the DD direction of FIG.
- a p-type single crystal silicon substrate having a thickness of several hundred ⁇ m is prepared as the semiconductor substrate 2 (FIG. 7). Since the p-type single crystal silicon substrate is manufactured by slicing an ingot formed by cooling and solidifying molten silicon with a wire saw, damage at the time of slicing remains on the surface. Therefore, the p-type single crystal silicon substrate is etched near the surface of the p-type single crystal silicon substrate by etching the surface by immersing the surface in an acid or heated alkaline solution, for example, an aqueous sodium hydroxide solution. Remove the damage area that exists in the.
- an acid or heated alkaline solution for example, an aqueous sodium hydroxide solution.
- the surface is removed by a thickness of 10 ⁇ m to 20 ⁇ m with an alkali solution such as sodium hydroxide or potassium hydroxide of several wt% to 20 wt%.
- an alkali solution such as sodium hydroxide or potassium hydroxide of several wt% to 20 wt%.
- a p-type silicon substrate used for the semiconductor substrate 2 a p-type single crystal silicon substrate having a specific resistance of 0.1 ⁇ ⁇ cm to 5 ⁇ ⁇ cm and having a (100) plane orientation will be described as an example.
- an additive that promotes anisotropic etching such as IPA (isopropyl alcohol) is added to the same alkali low concentration solution, such as several wt% sodium hydroxide or potassium hydroxide.
- Anisotropic etching is performed with the solution.
- a micro-concave pattern 2a having a substantially quadrangular pyramid shape is formed on the light-receiving surface side and back surface side of the p-type single crystal silicon substrate so that the silicon (111) surface is exposed, thereby forming a texture structure. (Step S10, FIG. 8). That is, the texture structure is formed on the front and back surfaces of the p-type single crystal silicon substrate by wet etching (alkali texture method) using an alkaline solution.
- a pn junction is formed in the semiconductor substrate 2 (step S20, FIG. 9). That is, a group V element such as phosphorus (P) is diffused into the semiconductor substrate 2 to form the n-type impurity diffusion layer 3 having a thickness of several hundred nm.
- a pn junction is formed by diffusing phosphorus oxychloride (POCl 3 ) by thermal diffusion with respect to a p-type single crystal silicon substrate having a texture structure on the surface.
- the p-type single crystal silicon substrate is several tens of minutes at a high temperature of, for example, 800 ° C. to 900 ° C. by a vapor phase diffusion method in a mixed gas atmosphere of, for example, phosphorus oxychloride (POCl 3 ) gas, nitrogen gas, and oxygen gas.
- the n-type impurity diffusion layer 3 in which phosphorus (P) is diffused is uniformly formed in the surface layer of the p-type single crystal silicon substrate by thermal diffusion. Good electrical characteristics of the solar cell can be obtained when the sheet resistance range of the n-type impurity diffusion layer 3 formed on the surface of the semiconductor substrate 2 is about 30 ⁇ / ⁇ to 80 ⁇ / ⁇ .
- the n-type impurity diffusion layer 3 is formed on the entire surface of the semiconductor substrate 2. For this reason, the front surface (light receiving surface) and the back surface of the semiconductor substrate 2 are in an electrically connected state. Therefore, in order to cut off this electrical connection, the end face region of the semiconductor substrate 2 is etched by dry etching, for example (FIG. 10). Further, a glassy (phosphosilicate glass, PSG: Phospho-Silicate Glass) layer deposited on the surface during the diffusion process is formed on the surface immediately after the formation of the n-type impurity diffusion layer 3. For this reason, the semiconductor substrate 2 is immersed in a hydrofluoric acid aqueous solution or the like to remove the PSG layer by etching.
- PSG Phospho-Silicate Glass
- an insulating film such as a silicon oxide film, a silicon nitride film, or a titanium oxide film is formed as a reflection preventing film 4 with a uniform thickness on one surface of the light receiving surface side of the semiconductor substrate 2 (see FIG. Step S30, FIG. 10).
- the film thickness and refractive index of the antireflection film 4 are set to values that most suppress light reflection.
- the antireflection film 4 is formed by using, for example, a plasma CVD method, using a mixed gas of silane (SiH 4 ) gas and ammonia (NH 3 ) gas as a raw material, and at 300 ° C. or higher and under reduced pressure. 4, a silicon nitride film is formed.
- the refractive index is, for example, about 2.0 to 2.2, and the optimum antireflection film thickness is, for example, 70 nm to 90 nm.
- the antireflection film 4 two or more films having different refractive indexes may be laminated.
- the antireflection film 4 may be formed by vapor deposition, thermal CVD, or the like. It should be noted that the antireflection film 4 formed in this manner is an insulator, and simply forming the light receiving surface side electrode 12 on the surface does not act as a solar battery cell.
- the n-type impurity diffusion layer 3 formed on the back surface of the semiconductor substrate 2 is removed by diffusion of phosphorus (P).
- P phosphorus
- the semiconductor substrate 2 made of p-type single crystal silicon which is the first conductivity type layer, and the n-type impurity diffusion layer 3 which is the second conductivity type layer formed on the light receiving surface side of the semiconductor substrate 2 A semiconductor substrate 11 having a pn junction is obtained (FIG. 11).
- the n-type impurity diffusion layer 3 is formed only on one surface of the semiconductor substrate 2, the above-described etching of the end surface region of the semiconductor substrate 2 and the removal of the n-type impurity diffusion layer 3 formed on the back surface of the semiconductor substrate 2 are performed. Is unnecessary.
- thermosetting resin a resin having resistance to the temperature (deposition temperature) at the time of forming the back surface passivation film 7 is used.
- the shape of the mask pattern 21 is created based on a desired electrode pattern.
- the mask pattern 21 is formed in a comb shape, and the intersection of the line-shaped region extending in the vertical direction and the line-shaped region extending in the horizontal direction in the comb-shaped shape is a square shape.
- thermosetting resin is solidified by introducing the semiconductor substrate 11 into a baking furnace and performing heat treatment (step S40, FIG. 12, FIG. 17).
- This thermosetting resin solidification step is performed in the chamber preceding the film forming chamber for forming the back surface passivation film 7 when the apparatus used for forming the back surface passivation film 7 to be described later is an apparatus having a multi-chamber system.
- the semiconductor substrate 11 is held, and the temperature in the chamber is set to be equal to or higher than the solidification temperature of the thermosetting resin.
- the semiconductor substrate 11 may be held in a film formation chamber where the back surface passivation film 7 is formed, and the temperature in the chamber may be equal to or higher than the solidification temperature of the thermosetting resin. Thereafter, the back surface passivation film 7 is formed as it is in the film forming chamber. Thereby, the continuous process of the process of solidifying a thermosetting resin and the film-forming process of the back surface passivation film 7 is possible, and the process can be simplified.
- thermosetting resin used as a printing paste for forming the mask pattern 21
- the film has a resistance to the film formation temperature in the subsequent film formation process of the back surface passivation film 7, and the subsequent process. If it can be easily removed by incineration or dry etching, it is not limited to this.
- a printing paste having a solidification characteristic different from that of the thermosetting resin such as an ultraviolet curable resin.
- an ultraviolet curable resin is used as a printing paste for forming a mask pattern, after the ultraviolet curable resin is pattern printed on the back side of the semiconductor substrate 11, the ultraviolet curable resin is irradiated with ultraviolet rays to be solidified.
- the ultraviolet curable resin a resin having resistance to the temperature (film formation temperature) at the time of forming the back surface passivation film 7 is used.
- a back surface passivation film 7 made of a silicon nitride film (SiN film) is formed on the entire back surface side of the semiconductor substrate 11 on which the mask pattern 21 is formed (step S50, FIG. 13, FIG. 18). That is, a silicon nitride film (SiN film) having a refractive index of 1.9 to 2.2 and a thickness of 60 nm to 300 nm is formed on the back side of the semiconductor substrate 11 on which the mask pattern 21 is formed by thermosetting resin, for example, by plasma CVD. A back surface passivation film 7 made of is formed.
- the back surface passivation film 7 is formed by embedding the mask pattern 21 with a film thickness smaller than the thickness of the mask pattern 21 so that at least a part of the upper side surface of the mask pattern 21 is exposed. Note that the mask pattern 21 in FIG. 18A is shown through the back surface passivation film 7.
- thermosetting resin may not be successfully removed in the process. That is, when the entire surface of the thermosetting resin is covered with the back surface passivation film 7, oxygen is not supplied to the surface of the thermosetting resin, and the thermosetting resin is hardly burned. Therefore, the back surface passivation film 7 is formed such that at least a part of the upper side surface of the mask pattern 21 is exposed under a condition with poor step coverage.
- the plasma CVD method is used as the film formation method for the back surface passivation film 7, it is preferable to select conditions close to normal pressure (normal pressure plasma CVD method).
- a film forming method other than the plasma CVD method is used as the film forming method for the back surface passivation film 7, it is preferable to select the sputtering method.
- thermosetting resin of the mask pattern 21 is burned off by heat treatment (incineration removal).
- the heating temperature in the heat treatment is such that the thermosetting resin disappears and the back surface passivation film 7 has resistance.
- a comb-shaped opening 7 a that penetrates the back surface passivation film 7 in the film thickness direction and exposes the back surface side of the semiconductor substrate 2 is formed.
- the opening 7 a is formed in the same comb shape as the mask pattern 21.
- the back surface passivation film 7 since at least a part of the upper side surface of the mask pattern 21 is exposed from the back surface passivation film 7, oxygen is reliably supplied to the surface of the thermosetting resin, and the thermosetting resin is surely incinerated. . Further, by removing the mask pattern 21, the back surface passivation film 7 on the mask pattern 21 is also removed.
- the semiconductor substrate 11 is placed in a chamber subsequent to the film forming chamber on which the back surface passivation film 7 is formed. Hold. Then, the temperature in the chamber is adjusted to a temperature at which the thermosetting resin disappears and the back surface passivation film 7 has resistance. Thereby, the continuous process of the film-forming process of the back surface passivation film 7 and the process of removing the thermosetting resin is possible, and the process can be simplified.
- the semiconductor substrate 11 is held as it is in the film formation chamber where the back surface passivation film 7 is formed, and the temperature in the chamber is adjusted to a temperature at which the thermosetting resin disappears and the back surface passivation film 7 has resistance. May be. Thereby, the continuous process of the film-forming process of the back surface passivation film 7 and the process of removing the thermosetting resin is possible, and the process can be simplified.
- a gas having a sufficient chemical selectivity between the silicon nitride film (SiN film) and the thermosetting resin other than the incineration removal of the mask pattern 21 by high-temperature heat treatment can be obtained even by using dry etching using.
- the mask pattern 21 is formed on the back surface side of the semiconductor substrate 11 before the back surface passivation film 7 is formed, the back surface passivation film 7 is formed, and then the mask pattern 21 is removed by incineration. Therefore, in the present embodiment, drilling of the back surface passivation film 7 can be realized by using a thermosetting resin printing and heat treatment, which are inexpensive and simple methods.
- the back side electrode 13 is formed (before firing).
- the back silver paste 8a which is an electrode material paste, is applied to the shape of the back silver electrode 8 in a pad shape by screen printing on the back side of the semiconductor substrate 11 and dried (step S70, FIG. 20).
- the back silver paste 8a is partly formed in a square area at the intersection of the line-shaped area extending in the vertical direction and the line-shaped area extending in the horizontal direction in the comb-shaped opening 7a. Is printed so as to protrude from the surface of the back surface passivation film 7.
- the back aluminum paste 9a which is an electrode material paste, is applied to the shape of the back aluminum electrode 9 by screen printing on the back side of the semiconductor substrate 11, and dried (step S80, FIG. 15, FIG. 21).
- the back aluminum paste 9a is applied in such a manner that the region excluding the application region of the back silver paste 8a in the comb-shaped opening 7a is filled and brought into contact with the back silver paste 8a.
- the back aluminum paste 9 a is also applied to the back surface passivation film 7 so as to surround the back silver electrode 8 on the back surface of the semiconductor substrate 11, and is applied to almost the entire back surface of the semiconductor substrate 11 surrounding the back silver electrode 8. . Therefore, the back aluminum paste 9a is printed on the back surface of the semiconductor substrate 11 except for the region of the back silver paste 8a that has been printed and dried previously.
- the back silver paste 8a is applied to the inner side area of the square area of the opening 7a, and the back aluminum paste is applied to the outer side area of the square area of the opening 7a. Although the case where 9a is applied is shown, the back silver paste 8a may be applied to the entire square area.
- a surface silver electrode (light-receiving surface side electrode 12) is formed on the light-receiving surface side by screen printing (before firing). That is, a silver paste 5a, which is an electrode material paste containing glass frit, is applied to the shape of the front silver grid electrode 5 and the front silver bus electrode 6 on the antireflection film 4 which is the light receiving surface of the semiconductor substrate 11 by screen printing. After that, the silver paste 5a is dried (step S90, FIG. 15). 12 to 16 show a case where the interval between adjacent front silver grid electrodes 5 on the light receiving surface side is the same as the interval between adjacent back aluminum electrodes 9 serving as grid electrodes on the back surface side. Further, FIG. 15 corresponds to the cross-sectional view in the AA direction of FIG. 1, and therefore the back silver paste 8a is not shown in FIG.
- the electrode paste on the front and back surfaces of the semiconductor substrate 11 is simultaneously fired at, for example, 600 ° C. to 900 ° C., so that the antireflection film 4 is melted with the glass material contained in the silver paste on the front side of the semiconductor substrate 11.
- the silver material comes into contact with silicon and re-solidifies.
- the front silver grid electrode 5 and the front silver bus electrode 6 as the light receiving surface side electrode 12 are obtained, and conduction between the light receiving surface side electrode 12 and the silicon of the semiconductor substrate 11 is ensured (step S100, FIG. 16). ).
- Such a process is called a fire-through method.
- the silver material of the back silver paste 8a comes into contact with silicon and re-solidifies to obtain the back silver electrode 8 (FIG. 22).
- the back aluminum paste 9 a applied to the opening 7 a reacts with the silicon of the semiconductor substrate 11 to obtain the back aluminum electrode 9, and the p + layer 10 is formed immediately below the back aluminum electrode 9.
- the back aluminum paste 9 a applied on the back surface passivation film 7 is also baked, and the back aluminum electrode 9 is obtained also on the back surface passivation film 7. Therefore, the back aluminum electrode 9 is formed on the back surface of the semiconductor substrate 11 except for the region of the back silver electrode 8.
- the back aluminum paste 9a does not contain glass frit. For this reason, no fire-through occurs in the baking of the back aluminum paste 9a.
- the solar battery cell 1 according to the present embodiment shown in FIGS. 1 to 5 is obtained.
- the order (printing order) of arrangement of the paste, which is an electrode material, on the semiconductor substrate 11 may be switched between the light receiving surface side and the back surface side.
- the back surface passivation film 7 is formed after forming the mask pattern 21 on the back surface side of the semiconductor substrate 11, and then the mask pattern 21 is removed.
- the opening part 7a can be formed in the back surface passivation film 7 by an inexpensive and simple process.
- the method for manufacturing a solar battery cell according to the present invention is useful when manufacturing a solar battery cell having a back surface passivation film and excellent in photoelectric conversion efficiency with a simple process and high productivity.
- 1 solar cell 2 semiconductor substrate, 2a minute unevenness, 3 n-type impurity diffusion layer, 4 antireflection film, 5 surface silver grid electrode, 5a silver paste, 6 surface silver bus electrode, 7 back surface passivation film, 7a opening, 8 back silver electrode, 8a back silver paste, 9 back aluminum electrode, 9a back aluminum paste, 10 p + layer, 11 semiconductor substrate, 12 light receiving surface side electrode, 13 back surface side electrode, 21 mask pattern.
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Abstract
This solar cell manufacturing method includes: a first step wherein a second conductivity-type impurity diffused layer is formed on one surface side of a first conductivity-type semiconductor substrate, said one surface side being to be the light receiving surface side; a second step wherein a mask pattern is formed on the other surface side of the semiconductor substrate; a third step wherein a passivation film having a film thickness that is less than the thickness of the mask pattern is formed on the other surface side of the semiconductor substrate, and the mask pattern is embedded in the passivation film such that a part of a side surface of the mask pattern is exposed; a fourth step wherein an opening is formed by removing the passivation film, said opening penetrating the passivation film in the film thickness direction, and exposing the other surface side of the semiconductor substrate; a fifth step wherein a rear surface-side electrode that is to be electrically connected to the other surface side of the semiconductor substrate is embedded in the opening; and a sixth step wherein a light receiving surface-side electrode to be electrically connected to the impurity diffused layer is formed on the one surface side of the semiconductor substrate.
Description
本発明は、太陽電池セルの製造方法に関するものである。
The present invention relates to a method for manufacturing a solar battery cell.
従来のバルク型シリコン太陽電池セル(以下、太陽電池セルと呼ぶ場合がある)は、一般的に以下のような方法により作製されている。まず、例えば第1導電型の基板としてp型シリコン基板を用意する。そして、シリコン基板において鋳造インゴットからスライスした際に発生するシリコン表面のダメージ層を、例えば数wt%~20wt%の水酸化ナトリウムや水酸化カリウムのようなアルカリ溶液で10μm~20μm厚除去する。
Conventional bulk silicon solar cells (hereinafter sometimes referred to as solar cells) are generally manufactured by the following method. First, for example, a p-type silicon substrate is prepared as a first conductivity type substrate. Then, the damaged layer on the silicon surface generated when the silicon substrate is sliced from the cast ingot is removed with a thickness of 10 μm to 20 μm with an alkaline solution such as sodium hydroxide or potassium hydroxide of several wt% to 20 wt%, for example.
つぎに、ダメージ層を除去した表面にテクスチャーと呼ばれる表面凸凹構造を作製する。太陽電池セルの表面側(受光面側)では、通常、光反射を抑制させて太陽光をできるだけ多くp型シリコン基板上に取り込むために、このようなテクスチャーを形成する。テクスチャーの作製方法としては、例えばアルカリテクスチャー法と呼ばれる方法がある。アルカリテクスチャー法では、数wt%の水酸化ナトリウムや水酸化カリウムの様なアルカリ低濃度液にIPA(イソプロピルアルコール)等の異方性エッチングを促進する添加剤を添加した溶液で異方性エッチングを行ない、シリコン(111)面が出るようにテクスチャーを形成する。
Next, a surface uneven structure called texture is formed on the surface from which the damage layer has been removed. On the surface side (light-receiving surface side) of the solar battery cell, such a texture is usually formed in order to suppress light reflection and capture as much sunlight as possible onto the p-type silicon substrate. As a method for producing the texture, for example, there is a method called an alkali texture method. In the alkaline texture method, anisotropic etching is performed with a solution in which an additive that promotes anisotropic etching such as IPA (isopropyl alcohol) is added to a low concentration alkali solution such as sodium hydroxide or potassium hydroxide of several wt%. Then, the texture is formed so that the silicon (111) surface appears.
続いて、拡散処理としてp型シリコン基板を例えばオキシ塩化リン(POCl3)、窒素、酸素の混合ガス雰囲気で例えば800℃~900℃で数十分間処理し、表面全面に一様に第2導電型の不純物層としてn型層を形成する。シリコン表面に一様に形成されたn型層のシート抵抗を30~80Ω/□程度とすることで、良好な太陽電池の電気特性が得られる。
Subsequently, as a diffusion treatment, the p-type silicon substrate is treated for several tens of minutes at, for example, 800 ° C. to 900 ° C. in a mixed gas atmosphere of, for example, phosphorus oxychloride (POCl 3 ), nitrogen, and oxygen, and the second surface is uniformly applied to the entire surface. An n-type layer is formed as a conductive impurity layer. By setting the sheet resistance of the n-type layer uniformly formed on the silicon surface to about 30 to 80 Ω / □, good electric characteristics of the solar cell can be obtained.
ここで、n型層は、シリコン表面に一様に形成されるので、表面と裏面とは電気的に接続された状態である。この電気的接続を遮断するために、例えばドライエチングによりp型シリコン基板の端面領域をエッチングする。また、その他の方法として、レーザによりp型シリコン基板の端面分離を行うこともある。この後、p型シリコン基板をフッ酸水溶液に浸漬し、拡散処理中に表面に堆積したガラス質(PSG)をエッチング除去する。
Here, since the n-type layer is uniformly formed on the silicon surface, the front surface and the back surface are in an electrically connected state. In order to cut off this electrical connection, the end face region of the p-type silicon substrate is etched by dry etching, for example. As another method, end face separation of the p-type silicon substrate may be performed by a laser. Thereafter, the p-type silicon substrate is immersed in a hydrofluoric acid aqueous solution, and the glassy material (PSG) deposited on the surface during the diffusion treatment is removed by etching.
つぎに、反射防止を目的とした絶縁膜(反射防止膜)としてシリコン酸化膜、シリコン窒化膜、酸化チタン膜などの絶縁膜をn型層の表面に一様な厚みで形成する。反射防止膜としてシリコン窒化膜を形成する場合は、例えばプラズマCVD法でシラン(SiH4)ガス及びアンモニア(NH3)ガスを原材料にして、300℃以上、減圧下の条件で成膜形成する。反射防止膜の屈折率は2.0~2.2程度であり、最適な膜厚は70nm~90nm程度である。なお、このようにして形成される反射防止膜は絶縁体であることに注意すべきであり、表面側電極をこの上に単に形成しただけでは、太陽電池として作用しない。
Next, an insulating film such as a silicon oxide film, a silicon nitride film, or a titanium oxide film is formed with a uniform thickness on the surface of the n-type layer as an insulating film (antireflection film) for the purpose of preventing reflection. In the case of forming a silicon nitride film as the antireflection film, for example, it is formed by plasma CVD using silane (SiH 4 ) gas and ammonia (NH 3 ) gas as raw materials under conditions of 300 ° C. or higher and reduced pressure. The refractive index of the antireflection film is about 2.0 to 2.2, and the optimum film thickness is about 70 nm to 90 nm. It should be noted that the antireflection film formed in this way is an insulator, and merely forming the surface-side electrode thereon does not act as a solar cell.
つぎに、グリッド電極形成用およびバス電極形成用のマスクを使用して、表面側電極となる銀ペーストを反射防止膜上にグリッド電極およびバス電極の形状にスクリーン印刷法により塗布し、乾燥させる。ここでは、表面側電極用の銀ペーストは、反射防止を目的とした絶縁膜に形成される。
Next, using a grid electrode forming mask and a bus electrode forming mask, a silver paste to be a surface side electrode is applied to the shape of the grid electrode and the bus electrode on the antireflection film by a screen printing method and dried. Here, the silver paste for the surface-side electrode is formed on an insulating film for the purpose of preventing reflection.
つぎに、裏アルミニウム電極となりアルミニウム、ガラス等を含む裏アルミニウム電極ペースト、および裏銀バス電極となる裏銀ペーストを基板の裏面にそれぞれ裏アルミニウム電極の形状および裏銀バス電極の形状にスクリーン印刷法により塗布し、乾燥させる。
Next, the back aluminum electrode paste containing aluminum, glass, etc., which becomes the back aluminum electrode, and the back silver paste which becomes the back silver bus electrode are screen-printed into the shape of the back aluminum electrode and the shape of the back silver bus electrode on the back surface of the substrate, respectively. Apply and dry.
つぎに、シリコン基板の表裏面に塗布した電極ペーストを同時に600℃~900℃程度で数分間~数十秒間焼成する。これにより、シリコン基板の表面側に表面側電極としてグリッド電極およびバス電極が形成され、シリコン基板の裏面側に裏面側電極として裏アルミニウム電極および裏銀バス電極が形成される。ここで、シリコン基板の表面側では銀ペースト中に含まれているガラス材料で反射防止膜が溶融している間に銀材料がシリコンと接触し、再凝固する。これにより、表面側電極とシリコン基板(n型層)との導通が確保される。このようなプロセスは、ファイヤースルー法と呼ばれている。また、裏アルミニウム電極ペーストもシリコン基板の裏面と反応し、裏アルミニウム電極の直下に拡散によって形成されていたn型層を補償してp+層が形成される。このような工程を実施することにより、バルク型シリコン太陽電池セルが形成される。
Next, the electrode paste applied to the front and back surfaces of the silicon substrate is simultaneously fired at about 600 ° C. to 900 ° C. for several minutes to several tens of seconds. As a result, a grid electrode and a bus electrode are formed on the front surface side of the silicon substrate as surface side electrodes, and a back aluminum electrode and a back silver bus electrode are formed on the back surface side of the silicon substrate as back surface side electrodes. Here, on the surface side of the silicon substrate, the silver material comes into contact with silicon and re-solidifies while the antireflection film is melted with the glass material contained in the silver paste. Thereby, electrical connection between the surface side electrode and the silicon substrate (n-type layer) is ensured. Such a process is called a fire-through method. Further, the back aluminum electrode paste also reacts with the back surface of the silicon substrate to compensate for the n-type layer formed by diffusion immediately below the back aluminum electrode, thereby forming a p + layer. By carrying out such a process, a bulk type silicon solar battery cell is formed.
ここで、更に高光電変換効率を有する太陽電池セルを得るために、太陽電池セルの裏面(受光面と反対側の面)における電気を取り出すための電極領域を除く全体に、シリコン窒化膜(SiN膜)や酸化膜を裏面パッシベーション膜として形成することがある(たとえば、非特許文献1、非特許文献2参照)。
Here, in order to obtain a solar cell having higher photoelectric conversion efficiency, a silicon nitride film (SiN) is entirely formed except for an electrode region for taking out electricity on the back surface (surface opposite to the light receiving surface) of the solar cell. Film) or an oxide film may be formed as a back surface passivation film (see, for example, Non-Patent Document 1 and Non-Patent Document 2).
しかしながら、シリコン窒化膜(SiN膜)や酸化膜を裏面パッシベーション膜として採用する場合には、太陽電池基板の裏面との導通のために絶縁膜である裏面パッシベーション膜の一部に穴あけを行う工程が別途必要である。この穴あけを行う工程は、量産化の障害となっている。
However, when a silicon nitride film (SiN film) or an oxide film is used as the back surface passivation film, there is a step of drilling a part of the back surface passivation film, which is an insulating film, for conduction with the back surface of the solar cell substrate. It is necessary separately. This process of drilling is an obstacle to mass production.
初期の段階では、フォトリソグラフィー技術を用いた高価で手間のかかる工程により、絶縁膜の穴あけが行われていた。一方、近年は、工程数が少ない、レーザによる直接穴あけを行う技術も確立されつつある。しかし、レーザによる穴あけは、処理能力が低く、量産には適しているとは言い難い。
In the initial stage, the insulating film was drilled by an expensive and laborious process using photolithography technology. On the other hand, in recent years, a technique for directly drilling with a laser having a small number of processes has been established. However, laser drilling has a low processing capability and is not suitable for mass production.
本発明は、上記に鑑みてなされたものであって、裏面パッシベーション膜を備えて光電変換効率に優れた太陽電池セルを簡便な工程で生産性良く製造可能な太陽電池セルの製造方法を得ることを目的とする。
This invention is made in view of the above, Comprising: Obtaining the manufacturing method of the photovoltaic cell which can manufacture the photovoltaic cell which was provided with the back surface passivation film and was excellent in photoelectric conversion efficiency with a simple process with sufficient productivity. With the goal.
上述した課題を解決し、目的を達成するために、本発明にかかる太陽電池セルの製造方法は、第1導電型の半導体基板における受光面側となる一面側に第2導電型の不純物拡散層を形成する第1工程と、前記半導体基板の他面側にマスクパターンを形成する第2工程と、前記マスクパターンの厚みよりも薄い膜厚のパッシベーション膜を前記半導体基板の他面側に形成して、前記マスクパターンの側面の一部が露出するように前記マスクパターンを前記パッシベーション膜に埋設する第3工程と、前記パッシベーション膜を除去することにより前記パッシベーション膜を膜厚方向に貫通して前記半導体基板の他面側を露出させる開口部を形成する第4工程と、前記半導体基板の他面側に電気的に接続する裏面側電極を前記開口部内に埋設する第5工程と、前記不純物拡散層に電気的に接続する受光面側電極を前記半導体基板の一面側に形成する第6工程と、を含むことを特徴とする。
In order to solve the above-described problems and achieve the object, a method for manufacturing a solar battery cell according to the present invention includes a second conductivity type impurity diffusion layer on one surface side that is a light receiving surface side in a first conductivity type semiconductor substrate. A second step of forming a mask pattern on the other side of the semiconductor substrate, and a passivation film having a thickness smaller than the thickness of the mask pattern is formed on the other side of the semiconductor substrate. A third step of burying the mask pattern in the passivation film so that a part of the side surface of the mask pattern is exposed, and removing the passivation film to penetrate the passivation film in the film thickness direction. A fourth step of forming an opening that exposes the other surface of the semiconductor substrate; and a back-side electrode that is electrically connected to the other surface of the semiconductor substrate is embedded in the opening. A fifth step, characterized in that it comprises a sixth step of the light-receiving surface side electrode is formed on one surface side of the semiconductor substrate electrically connected to the impurity diffusion layer.
本発明によれば、裏面パッシベーション膜を備えて光電変換効率に優れた太陽電池セルを簡便な工程で生産性良く製造できる、という効果を奏する。
According to the present invention, there is an effect that a solar battery cell having a back surface passivation film and excellent in photoelectric conversion efficiency can be manufactured with high productivity by a simple process.
以下に、本発明にかかる太陽電池セルの製造方法の実施の形態を図面に基づいて詳細に説明する。なお、本発明は以下の記述に限定されるものではなく、本発明の要旨を逸脱しない範囲において適宜変更可能である。また、以下に示す図面においては、理解の容易のため、各部材の縮尺が実際とは異なる場合がある。各図面間においても同様である。また、平面図であっても、図面を見易くするためにハッチングを付す場合がある。
Hereinafter, embodiments of a method for manufacturing a solar battery cell according to the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably. In the drawings shown below, the scale of each member may be different from the actual scale for easy understanding. The same applies between the drawings. Further, even a plan view may be hatched to make the drawing easy to see.
実施の形態.
図1~図5は、本発明の実施の形態にかかる太陽電池セル1の構成を模式的に示す図である。図1は、受光面側から見た太陽電池セル1の上面図である。図2は、受光面と反対側(裏面)から見た太陽電池セル1の下面図である。図3は、太陽電池セル1の要部断面図であり、図1のA-A方向における要部断面図である。図4は、太陽電池セル1の要部断面図であり、図1のB-B方向における要部断面図である。図5は、太陽電池セル1の裏面側に設けられた裏面パッシベーション膜に形成された櫛型の開口部の形状を示す太陽電池セル1の下面図である。 Embodiment.
1 to 5 are diagrams schematically showing a configuration of asolar battery cell 1 according to an embodiment of the present invention. FIG. 1 is a top view of the solar battery cell 1 viewed from the light receiving surface side. FIG. 2 is a bottom view of the solar battery cell 1 viewed from the side opposite to the light receiving surface (back surface). FIG. 3 is a cross-sectional view of the main part of the solar battery cell 1, and is a cross-sectional view of the main part in the AA direction of FIG. 4 is a cross-sectional view of main parts of the solar battery cell 1, and is a cross-sectional view of main parts in the BB direction of FIG. FIG. 5 is a bottom view of the solar cell 1 showing the shape of the comb-shaped opening formed in the back surface passivation film provided on the back surface side of the solar cell 1.
図1~図5は、本発明の実施の形態にかかる太陽電池セル1の構成を模式的に示す図である。図1は、受光面側から見た太陽電池セル1の上面図である。図2は、受光面と反対側(裏面)から見た太陽電池セル1の下面図である。図3は、太陽電池セル1の要部断面図であり、図1のA-A方向における要部断面図である。図4は、太陽電池セル1の要部断面図であり、図1のB-B方向における要部断面図である。図5は、太陽電池セル1の裏面側に設けられた裏面パッシベーション膜に形成された櫛型の開口部の形状を示す太陽電池セル1の下面図である。 Embodiment.
1 to 5 are diagrams schematically showing a configuration of a
本実施の形態にかかる太陽電池セル1においては、p型単結晶シリコンからなる半導体基板2の受光面側にリン拡散によってn型不純物拡散層3が形成されてpn接合を有する半導体基板11が形成されているとともに、n型不純物拡散層3上にシリコン窒化膜(SiN膜)よりなる反射防止膜4が形成されている。なお、半導体基板2としてはp型単結晶のシリコン基板に限定されず、n型の単結晶シリコン基板を用いてもよい。
In solar cell 1 according to the present embodiment, n-type impurity diffusion layer 3 is formed by phosphorous diffusion on the light-receiving surface side of semiconductor substrate 2 made of p-type single crystal silicon, and semiconductor substrate 11 having a pn junction is formed. In addition, an antireflection film 4 made of a silicon nitride film (SiN film) is formed on the n-type impurity diffusion layer 3. The semiconductor substrate 2 is not limited to a p-type single crystal silicon substrate, and an n-type single crystal silicon substrate may be used.
また、図3に示されるように、半導体基板11の受光面側(n型不純物拡散層3)および裏面側の表面には、微小凹凸2aにより構成されるテクスチヤー構造が形成されている。テクスチヤー構造は、受光面において外部からの光を吸収する面積を増加し、受光面における光反射率を抑え、光を閉じ込める構造となっている。
Further, as shown in FIG. 3, a texture structure constituted by minute irregularities 2a is formed on the light receiving surface side (n-type impurity diffusion layer 3) and the back surface side of the semiconductor substrate 11. The texture structure increases the area that absorbs light from the outside on the light receiving surface, suppresses the light reflectance on the light receiving surface, and confines light.
反射防止膜4は、シリコン窒化膜(SiN膜)、シリコン酸化膜(SiO2膜)や酸化チタン膜(TiO2膜)などの反射防止を目的とした絶縁膜からなる。また、半導体基板11の受光面側には、長尺細長の表銀グリッド電極5が複数並べて設けられ、この表銀グリッド電極5と導通する表銀バス電極6が該表銀グリッド電極5と略直交するように設けられており、それぞれ底面部において、n型不純物拡散層3に電気的に接続している。表銀グリッド電極5および表銀バス電極6は銀材料により構成されている。
The antireflection film 4 is made of an insulating film for the purpose of preventing reflection, such as a silicon nitride film (SiN film), a silicon oxide film (SiO 2 film), or a titanium oxide film (TiO 2 film). In addition, a plurality of long and narrow surface silver grid electrodes 5 are arranged side by side on the light receiving surface side of the semiconductor substrate 11, and a surface silver bus electrode 6 electrically connected to the surface silver grid electrode 5 is substantially the same as the surface silver grid electrode 5. They are provided so as to be orthogonal to each other, and are electrically connected to the n-type impurity diffusion layer 3 at the bottom portions. The front silver grid electrode 5 and the front silver bus electrode 6 are made of a silver material.
表銀グリッド電極5は、例えば100μm~200μm程度の幅を有するとともに2mm程度の間隔で略平行に配置され、半導体基板11の内部で発電した電気を集電する。また、表銀バス電極6は、例えば1mm~3mm程度の幅を有するとともに太陽電池セル1枚当たりに2本~4本配置され、表銀グリッド電極5で集電した電気を外部に取り出す。そして、表銀グリッド電極5と表銀バス電極6とにより第1電極である受光面側電極12が構成される。受光面側電極12は、半導体基板11に入射する太陽光を遮ってしまうため、可能なかぎり面積を小さくすることが発電効率向上の観点では望ましく、図1に示すような櫛型の表銀グリッド電極5とバー状の表銀バス電極6として配置するのが一般的である。
The front silver grid electrode 5 has a width of about 100 μm to 200 μm, for example, and is arranged substantially in parallel at intervals of about 2 mm, and collects electricity generated inside the semiconductor substrate 11. Further, the front silver bus electrodes 6 have a width of, for example, about 1 mm to 3 mm and are arranged in a number of 2 to 4 per solar battery cell, and the electricity collected by the front silver grid electrode 5 is taken out to the outside. The front silver grid electrode 5 and the front silver bus electrode 6 constitute a light receiving surface side electrode 12 as a first electrode. Since the light receiving surface side electrode 12 blocks sunlight incident on the semiconductor substrate 11, it is desirable to reduce the area as much as possible from the viewpoint of improving the power generation efficiency, and a comb-shaped surface silver grid as shown in FIG. Generally, the electrodes 5 and the bar-shaped surface silver bus electrodes 6 are arranged.
シリコン太陽電池セルの受光面側電極の電極材料には、通常、銀ペーストが用いられ、例えば、鉛ボロンガラスが添加されている。このガラスはフリット状のもので、例えば、鉛(Pb)5~30wt%、ボロン(B)5~10wt%、シリコン(Si)5~l5wt%、酸素(O)30~60wt%の組成から成り、さらに、亜鉛(Zn)やカドミウム(Cd)なども数wt%程度混合される場合もある。このような鉛ボロンガラスは、数百℃(例えば、800℃)の加熱で溶解し、その際にシリコンを侵食する性質を有している。また一般に、結晶系シリコン太陽電池セルの製造方法においては、このガラスフリットの特性を利用して、シリコン基板と銀ペーストとの電気的接触を得る方法が用いられている。
For the electrode material of the light receiving surface side electrode of the silicon solar battery cell, a silver paste is usually used, for example, lead boron glass is added. This glass has a frit shape and is composed of, for example, lead (Pb) 5 to 30 wt%, boron (B) 5 to 10 wt%, silicon (Si) 5 to 15 wt%, and oxygen (O) 30 to 60 wt%. Furthermore, zinc (Zn), cadmium (Cd), etc. may be mixed by several wt%. Such lead boron glass has a property of melting by heating at several hundred degrees C. (for example, 800.degree. C.) and eroding silicon at that time. In general, in a method for manufacturing a crystalline silicon solar battery cell, a method of obtaining electrical contact between a silicon substrate and a silver paste by using the characteristics of the glass frit is used.
一方、半導体基板11の裏面(受光面と反対側の面)には、全体にわたってシリコン窒化膜(SiN膜)からなる裏面絶縁膜である裏面パッシベーション膜7が形成されている。裏面パッシベーション膜7には、図5に示されるように図中の縦方向および横方向に延在する櫛型形状の開口部7aが設けられている。なお、図5においては、裏面パッシベーション膜7における開口部7aの形状に注目して示しており、一部部材の記載を省略している。
On the other hand, a back surface passivation film 7 which is a back surface insulating film made of a silicon nitride film (SiN film) is formed on the entire back surface (surface opposite to the light receiving surface) of the semiconductor substrate 11. As shown in FIG. 5, the back surface passivation film 7 is provided with comb-shaped openings 7a extending in the vertical and horizontal directions in the figure. In FIG. 5, attention is paid to the shape of the opening 7 a in the back surface passivation film 7, and the description of some members is omitted.
開口部7a内には、銀材料を含む裏銀電極8とアルミニウム材料を含む裏アルミニウム電極9とが埋設されている。櫛型形状の開口部7aにおける縦方向に延在するライン状領域と横方向に延在するライン状領域との交点部分は、正方形状に形成されている。この交点部分は、表銀バス電極6と略同一方向に配列して設けられている。開口部7aにおけるこの正方形状の交点部分には、一部が裏面パッシベーション膜7の表面から突出した状態で裏銀電極8が埋設されている。
In the opening 7a, a back silver electrode 8 including a silver material and a back aluminum electrode 9 including an aluminum material are embedded. The intersection portion between the line-shaped region extending in the vertical direction and the line-shaped region extending in the horizontal direction in the comb-shaped opening 7a is formed in a square shape. The intersections are arranged in substantially the same direction as the front silver bus electrode 6. A back silver electrode 8 is embedded in this square intersection portion of the opening 7 a in a state in which a part protrudes from the surface of the back surface passivation film 7.
開口部7aにおいて裏銀電極8が埋設されていない領域には、裏アルミニウム電極9が埋設されている。裏アルミニウム電極9は、半導体基板11の裏面からの集電が効率良くできるように半導体基板11の受光面側の電極と同様に、開口部7aにおいて櫛型形状に埋設されている。さらに、裏アルミニウム電極9は、半導体基板11の裏面において裏銀電極8を囲んで裏面パッシベーション膜7上にも形成されており、裏銀電極8を囲んで半導体基板11の裏面のほぼ全面に形成されている。そして、裏銀電極8と裏アルミニウム電極9とにより、第2電極である裏面側電極13が構成されている。
A back aluminum electrode 9 is embedded in a region where the back silver electrode 8 is not embedded in the opening 7a. The back aluminum electrode 9 is embedded in a comb shape in the opening 7a, like the electrode on the light receiving surface side of the semiconductor substrate 11, so that current collection from the back surface of the semiconductor substrate 11 can be efficiently performed. Further, the back aluminum electrode 9 is also formed on the back surface passivation film 7 so as to surround the back silver electrode 8 on the back surface of the semiconductor substrate 11, and is formed on almost the entire back surface of the semiconductor substrate 11 surrounding the back silver electrode 8. Has been. The back silver electrode 8 and the back aluminum electrode 9 constitute a back electrode 13 that is a second electrode.
また、半導体基板11の裏面(受光面と反対側の面)側の表層部における裏アルミニウム電極9の下部領域には、高濃度不純物を含んだp+層(BSF(Back Surface Field)層)10が形成されている。p+層10は、BSF効果を得るために設けられ、p型層(半導体基板2)中の電子が消滅しないようにバンド構造の電界でp型層(半導体基板2)電子濃度を高めるようにする。
Further, a p + layer (BSF (Back Surface Field) layer) 10 containing a high concentration impurity is formed in the lower region of the back aluminum electrode 9 in the surface layer portion on the back surface (surface opposite to the light receiving surface) of the semiconductor substrate 11. Is formed. The p + layer 10 is provided to obtain the BSF effect, and the electron concentration of the p-type layer (semiconductor substrate 2) is increased by an electric field having a band structure so that electrons in the p-type layer (semiconductor substrate 2) do not disappear. .
このように構成された太陽電池セル1では、太陽光が太陽電池セル1の受光面側から半導体基板11のpn接合面(半導体基板2と、n型不純物拡散層3との接合面)に照射されると、ホールと電子が生成する。pn接合部の電界によって、生成した電子は、n型不純物拡散層3に向かって移動し、ホールはp+層10に向かって移動する。これにより、n型不純物拡散層3に電子が過剰となり、p+層10にホールが過剰となる結果、光起電力が発生する。この光起電力はpn接合を順方向にバイアスする向きに生じ、n型不純物拡散層3に接続した受光面側電極12がマイナス極となり、p+層10に接続した裏アルミニウム電極9がプラス極となって、図示しない外部回路に電流が流れる。なお、裏銀電極8が存在する理由は、複数の太陽電池セル1を接続してモジュールを作製する際に、太陽電池セル1同士をタブ接続するために必要であるからである。
In the solar cell 1 configured as described above, sunlight is irradiated from the light receiving surface side of the solar cell 1 to the pn junction surface of the semiconductor substrate 11 (the junction surface between the semiconductor substrate 2 and the n-type impurity diffusion layer 3). As a result, holes and electrons are generated. Due to the electric field of the pn junction, the generated electrons move toward the n-type impurity diffusion layer 3 and the holes move toward the p + layer 10. As a result, electrons are excessive in the n-type impurity diffusion layer 3 and holes are excessive in the p + layer 10. As a result, a photovoltaic force is generated. This photovoltaic force is generated in the direction of biasing the pn junction in the forward direction, the light receiving surface side electrode 12 connected to the n-type impurity diffusion layer 3 becomes a negative pole, and the back aluminum electrode 9 connected to the p + layer 10 becomes a positive pole. Thus, a current flows through an external circuit (not shown). The reason for the presence of the back silver electrode 8 is that it is necessary to tab-connect the solar cells 1 when connecting a plurality of solar cells 1 to produce a module.
以下、本実施の形態にかかる太陽電池セル1の製造方法について図面に沿って説明する。図6は、本発明の実施の形態にかかる太陽電池セル1の製造工程を説明するためのフローチャートである。図7~図16は、本発明の実施の形態にかかる太陽電池セル1の製造工程の一例を模式的に示す工程図であり、図3に対応する要部断面図である。図17~図22は、本発明の実施の形態にかかる太陽電池セル1の製造工程のうち、裏面側電極13の製造工程を模式的に示す工程図である。図17~図22における(a)は、半導体基板11を受光面と反対側(裏面)から見た下面図である。図17~図19における(b)は、各図の(a)のC-C方向における要部断面図である。図20~図22における(b)は、各図の(a)のD-D方向における要部断面図である。
Hereinafter, the manufacturing method of the photovoltaic cell 1 according to the present embodiment will be described with reference to the drawings. FIG. 6 is a flowchart for explaining a manufacturing process of the solar battery cell 1 according to the embodiment of the present invention. 7 to 16 are process diagrams schematically showing an example of the manufacturing process of the solar battery cell 1 according to the embodiment of the present invention, and are sectional views corresponding to FIG. 17 to 22 are process diagrams schematically showing a manufacturing process of the back surface side electrode 13 among the manufacturing processes of the solar battery cell 1 according to the embodiment of the present invention. FIG. 17A to FIG. 22A are bottom views of the semiconductor substrate 11 as viewed from the side opposite to the light receiving surface (back surface). (B) in FIGS. 17 to 19 is a cross-sectional view of the main part in the CC direction of (a) in each figure. 20B to 22B are cross-sectional views of the main part in the DD direction of FIG.
まず、半導体基板2として例えば数百μm厚のp型単結晶シリコン基板を用意する(図7)。p型単結晶シリコン基板は、溶融したシリコンを冷却固化してできたインゴットをワイヤーソーでスライスして製造するため、表面にスライス時のダメージが残っている。そこで、p型単結晶シリコン基板を酸または加熱したアルカリ溶液中、例えば水酸化ナトリウム水溶液に浸漬して表面をエッチングすることにより、シリコン基板の切り出し時に発生してp型単結晶シリコン基板の表面近くに存在するダメージ領域を取り除く。例えば数wt%~20wt%の水酸化ナトリウムや水酸化カリウムのようなアルカリ溶液で10μm~20μm厚だけ表面を除去する。なお、ここでは、半導体基板2に用いるp型シリコン基板として、比抵抗が0.1Ω・cm~5Ω・cmであり、(100)面方位のp型単結晶シリコン基板を例に説明する。
First, for example, a p-type single crystal silicon substrate having a thickness of several hundred μm is prepared as the semiconductor substrate 2 (FIG. 7). Since the p-type single crystal silicon substrate is manufactured by slicing an ingot formed by cooling and solidifying molten silicon with a wire saw, damage at the time of slicing remains on the surface. Therefore, the p-type single crystal silicon substrate is etched near the surface of the p-type single crystal silicon substrate by etching the surface by immersing the surface in an acid or heated alkaline solution, for example, an aqueous sodium hydroxide solution. Remove the damage area that exists in the. For example, the surface is removed by a thickness of 10 μm to 20 μm with an alkali solution such as sodium hydroxide or potassium hydroxide of several wt% to 20 wt%. Here, as a p-type silicon substrate used for the semiconductor substrate 2, a p-type single crystal silicon substrate having a specific resistance of 0.1Ω · cm to 5Ω · cm and having a (100) plane orientation will be described as an example.
ダメージ除去に続いて、同様のアルカリ低濃度液、数wt%の水酸化ナトリウムや水酸化カリウムのようなアルカリ低濃度液にIPA(イソプロピルアルコール)等の異方性エッチングを促進する添加剤を添加した溶液で異方性エッチングを行う。この異方性エッチングにより、シリコン(111)面が出るようにp型単結晶シリコン基板の受光面側および裏面側の表面に略4角錐形状の微小凹凸2aが形成されてテクスチヤー構造が形成される(ステップS10、図8)。すなわち、p型単結晶シリコン基板の表裏面に対して、アルカリ系溶液を用いたウエットエッチング(アルカリテクスチャー法)によるテクスチャー構造の形成を行う。
Following the removal of damage, an additive that promotes anisotropic etching such as IPA (isopropyl alcohol) is added to the same alkali low concentration solution, such as several wt% sodium hydroxide or potassium hydroxide. Anisotropic etching is performed with the solution. By this anisotropic etching, a micro-concave pattern 2a having a substantially quadrangular pyramid shape is formed on the light-receiving surface side and back surface side of the p-type single crystal silicon substrate so that the silicon (111) surface is exposed, thereby forming a texture structure. (Step S10, FIG. 8). That is, the texture structure is formed on the front and back surfaces of the p-type single crystal silicon substrate by wet etching (alkali texture method) using an alkaline solution.
つぎに、半導体基板2にpn接合を形成する(ステップS20、図9)。すなわち、リン(P)等のV族元素を半導体基板2に拡散等させて数百nm厚のn型不純物拡散層3を形成する。ここでは、表面にテクスチャー構造を形成したp型単結晶シリコン基板に対して、熱拡散によりオキシ塩化リン(POCl3)を拡散させてpn接合を形成する。
Next, a pn junction is formed in the semiconductor substrate 2 (step S20, FIG. 9). That is, a group V element such as phosphorus (P) is diffused into the semiconductor substrate 2 to form the n-type impurity diffusion layer 3 having a thickness of several hundred nm. Here, a pn junction is formed by diffusing phosphorus oxychloride (POCl 3 ) by thermal diffusion with respect to a p-type single crystal silicon substrate having a texture structure on the surface.
この拡散工程では、p型単結晶シリコン基板を例えばオキシ塩化リン(POCl3)ガス、窒素ガス、酸素ガスの混合ガス雰囲気中で気相拡散法により例えば800℃~900℃の高温で数十分間、熱拡散させて、p型単結晶シリコン基板の表面層にリン(P)が拡散したn型不純物拡散層3を一様に形成する。半導体基板2の表面に形成されたn型不純物拡散層3のシート抵抗の範囲が30Ω/□~80Ω/□程度である場合に良好な太陽電池の電気特性が得られる。
In this diffusion step, the p-type single crystal silicon substrate is several tens of minutes at a high temperature of, for example, 800 ° C. to 900 ° C. by a vapor phase diffusion method in a mixed gas atmosphere of, for example, phosphorus oxychloride (POCl 3 ) gas, nitrogen gas, and oxygen gas. The n-type impurity diffusion layer 3 in which phosphorus (P) is diffused is uniformly formed in the surface layer of the p-type single crystal silicon substrate by thermal diffusion. Good electrical characteristics of the solar cell can be obtained when the sheet resistance range of the n-type impurity diffusion layer 3 formed on the surface of the semiconductor substrate 2 is about 30Ω / □ to 80Ω / □.
ここで、n型不純物拡散層3は半導体基板2の全面に形成される。このため、半導体基板2の表面(受光面)と裏面とは電気的に接続された状態である。そこで、この電気的接続を遮断するために、たとえばドライエッチングにより半導体基板2の端面領域をエッチングする(図10)。また、n型不純物拡散層3の形成直後の表面には拡散処理中に表面に堆積したガラス質(燐珪酸ガラス、PSG:Phospho-Silicate Glass)層が形成されている。このため、半導体基板2をフッ酸水溶液等に浸漬してPSG層をエッチング除去する。
Here, the n-type impurity diffusion layer 3 is formed on the entire surface of the semiconductor substrate 2. For this reason, the front surface (light receiving surface) and the back surface of the semiconductor substrate 2 are in an electrically connected state. Therefore, in order to cut off this electrical connection, the end face region of the semiconductor substrate 2 is etched by dry etching, for example (FIG. 10). Further, a glassy (phosphosilicate glass, PSG: Phospho-Silicate Glass) layer deposited on the surface during the diffusion process is formed on the surface immediately after the formation of the n-type impurity diffusion layer 3. For this reason, the semiconductor substrate 2 is immersed in a hydrofluoric acid aqueous solution or the like to remove the PSG layer by etching.
つぎに、光電変換効率改善のために、半導体基板2の受光面側の一面に反射防止膜4としてシリコン酸化膜、シリコン窒化膜、酸化チタン膜などの絶縁膜を一様な厚みで形成する(ステップS30、図10)。反射防止膜4の膜厚および屈折率は、光反射を最も抑制する値に設定する。反射防止膜4の形成は、例えばプラズマCVD法を使用し、シラン(SiH4)ガスとアンモニア(NH3)ガスの混合ガスを原材料に用いて、300℃以上、減圧下の条件で反射防止膜4として窒化シリコン膜を成膜形成する。屈折率は例えば2.0~2.2程度であり、最適な反射防止膜厚は例えば70nm~90nmである。
Next, in order to improve the photoelectric conversion efficiency, an insulating film such as a silicon oxide film, a silicon nitride film, or a titanium oxide film is formed as a reflection preventing film 4 with a uniform thickness on one surface of the light receiving surface side of the semiconductor substrate 2 (see FIG. Step S30, FIG. 10). The film thickness and refractive index of the antireflection film 4 are set to values that most suppress light reflection. The antireflection film 4 is formed by using, for example, a plasma CVD method, using a mixed gas of silane (SiH 4 ) gas and ammonia (NH 3 ) gas as a raw material, and at 300 ° C. or higher and under reduced pressure. 4, a silicon nitride film is formed. The refractive index is, for example, about 2.0 to 2.2, and the optimum antireflection film thickness is, for example, 70 nm to 90 nm.
なお、反射防止膜4として、屈折率の異なる2層以上の膜を積層してもよい。また、反射防止膜4の形成方法は、プラズマCVD法の他に蒸着法、熱CVD法などを用いてもよい。なお、このようにして形成される反射防止膜4は絶縁体であることに注意すべきであり、受光面側電極12をこの上に単に形成しただけでは、太陽電池セルとして作用しない。
In addition, as the antireflection film 4, two or more films having different refractive indexes may be laminated. In addition to the plasma CVD method, the antireflection film 4 may be formed by vapor deposition, thermal CVD, or the like. It should be noted that the antireflection film 4 formed in this manner is an insulator, and simply forming the light receiving surface side electrode 12 on the surface does not act as a solar battery cell.
つぎに、リン(P)の拡散により半導体基板2の裏面に形成されたn型不純物拡散層3を除去する。これにより、第1導電型層であるp型単結晶シリコンからなる半導体基板2と、該半導体基板2の受光面側に形成された第2導電型層であるn型不純物拡散層3と、によりpn接合が構成された半導体基板11が得られる(図11)。なお、半導体基板2の片面のみにn型不純物拡散層3を形成する場合には、上述した半導体基板2の端面領域のエッチングおよび半導体基板2の裏面に形成されたn型不純物拡散層3の除去は不要である。
Next, the n-type impurity diffusion layer 3 formed on the back surface of the semiconductor substrate 2 is removed by diffusion of phosphorus (P). Thus, the semiconductor substrate 2 made of p-type single crystal silicon which is the first conductivity type layer, and the n-type impurity diffusion layer 3 which is the second conductivity type layer formed on the light receiving surface side of the semiconductor substrate 2, A semiconductor substrate 11 having a pn junction is obtained (FIG. 11). In the case where the n-type impurity diffusion layer 3 is formed only on one surface of the semiconductor substrate 2, the above-described etching of the end surface region of the semiconductor substrate 2 and the removal of the n-type impurity diffusion layer 3 formed on the back surface of the semiconductor substrate 2 are performed. Is unnecessary.
つぎに、半導体基板11の裏面側に、マスクパターン21としてペースト状の熱硬化型樹脂を、たとえばスクリーン印刷によりパターン印刷して塗布する。マスクパターン21は、後述するように半導体基板11の裏面側に裏面パッシベーション膜7を形成する際のマスクとして機能する。熱硬化型樹脂には、裏面パッシベーション膜7の形成時の温度(成膜温度)に耐性を有する樹脂が用いられる。マスクパターン21の形状については、所望の電極パターンに基づき作成する。本実施の形態では、マスクパターン21を櫛形形状に形成し、櫛形形状における縦方向に延在するライン状領域と横方向に延在するライン状領域との交点部分は正方形状とする。
Next, a paste-like thermosetting resin is applied as a mask pattern 21 to the back side of the semiconductor substrate 11 by pattern printing, for example, by screen printing. The mask pattern 21 functions as a mask when forming the back surface passivation film 7 on the back surface side of the semiconductor substrate 11 as described later. As the thermosetting resin, a resin having resistance to the temperature (deposition temperature) at the time of forming the back surface passivation film 7 is used. The shape of the mask pattern 21 is created based on a desired electrode pattern. In the present embodiment, the mask pattern 21 is formed in a comb shape, and the intersection of the line-shaped region extending in the vertical direction and the line-shaped region extending in the horizontal direction in the comb-shaped shape is a square shape.
その後、半導体基板11をベーク炉に導入して加熱処理することにより、熱硬化型樹脂を固化させる(ステップS40、図12、図17)。この熱硬化型樹脂の固化工程は、後述する裏面パッシベーション膜7の形成に用いる装置がマルチチャンバーシステムを備える装置である場合には、裏面パッシベーション膜7を成膜する成膜チャンバーの前段のチャンバー内に半導体基板11を保持し、該チャンバー内の温度を熱硬化型樹脂の固化温度以上とする。これにより、熱硬化型樹脂を固化する工程と、裏面パッシベーション膜7の成膜工程との連続処理が可能であり、工程の簡略化が可能である。
Then, the thermosetting resin is solidified by introducing the semiconductor substrate 11 into a baking furnace and performing heat treatment (step S40, FIG. 12, FIG. 17). This thermosetting resin solidification step is performed in the chamber preceding the film forming chamber for forming the back surface passivation film 7 when the apparatus used for forming the back surface passivation film 7 to be described later is an apparatus having a multi-chamber system. The semiconductor substrate 11 is held, and the temperature in the chamber is set to be equal to or higher than the solidification temperature of the thermosetting resin. Thereby, the continuous process of the process of solidifying a thermosetting resin and the film-forming process of the back surface passivation film 7 is possible, and the process can be simplified.
また、裏面パッシベーション膜7を成膜する成膜チャンバー内に半導体基板11を保持し、該チャンバー内の温度を熱硬化型樹脂の固化温度以上としてもよい。その後、該成膜チャンバーにおいてそのまま裏面パッシベーション膜7を成膜する。これにより、熱硬化型樹脂を固化する工程と、裏面パッシベーション膜7の成膜工程との連続処理が可能であり、工程の簡略化が可能である。
Alternatively, the semiconductor substrate 11 may be held in a film formation chamber where the back surface passivation film 7 is formed, and the temperature in the chamber may be equal to or higher than the solidification temperature of the thermosetting resin. Thereafter, the back surface passivation film 7 is formed as it is in the film forming chamber. Thereby, the continuous process of the process of solidifying a thermosetting resin and the film-forming process of the back surface passivation film 7 is possible, and the process can be simplified.
ここではマスクパターン21を形成するための印刷ペーストとして熱硬化型樹脂を使用する場合について説明したが、後の裏面パッシベーション膜7の成膜工程での成膜温度に耐性があり、更に後の工程で容易に焼却またドライエッチングにより除去できれば、これに限定されない。たとえば紫外線硬化型樹脂のように熱硬化型樹脂とは異なる固化特性を有する印刷ペーストを使用することも可能である。マスクパターンを形成する印刷ペーストとして紫外線硬化型樹脂を用いる場合には、半導体基板11の裏面側に紫外線硬化型樹脂をパターン印刷した後に、該紫外線硬化型樹脂に紫外線を照射して固化させる。なお、紫外線硬化型樹脂についても、裏面パッシベーション膜7の形成時の温度(成膜温度)に耐性を有する樹脂が用いられる。
Here, the case where a thermosetting resin is used as a printing paste for forming the mask pattern 21 has been described, but the film has a resistance to the film formation temperature in the subsequent film formation process of the back surface passivation film 7, and the subsequent process. If it can be easily removed by incineration or dry etching, it is not limited to this. For example, it is also possible to use a printing paste having a solidification characteristic different from that of the thermosetting resin, such as an ultraviolet curable resin. When an ultraviolet curable resin is used as a printing paste for forming a mask pattern, after the ultraviolet curable resin is pattern printed on the back side of the semiconductor substrate 11, the ultraviolet curable resin is irradiated with ultraviolet rays to be solidified. As for the ultraviolet curable resin, a resin having resistance to the temperature (film formation temperature) at the time of forming the back surface passivation film 7 is used.
つぎに、マスクパターン21が形成された半導体基板11の裏面側の全面に、シリコン窒化膜(SiN膜)からなる裏面パッシベーション膜7を形成する(ステップS50、図13、図18)。すなわち、熱硬化型樹脂によりマスクパターン21が形成された半導体基板11の裏面側に、たとえばプラズマCVD法により屈折率1.9~2.2、厚さ60nm~300nmのシリコン窒化膜(SiN膜)からなる裏面パッシベーション膜7を成膜する。ここで、裏面パッシベーション膜7は、マスクパターン21の厚みよりも薄い膜厚で、マスクパターン21の少なくとも上部の側面の一部が露出するようにマスクパターン21を埋設して成膜される。なお、図18(a)におけるマスクパターン21の部分については裏面パッシベーション膜7を透過して示している。
Next, a back surface passivation film 7 made of a silicon nitride film (SiN film) is formed on the entire back surface side of the semiconductor substrate 11 on which the mask pattern 21 is formed (step S50, FIG. 13, FIG. 18). That is, a silicon nitride film (SiN film) having a refractive index of 1.9 to 2.2 and a thickness of 60 nm to 300 nm is formed on the back side of the semiconductor substrate 11 on which the mask pattern 21 is formed by thermosetting resin, for example, by plasma CVD. A back surface passivation film 7 made of is formed. Here, the back surface passivation film 7 is formed by embedding the mask pattern 21 with a film thickness smaller than the thickness of the mask pattern 21 so that at least a part of the upper side surface of the mask pattern 21 is exposed. Note that the mask pattern 21 in FIG. 18A is shown through the back surface passivation film 7.
このような裏面パッシベーション膜7を形成することにより、半導体基板11の裏面におけるキャリアの再結合速度を抑制することができ、高出力化のために十分な裏面界面を実現することができる。この工程で注意すべき点は、ステップカバレッジの良い条件で裏面パッシベーション膜7の成膜を行うと、熱硬化型樹脂の側面にもシリコン窒化膜(SiN膜)が成膜されてしまい、つぎの工程で熱硬化型樹脂が上手く除去できなくなる可能性があるということである。すなわち、熱硬化型樹脂の表面の全面が裏面パッシベーション膜7で覆われると、熱硬化型樹脂の表面に酸素が供給されなくなり、熱硬化型樹脂が焼却されにくくなる。したがって、裏面パッシベーション膜7の成膜は、ステップカバレッジの悪い条件で、マスクパターン21の少なくとも上部の側面の一部が露出するように行われる。
By forming such a back surface passivation film 7, the recombination speed of carriers on the back surface of the semiconductor substrate 11 can be suppressed, and a sufficient back surface interface can be realized for high output. The point to be noted in this step is that when the back surface passivation film 7 is formed under good step coverage conditions, a silicon nitride film (SiN film) is also formed on the side surface of the thermosetting resin. This means that the thermosetting resin may not be successfully removed in the process. That is, when the entire surface of the thermosetting resin is covered with the back surface passivation film 7, oxygen is not supplied to the surface of the thermosetting resin, and the thermosetting resin is hardly burned. Therefore, the back surface passivation film 7 is formed such that at least a part of the upper side surface of the mask pattern 21 is exposed under a condition with poor step coverage.
裏面パッシベーション膜7の成膜法としてプラズマCVD法を用いる場合には、常圧に近い条件(常圧プラズマCVD法)を選択することが好ましい。裏面パッシベーション膜7の成膜法としてプラズマCVD法以外の成膜法を用いる場合には、スパッタリング法を選択することが好ましい。
When the plasma CVD method is used as the film formation method for the back surface passivation film 7, it is preferable to select conditions close to normal pressure (normal pressure plasma CVD method). When a film forming method other than the plasma CVD method is used as the film forming method for the back surface passivation film 7, it is preferable to select the sputtering method.
つぎに、同一のチャンバー内、またはマルチチャンバーシステムであれば別のチャンバー内において、マスクパターン21の熱硬化型樹脂を加熱処理により焼き飛ばして除去(焼却除去)する。加熱処理における加熱温度は、熱硬化型樹脂が消失し、且つ裏面パッシベーション膜7が耐性を有する条件とされる。これにより、半導体基板2の裏面側においてマスクパターン21が形成されていた領域に、裏面パッシベーション膜7を膜厚方向に貫通して半導体基板2の裏面側を露出させる櫛形形状の開口部7aが形成される(ステップS60、図14、図19)。開口部7aは、マスクパターン21と同じ櫛形形状に形成される。ここで、マスクパターン21の少なくとも上部の側面の一部が裏面パッシベーション膜7から露出しているため、熱硬化型樹脂の表面に確実に酸素が供給され、熱硬化型樹脂が確実に焼却される。また、マスクパターン21が除去されることにより、該マスクパターン21上の裏面パッシベーション膜7も除去される。
Next, in the same chamber or in another chamber in the case of a multi-chamber system, the thermosetting resin of the mask pattern 21 is burned off by heat treatment (incineration removal). The heating temperature in the heat treatment is such that the thermosetting resin disappears and the back surface passivation film 7 has resistance. Thereby, in the region where the mask pattern 21 is formed on the back surface side of the semiconductor substrate 2, a comb-shaped opening 7 a that penetrates the back surface passivation film 7 in the film thickness direction and exposes the back surface side of the semiconductor substrate 2 is formed. (Step S60, FIG. 14, FIG. 19). The opening 7 a is formed in the same comb shape as the mask pattern 21. Here, since at least a part of the upper side surface of the mask pattern 21 is exposed from the back surface passivation film 7, oxygen is reliably supplied to the surface of the thermosetting resin, and the thermosetting resin is surely incinerated. . Further, by removing the mask pattern 21, the back surface passivation film 7 on the mask pattern 21 is also removed.
この加熱処理では、裏面パッシベーション膜7の形成に用いた装置がマルチチャンバーシステムを備える装置である場合には、裏面パッシベーション膜7が成膜された成膜チャンバーの後段のチャンバー内に半導体基板11を保持する。そして、該チャンバー内の温度を、熱硬化型樹脂が消失し且つ裏面パッシベーション膜7が耐性を有する温度に調整する。これにより、裏面パッシベーション膜7の成膜工程と、熱硬化型樹脂を除去する工程との連続処理が可能であり、工程の簡略化が可能である。
In this heat treatment, when the apparatus used to form the back surface passivation film 7 is an apparatus having a multi-chamber system, the semiconductor substrate 11 is placed in a chamber subsequent to the film forming chamber on which the back surface passivation film 7 is formed. Hold. Then, the temperature in the chamber is adjusted to a temperature at which the thermosetting resin disappears and the back surface passivation film 7 has resistance. Thereby, the continuous process of the film-forming process of the back surface passivation film 7 and the process of removing the thermosetting resin is possible, and the process can be simplified.
また、裏面パッシベーション膜7が成膜された成膜チャンバー内に半導体基板11をそのまま保持し、該チャンバー内の温度を、熱硬化型樹脂が消失し且つ裏面パッシベーション膜7が耐性を有する温度に調整してもよい。これにより、裏面パッシベーション膜7の成膜工程と、熱硬化型樹脂を除去する工程との連続処理が可能であり、工程の簡略化が可能である。
Further, the semiconductor substrate 11 is held as it is in the film formation chamber where the back surface passivation film 7 is formed, and the temperature in the chamber is adjusted to a temperature at which the thermosetting resin disappears and the back surface passivation film 7 has resistance. May be. Thereby, the continuous process of the film-forming process of the back surface passivation film 7 and the process of removing the thermosetting resin is possible, and the process can be simplified.
なお、このマスクパターン21の除去工程では、高温加熱処理によるマスクパターン21の焼却除去以外に、シリコン窒化膜(SiN膜)と熱硬化型樹脂との間で充分な化学的選択比が存在するガスを用いたドライエッチングを使用しても同一の効果が得られる。
In this mask pattern 21 removal step, a gas having a sufficient chemical selectivity between the silicon nitride film (SiN film) and the thermosetting resin other than the incineration removal of the mask pattern 21 by high-temperature heat treatment. The same effect can be obtained even by using dry etching using.
このように、本実施の形態では裏面パッシベーション膜7の形成前に半導体基板11の裏面側にマスクパターン21を形成し、裏面パッシベーション膜7を形成し、その後、マスクパターン21を焼却除去する。したがって、本実施の形態では、安価かつ簡便な手法である熱硬化型樹脂の印刷および加熱処理を用いることにより、裏面パッシベーション膜7に対する穴あけ加工が実現できる。
Thus, in this embodiment, the mask pattern 21 is formed on the back surface side of the semiconductor substrate 11 before the back surface passivation film 7 is formed, the back surface passivation film 7 is formed, and then the mask pattern 21 is removed by incineration. Therefore, in the present embodiment, drilling of the back surface passivation film 7 can be realized by using a thermosetting resin printing and heat treatment, which are inexpensive and simple methods.
つぎに、裏面側電極13を形成する(焼成前)。まず、半導体基板11の裏面側にスクリーン印刷によって、電極材料ペーストである裏銀ペースト8aを裏銀電極8の形状に、パッド状に塗布し、乾燥させる(ステップS70、図20)。ここで、裏銀ペースト8aは、櫛形形状の開口部7aのうち、縦方向に延在するライン状領域と横方向に延在するライン状領域との交点部分の正方形状の領域に、一部が裏面パッシベーション膜7の表面から突出するように印刷される。
Next, the back side electrode 13 is formed (before firing). First, the back silver paste 8a, which is an electrode material paste, is applied to the shape of the back silver electrode 8 in a pad shape by screen printing on the back side of the semiconductor substrate 11 and dried (step S70, FIG. 20). Here, the back silver paste 8a is partly formed in a square area at the intersection of the line-shaped area extending in the vertical direction and the line-shaped area extending in the horizontal direction in the comb-shaped opening 7a. Is printed so as to protrude from the surface of the back surface passivation film 7.
つぎに、半導体基板11の裏面側にスクリーン印刷によって、裏アルミニウム電極9の形状に電極材料ペーストである裏アルミニウムペースト9aを塗布し、乾燥させる(ステップS80、図15、図21)。ここで、裏アルミニウムペースト9aは、櫛形形状の開口部7aのうち裏銀ペースト8aの塗布領域を除いた領域を埋めて、裏銀ペースト8aに接触させて塗布される。また、裏アルミニウムペースト9aは、半導体基板11の裏面において裏銀電極8を囲んで裏面パッシベーション膜7上にも塗布され、裏銀電極8を囲んで半導体基板11の裏面のほぼ全面に塗布される。したがって、裏アルミニウムペースト9aは、半導体基板11の裏面において、先に印刷・乾燥した裏銀ペースト8aの領域を除いて印刷される。
Next, the back aluminum paste 9a, which is an electrode material paste, is applied to the shape of the back aluminum electrode 9 by screen printing on the back side of the semiconductor substrate 11, and dried (step S80, FIG. 15, FIG. 21). Here, the back aluminum paste 9a is applied in such a manner that the region excluding the application region of the back silver paste 8a in the comb-shaped opening 7a is filled and brought into contact with the back silver paste 8a. The back aluminum paste 9 a is also applied to the back surface passivation film 7 so as to surround the back silver electrode 8 on the back surface of the semiconductor substrate 11, and is applied to almost the entire back surface of the semiconductor substrate 11 surrounding the back silver electrode 8. . Therefore, the back aluminum paste 9a is printed on the back surface of the semiconductor substrate 11 except for the region of the back silver paste 8a that has been printed and dried previously.
また、図20および図21では、開口部7aの正方形状の領域のうちの内部側領域に裏銀ペースト8aが塗布され、開口部7aの正方形状の領域のうちの外部側領域に裏アルミニウムペースト9aが塗布される場合について示しているが、正方形状の領域の全体に裏銀ペースト8aが塗布されてもよい。
20 and 21, the back silver paste 8a is applied to the inner side area of the square area of the opening 7a, and the back aluminum paste is applied to the outer side area of the square area of the opening 7a. Although the case where 9a is applied is shown, the back silver paste 8a may be applied to the entire square area.
ついで、スクリーン印刷により受光面側に表銀電極(受光面側電極12)を形成する(焼成前)。すなわち、半導体基板11の受光面である反射防止膜4上に、表銀グリッド電極5と表銀バス電極6との形状に、ガラスフリットを含む電極材料ペーストである銀ペースト5aをスクリーン印刷によって塗布した後、銀ペースト5aを乾燥させる(ステップS90、図15)。なお、図12~図16では、受光面側において隣接する表銀グリッド電極5の間隔と、裏面側においてグリッド電極として隣接する裏アルミニウム電極9の間隔とが同じである場合を示している。また、図15は図1のA-A方向における断面図に対応するため、図15では裏銀ペースト8aは示されていない。
Next, a surface silver electrode (light-receiving surface side electrode 12) is formed on the light-receiving surface side by screen printing (before firing). That is, a silver paste 5a, which is an electrode material paste containing glass frit, is applied to the shape of the front silver grid electrode 5 and the front silver bus electrode 6 on the antireflection film 4 which is the light receiving surface of the semiconductor substrate 11 by screen printing. After that, the silver paste 5a is dried (step S90, FIG. 15). 12 to 16 show a case where the interval between adjacent front silver grid electrodes 5 on the light receiving surface side is the same as the interval between adjacent back aluminum electrodes 9 serving as grid electrodes on the back surface side. Further, FIG. 15 corresponds to the cross-sectional view in the AA direction of FIG. 1, and therefore the back silver paste 8a is not shown in FIG.
その後、半導体基板11の表面および裏面の電極ペーストを例えば600℃~900℃で同時に焼成することで、半導体基板11の表側では銀ペースト中に含まれているガラス材料で反射防止膜4が溶融している問に銀材料がシリコンと接触し再凝固する。これにより、受光面側電極12としての表銀グリッド電極5および表銀バス電極6とが得られ、受光面側電極12と半導体基板11のシリコンとの導通が確保される(ステップS100、図16)。このようなプロセスは、ファイヤースルー法と呼ばれる。
Thereafter, the electrode paste on the front and back surfaces of the semiconductor substrate 11 is simultaneously fired at, for example, 600 ° C. to 900 ° C., so that the antireflection film 4 is melted with the glass material contained in the silver paste on the front side of the semiconductor substrate 11. The silver material comes into contact with silicon and re-solidifies. As a result, the front silver grid electrode 5 and the front silver bus electrode 6 as the light receiving surface side electrode 12 are obtained, and conduction between the light receiving surface side electrode 12 and the silicon of the semiconductor substrate 11 is ensured (step S100, FIG. 16). ). Such a process is called a fire-through method.
半導体基板11の裏面側では、裏銀ペースト8aの銀材料がシリコンと接触し再凝固して裏銀電極8が得られる(図22)。また、開口部7aに塗布された裏アルミニウムペースト9aも半導体基板11のシリコンと反応して裏アルミニウム電極9が得られ、かつ裏アルミニウム電極9の直下にp+層10を形成する。また、裏面パッシベーション膜7上に塗布された裏アルミニウムペースト9aも焼成されて、裏面パッシベーション膜7上にも裏アルミニウム電極9が得られる。したがって、裏アルミニウム電極9は、半導体基板11の裏面において、裏銀電極8の領域を除いて形成される。なお、裏アルミニウムペースト9aはガラスフリットを含まない。このため、裏アルミニウムペースト9aの焼成においてはファイヤースルーは生じない。
On the back side of the semiconductor substrate 11, the silver material of the back silver paste 8a comes into contact with silicon and re-solidifies to obtain the back silver electrode 8 (FIG. 22). Also, the back aluminum paste 9 a applied to the opening 7 a reacts with the silicon of the semiconductor substrate 11 to obtain the back aluminum electrode 9, and the p + layer 10 is formed immediately below the back aluminum electrode 9. Further, the back aluminum paste 9 a applied on the back surface passivation film 7 is also baked, and the back aluminum electrode 9 is obtained also on the back surface passivation film 7. Therefore, the back aluminum electrode 9 is formed on the back surface of the semiconductor substrate 11 except for the region of the back silver electrode 8. The back aluminum paste 9a does not contain glass frit. For this reason, no fire-through occurs in the baking of the back aluminum paste 9a.
以上の工程を実施することにより、図1~図5に示される本実施の形態にかかる太陽電池セル1が得られる。なお、電極材料であるペーストの半導体基板11への配置の順番(印刷の順番)を、受光面側と裏面側とで入れ替えてもよい。
By performing the above steps, the solar battery cell 1 according to the present embodiment shown in FIGS. 1 to 5 is obtained. Note that the order (printing order) of arrangement of the paste, which is an electrode material, on the semiconductor substrate 11 may be switched between the light receiving surface side and the back surface side.
上述したように、実施の形態1においては、半導体基板11の裏面側にマスクパターン21を形成した後に裏面パッシベーション膜7を形成し、その後、マスクパターン21を除去する。これにより、実施の形態1においては、安価かつ簡便な工程により、裏面パッシベーション膜7に開口部7aを形成することができる。
As described above, in the first embodiment, the back surface passivation film 7 is formed after forming the mask pattern 21 on the back surface side of the semiconductor substrate 11, and then the mask pattern 21 is removed. Thereby, in Embodiment 1, the opening part 7a can be formed in the back surface passivation film 7 by an inexpensive and simple process.
したがって、実施の形態1によれば、裏面パッシベーション膜を備えて光電変換効率に優れた太陽電池セルを、安価かつ簡便な工程で生産性良く製造できる、という効果を奏する。
Therefore, according to the first embodiment, there is an effect that a solar battery cell having a back surface passivation film and excellent in photoelectric conversion efficiency can be manufactured with high productivity by an inexpensive and simple process.
以上のように、本発明にかかる太陽電池セルの製造方法は、裏面パッシベーション膜を備えて光電変換効率に優れた太陽電池セルを簡便な工程で生産性良く製造する場合に有用である。
As described above, the method for manufacturing a solar battery cell according to the present invention is useful when manufacturing a solar battery cell having a back surface passivation film and excellent in photoelectric conversion efficiency with a simple process and high productivity.
1 太陽電池セル、2 半導体基板、2a 微小凹凸、3 n型不純物拡散層、4 反射防止膜、5 表銀グリッド電極、5a 銀ペースト、6 表銀バス電極、7 裏面パッシベーション膜、7a 開口部、8 裏銀電極、8a 裏銀ペースト、9 裏アルミニウム電極、9a 裏アルミニウムペースト、10 p+層、11 半導体基板、12 受光面側電極、13 裏面側電極、21 マスクパターン。
1 solar cell, 2 semiconductor substrate, 2a minute unevenness, 3 n-type impurity diffusion layer, 4 antireflection film, 5 surface silver grid electrode, 5a silver paste, 6 surface silver bus electrode, 7 back surface passivation film, 7a opening, 8 back silver electrode, 8a back silver paste, 9 back aluminum electrode, 9a back aluminum paste, 10 p + layer, 11 semiconductor substrate, 12 light receiving surface side electrode, 13 back surface side electrode, 21 mask pattern.
Claims (9)
- 第1導電型の半導体基板における受光面側となる一面側に第2導電型の不純物拡散層を形成する第1工程と、
前記半導体基板の他面側にマスクパターンを形成する第2工程と、
前記マスクパターンの厚みよりも薄い膜厚のパッシベーション膜を前記半導体基板の他面側に形成して、前記マスクパターンの側面の一部が露出するように前記マスクパターンを前記パッシベーション膜に埋設する第3工程と、
前記パッシベーション膜を除去することにより前記パッシベーション膜を膜厚方向に貫通して前記半導体基板の他面側を露出させる開口部を形成する第4工程と、
前記半導体基板の他面側に電気的に接続する裏面側電極を前記開口部内に埋設する第5工程と、
前記不純物拡散層に電気的に接続する受光面側電極を前記半導体基板の一面側に形成する第6工程と、
を含むことを特徴とする太陽電池セルの製造方法。 A first step of forming a second conductivity type impurity diffusion layer on one side of the first conductivity type semiconductor substrate which is a light receiving surface side;
A second step of forming a mask pattern on the other side of the semiconductor substrate;
A passivation film having a thickness smaller than that of the mask pattern is formed on the other surface side of the semiconductor substrate, and the mask pattern is embedded in the passivation film so that a part of the side surface of the mask pattern is exposed. 3 steps,
A fourth step of forming an opening that penetrates the passivation film in the film thickness direction by removing the passivation film and exposes the other surface side of the semiconductor substrate;
A fifth step of burying a back side electrode electrically connected to the other side of the semiconductor substrate in the opening;
A sixth step of forming a light receiving surface side electrode electrically connected to the impurity diffusion layer on one surface side of the semiconductor substrate;
The manufacturing method of the photovoltaic cell characterized by including. - 前記第4工程では、前記パッシベーション膜が耐性を有する条件で前記マスクパターンを焼却またはドライエッチング法により除去すること、
を特徴とする請求項1に記載の太陽電池セルの製造方法。 In the fourth step, the mask pattern is removed by incineration or dry etching under a condition that the passivation film has resistance;
The manufacturing method of the photovoltaic cell of Claim 1 characterized by these. - 前記第3工程では、前記マスクパターンの側面の一部が露出する成膜条件で、常圧CVD法またはスパッタリング法により前記パッシベーション膜を形成し、
前記第4工程では、前記パッシベーション膜が耐性を有する条件で前記マスクパターンを焼却により除去すること、
を特徴とする請求項2に記載の太陽電池セルの製造方法。 In the third step, the passivation film is formed by a normal pressure CVD method or a sputtering method under a film forming condition in which a part of the side surface of the mask pattern is exposed.
In the fourth step, the mask pattern is removed by incineration under a condition that the passivation film has resistance;
The manufacturing method of the photovoltaic cell of Claim 2 characterized by these. - 前記第2工程では、前記パッシベーション膜の形成時の温度に耐性を有する樹脂を前記半導体基板の他面側に塗布する第7工程と、
前記樹脂を固化させて前記マスクパターンを形成する第8工程と、
を含むことを特徴とする請求項3に記載の太陽電池セルの製造方法。 In the second step, a seventh step of applying a resin having resistance to a temperature at the time of forming the passivation film to the other surface side of the semiconductor substrate;
An eighth step of solidifying the resin to form the mask pattern;
The manufacturing method of the photovoltaic cell of Claim 3 characterized by the above-mentioned. - 前記樹脂が熱硬化型合成樹脂であり、
前記第8工程では、前記熱硬化型合成樹脂を加熱して該熱硬化型合成樹脂を固化させること、
を特徴とする請求項4に記載の太陽電池セルの製造方法。 The resin is a thermosetting synthetic resin;
In the eighth step, the thermosetting synthetic resin is heated to solidify the thermosetting synthetic resin;
The manufacturing method of the photovoltaic cell of Claim 4 characterized by these. - 前記第8工程と、前記第3工程と、前記第4工程における焼却による前記マスクパターンの除去が、CVD装置におけるチャンバー内において前記チャンバー内の温度を調整することにより行われること、
を特徴とする請求項5に記載の太陽電池セルの製造方法。 The removal of the mask pattern by incineration in the eighth step, the third step, and the fourth step is performed by adjusting the temperature in the chamber in the chamber of the CVD apparatus;
The manufacturing method of the photovoltaic cell of Claim 5 characterized by these. - 前記第8工程と前記第3工程と前記第4工程における焼却による前記マスクパターンの除去とのそれぞれが、マルチチャンバーシステムを備える前記CVD装置において異なるチャンバー内で行われること、
を特徴とする請求項6に記載の太陽電池セルの製造方法。 Each of the removal of the mask pattern by incineration in the eighth step, the third step, and the fourth step is performed in different chambers in the CVD apparatus including a multi-chamber system;
The manufacturing method of the photovoltaic cell of Claim 6 characterized by these. - 前記第8工程と前記第3工程と前記第4工程における焼却による前記マスクパターンの除去とが、前記CVD装置における同一チャンバー内で行われること、
を特徴とする請求項6に記載の太陽電池セルの製造方法。 The removal of the mask pattern by incineration in the eighth step, the third step, and the fourth step is performed in the same chamber in the CVD apparatus;
The manufacturing method of the photovoltaic cell of Claim 6 characterized by these. - 前記樹脂が紫外線硬化型樹脂であり、
前記第8工程では、前記紫外線硬化型樹脂に紫外線を照射して該紫外線硬化型樹脂を固化させること、
を特徴とする請求項4に記載の太陽電池セルの製造方法。 The resin is an ultraviolet curable resin;
In the eighth step, the ultraviolet curable resin is irradiated with ultraviolet rays to solidify the ultraviolet curable resin;
The manufacturing method of the photovoltaic cell of Claim 4 characterized by these.
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