WO2014104419A1

WO2014104419A1 - Semiconductor device, and method for manufacturing same

Info

Publication number: WO2014104419A1
Application number: PCT/KR2012/011496
Authority: WO
Inventors: 오세종; 황규성; 유명철
Original assignee: (주)버티클
Priority date: 2012-12-26
Filing date: 2012-12-26
Publication date: 2014-07-03

Abstract

Disclosed are a semiconductor device and a method for manufacturing same. The semiconductor device according to one embodiment of the present invention comprises: a conductive support layer; a first semiconductor layer of a first type formed on the conductive support layer; a second semiconductor layer of a second type; an active layer interposed between the first semiconductor layer and the second semiconductor layer; and at least one barrier layer, which is a buffer for thermal expansion stress, formed into a predetermined shape pattern either on or inside the conductive support layer so as to minimize the thermal expansion stress between the conductive support layer and the first semiconductor layer. The barrier layer, which is a buffer for thermal expansion stress, includes a first barrier layer, which is a buffer for thermal expansion stress, having a first shape pattern which is patterned into a predetermined shape, or a second barrier layer, which is a buffer for thermal expansion stress, having a second shape pattern. The barrier layer, which is a buffer for thermal expansion stress, is configured such that at least one first barrier layer, which is a buffer for thermal expansion stress, and at least one second barrier layer, which is a buffer for thermal expansion stress, are spaced apart from each other or formed into a continuous double layer. Thus, in the semiconductor device having a vertical structure, stresses which may be caused due to the difference of thermal expansion coefficients between a light-emitting structure and the conductive support layer during package assembly and application of current can be minimized.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device, and more particularly, to a vertical structure semiconductor device, which may be generated during package assembly and current application due to a difference in thermal expansion coefficient between a light emitting structure, for example, a light emitting device (LED) and a conductive support layer. A semiconductor device capable of minimizing stress and a method of manufacturing the same.

A light emitting diode (LED) is a semiconductor device capable of generating light of various colors based on recombination of electrons and holes at a junction portion of a p and n type semiconductor when current is applied thereto. These LEDs have a number of advantages over filament based light emitting devices, such as long life, low power, excellent initial driving characteristics, high vibration resistance, and high tolerance for repetitive power interruptions. In recent years, group III nitride semiconductors capable of emitting light in a blue short wavelength region have been in the spotlight.

The nitride single crystal constituting the light emitting device using the group III nitride semiconductor is formed on a specific single crystal growth substrate, such as a sapphire or SiC substrate. However, in the case of using an insulating substrate such as sapphire, the arrangement of electrodes is greatly limited. That is, in the conventional nitride semiconductor light emitting device, since the electrodes are generally arranged in the horizontal direction, the current flow becomes narrow. Due to such a narrow current flow, the forward voltage of the light emitting device is increased to decrease the current efficiency, and at the same time, there is a problem of being vulnerable to electrostatic discharge.

In order to solve the above problem, a nitride semiconductor light emitting device having a vertical structure is required. However, in order to form an electrode on the upper and lower surfaces of the nitride semiconductor light emitting device having a vertical structure, a process of removing an insulating preliminary substrate such as sapphire should be involved.

In the process of removing the sapphire preliminary substrate from the light emitting structure according to the prior art, after attaching a conductive support substrate (or conductive support layer) using a conductive adhesive layer on the nitride single crystal light emitting structure, a laser lift-off process (Laser lift-off) By removing the sapphire preliminary substrate.

However, the thermal expansion coefficient of GaN single crystal, which is the main material constituting the light emitting structure, is about 3.17 × 10 −6 / K at room temperature, and the thermal expansion coefficient of copper mainly used as the conductive support substrate is about 16.6 × 10 −6 / K. Since the thermal expansion coefficient of the GaN single crystal and the conductive support substrate show a large difference, thermal expansion stress is generated between the light emitting structure and the conductive support substrate.

Due to such thermal expansion stress, the performance of the internal quantum efficiency of the GaN single crystal layer, in particular, the active layer, is degraded, and thus there is a problem that the optical characteristics and reliability of the vertical nitride semiconductor light emitting device according to the prior art are degraded.

Therefore, there is a need for a technique capable of minimizing the stress that may occur due to the difference in thermal expansion coefficient between the light emitting structure and the conductive support substrate.

The present invention is derived to solve the problems of the prior art as described above, in the vertical structure semiconductor device, due to the difference in thermal expansion coefficient between the light emitting structure and the conductive support layer can minimize the stress that can be generated during package assembly and current application. An object of the present invention is to provide a semiconductor device and a method of manufacturing the same.

Specifically, the present invention minimizes thermal expansion stress between the light emitting structure and the conductive support layer by the buffer material by adding at least one buffer material capable of minimizing thermal expansion stress between the conductive support layer and the light emitting structure or between the two layers within the conductive support layer. Accordingly, the stress due to heat generated when driving the semiconductor device and assembling the semiconductor device into the package can be minimized.

In order to achieve the above object, the semiconductor device according to an embodiment of the present invention comprises a conductive support layer; A first semiconductor layer of a first type formed on the conductive support layer; A second semiconductor layer of a second type; An active layer positioned between the first semiconductor layer and the second semiconductor layer; And at least one thermal expansion stress buffer barrier layer formed in a predetermined pattern shape on at least one of the top or the inside of the conductive support layer to minimize thermal expansion stress between the conductive support layer and the first semiconductor layer.

The thermal expansion stress buffer barrier layer may be formed of any one of Pt, Ti, W, Mo, Cr, SiOx, SiNx, SOG (spin-on-glass), Ni, Co, Cu, Fe, Mn, or at least one compound. Can be done.

The thermal expansion stress buffer barrier layer may include a first thermal expansion stress buffer barrier layer having a first pattern shape patterned in a predetermined shape or a second thermal expansion stress buffer barrier layer having a second pattern shape.

The thermal expansion stress buffer barrier layer may be formed by at least one or more first thermal expansion stress buffer barrier layers, or may be formed by at least one or more second thermal expansion stress buffer barrier layers, and at least one or more first thermal expansion. The stress buffer barrier layer and the at least one second thermal expansion stress buffer barrier layer may be spaced apart from each other, or may be formed in a plurality of continuous layers.

The first thermal expansion stress buffer barrier layer may have a width and an interval of 5 to 400 [um], and a height may be less than or equal to half the height of the conductive support layer.

The first thermal expansion stress buffer barrier layer may have at least one circular pattern or at least one polygonal pattern corresponding to the shape of the semiconductor device.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first semiconductor layer of a first type; Forming an active layer on the first semiconductor layer; Forming a second semiconductor layer of a second type on the active layer; And forming a conductive support layer on the second semiconductor layer, the conductive support layer including at least one thermal expansion stress buffer barrier layer, wherein the thermal expansion stress buffer barrier layer minimizes thermal expansion stress between two layers having different thermal expansion coefficients. And a predetermined pattern shape between at least one of the second semiconductor layer and the conductive support layer or inside the conductive support layer.

According to the present invention, in order to minimize the stress change due to heat that may be generated due to the difference in thermal expansion coefficient between the light emitting structure and the conductive support layer of the vertical semiconductor device, for example, copper support layer, between the conductive support layer and the light emitting structure or inside the conductive support layer By adding at least one buffer material capable of minimizing thermal expansion stress between the two layers, the thermal expansion stress between the light emitting structure and the conductive support layer can be minimized by the buffer material, thereby driving the semiconductor device and the semiconductor device into the package. It is possible to minimize the stress change due to the heat generated during assembly.

Furthermore, according to the present invention, by minimizing the thermal expansion stress between the light emitting structure and the conductive support layer, it is possible to further improve the optical characteristics of the semiconductor device.

1 illustrates a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

2 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

3 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

4 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

5 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

6 is a sectional view of a semiconductor device according to another embodiment of the present invention.

7 is a plan view of embodiments of the first thermal expansion stress buffer pattern barrier layer in the present invention.

8 is a plan view of other embodiments of the first thermal expansion stress buffer pattern barrier layer in the present invention.

9 is a flowchart illustrating an operation of a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

10 to 12 illustrate cross-sectional views of one embodiment for describing a process of the method of manufacturing the semiconductor device of FIG. 1.

A semiconductor device according to an embodiment of the present invention includes a conductive support layer; A first semiconductor layer of a first type formed on the conductive support layer; A second semiconductor layer of a second type; An active layer positioned between the first semiconductor layer and the second semiconductor layer; And at least one thermal expansion stress buffer barrier layer formed in a predetermined pattern shape on at least one of the top or the inside of the conductive support layer to minimize thermal expansion stress between the conductive support layer and the first semiconductor layer.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the term "comprises" and the like is intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features, numbers, steps It is to be understood that the present invention does not exclude in advance the possibility of the presence or the addition of operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

However, the present invention is not limited or limited by the embodiments. Like reference numerals in the drawings denote like elements.

Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 12.

Referring to FIG. 1, the semiconductor device according to the present invention may include an electrode layer 110, a first semiconductor layer 120, an active layer 130, a second semiconductor layer 140, a reflective layer 150, a barrier layer 160, A thermal stress buffer barrier layer 170 and a conductive support layer 180 are included.

The first semiconductor layer 120 may be a first type semiconductor layer, and may be an N type semiconductor layer. For example, the first semiconductor layer 120 may be an N type GaN layer.

In this case, the first semiconductor layer 120 may be formed by epitaxial growth.

The active layer 130 is formed in contact with one surface of the first semiconductor layer 120, and is formed between the first semiconductor layer 120 and the second semiconductor layer 140 to increase the light emitting efficiency of the light emitting diode semiconductor device.

In this case, the active layer 130 may be referred to as a quantum well bonding layer (MQW).

The second semiconductor layer 140 is a second type of semiconductor layer, which may be a P type semiconductor layer, and for example, may be a P type GaN layer.

In this case, the second semiconductor layer 140 may also be formed by epitaxial growth.

The reflective layer 150 is formed on one surface of the second semiconductor layer 140 and serves to reflect the light generated in the active layer 130 and traveling backward.

The barrier layer 160 is formed on one surface of the reflective layer 150, and is a barrier layer for preventing diffusion between the reflective layer 150 and the conductive support layer 180. In some cases, the barrier layer 160 may not be formed. It may be.

The conductive support layer 180 is a layer providing mechanical support of the semiconductor device and is formed on one surface of the barrier layer 160. Of course, when the barrier layer 160 is not formed on the semiconductor device, the barrier layer 160 may be formed on one surface of the reflective layer 150.

In this case, the conductive support layer 180 may be formed of a metal having high electrical conductivity and thermal conductivity and having a relatively high mechanical strength, for example, copper or a copper compound.

In addition, the conductive support layer 180 may be formed through an electroplating method, and may be composed of a plurality of layers having different densities and strengths.

The electrode layer 110 is formed on the other surface of the first semiconductor layer 120 and is a layer for applying power to the semiconductor device.

In this case, the electrode layer 110 may be formed using a metal and a metal compound.

The thermal expansion stress buffer barrier layer 170 is a layer for minimizing thermal expansion stress between two layers having different coefficients of thermal expansion (CTE). In the present invention, the first semiconductor layer 120, the active layer 130, Thermal expansion coefficient of the light emitting structure including the second semiconductor layer 140 and the conductive support layer 180, for example, as shown in Table 1 to minimize the stress due to the difference in the thermal expansion coefficient of GaN and Cu. In some cases, the thermal expansion stress buffer barrier layer 170 may be a layer for minimizing thermal expansion stress between the second semiconductor layer 140 and the conductive support layer 180 rather than the light emitting structure.

Table 1

In this case, at least one thermal expansion stress buffer barrier layer 170 may be formed in at least one of a partial region between the second semiconductor layer 140 and the conductive support layer 180 or a partial region inside the conductive support layer 180. Of course, the thermal expansion stress buffer barrier layer 170 in FIG. 1 is illustrated as being formed inside the conductive support layer 180, but is not limited thereto, and may be formed between the barrier layer 160 and the conductive support layer 180. When the barrier layer 160 is not configured, the barrier layer 160 may be formed between the reflective layer 150 and the conductive support layer 180.

Since the thermal expansion stress buffer barrier layer 170 is intended to minimize thermal expansion stress between a layer having a high coefficient of thermal expansion and a layer having a low coefficient of thermal expansion, a material having a small coefficient of thermal expansion, for example, has a thermal expansion coefficient similar to that of a layer having a small coefficient of thermal expansion. By forming a material having a high thermal expansion coefficient in or on the conductive support layer 180, a stress barrier is provided in the X-axis direction (lateral direction) to buffer thermal expansion stress in the X-axis direction, thereby dispersing the stress. You can.

In this case, the thermal expansion stress buffer barrier layer 170 is any one of Pt, Ti, W, Mo, Cr, SiOx, SiNx, spin-on-glass (SOG), Ni, Co, Cu, Fe, Mn or It may be made of at least one compound, but is not limited thereto, and may include all materials and compounds capable of minimizing thermal expansion stress due to a difference in thermal expansion coefficient between the light emitting structure and the conductive support layer 180. For example, the thermal expansion stress buffer barrier layer 170 may be made of two or more compounds such as NiCo, NiCu, NiFe, NiMo, NiMoCr, NiCr, NiFeCu, NiCoMn, NiCrFe, and NiCrMoCu.

The thermal expansion stress buffer barrier layer 170 is formed on a portion of the conductive support layer 180 or in an interior thereof, and may have a first pattern shape that is patterned in a predetermined shape, or may have a second pattern shape. It may be.

In this case, the second pattern shape may refer to a pattern shape in which only a part of the outer region of the conductive support layer 180 is patterned and the inner area is formed of a single shape layer.

That is, when the thermal expansion stress buffer barrier layer 170 has a first pattern shape, the thermal expansion stress buffer barrier layer 170 has a width and an interval between patterns, and when the thermal expansion stress buffer barrier layer 170 has a second pattern shape, only the length and the height are provided.

The thermal expansion stress buffer barrier layer 170 illustrated in FIG. 1 corresponds to a case in which one layer is formed by a first pattern shape patterned in a predetermined shape.

Here, the thermal expansion stress buffer barrier layer 170 has a width (W) and the interval of 5 ~ 400 [um], the height (h) may be formed to less than half the height of the conductive support layer.

The thermal expansion stress buffer barrier layer may have various first pattern shapes, as shown in FIGS. 7 and 8. For example, as illustrated in FIG. 7, the thermal expansion stress buffer barrier layer may be formed by separating a plurality of square patterns at a predetermined distance from each other based on the center of the device, and forming a predetermined number of grid patterns. In addition, a pattern for a shape or a square shape of the device may be formed only in an outer region of the device, or at least one polygonal pattern shape may be formed. As another example, as shown in FIG. 8, the thermal expansion stress buffer barrier layer may have a pattern shape corresponding to the shape of the semiconductor device, wherein the pattern shape includes at least one circular pattern or at least one corresponding to the shape of the semiconductor device. The above-described polygonal pattern may be formed, and the circular pattern and the polygonal pattern may be formed to be spaced apart by a predetermined interval based on the center of the semiconductor device. Of course, the circular pattern and the polygonal pattern may include at least one or more linear patterns connecting the spaced patterns in a state formed by being spaced apart by a predetermined interval.

The pattern shape corresponding to the shape of the semiconductor device is not limited to the circular pattern and the polygonal pattern, and may have a shape including a circle and a polygon, or may have a shape including polygons of different shapes.

As such, the thermal expansion stress buffer barrier layer 170 may be formed by a layer having at least one first pattern shape (hereinafter, referred to as a 'first thermal expansion stress buffer barrier layer'), and at least one second pattern. It may be formed by a layer having a shape (hereinafter referred to as a 'second thermal expansion stress buffer barrier layer'), and the layer having at least one or more first pattern shapes is spaced apart from the layer having at least one second pattern shape. It may be formed in multiple layers formed or continuous.

This thermal expansion stress buffer barrier layer 170 will be described in detail with reference to FIGS. 2 to 6.

2 is a cross-sectional view of a semiconductor device according to another exemplary embodiment of the present invention, and illustrates a form in which a sealing unit 220 is added to the configuration of FIG. 1.

That is, as shown in FIG. 2, the sealing part 220 is formed on both sides of the reflective layer 150, and is formed between the light emitting structure 210 and a portion of the conductive support layer 180 and the barrier layer 160. do.

The sealing unit 220 protects the semiconductor device periphery in a semiconductor device manufacturing process having a vertical structure, and prevents various chemical solutions used in the semiconductor device manufacturing process from penetrating into the reflective layer 150. The sealing unit 220 may prevent the chemical solution from penetrating into the reflective layer 150, thereby preventing the leakage current and the characteristics of the semiconductor device from deteriorating.

Although the upper portion of the light emitting structure 210 illustrated in FIG. 2 is illustrated in an uneven form, this is only one embodiment for improving light emission efficiency, and the upper shape of the light emitting structure is not limited to the uneven form.

As shown in FIG. 3, the thermal expansion stress buffer barrier layer 170 is formed in the conductive support layer 180, and the layer 310 patterned in the first pattern shape and the layer 320 patterned in the second pattern shape. It is composed of two layers.

That is, the thermal expansion stress buffer barrier layer 170 is composed of two layers including one layer of the first thermal expansion stress buffer barrier layer 310 and one layer of the second thermal expansion stress buffer barrier layer 320. Here, the second thermal expansion stress buffer barrier layer 320 may be formed to have an area smaller than the area of the conductive support layer 180.

Of course, the two

layers

310 and 320 shown in FIG. 3 may be formed together in one process or may be formed in two processes, respectively.

In this case, as shown in FIG. 4, the two

layers

310 and 320 constituting the thermal expansion stress buffer barrier layer 170 may be formed in opposite positions.

That is, as shown in FIG. 4, the thermal expansion stress buffer barrier layer 170 includes two layers including one layer of the second thermal expansion stress buffer barrier layer 410 and one layer of the first thermal expansion stress buffer barrier layer 420. It is done.

The two layers shown in FIGS. 3 and 4 may be formed by the same single material or the same compound.

As shown in FIG. 5, the thermal expansion stress buffer barrier layer 170 is formed inside the conductive support layer 180, and the two first thermal expansion stress buffer barrier layers 510 and 530 and the second thermal expansion stress of one layer are formed. The buffer barrier layer 520 is formed continuously.

That is, the thermal expansion stress buffer barrier layer 170 in FIG. 5 includes the first-first thermal expansion stress buffer barrier layer 510, the second thermal expansion stress buffer barrier layer 520, and the 1-2 thermal expansion stress buffer barrier layer 530. ) Has a multilayer structure formed sequentially.

In this case, the first-first thermal expansion stress buffer barrier layer 510 and the first-second thermal expansion stress buffer barrier layer 530 may have the same pattern shape or may have different pattern shapes.

In FIG. 5, the 1-1 thermal expansion stress buffer barrier layer 510, the second thermal expansion stress buffer barrier layer 520, and the 1-2 thermal expansion stress buffer barrier layer 530 are also formed of the same material or the same compound. It can be formed by.

6 illustrates a cross-sectional view of a semiconductor device according to another embodiment of the present invention, in which the thermal expansion stress buffer barrier layer 170 is formed in an outer region of an upper portion of the conductive support layer 180.

As illustrated in FIG. 6, the thermal expansion stress buffer barrier layer 170 may be formed in the upper outer region of the conductive support layer 180 and may have a shape surrounding the upper outer region of the conductive support layer 180.

In this case, the height and width of the thermal expansion stress buffer barrier layer 170 may be determined in consideration of the difference in thermal expansion coefficient between the light emitting structure 210 and the conductive support layer 180.

In addition, although one thermal expansion stress buffer barrier layer 170 having a shape surrounding the upper outer region of the conductive support layer is illustrated in FIG. 6, the thermal expansion stress buffer barrier layer 170 having the same shape is not limited thereto. 180 may be formed inside.

As described above, the thermal expansion stress buffer barrier layer of the present invention is formed by at least one of the at least one first thermal expansion stress buffer barrier layer and the at least one second thermal expansion stress buffer barrier layer, thereby providing an example of the thermal expansion coefficient of the light emitting structure. For example, GaN thermal expansion coefficient and the conductive support layer, for example, by minimizing the thermal expansion stress that can be generated by the difference of the Cu thermal expansion coefficient and thereby minimize the stress generated during package assembly or current application by the difference in thermal expansion coefficient semiconductor device The performance of the semiconductor device can be improved, and thus the optical properties and reliability of the semiconductor device can be improved.

9 is a flowchart illustrating an operation of a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 10 to 12 are cross-sectional views illustrating an embodiment of a process of the method of manufacturing the semiconductor device of FIG. 1. .

9 to 12, a method of manufacturing a semiconductor device according to the present invention includes a substrate 1010, for example, a first type having a predetermined thickness using epitaxial growth on an sapphire substrate or an SiC substrate, for example, N. A type first semiconductor layer 1020 is formed (S1010).

The active layer 1030 and the second semiconductor layer 1040 are sequentially formed on the first semiconductor layer 1020 (S920 and S930).

In this case, the second semiconductor layer 1040 may be a second type, for example, a P type semiconductor layer having a predetermined thickness formed using epitaxial growth.

When the light emitting structure of the semiconductor device is formed by the steps S910 to S930, the conductive support layer 1070 including the thermal expansion stress buffer barrier layer 1080 is formed on the formed light emitting structure (S940).

If necessary, after the reflective layer 1050 and the barrier layer 1060 are sequentially formed on the light emitting structure, that is, the second semiconductor layer 1040, the thermal expansion stress buffer barrier layer 1080 is included on the barrier layer 1060. The conductive support layer 1070 may be formed.

In this case, the thermal expansion stress buffer barrier layer may be formed in a predetermined pattern on at least one of the conductive support layer or inside the thermal expansion stress buffer barrier layer, and the thermal expansion stress buffer barrier layer may be formed between two layers having different thermal expansion coefficients. Or to minimize thermal expansion stress between the second semiconductor layer and the conductive support layer, and preferably to minimize thermal expansion stress between the thermal expansion coefficient of GaN included in the light emitting structure and the thermal expansion coefficient of Cu forming the conductive support layer.

The thermal expansion stress buffer barrier layer 1080 may be formed of at least one of Pt, Ti, W, Mo, Cr, SiOx, SiNx, spin-on-glass (SOG), Ni, Co, Cu, Fe, and Mn. It may be formed of the above compound, and may include at least one of a first thermal expansion stress buffer barrier layer having a first pattern shape patterned in a predetermined shape and a second thermal expansion stress buffer barrier layer having a predetermined second pattern shape. . That is, the thermal expansion stress buffer barrier layer may be formed of a plurality of layers in which at least one or more first thermal expansion stress buffer barrier layers and at least one second thermal expansion stress buffer barrier layer are spaced apart from each other, or at least one first thermal expansion stress. It may be formed of only the buffer barrier layer, or may be formed of only at least one second thermal expansion stress buffer barrier layer.

The first thermal expansion stress buffer barrier layer formed by step S940 may have a width and a spacing of 5 to 400 [um] and a height less than half the height of the conductive support layer, and at least one or more shapes corresponding to the shape of the semiconductor device. It may be formed in a circular pattern or at least one polygonal pattern. Of course, the pattern shape of the first thermal expansion stress buffer barrier layer may be a pattern shape in which various shapes are mixed, or may be a pattern shape in which one shape is repeated.

In step S940, as shown in FIG. 10, after forming a part 1071 of the conductive support layer, the thermal expansion stress buffer barrier layer is patterned and etched in a pattern shape of the first thermal expansion stress buffer barrier layer, and illustrated in FIG. 11. As described above, after the first thermal expansion stress buffer barrier layer 1080 is formed in the etched region, the remaining portion of the conductive support layer is formed thereon to form the conductive support layer 1070 including the thermal expansion stress buffer barrier layer 1080. do.

When the conductive support layer 1070 is formed, as shown in FIGS. 11 and 12, after the process of separating the substrate 1010 and the first semiconductor layer 1020, the upper surface of the first semiconductor layer 1020 is formed. An electrode layer 1090 for supplying power to the semiconductor device is formed in steps S950 and S960.

At this time, the method of separating the substrate 1010 and the first semiconductor layer 1020 is a laser lift off (LLO) method, a laser having a specific frequency band that can pass through the substrate 1010 When irradiated to the 1010, the laser beam transmitted through the substrate 1010 is absorbed by the interface between the substrate 1010 and the first semiconductor layer 1020 to generate heat, thereby causing the substrate 1010 and the first semiconductor layer ( The interface between the 1020 may be melted to separate the substrate 1010 and the first semiconductor layer 1020. Of course, as a method of separating the substrate 1010 and the first semiconductor layer 1020, a chemical lift off (CLO) method using a chemical reaction of the boundary material between the substrate and the first semiconductor layer may be used.

In the present invention as described above has been described by the specific embodiments, such as specific components and limited embodiments and drawings, but this is provided to help a more general understanding of the present invention, the present invention is not limited to the above embodiments. For those skilled in the art, various modifications and variations are possible from these descriptions.

Therefore, the spirit of the present invention should not be limited to the described embodiments, and all of the equivalents and equivalents of the claims, as well as the following claims, will fall within the scope of the present invention. .

Disclosed are a semiconductor device and a method of manufacturing the same. A semiconductor device according to an embodiment of the present invention includes a conductive support layer; A first semiconductor layer of a first type formed on the conductive support layer; A second semiconductor layer of a second type; An active layer positioned between the first semiconductor layer and the second semiconductor layer; And at least one thermal expansion stress buffer barrier layer formed in a predetermined pattern shape on at least one of the top or the inside of the conductive support layer to minimize thermal expansion stress between the conductive support layer and the first semiconductor layer. The stress buffer barrier layer includes a first thermal expansion stress buffer barrier layer having a first pattern shape patterned in a predetermined shape or a second thermal expansion stress buffer barrier layer having a second pattern shape, wherein the thermal expansion stress buffer barrier layer is at least one. Wherein the first thermal expansion stress buffer barrier layer and the at least one second thermal expansion stress buffer barrier layer are formed in a spaced apart or continuous multiple layer, thereby providing a thermal expansion coefficient between the light emitting structure and the conductive support layer in a vertical structure semiconductor device. The difference minimizes the stress that can occur during package assembly and current application.

Claims

Conductive support layer;

A first semiconductor layer of a first type formed on the conductive support layer;

A second semiconductor layer of a second type;

An active layer positioned between the first semiconductor layer and the second semiconductor layer; And

At least one thermal expansion stress buffer barrier layer formed in a predetermined pattern shape on at least one of the top or the inside of the conductive support layer to minimize thermal expansion stress between the conductive support layer and the first semiconductor layer.

Semiconductor device comprising a.
The method of claim 1,

The thermal expansion stress buffer barrier layer

A semiconductor device comprising any one of Pt, Ti, W, Mo, Cr, SiOx, SiNx, spin-on-glass (SOG), Ni, Co, Cu, Fe, Mn, or at least one compound .
The method of claim 1,

The thermal expansion stress buffer barrier layer

And a first thermal expansion stress buffer barrier layer having a first pattern shape patterned in a predetermined shape or a second thermal expansion stress buffer barrier layer having a second pattern shape.
The method of claim 3,

The thermal expansion stress buffer barrier layer

And at least one first thermal expansion stress buffer barrier layer.
The method of claim 3,

The thermal expansion stress buffer barrier layer

And at least one second thermal expansion stress buffer barrier layer.
The method of claim 3,

The thermal expansion stress buffer barrier layer

And at least one of the first thermal expansion stress buffer barrier layers and the at least one second thermal expansion stress buffer barrier layer are formed in a plurality of layers which are spaced apart or continuous.
The method of claim 3,

The first thermal expansion stress buffer barrier layer

A width and an interval are 5 to 400 [um], and a height is less than half of the height of the said conductive support layer, The semiconductor element characterized by the above-mentioned.
The method of claim 3,

The first thermal expansion stress buffer barrier layer

A semiconductor device comprising at least one circular pattern or at least one polygonal pattern corresponding to the shape of the semiconductor device.
Forming a first semiconductor layer of a first type;

Forming an active layer on the first semiconductor layer;

Forming a second semiconductor layer of a second type on the active layer; And

Forming a conductive support layer on the second semiconductor layer, the conductive support layer including at least one thermal expansion stress buffer barrier layer;

Including,

The thermal expansion stress buffer barrier layer

In order to minimize thermal expansion stress between the two layers having different coefficients of thermal expansion, semiconductor device manufacturing, characterized in that formed in a predetermined pattern shape between at least one of the second semiconductor layer and the conductive support layer or the inside of the conductive support layer Way.
The method of claim 9,

The thermal expansion stress buffer barrier layer

A semiconductor characterized in that it is formed of any one of Pt, Ti, W, Mo, Cr, SiOx, SiNx, spin-on-glass (SOG), Ni, Co, Cu, Fe, Mn, or at least one compound Device manufacturing method.
The method of claim 9,

The thermal expansion stress buffer barrier layer

And a second thermal expansion stress buffer barrier layer having a first pattern shape patterned in a predetermined shape or a second thermal expansion stress buffer barrier layer having a second pattern shape.
The method of claim 11,

The thermal expansion stress buffer barrier layer

And at least one of the first thermal expansion stress buffer barrier layer and the at least one second thermal expansion stress buffer barrier layer are formed in a plurality of layers which are spaced apart or continuous.
The method of claim 11,

The first thermal expansion stress buffer barrier layer

The semiconductor device manufacturing method characterized in that the width and the spacing is 5 to 400 [um], the height is less than half the height of the conductive support layer.
The method of claim 11,

The first thermal expansion stress buffer barrier layer

Method of manufacturing a semiconductor device, characterized in that formed in at least one circular pattern or at least one polygonal pattern corresponding to the shape of the semiconductor device.