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WO2014104332A1 - Power supply device - Google Patents

Power supply device Download PDF

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Publication number
WO2014104332A1
WO2014104332A1 PCT/JP2013/085190 JP2013085190W WO2014104332A1 WO 2014104332 A1 WO2014104332 A1 WO 2014104332A1 JP 2013085190 W JP2013085190 W JP 2013085190W WO 2014104332 A1 WO2014104332 A1 WO 2014104332A1
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WO
WIPO (PCT)
Prior art keywords
fet
circuit
voltage
power supply
type fet
Prior art date
Application number
PCT/JP2013/085190
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French (fr)
Japanese (ja)
Inventor
宮澤　明
Original Assignee
アルプス電気株式会社
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Filing date
Publication date
Application filed by アルプス電気株式会社 filed Critical アルプス電気株式会社
Publication of WO2014104332A1 publication Critical patent/WO2014104332A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10—Parallel operation of dc sources

Definitions

  • the present invention relates to a power supply device, and more particularly to a power supply device connected to an in-vehicle battery.
  • the power supply device is configured to supply and control power for driving a load circuit using an FET (Field Effect Transistor).
  • FET Field Effect Transistor
  • enhancement-type FETs can be easily switched, so that they are used for power supply devices in in-vehicle electronic devices.
  • a booster circuit is used for driving the FET.
  • Patent Document 1 discloses an in-vehicle electronic device that uses a booster circuit to drive an FET of a power supply device.
  • FIG. 5 shows a power supply device 900 for the electronic control device 941 disclosed in Patent Document 1 as a first conventional example.
  • an appropriate voltage is applied to the gate of the FET, and the voltage drop between the drain and source of the FET is about 0.4 V. Proceed as if there is. Further, the discussion will be made assuming that the FET is in an off state when substantially the same voltage is applied to the drain and the gate of the FET or when the voltage drop between the drain and the source of the FET is about 2V.
  • the power supply apparatus 900 includes a power supply terminal 905 connected to the battery 903 and an FET 921 connected to the power supply terminal 905.
  • the gate voltage needs to be higher than the source voltage by a predetermined voltage (about 3 V).
  • the output terminal of the booster circuit 943 is connected to the gate of the FET 921.
  • the booster circuit 943 is configured to generate a voltage higher than the voltage VB of the battery 903 by a predetermined voltage or more and apply the generated boosted voltage to the gate of the FET 921 to turn on the FET 921.
  • a conventional on-vehicle power supply device 800 includes an input terminal 811 connected to a battery 851, an FET circuit 801, an output terminal 812 connected to a load circuit 852, and a booster circuit 803. And a control circuit 804.
  • the anode of the protective diode 801c is connected to the input terminal 811
  • the cathode of the protective diode 801c is connected to the drain D0 of the FET 801a
  • the source S0 of the FET 801a is connected to the output terminal 812. Yes.
  • a resistor 801b and a protective diode 801d are connected in series, and are connected between the gate G0 of the FET 801a and the input terminal 811.
  • the booster circuit 803 is supplied with the output voltage Vout from the output terminal 812 as a power supply voltage, and its output terminal is connected to the gate G0 of the FET 801a. Note that the booster circuit 803 is designed to operate at 7 V or higher so that internal loss during operation does not become excessive.
  • the control circuit 804 is provided for controlling the operation of the booster circuit 803 and controlling the operation of the load circuit 852. Note that an enhancement type FET is used as the FET 801a, and a circuit through which a current of about 3 A or more flows is assumed as the load circuit 852.
  • the voltage of the gate G of the FET 801a needs to be higher than the voltage of the source S by a predetermined voltage (about 3V) or more. Therefore, the booster circuit 803 is operated, and the voltage output from the booster circuit 803 is applied to the gate of the FET 801a.
  • the booster circuit 803 is configured to boost the voltage supplied to the booster circuit 803 to a voltage approximately twice as large as the voltage output.
  • FIG. 7A shows a state before the FET 801a is turned on.
  • 9V is supplied to the booster circuit 803 as the power supply voltage, 18V, which is twice 9V, is output to the output terminal of the booster circuit 803 which is a voltage doubler generation circuit. Accordingly, when the voltage of the gate G0 with respect to the source S0 becomes 9V, the FET 801a can be turned on.
  • FIG. 7B shows a state when the FET 801a is turned on.
  • the output voltage Vout at the output terminal 812 is 10.6V.
  • the FET 801a since 21.2 V is applied to the gate G0 of the FET 801a, the FET 801a can be kept on.
  • the output voltage (Vout) at which the load circuit 852 can operate is assumed to be 7 V or more and less than 13 V. As described above, there is no particular problem if the voltage Vin at the input terminal 811 is the normal voltage 12V.
  • the conventional power supply apparatus 900 or 800 shown in FIG. 5 or 6 has the following problem when the voltage at the input terminal 811 drops to, for example, 9V.
  • FIG. 7C shows the state before and after the start of power supply to the load circuit 852 when the voltage Vin at the input terminal 811 is lowered to 9 V in the power supply apparatus 800 shown in FIG.
  • the booster circuit 803 is designed to operate with a voltage of Vout of 7V or higher.
  • the output voltage Vout at the output terminal 812 that is, the power supply voltage of the booster circuit 803 decreases to 6V. Since the booster circuit 803 is designed to operate at 7 V or higher, the booster circuit 803 cannot operate when Vout decreases to 6 V. Therefore, the voltage necessary for turning on the FET 801a from the booster circuit 803 is not applied to the gate G0 of the FET 801a, and the state of the FET 801a remains unchanged and remains as shown in FIG. Therefore, the FET 801a cannot be turned on.
  • the FET 801a cannot be turned on. Therefore, when the voltage Vin at the input terminal 811 decreases, the conventional power supply apparatus 800 has a problem in that power cannot be supplied to the load circuit 852.
  • the present invention has been made in view of the actual situation of the prior art, and an object of the present invention is to stably supply power for driving the load circuit even when the voltage output from the battery is lowered. It is an object of the present invention to provide a power supply device that can perform the above-described operation.
  • the power supply device of the present invention includes an input terminal to which power is supplied from a battery, an output terminal to which a load circuit is connected, a drain connected to the input terminal, and the output terminal.
  • the 1FET is an element that is turned off when the same voltage is supplied to the drain and gate of the first FET, and a voltage boosted by the booster circuit is applied to the gate of the first FET.
  • the drain of T is connected to the drain of the first FET
  • the source of the second FET is connected to the source of the first FET
  • the second FET has the same voltage supplied to the drain and gate of the second FET Is an element that can be turned on, and before turning on the power supply to the load circuit, the second FET is turned on, and when the power supply is started, the booster circuit is connected to the load circuit via the second FET. It has a feature that voltage is supplied.
  • the power supply device configured as described above turns on the second FET when power supply to the load circuit is started and supplies the voltage to the booster circuit via the second FET. A sufficiently high voltage can be obtained. Therefore, even when the voltage output from the battery decreases, the first FET can be turned on, so that it is possible to stably supply power for driving the load circuit.
  • the voltage is supplied from the battery to the first FET and the second FET before the start of power supply to the load circuit, and the control is performed when the power supply to the load circuit is started.
  • the booster circuit is operated by a first control signal from the circuit to turn on the first FET, and the load circuit can be operated.
  • the power supply device configured as described above controls the booster circuit and the load circuit with the first control signal from the control circuit when the power supply to the load circuit is started. Can be determined.
  • the second FET is turned off by a second control signal from the control circuit after the first FET is turned on.
  • the first FET is an enhancement type FET
  • the second FET is a depletion type FET
  • the drain and gate of the enhancement type FET are connected via a resistor
  • the drain and gate of the depletion type FET have a resistance. It has the characteristic that it is connected via.
  • the second FET can be turned on when the power supply to the load circuit is started, and the voltage drop of the second FET is reduced. A voltage can be supplied to the booster circuit in a small state.
  • the depletion type FET is characterized by being a MOS • FET.
  • the power supply device configured as described above uses a MOS • FET as a depletion type FET, the gate voltage with respect to the source can be used from a negative voltage to a positive voltage. For this reason, since the ON / OFF of the second FET can be controlled with a low voltage, it is easy to use, and power can be easily supplied to the booster circuit when power supply to the load circuit is started.
  • the above configuration has a feature that it is connected to a battery mounted on the vehicle.
  • the power supply device configured as described above can operate the electronic devices in the vehicle without any trouble even when the voltage of the battery mounted on the vehicle decreases at a low temperature or the like.
  • the power supply device of the present invention can stably supply power for driving the load circuit even when the voltage output from the battery drops.
  • FIG. 1 is a circuit diagram showing a configuration of a power supply device according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the power supply apparatus which concerns on 2nd Embodiment of this invention. It is a circuit diagram for showing operation of a power supply device concerning a 2nd embodiment of the present invention. It is a circuit diagram for showing operation of a power supply device concerning a 2nd embodiment of the present invention. It is a circuit diagram which shows the structure of the power supply apparatus which concerns on a 1st prior art example. It is a circuit diagram for demonstrating the structure of the power supply apparatus which concerns on a 2nd prior art example. It is a circuit diagram for demonstrating operation
  • the voltage drop between the drain and the source is about 0.4 V under the condition that power is supplied to the drain of the enhancement type FET and an appropriate voltage is applied to the gate. Let's talk about time as if the enhancement FET is on.
  • the enhancement type FET is off regardless of the drain and source voltage values.
  • the depletion type FET is supplied with power to its drain and the appropriate voltage for turning off the FET is not applied to the gate, the depletion type FET is turned on. .
  • the case where power is supplied to the drain and an appropriate voltage for turning off the FET is applied to the gate is assumed to be that the depletion type FET is turned off.
  • the battery output voltage is assumed to be a normal output voltage of 12V, but the voltage value will change from 9V to about 16V. Further, it is assumed that the load circuit and the booster circuit can operate at a power supply voltage of 7V to 13V, and that the power supply voltage from 7V to 13V is supplied to the load circuit and the booster circuit.
  • the power supply to the load circuit refers to the power supply when the load circuit is driven by the control signal from the control circuit. In the state where the voltage is simply supplied to the output terminal, It does not say that it is supplying power to the circuit.
  • the names of the standby signal SG1off and the standby release signal SG1on are used as the first control signal SG1 from the control circuit to the booster circuit and the load circuit.
  • the standby signal SG1off is a control signal for stopping the operation of the target circuit
  • the standby release signal SG1on is a signal for starting up and operating the target circuit whose operation is stopped.
  • the name of the second control signal SG2 is used as a control signal from the control circuit to the depletion type FET.
  • the second control signal SG2 is a control signal for turning off the depletion type FET.
  • the second control signal SG2 is not output, and the description will be made on the assumption that the connection between the control circuit and the depletion type FET can be opened.
  • FIG. 1 is a circuit diagram showing a configuration of a power supply apparatus 100 according to the first embodiment of the present invention.
  • the first FET circuit 1, the second FET circuit 2, and these circuits according to the first embodiment It is a circuit diagram which shows the relationship with a block.
  • the power supply device 100 includes an input terminal 11 to which power is supplied from a battery 51, an output terminal 12 to which a load circuit 52 is connected, a drain D1 connected to the input terminal 11, and an output terminal.
  • 12 includes a first FET 1a to which a source S1 is connected.
  • a resistor 1b is connected between the drain D1 and the gate G1 of the first FET 1a, and the first FET circuit 1 is constituted by the first FET 1a and the resistor 1b.
  • the first FET 1a is an enhancement type FET.
  • the second FET 2a is connected to the first FET 1a.
  • the second FET 2a is a depletion type FET.
  • the drain D2 of the depletion type FET that is the second FET 2a is connected to the drain D1 of the enhancement type FET that is the first FET 1a, and the source S2 of the depletion type FET is connected to the source S1 of the enhancement type FET.
  • a resistor 2b is connected between the drain D2 and the gate G2 of the second FET 2a, and the second FET 2a and the resistor 2b constitute the second FET circuit 2.
  • the first FET 1a will be referred to as an enhancement type FET 1a
  • the second FET 2a will be referred to as a depletion type FET 2a.
  • the power supply apparatus 100 includes a booster circuit 3 that is connected to the output terminal 12 and boosts an output voltage from the output terminal 12, and a control circuit 4 that controls the booster circuit 3. .
  • the booster circuit 3 has its output terminal connected to the gate G1 of the enhancement type FET 1a so that the boosted voltage is applied to the gate G1 of the enhancement type FET 1a.
  • the control circuit 4 is connected to the booster circuit 3 in order to control the booster circuit 3, and is also connected to the gate G2 of the depletion type FET 2a in order to control the depletion type FET 2a.
  • the control circuit 4 is also connected to the load circuit 52, and is configured to control the load circuit 52 simultaneously with controlling the booster circuit 3.
  • the power supply voltage of the control circuit 4 is always supplied from the battery 51 via a regulator (not shown) in a separate system. Further, the power supply voltage value of the control circuit 4 is configured to use 5V.
  • the enhancement type FET 1a is an element that is turned off when the same voltage is supplied to the drain D1 and the gate G1 of the enhancement type FET 1a.
  • the depletion type FET 2a is an element that can be turned on when the same voltage is supplied to the drain D2 and the gate G2 of the depletion type FET 2a. In this state, when the second control signal SG2 is not applied from the control circuit 4 to the gate G2 of the depletion type FET 2a, that is, when the connection between the gate G2 of the depletion type FET 2a and the control circuit 4 is open, the depletion type FET 2a Is on.
  • the same voltage is supplied from the battery 51 to the drain D1 and the gate G1 of the enhancement type FET 1a, and at the same time, the same is applied to the drain D2 and the gate G2 of the depletion type FET 2a. Voltage is being supplied.
  • the second control signal SG2 from the control circuit 4 is not applied to the gate G2 of the depletion type FET 2a. Therefore, the enhancement type FET 1a is in an off state and the depletion type FET 2a is in an on state.
  • the standby signal SG1off is supplied from the control circuit 4 to the booster circuit 3 as the first control signal SG1.
  • the control circuit 4 supplies the first control signal SG1 to the booster circuit 3 and the same first control signal SG1 to the load circuit 52 at the same time. Therefore, before the start of power supply to the load circuit 52, the standby signal SG1off is supplied to the booster circuit 3 and the load circuit 52, and the operations of the booster circuit 3 and the load circuit 52 are stopped.
  • the standby release signal SG1on is output as the first control signal SG1 from the control circuit 4, and the booster circuit 3 and the load circuit 52 are made operable.
  • the depletion type FET 2a is in an on state, a voltage is supplied to the booster circuit 3 via the depletion type FET 2a. In this state, the standby release signal SG1on is supplied from the control circuit 4 to the booster circuit 3.
  • the booster circuit 3 to which the standby release signal SG1on is supplied boosts the voltage supplied via the depletion type FET 2a and applies it to the gate G1 of the enhancement type FET 1a to turn on the enhancement type FET.
  • the booster circuit 3 is configured by a circuit called a charge pump circuit, and has a function of boosting the supplied voltage to twice the voltage.
  • the charge pump circuit includes an oscillation circuit (not shown) and a multistage capacitor group (not shown) that is sequentially charged and discharged by the oscillation of the oscillation circuit.
  • the voltage stored in the last capacitor of the capacitor group is output from the output terminal of the booster circuit 3. Since such a circuit configuration is a well-known circuit configuration, detailed description thereof is omitted.
  • the output voltage Vout is output to the output terminal 12 via the enhancement type FET 1a.
  • the output voltage Vout is supplied to the load circuit 52 to which the standby release signal SG1on is supplied, and the load circuit 52 starts its operation. Further, a voltage is supplied to the booster circuit 3 via the enhancement type FET 1a, and the supplied voltage is boosted and continuously applied to the gate G1 of the enhancement type FET 1a.
  • the depletion type FET 2a is turned off by the second control signal SG2 from the control circuit 4.
  • the depletion type FET 2a can be turned off.
  • the power supply device 100 supplies the voltage to the booster circuit 3 via the depletion type FET 2a that is already turned on when the power supply to the load circuit 52 is started. .
  • the voltage drop when the depletion type FET 2a is on is about 0.4V. Therefore, the power supply apparatus 100 according to the first embodiment of the present invention has a booster circuit 803 of the second conventional example, which is approximately the same as when the output voltage of the enhancement type FET 801a having a voltage drop of approximately 2 V is supplied.
  • a voltage higher by 1.6 V can be supplied to the booster circuit 3. Therefore, even when the voltage output from the battery 51 decreases, the voltage supplied to the booster circuit can be set to the required voltage, and the enhancement FET 1a can be turned on. Therefore, the power to the load circuit 52 can be stably supplied.
  • FIG. 2 is a circuit diagram showing the configuration of the third FET circuit 21 and the fourth FET circuit 22 of the power supply apparatus 200 according to the second embodiment of the present invention, and the relationship between these circuits and other blocks.
  • the booster circuit 3 the control circuit 4, and the like, the same reference numerals as those in the first embodiment are used for those having the same functions as those in the first embodiment.
  • the block configuration of the power supply apparatus 200 according to the second embodiment of the present invention will be described with reference to FIG.
  • the power supply device 200 according to the second embodiment of the present invention is an embodiment having a configuration closer to the actual product configuration than the power supply device 100 according to the first embodiment of the present invention.
  • the power supply device 200 includes an input terminal 11 to which a battery 51 is connected, a third FET circuit 21, an output terminal 12 to which a load circuit 52 is connected, a fourth FET circuit 22, and a booster circuit. 3, a control circuit 4, and a protection circuit 31.
  • the third FET circuit 21 is connected between the input terminal 11 and the output terminal 12.
  • the booster circuit 3 is connected to the output terminal 12 and the output voltage Vout from the output terminal 12 is supplied as a power supply voltage.
  • the booster circuit 3 boosts the output voltage Vout from the output terminal 12 to the third FET circuit 21. It is configured to supply.
  • a protection circuit 31 is connected between the output terminal 12, the third FET circuit 21, and the ground.
  • a control circuit 4 is provided to control the operation of the circuit in the apparatus.
  • the control circuit 4 is connected to the booster circuit 3 in order to control the booster circuit 3.
  • the control circuit 4 is also connected to the load circuit 52, and is configured to control the load circuit 52 simultaneously with controlling the booster circuit 3.
  • the power supply voltage of the control circuit 4 is always supplied from the battery 51 via a regulator (not shown) in a separate system. Further, the power supply voltage value of the control circuit 4 is configured to use 5V.
  • the fourth FET circuit 22 is connected in parallel to the third FET circuit 21.
  • the control circuit 4 is also connected to the fourth FET circuit 22 in order to control the fourth FET circuit 22.
  • the circuit configuration of the power supply device 200 will be described in detail with reference to FIG. 2, focusing on the third FET circuit 21 and the fourth FET circuit 22.
  • the third FET circuit 21 includes an enhancement type FET 21a connected between the input terminal 11 and the output terminal 12, a resistor 21b, a diode 21c, and a diode 21d.
  • the protection circuit 31 is connected between the output terminal 12 and the gate G1 of the enhancement type FET 1a and the ground.
  • the protection circuit 31 is configured using a Zener diode (not shown), and is a circuit for controlling the output voltage Vout at the output terminal 12 so as not to exceed a predetermined voltage.
  • a Zener diode not shown
  • omitted since the structure of the protection circuit 31 in 2nd Embodiment is known, detailed description is abbreviate
  • the anode of the diode 21c is connected to the input terminal 11
  • the drain D3 of the enhancement type FET 21a is connected to the cathode of the diode 21c
  • the source S3 of the enhancement type FET 21a is connected to the output terminal 12.
  • a gate G3 of the enhancement type FET 21a is connected to the input terminal 11 through a series connection circuit of a diode 21d and a resistor 21b, and is connected to the output terminal of the booster circuit 3.
  • the diode 21c and the diode 21d are diodes for preventing reverse connection. These diodes break down the power supply device 200 and the load circuit 52 when the power output terminal and the ground terminal of the battery 51 are connected to the input terminal 11 and the ground terminal of the power supply device 200 in reverse. Has been inserted so as not to. When the voltage from the battery 51 is supplied to the input terminal 11, a voltage drop of about 1 V occurs between the anode and cathode of the diode 21c and the diode 21d.
  • the voltage output from the booster circuit 3 is applied to the gate G3 of the FET 21a.
  • the booster circuit 3 is connected to the control circuit 4 and is controlled by the first control signal SG1 from the control circuit 4. Prior to the start of the supply of drive power to the load circuit 52, the booster circuit 3 receives the standby signal SG1off from the control circuit 4 as the first control signal SG1, and stops the operation of the circuit.
  • the booster circuit 3 is set to perform a boost operation after the power supply voltage supplied to the booster circuit 3 is 7 V or more and the standby release signal SG1on from the control circuit 4 is input.
  • the fourth FET circuit 22 has a depletion type FET 22a, a resistor 22b, and a Zener diode 22c.
  • the depletion type FET 22a has a drain D4 connected to the drain D3 of the enhancement type FET 21a and a source S4 connected to the source S3 of the enhancement type FET 21a.
  • a depletion type FET has an operation region that is turned on even when the gate voltage is lower than the source voltage. For example, it is turned on even if the gate voltage is about 2 V lower than the source voltage. Therefore, the depletion type FET can be turned off by setting the gate voltage to be lower than the source voltage by a predetermined voltage (about 3 V) or more. For example, when the source voltage of the depletion type FET is equal to or higher than a predetermined voltage (about 3 V), the gate voltage can be set to 0 V to turn it off.
  • a depletion type FET has few elements capable of flowing a large current of several A or more like an enhancement type FET, and can only supply a current of about 1 A. Therefore, a method of using a large current through the depletion type FET is rarely used. Further, such a depletion type FET is likely to be very expensive even if it exists, and is not generally used.
  • a depletion type MOS • FET Metal • Oxide • Semiconductor • Field • Effect • Transistor
  • the depletion type MOS • FET can be used from a negative voltage to a positive voltage as a gate voltage with respect to the source, and is therefore easy to use.
  • the resistor 22b is connected between the drain D4 and the gate G4 of the depletion type FET 22a.
  • the zener diode 22c is connected between the gate G4 of the depletion type FET 22a and the ground.
  • the Zener diode 22c has a Zener voltage value set so that a voltage higher than the threshold is not applied to the gate G4 of the depletion type FET 22a even when a high voltage higher than a certain threshold (Zener voltage) is externally applied to the gate G4. ing.
  • the Zener voltage value is set to 17.5V.
  • the output terminal of the control circuit 4 is connected to the gate G4 of the depletion type FET 22a.
  • the control circuit 4 is configured to output a second control signal SG2 for turning off the depletion type FET 22a. For example, when 0V is applied to the gate G2 of the depletion type FET 22a as the second control signal SG2 from the control circuit 4, the depletion type FET 22a is turned off.
  • the control circuit 4 and the gate G2 of the depletion type FET 2a are disconnected. Since the resistor 22b is connected between the drain D4 and the gate G4 of the depletion type FET 22a, the same voltage as the drain D4 is applied to the gate G4, and the depletion type FET 2a is turned on.
  • FIG. 2 The operation of the power supply apparatus 200 shown in FIG. 2 from when the power supply to the load circuit 52 is started until the power is supplied when the voltage of the battery 51 is in a normal state (about 12 V) is shown in FIG. This will be described with reference to 3 (a) and FIG. 3 (b).
  • the operation of the power supply device 200 when the voltage of the battery 51 is lowered will be described with reference to FIGS. 4 (a) and 4 (b).
  • the required output voltage (Vout) is assumed to be 7V or more and less than 13V.
  • the enhancement type FET 21a is supplied with the voltage Vin via the diode 21c. Since there is a voltage drop of about 1V between both ends of the diode 21c, the voltage 11V is applied to the drain D3 of the enhancement type FET 21a, but the standby signal SG1off is input from the control circuit 4 to the booster circuit 3. Therefore, no voltage is applied from the booster circuit 3 to the gate G3 of the enhancement type FET 21a, and the enhancement type FET 21a is turned off.
  • the control circuit 4 does not output a signal for turning off the depletion type FET 22a, and is disconnected from the gate G4 of the depletion type FET 22a. Therefore, since the voltage of the gate G4 of the depletion type FET 22a is the same as the voltage of the drain D4 of the depletion type FET 22a, the depletion type FET 22a is on.
  • the output terminal 12 outputs a voltage of 10.6 V via the depletion type FET 22a as the output voltage Vout.
  • the standby signal SG1off is input from the control circuit 4 to the booster circuit 3 and the load circuit 52 as described above. Therefore, an appropriate voltage for turning on the enhancement type FET 21a is not applied to the gate G3 of the enhancement type FET 21a. Therefore, the enhancement type FET 21a is still off.
  • FIG. 3B shows a state after the standby release signal SG1on is input from the control circuit 4 to the booster circuit 3 and the load circuit 52.
  • the booster circuit 3 outputs 21.2V, which is twice the voltage of 10.6V, and is applied to the gate G3 of the enhancement type FET 21a.
  • 21.2 V is applied to the gate G1
  • the enhancement type FET 21a is turned on, and a voltage is output to the output terminal 12 via the enhancement type FET 21a. Since the voltage drop is 0.4V after the enhancement type FET 21a is turned on, 10.6V is output to the output terminal 12.
  • the depletion type FET 22a is turned off after the booster circuit 3 has been started. Although the depletion type FET 2a cannot flow a large current of several A, it can flow a necessary current to the booster circuit 3. Therefore, there is no problem in using it for starting up the booster circuit 3. .
  • the second control signal SG2 is applied to the gate G4 of the depletion type FET 22a. Specifically, 0 V is applied from the control circuit 4 to the gate G2 of the depletion type FET 2a. For this reason, a voltage 10.6V lower than the source S2 is applied to the gate G2 of the depletion type FET 2a. Therefore, the depletion type FET 2a is turned off.
  • the operation of the power supply device 200 when the voltage Vin at the input terminal 11, that is, the voltage from the battery 51 is lowered to a voltage lower than the normal voltage 12 V, for example, 9 V, for example, due to low temperature or the like will be described.
  • 4A and 4B show the states before and after the start of power supply for driving the load circuit 52 when the voltage at the input terminal 11 is lowered to 9 V in the power supply apparatus 200 shown in FIG. Show.
  • the enhancement type FET 21a is supplied with the voltage Vin via the diode 21c. Since there is a voltage drop of about 1V across the diode 21c, a voltage of 8V is applied to the drain D3 of the enhancement type FET 21a. However, since the standby signal SG1off is input from the control circuit 4 to the booster circuit 3 and the load circuit 52, no voltage is applied from the booster circuit 3 to the gate G3 of the enhancement type FET 21a, and the enhancement type FET 21a is turned off. ing.
  • a voltage is supplied to the drain D4 of the depletion type FET 22a through the diode 21c, and a voltage is supplied to the gate G4 through the diode 21c and the resistor 22b. Accordingly, the voltage 8V is applied to the drain D4 and the gate G4 of the depletion type FET 22a, similarly to the enhancement type FET 21a.
  • the control circuit 4 does not output a signal for turning off the depletion type FET 22a, and is disconnected from the gate G4 of the depletion type FET 22a. Therefore, since the voltage of the gate G4 of the depletion type FET 22a is the same as the voltage of the drain D4 of the depletion type FET 22a, the depletion type FET 22a is on.
  • the output terminal 12 outputs a voltage 7.6 V via the depletion type FET 22a as the output voltage Vout.
  • the standby signal SG1off is input from the control circuit 4 to the booster circuit 3 and the load circuit 52. Therefore, an appropriate voltage for turning on the enhancement type FET 21a is not applied to the gate of the enhancement type FET 21a. Therefore, the enhancement type FET 21a is still off.
  • FIG. 4B shows a state after the standby release signal SG1on is input from the control circuit 4 to the booster circuit 3 and the load circuit 52.
  • the booster circuit 3 outputs 15.2V, which is twice the voltage of 7.6V, and is applied to the gate G3 of the enhancement type FET 21a.
  • 15.2 V is applied to the gate G3
  • the enhancement type FET 21a is turned on, and a voltage is output to the output terminal 12 via the enhancement type FET 21a. Note that, after the enhancement type FET 21a is turned on, the voltage drop is 0.4V, so 7.6V is output to the output terminal 12.
  • the output voltage Vout at the output terminal 12 is 7.6V, which is the voltage at which the booster circuit 3 can operate. It can be. Therefore, even when the voltage from the battery 51 drops to 9V, the same operation as when the voltage from the battery 51 is 12V can be expected.
  • the discussion has been made assuming that the voltage at which the booster circuit 3 can operate is 7 V or more. However, when the operating voltage of the booster circuit 3 is from a lower voltage, for example, the voltage from the battery 51 can of course correspond to a lower voltage.
  • the power supply apparatus 200 can stably supply power to the load circuit 52 even when the voltage from the battery 51 decreases.
  • the voltage from the battery 51 is normally 12V and the case where the voltage is lowered to 9V has been described.
  • the voltage from the battery 51 may rise over 12V to about 16V even in normal times. For example, when the engine is started, since the battery is charged, its output voltage rises. In recent vehicles such as hybrid cars, charging is performed even during deceleration, and the output voltage of the battery increases.
  • the protection circuit 31 provided in the power supply device 200 can prevent a voltage higher than a predetermined output voltage from being supplied to the load circuit 52.
  • the protection circuit 31 includes a transistor (not shown) and a Zener diode (not shown). By setting the Zener voltage of the Zener diode to an appropriate value, the output voltage at the output terminal 12 is regulated. The voltage value (13V) is not exceeded.
  • the power supply device 200 of the present invention described so far has been described on the assumption that the battery 51 is mounted on the vehicle. Therefore, the power supply device 200 configured in this way can operate the electronic devices in the vehicle without any trouble even at low temperatures.
  • the power supply device 200 of the present invention is not limited to a battery mounted on a vehicle, but can be applied to a battery mounted on various devices other than the vehicle.
  • the power supply device 100 according to the first embodiment of the present invention or the power supply device 200 according to the second embodiment supplies the booster circuit 3 even when the voltage output from the battery 51 decreases. To a sufficiently high voltage. Therefore, even when the voltage output from the battery 51 is reduced, the power for driving the load circuit 52 can be stably supplied.

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Abstract

[Problem] To provide a power supply device capable of reliably supplying power to a load circuit even in a case in which output voltage of a battery has decreased. [Solution] The invention is provided with: a first FET (1a) in which a drain (D1) is connected to an input terminal (11), a source (S1) is connected to an output terminal (12), and which is off in a state in which the same voltage is supplied to the drain (D1) and a gate (G1); a boosting circuit (3) which boosts output voltage from the output terminal (12); and a control circuit (4) which is connected to the boosting circuit (3) and a load circuit (52). It is possible to set the invention on in a state in which the same voltage is supplied to a drain (D2) and a gate (G2), and the invention is set so that: a second FET (2a), which can be controlled by the control circuit (4), is connected to the first FET (1a); at a start time of power supply to the load circuit (52), the second FET (2a) is set on; and voltage is supplied to the boosting circuit (3) via the second FET (2a).

Description

電源供給装置Power supply device
　本発明は電源供給装置に係り、特に車載用バッテリに接続された電源供給装置に係わる。 The present invention relates to a power supply device, and more particularly to a power supply device connected to an in-vehicle battery.
　従来より、自動車等に搭載されている電子機器には、車載用バッテリから電源が供給されている。また、車載用バッテリには、電子機器内の負荷回路を駆動するための電源供給装置が接続されている。 Conventionally, power is supplied from an in-vehicle battery to an electronic device mounted on an automobile or the like. In addition, a power supply device for driving a load circuit in the electronic device is connected to the in-vehicle battery.
　電源供給装置では、近年、ＦＥＴ（Field Effect Transistor（電界効果トランジスタ））を使用して負荷回路を駆動するための電源を供給し、制御するように構成されている。特に、エンハンスメント型ＦＥＴは、スイッチング動作を容易に行えるため、車載電子機器内の電源供給装置に用いられるようになっている。また、ＦＥＴの駆動用に昇圧回路が用いられるようになっている。特許文献１には、電源供給装置のＦＥＴを駆動するため、昇圧回路を利用した車載電子機器が開示されている。 In recent years, the power supply device is configured to supply and control power for driving a load circuit using an FET (Field Effect Transistor). In particular, enhancement-type FETs can be easily switched, so that they are used for power supply devices in in-vehicle electronic devices. In addition, a booster circuit is used for driving the FET. Patent Document 1 discloses an in-vehicle electronic device that uses a booster circuit to drive an FET of a power supply device.
　図５に、特許文献１に開示された電子制御装置９４１のための電源供給装置９００を、第１従来例として示す。尚、今後、従来例の各回路で、ＦＥＴのゲートに適正な電圧が印加されており、ＦＥＴのドレイン・ソース間の電圧降下が０．４Ｖ程度の時の状態を、ＦＥＴがオンの状態であるとして話を進める。また、ＦＥＴのドレインとゲートにほぼ同一の電圧が印加されているか、ＦＥＴのドレイン・ソース間の電圧降下が２Ｖ程度の時の状態をＦＥＴがオフの状態であるとして話を進める。 FIG. 5 shows a power supply device 900 for the electronic control device 941 disclosed in Patent Document 1 as a first conventional example. In the future, in each conventional circuit, an appropriate voltage is applied to the gate of the FET, and the voltage drop between the drain and source of the FET is about 0.4 V. Proceed as if there is. Further, the discussion will be made assuming that the FET is in an off state when substantially the same voltage is applied to the drain and the gate of the FET or when the voltage drop between the drain and the source of the FET is about 2V.
　電源供給装置９００には、バッテリ９０３に接続された電源端子９０５と、電源端子９０５に接続されたＦＥＴ９２１が備えられている。ＦＥＴ９２１を駆動するには、ゲートの電圧をソースの電圧より所定電圧（約３Ｖ）以上高くする必要があり、そのために、ＦＥＴ９２１のゲートには昇圧回路９４３の出力端が接続されている。 The power supply apparatus 900 includes a power supply terminal 905 connected to the battery 903 and an FET 921 connected to the power supply terminal 905. In order to drive the FET 921, the gate voltage needs to be higher than the source voltage by a predetermined voltage (about 3 V). For this purpose, the output terminal of the booster circuit 943 is connected to the gate of the FET 921.
　昇圧回路９４３は、バッテリ９０３の電圧ＶＢよりも所定電圧以上高い電圧を生成して、その生成した昇圧電圧をＦＥＴ９２１のゲートに印加することによりＦＥＴ９２１をオンさせるように構成されている。 The booster circuit 943 is configured to generate a voltage higher than the voltage VB of the battery 903 by a predetermined voltage or more and apply the generated boosted voltage to the gate of the FET 921 to turn on the FET 921.
　図５に示した電源供給装置９００における動作をわかりやすく説明するために、ＦＥＴと昇圧回路を用いた一般的な従来の電源供給装置の構成を、第２従来例として図６に示す。 In order to explain the operation of the power supply apparatus 900 shown in FIG. 5 in an easy-to-understand manner, the configuration of a general conventional power supply apparatus using an FET and a booster circuit is shown in FIG.
　図６に示すように、従来の車載用の電源供給装置８００は、バッテリ８５１に接続される入力端子８１１と、ＦＥＴ回路８０１と、負荷回路８５２が接続される出力端子８１２と、昇圧回路８０３と、制御回路８０４とから構成されている。 As shown in FIG. 6, a conventional on-vehicle power supply device 800 includes an input terminal 811 connected to a battery 851, an FET circuit 801, an output terminal 812 connected to a load circuit 852, and a booster circuit 803. And a control circuit 804.
　ＦＥＴ回路８０１においては、保護用のダイオード８０１ｃのアノードが入力端子８１１に接続され、保護用のダイオード８０１ｃのカソードが、ＦＥＴ８０１ａのドレインＤ０に接続され、ＦＥＴ８０１ａのソースＳ０が出力端子８１２に接続されている。また、抵抗８０１ｂと保護用のダイオード８０１ｄとが直列接続されて、ＦＥＴ８０１ａのゲートＧ０と入力端子８１１との間に接続されている。 In the FET circuit 801, the anode of the protective diode 801c is connected to the input terminal 811, the cathode of the protective diode 801c is connected to the drain D0 of the FET 801a, and the source S0 of the FET 801a is connected to the output terminal 812. Yes. A resistor 801b and a protective diode 801d are connected in series, and are connected between the gate G0 of the FET 801a and the input terminal 811.
　昇圧回路８０３には、出力端子８１２からの出力電圧Ｖｏｕｔが電源電圧として供給され、その出力端は、ＦＥＴ８０１ａのゲートＧ０に接続されている。尚、昇圧回路８０３は、動作時の内部損失が過大にならないように７Ｖ以上で動作するように設計されている。また、制御回路８０４は、昇圧回路８０３の動作を制御すると共に、負荷回路８５２の動作を制御するために設けられている。尚、ＦＥＴ８０１ａとしては、エンハンスメント型ＦＥＴを使用しており、また、負荷回路８５２としては、約３Ａ以上の電流が流れる回路を想定している。 The booster circuit 803 is supplied with the output voltage Vout from the output terminal 812 as a power supply voltage, and its output terminal is connected to the gate G0 of the FET 801a. Note that the booster circuit 803 is designed to operate at 7 V or higher so that internal loss during operation does not become excessive. The control circuit 804 is provided for controlling the operation of the booster circuit 803 and controlling the operation of the load circuit 852. Note that an enhancement type FET is used as the FET 801a, and a circuit through which a current of about 3 A or more flows is assumed as the load circuit 852.
　ＦＥＴ８０１ａをオンするには、ＦＥＴ８０１ａのゲートＧの電圧を、ソースＳの電圧より所定電圧（約３Ｖ）以上高くする必要がある。そのため、昇圧回路８０３を動作させ、昇圧回路８０３から出力される電圧をＦＥＴ８０１ａのゲートに印加するように構成されている。昇圧回路８０３では、昇圧回路８０３に供給される電圧を、約２倍の大きさの電圧に昇圧して出力するように構成されている。 In order to turn on the FET 801a, the voltage of the gate G of the FET 801a needs to be higher than the voltage of the source S by a predetermined voltage (about 3V) or more. Therefore, the booster circuit 803 is operated, and the voltage output from the booster circuit 803 is applied to the gate of the FET 801a. The booster circuit 803 is configured to boost the voltage supplied to the booster circuit 803 to a voltage approximately twice as large as the voltage output.
　電源供給装置８００において、バッテリ８５１の電源電圧が通常の１２Ｖである場合の動作について図７（ａ）、図７（ｂ）を用いて説明する。 Operation in the power supply apparatus 800 when the power supply voltage of the battery 851 is a normal 12V will be described with reference to FIGS. 7 (a) and 7 (b).
　図７（ａ）は、ＦＥＴ８０１ａがオンする前の状態を表している。図７（ａ）において、昇圧回路８０３には、電源電圧として９Ｖが供給されているため、倍電圧発生回路である昇圧回路８０３の出力端には、９Ｖの２倍の１８Ｖが出力される。従って、ソースＳ０に対するゲートＧ０の電圧が９Ｖとなることによって、ＦＥＴ８０１ａをオンとすることができる。 FIG. 7A shows a state before the FET 801a is turned on. In FIG. 7A, since 9V is supplied to the booster circuit 803 as the power supply voltage, 18V, which is twice 9V, is output to the output terminal of the booster circuit 803 which is a voltage doubler generation circuit. Accordingly, when the voltage of the gate G0 with respect to the source S0 becomes 9V, the FET 801a can be turned on.
　ＦＥＴ８０１ａがオンとなった場合の状態を図７（ｂ）に示す。ＦＥＴ８０１ａがオンとなっている時、出力端子８１２における出力電圧Ｖｏｕｔは１０．６Ｖとなる。図７（ｂ）において、ＦＥＴ８０１ａのゲートＧ０に２１．２Ｖが印加されているため、ＦＥＴ８０１ａはオンとなった状態を保つことができる。尚、負荷回路８５２が動作可能となる出力電圧（Ｖｏｕｔ）としては、７Ｖ以上１３Ｖ未満を想定している。上記の通り、入力端子８１１における電圧Ｖｉｎが通常の電圧１２Ｖであれば、特に問題はない。 FIG. 7B shows a state when the FET 801a is turned on. When the FET 801a is on, the output voltage Vout at the output terminal 812 is 10.6V. In FIG. 7B, since 21.2 V is applied to the gate G0 of the FET 801a, the FET 801a can be kept on. Note that the output voltage (Vout) at which the load circuit 852 can operate is assumed to be 7 V or more and less than 13 V. As described above, there is no particular problem if the voltage Vin at the input terminal 811 is the normal voltage 12V.
特開２００７－０８２３７４号公報JP 2007-082374 A
　しかしながら、図５又は図６に示す従来の電源供給装置９００又は８００には、入力端子８１１における電圧が、例えば９Ｖまで下がった場合、以下のような問題が発生する。 However, the conventional power supply apparatus 900 or 800 shown in FIG. 5 or 6 has the following problem when the voltage at the input terminal 811 drops to, for example, 9V.
　図６に示す電源供給装置８００において、入力端子８１１における電圧Ｖｉｎが９Ｖまで下がった時の、負荷回路８５２への電源供給開始時前後の状態を、図７（ｃ）に示す。 FIG. 7C shows the state before and after the start of power supply to the load circuit 852 when the voltage Vin at the input terminal 811 is lowered to 9 V in the power supply apparatus 800 shown in FIG.
　昇圧回路８０３は、Ｖｏｕｔが７Ｖ以上の電圧で動作するように設計されている。入力端子８１１における電圧が９Ｖまで下がった時、出力端子８１２における出力電圧Ｖｏｕｔ即ち昇圧回路８０３の電源電圧は、６Ｖまで下がってしまう。昇圧回路８０３は、７Ｖ以上で動作するように設計されているので、Ｖｏｕｔが６Ｖまで下がった場合、昇圧回路８０３は動作できなくなってしまう。そのため、昇圧回路８０３から、ＦＥＴ８０１ａがオンするために必要な電圧が、ＦＥＴ８０１ａのゲートＧ０に印加されず、ＦＥＴ８０１ａの状態は変化せずに、図７（ｃ）に示す状態のままである。従って、ＦＥＴ８０１ａをオンさせることができない状態となっている。 The booster circuit 803 is designed to operate with a voltage of Vout of 7V or higher. When the voltage at the input terminal 811 decreases to 9V, the output voltage Vout at the output terminal 812, that is, the power supply voltage of the booster circuit 803 decreases to 6V. Since the booster circuit 803 is designed to operate at 7 V or higher, the booster circuit 803 cannot operate when Vout decreases to 6 V. Therefore, the voltage necessary for turning on the FET 801a from the booster circuit 803 is not applied to the gate G0 of the FET 801a, and the state of the FET 801a remains unchanged and remains as shown in FIG. Therefore, the FET 801a cannot be turned on.
従って、バッテリ８５１からの電圧、即ち入力端子８１１における電圧Ｖｉｎが、９Ｖとなった場合、ＦＥＴ８０１ａをオンさせることができなくなる。よって、入力端子８１１における電圧Ｖｉｎが低下した場合、負荷回路８５２に電源を供給することができなくなってしまうという問題が、従来技術の電源供給装置８００にはあった。 Therefore, when the voltage from the battery 851, that is, the voltage Vin at the input terminal 811 becomes 9V, the FET 801a cannot be turned on. Therefore, when the voltage Vin at the input terminal 811 decreases, the conventional power supply apparatus 800 has a problem in that power cannot be supplied to the load circuit 852.
　本発明は、このような従来技術の実情に鑑みてなされたもので、その目的は、バッテリから出力される電圧が低下した場合においても、負荷回路を駆動するための電源を安定して供給することができる電源供給装置を提供することにある。 The present invention has been made in view of the actual situation of the prior art, and an object of the present invention is to stably supply power for driving the load circuit even when the voltage output from the battery is lowered. It is an object of the present invention to provide a power supply device that can perform the above-described operation.
　この課題を解決するために、本発明の電源供給装置は、バッテリから電源が供給される入力端子と、負荷回路が接続される出力端子と、前記入力端子にドレインが接続され、前記出力端子にソースが接続された第１ＦＥＴと、前記出力端子に接続され、前記出力端子からの出力電圧を昇圧する昇圧回路と、前記昇圧回路及び前記負荷回路に接続された制御回路と、を備え、前記第１ＦＥＴは、前記第１ＦＥＴのドレインとゲートに同一電圧が供給されている状態ではオフとなっている素子であり、前記昇圧回路によって昇圧された電圧を前記第１ＦＥＴのゲートに印加して前記第１ＦＥＴをオンさせることによって前記負荷回路に電源を供給する電源供給装置であって、前記制御回路により制御可能とされる第２ＦＥＴを設け、前記第２ＦＥＴのドレインを前記第１ＦＥＴのドレインに接続すると共に、前記第２ＦＥＴのソースを前記第１ＦＥＴのソースに接続し、前記第２ＦＥＴは、前記第２ＦＥＴのドレインとゲートに同一電圧が供給されている状態ではオンとしておくことが可能な素子であり、前記負荷回路への電源供給開始時より前に、前記第２ＦＥＴをオンとしておくと共に、前記電源供給開始時に、前記第２ＦＥＴを介して前記昇圧回路に電圧を供給するようにしたという特徴を有する。 In order to solve this problem, the power supply device of the present invention includes an input terminal to which power is supplied from a battery, an output terminal to which a load circuit is connected, a drain connected to the input terminal, and the output terminal. A first FET to which a source is connected; a booster circuit that is connected to the output terminal and boosts an output voltage from the output terminal; and a control circuit that is connected to the booster circuit and the load circuit. The 1FET is an element that is turned off when the same voltage is supplied to the drain and gate of the first FET, and a voltage boosted by the booster circuit is applied to the gate of the first FET. A power supply device for supplying power to the load circuit by turning on the second FET, the second FET being controllable by the control circuit, and the second F The drain of T is connected to the drain of the first FET, the source of the second FET is connected to the source of the first FET, and the second FET has the same voltage supplied to the drain and gate of the second FET Is an element that can be turned on, and before turning on the power supply to the load circuit, the second FET is turned on, and when the power supply is started, the booster circuit is connected to the load circuit via the second FET. It has a feature that voltage is supplied.
　このように構成された電源供給装置は、負荷回路への電源供給開始時に第２ＦＥＴをオンとしておくと共に、第２ＦＥＴを介して昇圧回路に電圧を供給するようにしたため、昇圧回路へ供給する電圧を十分高い電圧にすることができる。そのため、バッテリから出力される電圧が低下した場合においても、第１ＦＥＴをオンすることができるので、負荷回路を駆動するための電源を安定して供給することができる。 The power supply device configured as described above turns on the second FET when power supply to the load circuit is started and supplies the voltage to the booster circuit via the second FET. A sufficiently high voltage can be obtained. Therefore, even when the voltage output from the battery decreases, the first FET can be turned on, so that it is possible to stably supply power for driving the load circuit.
　また、上記の構成において、前記負荷回路への電源供給開始時より前に、前記第１ＦＥＴ及び前記第２ＦＥＴに前記バッテリから電圧が供給されていて、前記負荷回路への電源供給開始時に、前記制御回路からの第１制御信号によって前記昇圧回路を動作させて前記第１ＦＥＴをオンすると共に、前記負荷回路を動作可能としたという特徴を有する。 Further, in the above configuration, the voltage is supplied from the battery to the first FET and the second FET before the start of power supply to the load circuit, and the control is performed when the power supply to the load circuit is started. The booster circuit is operated by a first control signal from the circuit to turn on the first FET, and the load circuit can be operated.
　このように構成された電源供給装置は、負荷回路への電源供給開始時に、制御回路からの第１制御信号によって昇圧回路及び負荷回路を制御するようにしたので、電源供給開始の時期を明確に定めることができる。 The power supply device configured as described above controls the booster circuit and the load circuit with the first control signal from the control circuit when the power supply to the load circuit is started. Can be determined.
　また、上記の構成において、前記第１ＦＥＴがオンした後に、前記制御回路からの第２制御信号によって前記第２ＦＥＴをオフするようにしたという特徴を有する。 In the above-described configuration, the second FET is turned off by a second control signal from the control circuit after the first FET is turned on.
　このように構成された電源供給装置は、前記第１ＦＥＴががオンした後に、第２ＦＥＴをオフするようにしたので、負荷回路への電源供給開始後に必要のない第２ＦＥＴには、電流を流さないようにすることができる。 Since the power supply device configured as described above turns off the second FET after the first FET is turned on, no current flows through the second FET that is not necessary after the power supply to the load circuit is started. Can be.
　前記第１ＦＥＴはエンハンスメント型ＦＥＴであり、前記第２ＦＥＴはデプレッション型ＦＥＴであって、前記エンハンスメント型ＦＥＴのドレインとゲートが抵抗を介して接続されており、前記デプレッション型ＦＥＴのドレインとゲートが抵抗を介して接続されているという特徴を有する。 The first FET is an enhancement type FET, the second FET is a depletion type FET, and the drain and gate of the enhancement type FET are connected via a resistor, and the drain and gate of the depletion type FET have a resistance. It has the characteristic that it is connected via.
　このように構成された電源供給装置は、第２ＦＥＴとしてデプレッション型ＦＥＴを使用するようにしたので、負荷回路への電源供給開始時に、第２ＦＥＴをオンとしておくことができ、第２ＦＥＴの電圧降下が小さい状態で昇圧回路に電圧を供給することができる。 Since the power supply device configured as described above uses a depletion type FET as the second FET, the second FET can be turned on when the power supply to the load circuit is started, and the voltage drop of the second FET is reduced. A voltage can be supplied to the booster circuit in a small state.
　また、上記の構成において、前記デプレッション型ＦＥＴは、ＭＯＳ・ＦＥＴであるという特徴を有する。 Further, in the above configuration, the depletion type FET is characterized by being a MOS • FET.
　このように構成された電源供給装置は、デプレッション型ＦＥＴとして、ＭＯＳ・ＦＥＴを使用しているため、ソースに対するゲートの電圧を、負の電圧から正の電圧まで使用することができる。そのため、低い電圧で第２ＦＥＴのオン・オフを制御できるので、使い勝手が良く、負荷回路への電源供給開始時に、昇圧回路に容易に電源を供給することができる。 Since the power supply device configured as described above uses a MOS • FET as a depletion type FET, the gate voltage with respect to the source can be used from a negative voltage to a positive voltage. For this reason, since the ON / OFF of the second FET can be controlled with a low voltage, it is easy to use, and power can be easily supplied to the booster circuit when power supply to the load circuit is started.
　また、上記の構成において、車両に搭載されたバッテリに接続されているという特徴を有する。 Also, the above configuration has a feature that it is connected to a battery mounted on the vehicle.
　このように構成された電源供給装置は、低温時などで車両に搭載されたバッテリの電圧が低下した場合においても車両内の電子機器を支障なく動作させることができる。 The power supply device configured as described above can operate the electronic devices in the vehicle without any trouble even when the voltage of the battery mounted on the vehicle decreases at a low temperature or the like.
　本発明の電源供給装置は、バッテリから出力される電圧が低下した場合においても、負荷回路を駆動するための電源を安定して供給することができる。 The power supply device of the present invention can stably supply power for driving the load circuit even when the voltage output from the battery drops.
本発明の第１実施形態に係る電源供給装置の構成を示す回路図である。1 is a circuit diagram showing a configuration of a power supply device according to a first embodiment of the present invention. 本発明の第２実施形態に係る電源供給装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the power supply apparatus which concerns on 2nd Embodiment of this invention. 本発明の第２実施形態に係る電源供給装置の動作を示すための回路図である。It is a circuit diagram for showing operation of a power supply device concerning a 2nd embodiment of the present invention. 本発明の第２実施形態に係る電源供給装置の動作を示すための回路図である。It is a circuit diagram for showing operation of a power supply device concerning a 2nd embodiment of the present invention. 第１従来例に係る電源供給装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the power supply apparatus which concerns on a 1st prior art example. 第２従来例に係る電源供給装置の構成を説明するための回路図である。It is a circuit diagram for demonstrating the structure of the power supply apparatus which concerns on a 2nd prior art example. 第２従来例に係る電源供給装置の動作を説明するための回路図である。It is a circuit diagram for demonstrating operation | movement of the power supply apparatus which concerns on a 2nd prior art example.
　以下、本発明の実施形態について、図面を参照しながら説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　尚、今後、エンハンスメント型ＦＥＴに対し、そのドレインに電源が供給され、ゲートに適正な電圧が印加されているという条件の下で、ドレイン・ソース間の電圧降下が０．４Ｖ程度となっている時を、エンハンスメント型ＦＥＴがオンしているとして話を進める。また、エンハンスメント型ＦＥＴのドレインに電源が供給され、ドレインとゲートにほぼ同一の電圧が印加されている場合は、ドレイン及びソースの電圧値に関わらずエンハンスメント型ＦＥＴがオフしているとして話を進める。また、デプレッション型ＦＥＴに対し、そのドレインに電源が供給されている状態で、ゲートにＦＥＴをオフするための適正な電圧が印加されていない場合を、そのデプレッション型ＦＥＴがオンしているとする。また、そのドレインに電源が供給され、ゲートにＦＥＴをオフするための適正な電圧が印加されている場合をデプレッション型ＦＥＴがオフしているとして話を進める。 In the future, the voltage drop between the drain and the source is about 0.4 V under the condition that power is supplied to the drain of the enhancement type FET and an appropriate voltage is applied to the gate. Let's talk about time as if the enhancement FET is on. In addition, when power is supplied to the drain of the enhancement type FET and substantially the same voltage is applied to the drain and the gate, it is assumed that the enhancement type FET is off regardless of the drain and source voltage values. . In addition, when the depletion type FET is supplied with power to its drain and the appropriate voltage for turning off the FET is not applied to the gate, the depletion type FET is turned on. . Further, the case where power is supplied to the drain and an appropriate voltage for turning off the FET is applied to the gate is assumed to be that the depletion type FET is turned off.
　バッテリの出力電圧は、１２Ｖが通常の出力電圧であるとして話を進めるが、その電圧値は、９Ｖから約１６Ｖまで変化する可能性があるとして話を進める。また、負荷回路及び昇圧回路は、その電源電圧が７Ｖ以上１３Ｖ以下で動作可能であるとし、負荷回路及び昇圧回路へは、７Ｖから１３Ｖまでの電源電圧が供給されるとして話を進める。また、負荷回路への電源供給とは、制御回路からの制御信号により負荷回路を駆動させるようにした場合の電源供給を指し、ただ単に出力端子に電圧が供給されているだけの状態では、負荷回路へ電源供給しているとは言わない。 The battery output voltage is assumed to be a normal output voltage of 12V, but the voltage value will change from 9V to about 16V. Further, it is assumed that the load circuit and the booster circuit can operate at a power supply voltage of 7V to 13V, and that the power supply voltage from 7V to 13V is supplied to the load circuit and the booster circuit. The power supply to the load circuit refers to the power supply when the load circuit is driven by the control signal from the control circuit. In the state where the voltage is simply supplied to the output terminal, It does not say that it is supplying power to the circuit.
　制御回路から昇圧回路および負荷回路への第１制御信号ＳＧ１として、スタンバイ信号ＳＧ１ｏｆｆ、スタンバイ解除信号ＳＧ１ｏｎの名称を使用する。スタンバイ信号ＳＧ１ｏｆｆ、は対象の回路の動作を停止させておくための制御信号であり、スタンバイ解除信号ＳＧ１ｏｎは、動作を停止している対象の回路を立ち上げて動作させるための信号である。 The names of the standby signal SG1off and the standby release signal SG1on are used as the first control signal SG1 from the control circuit to the booster circuit and the load circuit. The standby signal SG1off is a control signal for stopping the operation of the target circuit, and the standby release signal SG1on is a signal for starting up and operating the target circuit whose operation is stopped.
　また、制御回路からデプレッション型ＦＥＴへの制御信号として、第２制御信号ＳＧ２の名称を使用する。第２制御信号ＳＧ２はデプレッション型ＦＥＴをオフとするための制御信号である。逆に、デプレッション型ＦＥＴをオンとするためには、第２制御信号ＳＧ２を出力せず、制御回路とデプレッション型ＦＥＴとの接続を開放状態とすることにより実現できるとして話を進める。 Also, the name of the second control signal SG2 is used as a control signal from the control circuit to the depletion type FET. The second control signal SG2 is a control signal for turning off the depletion type FET. On the other hand, in order to turn on the depletion type FET, the second control signal SG2 is not output, and the description will be made on the assumption that the connection between the control circuit and the depletion type FET can be opened.
　〔第１実施形態〕
　図１は、本発明の第１実施形態に係る電源供給装置１００の構成を示す回路図であり、第１実施形態に係る第１ＦＥＴ回路１と、第２ＦＥＴ回路２と、これらの回路と他のブロックとの関係を示す回路図である。 [First Embodiment]
FIG. 1 is a circuit diagram showing a configuration of a power supply apparatus 100 according to the first embodiment of the present invention. The first FET circuit 1, the second FET circuit 2, and these circuits according to the first embodiment It is a circuit diagram which shows the relationship with a block.
　本発明の第１実施形態に係る電源供給装置１００の構成について、図１を用いて説明する。 The configuration of the power supply apparatus 100 according to the first embodiment of the present invention will be described with reference to FIG.
　図１に示すように、電源供給装置１００は、バッテリ５１から電源が供給される入力端子１１と、負荷回路５２が接続される出力端子１２と、入力端子１１にドレインＤ１が接続され、出力端子１２にソースＳ１が接続された第１ＦＥＴ１ａを有している。また、第１ＦＥＴ１ａのドレインＤ１とゲートＧ１との間には、抵抗１ｂが接続されていて、第１ＦＥＴ１ａと抵抗１ｂとで第１ＦＥＴ回路１を構成している。尚、第１ＦＥＴ１ａは、エンハンスメント型ＦＥＴである。 As shown in FIG. 1, the power supply device 100 includes an input terminal 11 to which power is supplied from a battery 51, an output terminal 12 to which a load circuit 52 is connected, a drain D1 connected to the input terminal 11, and an output terminal. 12 includes a first FET 1a to which a source S1 is connected. A resistor 1b is connected between the drain D1 and the gate G1 of the first FET 1a, and the first FET circuit 1 is constituted by the first FET 1a and the resistor 1b. The first FET 1a is an enhancement type FET.
　第１ＦＥＴ１ａには第２ＦＥＴ２ａが接続されている。第２ＦＥＴ２ａは、デプレッション型ＦＥＴである。第２ＦＥＴ２ａであるデプレッション型ＦＥＴのドレインＤ２が第１ＦＥＴ１ａであるエンハンスメント型ＦＥＴのドレインＤ１に接続され、デプレッション型ＦＥＴのソースＳ２がエンハンスメント型ＦＥＴのソースＳ１に接続されている。また、第２ＦＥＴ２ａのドレインＤ２とゲートＧ２との間には、抵抗２ｂが接続されていて、第２ＦＥＴ２ａと抵抗２ｂとで第２ＦＥＴ回路２を構成している。尚、今後、第１ＦＥＴ１ａをエンハンスメント型ＦＥＴ１ａと称し、第２ＦＥＴ２ａをデプレッション型ＦＥＴ２ａと称する。 The second FET 2a is connected to the first FET 1a. The second FET 2a is a depletion type FET. The drain D2 of the depletion type FET that is the second FET 2a is connected to the drain D1 of the enhancement type FET that is the first FET 1a, and the source S2 of the depletion type FET is connected to the source S1 of the enhancement type FET. A resistor 2b is connected between the drain D2 and the gate G2 of the second FET 2a, and the second FET 2a and the resistor 2b constitute the second FET circuit 2. In the future, the first FET 1a will be referred to as an enhancement type FET 1a, and the second FET 2a will be referred to as a depletion type FET 2a.
　発明の第１実施形態に係る電源供給装置１００は、出力端子１２に接続され、出力端子１２からの出力電圧を昇圧する昇圧回路３と、昇圧回路３を制御する制御回路４とを備えている。昇圧回路３は、昇圧された電圧をエンハンスメント型ＦＥＴ１ａのゲートＧ１に印加するように、その出力端がエンハンスメント型ＦＥＴ１ａのゲートＧ１に接続されている。 The power supply apparatus 100 according to the first embodiment of the invention includes a booster circuit 3 that is connected to the output terminal 12 and boosts an output voltage from the output terminal 12, and a control circuit 4 that controls the booster circuit 3. . The booster circuit 3 has its output terminal connected to the gate G1 of the enhancement type FET 1a so that the boosted voltage is applied to the gate G1 of the enhancement type FET 1a.
　制御回路４は、昇圧回路３を制御するために昇圧回路３に接続されていると共に、デプレッション型ＦＥＴ２ａを制御可能とするためにデプレッション型ＦＥＴ２ａのゲートＧ２にも接続されている。また、制御回路４は、負荷回路５２にも接続されており、昇圧回路３を制御すると同時に負荷回路５２も制御するように構成されている。尚、制御回路４の電源電圧は、バッテリ５１から別系統でレギュレータ（図示せず）を介して常に供給されている。また、制御回路４の電源電圧値としては、５Ｖを用いるように構成されている。 The control circuit 4 is connected to the booster circuit 3 in order to control the booster circuit 3, and is also connected to the gate G2 of the depletion type FET 2a in order to control the depletion type FET 2a. The control circuit 4 is also connected to the load circuit 52, and is configured to control the load circuit 52 simultaneously with controlling the booster circuit 3. The power supply voltage of the control circuit 4 is always supplied from the battery 51 via a regulator (not shown) in a separate system. Further, the power supply voltage value of the control circuit 4 is configured to use 5V.
　次に、本発明の第１実施形態に係る電源供給装置１００の動作について、図１を用いて説明する。 Next, the operation of the power supply apparatus 100 according to the first embodiment of the present invention will be described with reference to FIG.
　エンハンスメント型ＦＥＴ１ａは、エンハンスメント型ＦＥＴ１ａのドレインＤ１とゲートＧ１に同一電圧が供給されている状態ではオフとなっている素子である。また、デプレッション型ＦＥＴ２ａは、デプレッション型ＦＥＴ２ａのドレインＤ２とゲートＧ２に同一電圧が供給されている状態ではオンとしておくことが可能な素子である。この状態で、デプレッション型ＦＥＴ２ａのゲートＧ２に制御回路４から第２制御信号ＳＧ２が印加されていない時、即ちデプレッション型ＦＥＴ２ａのゲートＧ２と制御回路４との接続が開放状態の時、デプレッション型ＦＥＴ２ａはオンとなっている。 The enhancement type FET 1a is an element that is turned off when the same voltage is supplied to the drain D1 and the gate G1 of the enhancement type FET 1a. The depletion type FET 2a is an element that can be turned on when the same voltage is supplied to the drain D2 and the gate G2 of the depletion type FET 2a. In this state, when the second control signal SG2 is not applied from the control circuit 4 to the gate G2 of the depletion type FET 2a, that is, when the connection between the gate G2 of the depletion type FET 2a and the control circuit 4 is open, the depletion type FET 2a Is on.
　負荷回路５２への電源供給開始時より前には、エンハンスメント型ＦＥＴ１ａのドレインＤ１とゲートＧ１に、バッテリ５１から同一電圧が供給されていると同時に、デプレッション型ＦＥＴ２ａのドレインＤ２とゲートＧ２にも同一電圧が供給されている。また、負荷回路５２への電源供給開始時より前には、デプレッション型ＦＥＴ２ａのゲートＧ２に制御回路４からの第２制御信号ＳＧ２が印加されていない。従って、エンハンスメント型ＦＥＴ１ａはオフの状態であり、デプレッション型ＦＥＴ２ａはオンの状態である。 Before the start of power supply to the load circuit 52, the same voltage is supplied from the battery 51 to the drain D1 and the gate G1 of the enhancement type FET 1a, and at the same time, the same is applied to the drain D2 and the gate G2 of the depletion type FET 2a. Voltage is being supplied. Prior to the start of power supply to the load circuit 52, the second control signal SG2 from the control circuit 4 is not applied to the gate G2 of the depletion type FET 2a. Therefore, the enhancement type FET 1a is in an off state and the depletion type FET 2a is in an on state.
　また負荷回路５２への電源供給開始時より前には、制御回路４から第１制御信号ＳＧ１として、スタンバイ信号ＳＧ１ｏｆｆが、昇圧回路３に供給されている。尚、制御回路４からは、昇圧回路３に第１制御信号ＳＧ１を供給すると同時に、負荷回路５２にも同一の第１制御信号ＳＧ１が供給される。従って、負荷回路５２への電源供給開始時より前には、昇圧回路３及び負荷回路５２にはスタンバイ信号ＳＧ１ｏｆｆが供給されており、昇圧回路３及び負荷回路５２の動作が停止されている。 Further, before the start of power supply to the load circuit 52, the standby signal SG1off is supplied from the control circuit 4 to the booster circuit 3 as the first control signal SG1. The control circuit 4 supplies the first control signal SG1 to the booster circuit 3 and the same first control signal SG1 to the load circuit 52 at the same time. Therefore, before the start of power supply to the load circuit 52, the standby signal SG1off is supplied to the booster circuit 3 and the load circuit 52, and the operations of the booster circuit 3 and the load circuit 52 are stopped.
　次に、負荷回路５２へ電源供給を開始しようとする場合、制御回路４から第１制御信号ＳＧ１として、スタンバイ解除信号ＳＧ１ｏｎが出力され、昇圧回路３及び負荷回路５２を動作可能の状態とする。 Next, when the power supply to the load circuit 52 is to be started, the standby release signal SG1on is output as the first control signal SG1 from the control circuit 4, and the booster circuit 3 and the load circuit 52 are made operable.
　負荷回路５２への電源供給開始時には、前述したように、デプレッション型ＦＥＴ２ａがオン状態となっているため、昇圧回路３には、デプレッション型ＦＥＴ２ａを介して電圧が供給されている。この状態で、制御回路４から昇圧回路３にスタンバイ解除信号ＳＧ１ｏｎが供給される。 At the start of power supply to the load circuit 52, as described above, since the depletion type FET 2a is in an on state, a voltage is supplied to the booster circuit 3 via the depletion type FET 2a. In this state, the standby release signal SG1on is supplied from the control circuit 4 to the booster circuit 3.
　スタンバイ解除信号ＳＧ１ｏｎが供給された昇圧回路３は、デプレッション型ＦＥＴ２ａを介して供給された電圧を昇圧して、エンハンスメント型ＦＥＴ１ａのゲートＧ１に印加し、エンハンスメント型ＦＥＴをオンさせる。 The booster circuit 3 to which the standby release signal SG1on is supplied boosts the voltage supplied via the depletion type FET 2a and applies it to the gate G1 of the enhancement type FET 1a to turn on the enhancement type FET.
　本発明の第１実施形態の昇圧回路３は、チャージポンプ回路と呼ばれる回路で構成されており、供給された電圧を２倍の電圧に昇圧する機能を有している。チャージポンプ回路の内部には、発振回路（図示せず）と、その発振回路の発振によって順次充放電される多段のキャパシタ群（図示せず）とが備えられている。そして、キャパシタ群の最終段のキャパシタに蓄えられた電圧が、昇圧回路３の出力端から出力されるように構成されている。尚、このような回路構成は周知の回路構成であるため、詳細な説明を省略する。 The booster circuit 3 according to the first embodiment of the present invention is configured by a circuit called a charge pump circuit, and has a function of boosting the supplied voltage to twice the voltage. The charge pump circuit includes an oscillation circuit (not shown) and a multistage capacitor group (not shown) that is sequentially charged and discharged by the oscillation of the oscillation circuit. The voltage stored in the last capacitor of the capacitor group is output from the output terminal of the booster circuit 3. Since such a circuit configuration is a well-known circuit configuration, detailed description thereof is omitted.
　エンハンスメント型ＦＥＴ１ａがオンした後は、エンハンスメント型ＦＥＴ１ａを介して出力端子１２に出力電圧Ｖｏｕｔが出力される。出力電圧Ｖｏｕｔは、スタンバイ解除信号ＳＧ１ｏｎが供給されている負荷回路５２に供給され、負荷回路５２が、その動作を開始する。また、昇圧回路３にエンハンスメント型ＦＥＴ１ａを介して電圧が供給され、その供給された電圧を昇圧して、エンハンスメント型ＦＥＴ１ａのゲートＧ１に印加し続ける。 After the enhancement type FET 1a is turned on, the output voltage Vout is output to the output terminal 12 via the enhancement type FET 1a. The output voltage Vout is supplied to the load circuit 52 to which the standby release signal SG1on is supplied, and the load circuit 52 starts its operation. Further, a voltage is supplied to the booster circuit 3 via the enhancement type FET 1a, and the supplied voltage is boosted and continuously applied to the gate G1 of the enhancement type FET 1a.
　エンハンスメント型ＦＥＴ１ａがオンした後には、制御回路４からの第２制御信号ＳＧ２によってデプレッション型ＦＥＴ２ａをオフする。第２制御信号ＳＧ２として、０Ｖの電圧をデプレッション型ＦＥＴ２ａのゲートＧ２に印加することで、デプレッション型ＦＥＴ２ａをオフすることができる。 After the enhancement type FET 1a is turned on, the depletion type FET 2a is turned off by the second control signal SG2 from the control circuit 4. By applying a voltage of 0V to the gate G2 of the depletion type FET 2a as the second control signal SG2, the depletion type FET 2a can be turned off.
　上述したとおり、本発明の第１実施形態の電源供給装置１００は、負荷回路５２への電源供給開始時に、既にオンしているデプレッション型ＦＥＴ２ａを介して昇圧回路３に電圧を供給するようにした。デプレッション型ＦＥＴ２ａのオン時の電圧降下は、約０．４Ｖである。従って、本発明の第１実施形態の電源供給装置１００は、第２従来例の昇圧回路８０３が、電圧降下が約２Ｖあるエンハンスメント型ＦＥＴ８０１ａの出力電圧を供給されていた場合に比較して、約１．６Ｖ高い電圧を昇圧回路３に供給することができる。よって、バッテリ５１から出力される電圧が低下した場合においても、昇圧回路へ供給する電圧を、必要とされる電圧にすることができ、エンハンスメント型ＦＥＴ１ａをオンすることができる。そのため、負荷回路５２への電源を安定して供給することができる。 As described above, the power supply device 100 according to the first embodiment of the present invention supplies the voltage to the booster circuit 3 via the depletion type FET 2a that is already turned on when the power supply to the load circuit 52 is started. . The voltage drop when the depletion type FET 2a is on is about 0.4V. Therefore, the power supply apparatus 100 according to the first embodiment of the present invention has a booster circuit 803 of the second conventional example, which is approximately the same as when the output voltage of the enhancement type FET 801a having a voltage drop of approximately 2 V is supplied. A voltage higher by 1.6 V can be supplied to the booster circuit 3. Therefore, even when the voltage output from the battery 51 decreases, the voltage supplied to the booster circuit can be set to the required voltage, and the enhancement FET 1a can be turned on. Therefore, the power to the load circuit 52 can be stably supplied.
　〔第２実施形態〕
　次に、本発明の第２実施形態について、図２乃至図４を用いて説明する。 [Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS.
　図２は、本発明の第２実施形態に係る電源供給装置２００の第３ＦＥＴ回路２１と第４ＦＥＴ回路２２の構成、及びこれらの回路と他のブロックとの関係を示す回路図である。尚、昇圧回路３及び制御回路４等については、その働きが第１実施形態と同一であるものについては、第１実施形態と同じ符号を使用する。 FIG. 2 is a circuit diagram showing the configuration of the third FET circuit 21 and the fourth FET circuit 22 of the power supply apparatus 200 according to the second embodiment of the present invention, and the relationship between these circuits and other blocks. For the booster circuit 3, the control circuit 4, and the like, the same reference numerals as those in the first embodiment are used for those having the same functions as those in the first embodiment.
　本発明の第２実施形態に係る電源供給装置２００のブロック構成について、図２を用いて説明する。尚、本発明の第２実施形態に係る電源供給装置２００は、本発明の第１実施形態に係る電源供給装置１００に対し、実際の製品構成により近い構成を有した実施形態である。 The block configuration of the power supply apparatus 200 according to the second embodiment of the present invention will be described with reference to FIG. The power supply device 200 according to the second embodiment of the present invention is an embodiment having a configuration closer to the actual product configuration than the power supply device 100 according to the first embodiment of the present invention.
　図２に示すように、電源供給装置２００は、バッテリ５１が接続される入力端子１１と、第３ＦＥＴ回路２１と、負荷回路５２が接続される出力端子１２と、第４ＦＥＴ回路２２と、昇圧回路３と、制御回路４と、保護回路３１とを備えている。 As shown in FIG. 2, the power supply device 200 includes an input terminal 11 to which a battery 51 is connected, a third FET circuit 21, an output terminal 12 to which a load circuit 52 is connected, a fourth FET circuit 22, and a booster circuit. 3, a control circuit 4, and a protection circuit 31.
　第３ＦＥＴ回路２１は、入力端子１１と出力端子１２との間に接続されている。昇圧回路３は、出力端子１２に接続されていると共に、出力端子１２からの出力電圧Ｖｏｕｔが、電源電圧として供給されていて、出力端子１２からの出力電圧Ｖｏｕｔを昇圧して第３ＦＥＴ回路２１に供給するように構成されている。また、保護回路３１が、出力端子１２と第３ＦＥＴ回路２１とグランドとの間に接続されている。 The third FET circuit 21 is connected between the input terminal 11 and the output terminal 12. The booster circuit 3 is connected to the output terminal 12 and the output voltage Vout from the output terminal 12 is supplied as a power supply voltage. The booster circuit 3 boosts the output voltage Vout from the output terminal 12 to the third FET circuit 21. It is configured to supply. A protection circuit 31 is connected between the output terminal 12, the third FET circuit 21, and the ground.
　装置内の回路の動作を制御するため、制御回路４が備えられている。制御回路４は、昇圧回路３を制御するために昇圧回路３に接続されている。また、制御回路４は、負荷回路５２にも接続されており、昇圧回路３を制御すると同時に負荷回路５２も制御するように構成されている。尚、制御回路４の電源電圧は、バッテリ５１から別系統でレギュレータ（図示せず）を介して常に供給されている。また、制御回路４の電源電圧値としては、５Ｖを用いるように構成されている。 A control circuit 4 is provided to control the operation of the circuit in the apparatus. The control circuit 4 is connected to the booster circuit 3 in order to control the booster circuit 3. The control circuit 4 is also connected to the load circuit 52, and is configured to control the load circuit 52 simultaneously with controlling the booster circuit 3. The power supply voltage of the control circuit 4 is always supplied from the battery 51 via a regulator (not shown) in a separate system. Further, the power supply voltage value of the control circuit 4 is configured to use 5V.
　本発明の第２実施形態に係る電源供給装置２００では、第３ＦＥＴ回路２１に並列に第４ＦＥＴ回路２２が接続されている。第４ＦＥＴ回路２２にも、第４ＦＥＴ回路２２を制御するため制御回路４が接続されている。 In the power supply apparatus 200 according to the second embodiment of the present invention, the fourth FET circuit 22 is connected in parallel to the third FET circuit 21. The control circuit 4 is also connected to the fourth FET circuit 22 in order to control the fourth FET circuit 22.
　電源供給装置２００の回路構成について、第３ＦＥＴ回路２１と第４ＦＥＴ回路２２を中心に、図２を用いて詳細に説明する。 The circuit configuration of the power supply device 200 will be described in detail with reference to FIG. 2, focusing on the third FET circuit 21 and the fourth FET circuit 22.
　図２に示すように、第３ＦＥＴ回路２１は、入力端子１１と出力端子１２との間に接続されたエンハンスメント型ＦＥＴ２１ａと、抵抗２１ｂと、ダイオード２１ｃ及びダイオード２１ｄとを有している。 As shown in FIG. 2, the third FET circuit 21 includes an enhancement type FET 21a connected between the input terminal 11 and the output terminal 12, a resistor 21b, a diode 21c, and a diode 21d.
　保護回路３１は、出力端子１２とエンハンスメント型ＦＥＴ１ａのゲートＧ１とグランドとの間に接続されている。保護回路３１は、ツェナーダイオード（図示せず）を用いて構成されており、出力端子１２における出力電圧Ｖｏｕｔが所定の電圧を超えないように制御するための回路である。尚、第２実施形態における保護回路３１の構成は周知であるため、詳細な説明を省略する。 The protection circuit 31 is connected between the output terminal 12 and the gate G1 of the enhancement type FET 1a and the ground. The protection circuit 31 is configured using a Zener diode (not shown), and is a circuit for controlling the output voltage Vout at the output terminal 12 so as not to exceed a predetermined voltage. In addition, since the structure of the protection circuit 31 in 2nd Embodiment is known, detailed description is abbreviate | omitted.
　第３ＦＥＴ回路２１では、入力端子１１にダイオード２１ｃのアノードが接続され、ダイオード２１ｃのカソードにエンハンスメント型ＦＥＴ２１ａのドレインＤ３が接続され、エンハンスメント型ＦＥＴ２１ａのソースＳ３が出力端子１２に接続されている。エンハンスメント型ＦＥＴ２１ａのゲートＧ３は、ダイオード２１ｄと抵抗２１ｂとの直列接続回路を介して入力端子１１に接続されていると共に、昇圧回路３の出力端に接続されている。 In the third FET circuit 21, the anode of the diode 21c is connected to the input terminal 11, the drain D3 of the enhancement type FET 21a is connected to the cathode of the diode 21c, and the source S3 of the enhancement type FET 21a is connected to the output terminal 12. A gate G3 of the enhancement type FET 21a is connected to the input terminal 11 through a series connection circuit of a diode 21d and a resistor 21b, and is connected to the output terminal of the booster circuit 3.
　ダイオード２１ｃ及びダイオード２１ｄは、逆接続防止用のダイオードである。これらのダイオードは、バッテリ５１の電源出力の端子及びグランドの端子が、電源供給装置２００の入力端子１１及びグランドの端子に、逆に接続された場合に、電源供給装置２００及び負荷回路５２が破壊されないように挿入されている。尚、入力端子１１にバッテリ５１からの電圧が供給された時、ダイオード２１ｃ及びダイオード２１ｄの各アノード・カソード間には、約１Ｖの電圧降下が発生する。 The diode 21c and the diode 21d are diodes for preventing reverse connection. These diodes break down the power supply device 200 and the load circuit 52 when the power output terminal and the ground terminal of the battery 51 are connected to the input terminal 11 and the ground terminal of the power supply device 200 in reverse. Has been inserted so as not to. When the voltage from the battery 51 is supplied to the input terminal 11, a voltage drop of about 1 V occurs between the anode and cathode of the diode 21c and the diode 21d.
　昇圧回路３から出力された電圧は、ＦＥＴ２１ａのゲートＧ３に印加される。また、昇圧回路３は、制御回路４に接続されており、制御回路４からの第１制御信号ＳＧ１によって制御される。昇圧回路３は、負荷回路５２への駆動電源供給開始時より前には、第１制御信号ＳＧ１として、スタンバイ信号ＳＧ１ｏｆｆが制御回路４から入力されており、回路の動作を停止している。また、昇圧回路３は、昇圧回路３に供給される電源電圧が７Ｖ以上で、かつ、制御回路４からのスタンバイ解除信号ＳＧ１ｏｎが入力された後に昇圧動作を行なうように設定されている。 The voltage output from the booster circuit 3 is applied to the gate G3 of the FET 21a. The booster circuit 3 is connected to the control circuit 4 and is controlled by the first control signal SG1 from the control circuit 4. Prior to the start of the supply of drive power to the load circuit 52, the booster circuit 3 receives the standby signal SG1off from the control circuit 4 as the first control signal SG1, and stops the operation of the circuit. The booster circuit 3 is set to perform a boost operation after the power supply voltage supplied to the booster circuit 3 is 7 V or more and the standby release signal SG1on from the control circuit 4 is input.
　第４ＦＥＴ回路２２は、デプレッション型ＦＥＴ２２ａと、抵抗２２ｂと、ツェナーダイオード２２ｃと、を有している。デプレッション型ＦＥＴ２２ａは、ドレインＤ４が、エンハンスメント型ＦＥＴ２１ａのドレインＤ３に接続され、ソースＳ４がエンハンスメント型ＦＥＴ２１ａのソースＳ３に接続されている。 The fourth FET circuit 22 has a depletion type FET 22a, a resistor 22b, and a Zener diode 22c. The depletion type FET 22a has a drain D4 connected to the drain D3 of the enhancement type FET 21a and a source S4 connected to the source S3 of the enhancement type FET 21a.
一般的に、デプレッション型ＦＥＴは、ソースの電圧に対してゲートの電圧が低い時でもオンする動作領域を有している。例えば、ゲートの電圧がソースの電圧に対して２Ｖ程度低くてもオンする。そのため、デプレッション型ＦＥＴをオフとするには、ソースの電圧に対してゲートの電圧を所定電圧（約３Ｖ）以上低くなるように設定すればオフとすることができる。例えば、デプレッション型ＦＥＴのソースの電圧が所定電圧（約３Ｖ）以上である時、ゲートの電圧を０Ｖとすることでオフとすることができる。 In general, a depletion type FET has an operation region that is turned on even when the gate voltage is lower than the source voltage. For example, it is turned on even if the gate voltage is about 2 V lower than the source voltage. Therefore, the depletion type FET can be turned off by setting the gate voltage to be lower than the source voltage by a predetermined voltage (about 3 V) or more. For example, when the source voltage of the depletion type FET is equal to or higher than a predetermined voltage (about 3 V), the gate voltage can be set to 0 V to turn it off.
　また、一般的に、デプレッション型ＦＥＴには、エンハンスメント型ＦＥＴのような数Ａ以上の大電流を流すことができる素子が少なく、１Ａ程度の電流しか流せない。従って、デプレッション型ＦＥＴを介して大電流を流すような使用方法が用いられることは少ない。また、そのようなデプレッション型ＦＥＴは、存在しても非常に高価である可能性が高く、一般的に用いられない。 In general, a depletion type FET has few elements capable of flowing a large current of several A or more like an enhancement type FET, and can only supply a current of about 1 A. Therefore, a method of using a large current through the depletion type FET is rarely used. Further, such a depletion type FET is likely to be very expensive even if it exists, and is not generally used.
　本発明の第２実施形態の第４ＦＥＴ回路２２には、デプレッション型ＦＥＴ２２ａとして、デプレッション型ＭＯＳ・ＦＥＴ（Metal Oxide Semiconductor・Field Effect Transistor）が使用される。デプレッション型ＭＯＳ・ＦＥＴは、ソースに対するゲートの電圧として、負の電圧から正の電圧まで使用することができるため、使い勝手が良いという特徴がある。 In the fourth FET circuit 22 of the second embodiment of the present invention, a depletion type MOS • FET (Metal • Oxide • Semiconductor • Field • Effect • Transistor) is used as the depletion type FET 22a. The depletion type MOS • FET can be used from a negative voltage to a positive voltage as a gate voltage with respect to the source, and is therefore easy to use.
　抵抗２２ｂは、デプレッション型ＦＥＴ２２ａのドレインＤ４とゲートＧ４との間に接続されている。また、ツェナーダイオード２２ｃは、デプレッション型ＦＥＴ２２ａのゲートＧ４とグランドとの間に接続されている。ツェナーダイオード２２ｃは、ある閾値（ツェナー電圧）以上の高い電圧が外部からゲートＧ４に印加されても、デプレッション型ＦＥＴ２２ａのゲートＧ４に閾値以上の電圧が掛からないように、そのツェナー電圧値が設定されている。尚、本発明の第２実施形態の電源供給装置２００では、ツェナー電圧値は、１７．５Ｖに設定されている。 The resistor 22b is connected between the drain D4 and the gate G4 of the depletion type FET 22a. The zener diode 22c is connected between the gate G4 of the depletion type FET 22a and the ground. The Zener diode 22c has a Zener voltage value set so that a voltage higher than the threshold is not applied to the gate G4 of the depletion type FET 22a even when a high voltage higher than a certain threshold (Zener voltage) is externally applied to the gate G4. ing. In the power supply device 200 according to the second embodiment of the present invention, the Zener voltage value is set to 17.5V.
　デプレッション型ＦＥＴ２２ａのゲートＧ４には、制御回路４の出力端が接続されている。制御回路４からは、デプレッション型ＦＥＴ２２ａをオフさせるための第２制御信号ＳＧ２が出力されるように構成されている。例えば、制御回路４から第２制御信号ＳＧ２として、０Ｖをデプレッション型ＦＥＴ２２ａのゲートＧ２に印加すると、デプレッション型ＦＥＴ２２ａはオフとなる。 The output terminal of the control circuit 4 is connected to the gate G4 of the depletion type FET 22a. The control circuit 4 is configured to output a second control signal SG2 for turning off the depletion type FET 22a. For example, when 0V is applied to the gate G2 of the depletion type FET 22a as the second control signal SG2 from the control circuit 4, the depletion type FET 22a is turned off.
　また、逆に制御回路４から第２制御信号ＳＧ２が出力されず、開放状態とすれば、制御回路４とデプレッション型ＦＥＴ２ａのゲートＧ２とは切り離される。抵抗２２ｂが、デプレッション型ＦＥＴ２２ａのドレインＤ４とゲートＧ４との間に接続されているので、ゲートＧ４にはドレインＤ４と同じ電圧が印加され、デプレッション型ＦＥＴ２ａはオンとなる。 Conversely, if the second control signal SG2 is not output from the control circuit 4 and is opened, the control circuit 4 and the gate G2 of the depletion type FET 2a are disconnected. Since the resistor 22b is connected between the drain D4 and the gate G4 of the depletion type FET 22a, the same voltage as the drain D4 is applied to the gate G4, and the depletion type FET 2a is turned on.
　次に、本発明の第２実施形態に係る電源供給装置２００の動作について、図２、図３及び図４を用いて説明する。 Next, the operation of the power supply apparatus 200 according to the second embodiment of the present invention will be described with reference to FIGS.
　図２に示す電源供給装置２００の、バッテリ５１の電圧が通常状態（約１２Ｖ）である時の、負荷回路５２への電源供給が開始される前から電源が供給されるまでの動作について、図３（ａ）、図３（ｂ）を用いて説明する。また、バッテリ５１の電圧が低下した場合の電源供給装置２００の動作について、図４（ａ）、図４（ｂ）を用いて説明する。尚、要求される出力電圧（Ｖｏｕｔ）としては、７Ｖ以上１３Ｖ未満を想定している。 The operation of the power supply apparatus 200 shown in FIG. 2 from when the power supply to the load circuit 52 is started until the power is supplied when the voltage of the battery 51 is in a normal state (about 12 V) is shown in FIG. This will be described with reference to 3 (a) and FIG. 3 (b). The operation of the power supply device 200 when the voltage of the battery 51 is lowered will be described with reference to FIGS. 4 (a) and 4 (b). The required output voltage (Vout) is assumed to be 7V or more and less than 13V.
　負荷回路５２への電源供給開始時より前の状態では、図３（ａ）に示すように、エンハンスメント型ＦＥＴ２１ａにはダイオード２１ｃを介して電圧Ｖｉｎが供給されている。ダイオード２１ｃの両端間には約１Ｖの電圧降下があるため、エンハンスメント型ＦＥＴ２１ａのドレインＤ３には電圧１１Ｖが掛かっているが、制御回路４から昇圧回路３にはスタンバイ信号ＳＧ１ｏｆｆが入力されている。そのため、エンハンスメント型ＦＥＴ２１ａのゲートＧ３には昇圧回路３から電圧が印加されず、エンハンスメント型ＦＥＴ２１ａはオフとなっている。 In the state before the start of power supply to the load circuit 52, as shown in FIG. 3A, the enhancement type FET 21a is supplied with the voltage Vin via the diode 21c. Since there is a voltage drop of about 1V between both ends of the diode 21c, the voltage 11V is applied to the drain D3 of the enhancement type FET 21a, but the standby signal SG1off is input from the control circuit 4 to the booster circuit 3. Therefore, no voltage is applied from the booster circuit 3 to the gate G3 of the enhancement type FET 21a, and the enhancement type FET 21a is turned off.
　この時、デプレッション型ＦＥＴ２２ａのドレインＤ４にはダイオード２１ｃを介して、そして、ゲートＧ４にはダイオード２１ｄ及び抵抗２２ｂを介して電源が供給されている。また、制御回路４からはデプレッション型ＦＥＴ２２ａをオフさせるための信号が出力されておらず、デプレッション型ＦＥＴ２２ａのゲートＧ４と切り離されている。そのため、デプレッション型ＦＥＴ２２ａのゲートＧ４の電圧は、デプレッション型ＦＥＴ２２ａのドレインＤ４の電圧と同一であるため、デプレッション型ＦＥＴ２２ａはオンとなっている。 At this time, power is supplied to the drain D4 of the depletion type FET 22a via the diode 21c, and to the gate G4 via the diode 21d and the resistor 22b. The control circuit 4 does not output a signal for turning off the depletion type FET 22a, and is disconnected from the gate G4 of the depletion type FET 22a. Therefore, since the voltage of the gate G4 of the depletion type FET 22a is the same as the voltage of the drain D4 of the depletion type FET 22a, the depletion type FET 22a is on.
　デプレッション型ＦＥＴ２２ａがオンとなっているため、デプレッション型ＦＥＴ２２ａのドレインＤ４とソースＳ４との間の電圧降下は、０．４Ｖとなっている。そのため、出力端子１２には、出力電圧Ｖｏｕｔとして、デプレッション型ＦＥＴ２２ａを介した電圧１０．６Ｖが出力される。 Since the depletion type FET 22a is on, the voltage drop between the drain D4 and the source S4 of the depletion type FET 22a is 0.4V. Therefore, the output terminal 12 outputs a voltage of 10.6 V via the depletion type FET 22a as the output voltage Vout.
　負荷回路５２への電源供給開始時より前の状態では、前述したように制御回路４から昇圧回路３及び負荷回路５２にスタンバイ信号ＳＧ１ｏｆｆが入力されている。そのため、エンハンスメント型ＦＥＴ２１ａのゲートＧ３にはエンハンスメント型ＦＥＴ２１ａをオンするための適正な電圧が印加されていない。従って、エンハンスメント型ＦＥＴ２１ａは、まだオフである。 In the state before the start of power supply to the load circuit 52, the standby signal SG1off is input from the control circuit 4 to the booster circuit 3 and the load circuit 52 as described above. Therefore, an appropriate voltage for turning on the enhancement type FET 21a is not applied to the gate G3 of the enhancement type FET 21a. Therefore, the enhancement type FET 21a is still off.
　次に、負荷回路５２への電源供給を開始するため、制御回路４から昇圧回路３及び負荷回路５２にスタンバイ解除信号ＳＧ１ｏｎが入力される。制御回路４から昇圧回路３及び負荷回路５２にスタンバイ解除信号ＳＧ１ｏｎが入力された後の状態を図３（ｂ）に示す。昇圧回路３からは、１０．６Ｖの倍の電圧である２１．２Ｖが出力され、エンハンスメント型ＦＥＴ２１ａのゲートＧ３に印加される。２１．２ＶがゲートＧ１に印加されれば、エンハンスメント型ＦＥＴ２１ａがオンし、出力端子１２には、エンハンスメント型ＦＥＴ２１ａを介して電圧が出力される。尚、エンハンスメント型ＦＥＴ２１ａがオンした後では、その電圧降下が０．４Ｖであるため、出力端子１２には、１０．６Ｖが出力される。 Next, in order to start power supply to the load circuit 52, the standby release signal SG1on is input from the control circuit 4 to the booster circuit 3 and the load circuit 52. FIG. 3B shows a state after the standby release signal SG1on is input from the control circuit 4 to the booster circuit 3 and the load circuit 52. The booster circuit 3 outputs 21.2V, which is twice the voltage of 10.6V, and is applied to the gate G3 of the enhancement type FET 21a. When 21.2 V is applied to the gate G1, the enhancement type FET 21a is turned on, and a voltage is output to the output terminal 12 via the enhancement type FET 21a. Since the voltage drop is 0.4V after the enhancement type FET 21a is turned on, 10.6V is output to the output terminal 12.
　デプレッション型ＦＥＴ２２ａは、昇圧回路３を起動させることが終了したら、その後オフとしておく。尚、デプレッション型ＦＥＴ２ａは数Ａの大電流を流すことができないが、昇圧回路３に必要な電流を流すことは可能であるため、昇圧回路３を立ち上げるために使用することには問題はない。 The depletion type FET 22a is turned off after the booster circuit 3 has been started. Although the depletion type FET 2a cannot flow a large current of several A, it can flow a necessary current to the booster circuit 3. Therefore, there is no problem in using it for starting up the booster circuit 3. .
　デプレッション型ＦＥＴ２２ａをオフとするには、デプレッション型ＦＥＴ２２ａのゲートＧ４に第２制御信号ＳＧ２を印加する。具体的には、制御回路４から、０Ｖをデプレッション型ＦＥＴ２ａのゲートＧ２に印加する。このため、デプレッション型ＦＥＴ２ａのゲートＧ２には、ソースＳ２に対して１０．６Ｖ低い電圧が印加されることになる。よって、デプレッション型ＦＥＴ２ａはオフとなる。 To turn off the depletion type FET 22a, the second control signal SG2 is applied to the gate G4 of the depletion type FET 22a. Specifically, 0 V is applied from the control circuit 4 to the gate G2 of the depletion type FET 2a. For this reason, a voltage 10.6V lower than the source S2 is applied to the gate G2 of the depletion type FET 2a. Therefore, the depletion type FET 2a is turned off.
　次に、入力端子１１における電圧Ｖｉｎ即ちバッテリ５１からの電圧が、低温等の理由によって、通常の電圧１２Ｖより低い電圧、例として９Ｖまで下がった場合の電源供給装置２００の動作を説明する。 Next, the operation of the power supply device 200 when the voltage Vin at the input terminal 11, that is, the voltage from the battery 51 is lowered to a voltage lower than the normal voltage 12 V, for example, 9 V, for example, due to low temperature or the like will be described.
図４（ａ）、（ｂ）は、図２に示す電源供給装置２００において、入力端子１１における電圧が９Ｖまで下がった時の、負荷回路５２を駆動するための電源供給開始時前後の状態を示している。 4A and 4B show the states before and after the start of power supply for driving the load circuit 52 when the voltage at the input terminal 11 is lowered to 9 V in the power supply apparatus 200 shown in FIG. Show.
　負荷回路５２への電源供給開始時より前の状態では、図４（ａ）に示すように、エンハンスメント型ＦＥＴ２１ａにはダイオード２１ｃを介して電圧Ｖｉｎが供給されている。ダイオード２１ｃの両端間には約１Ｖの電圧降下があるため、エンハンスメント型ＦＥＴ２１ａのドレインＤ３には電圧８Ｖが掛かっている。しかし、制御回路４から昇圧回路３及び負荷回路５２にはスタンバイ信号ＳＧ１ｏｆｆが入力されているため、エンハンスメント型ＦＥＴ２１ａのゲートＧ３には昇圧回路３から電圧が印加されず、エンハンスメント型ＦＥＴ２１ａはオフとなっている。 In a state before the start of power supply to the load circuit 52, as shown in FIG. 4A, the enhancement type FET 21a is supplied with the voltage Vin via the diode 21c. Since there is a voltage drop of about 1V across the diode 21c, a voltage of 8V is applied to the drain D3 of the enhancement type FET 21a. However, since the standby signal SG1off is input from the control circuit 4 to the booster circuit 3 and the load circuit 52, no voltage is applied from the booster circuit 3 to the gate G3 of the enhancement type FET 21a, and the enhancement type FET 21a is turned off. ing.
　この時、デプレッション型ＦＥＴ２２ａのドレインＤ４には、ダイオード２１ｃを介して電圧が供給され、ゲートＧ４には、ダイオード２１ｃ及び抵抗２２ｂを介して電圧が供給されている。従って、デプレッション型ＦＥＴ２２ａのドレインＤ４とゲートＧ４には、エンハンスメント型ＦＥＴ２１ａと同様に、電圧８Ｖが掛かっている。また、制御回路４からはデプレッション型ＦＥＴ２２ａをオフさせるための信号が出力されておらず、デプレッション型ＦＥＴ２２ａのゲートＧ４と切り離されている。そのため、デプレッション型ＦＥＴ２２ａのゲートＧ４の電圧は、デプレッション型ＦＥＴ２２ａのドレインＤ４の電圧と同一であるため、デプレッション型ＦＥＴ２２ａはオンとなっている。 At this time, a voltage is supplied to the drain D4 of the depletion type FET 22a through the diode 21c, and a voltage is supplied to the gate G4 through the diode 21c and the resistor 22b. Accordingly, the voltage 8V is applied to the drain D4 and the gate G4 of the depletion type FET 22a, similarly to the enhancement type FET 21a. The control circuit 4 does not output a signal for turning off the depletion type FET 22a, and is disconnected from the gate G4 of the depletion type FET 22a. Therefore, since the voltage of the gate G4 of the depletion type FET 22a is the same as the voltage of the drain D4 of the depletion type FET 22a, the depletion type FET 22a is on.
　デプレッション型ＦＥＴ２２ａがオンとなっているため、デプレッション型ＦＥＴ２２ａのドレインＤ４とソースＳ４との間の電圧降下は、０．４Ｖとなっている。そのため、出力端子１２には出力電圧Ｖｏｕｔとして、デプレッション型ＦＥＴ２２ａを介した電圧７．６Ｖが出力される。 Since the depletion type FET 22a is on, the voltage drop between the drain D4 and the source S4 of the depletion type FET 22a is 0.4V. Therefore, the output terminal 12 outputs a voltage 7.6 V via the depletion type FET 22a as the output voltage Vout.
　負荷回路５２への電源供給開始時より前の状態では、制御回路４から昇圧回路３及び負荷回路５２にスタンバイ信号ＳＧ１ｏｆｆが入力されている。そのため、エンハンスメント型ＦＥＴ２１ａのゲートにエンハンスメント型ＦＥＴ２１ａをオンするための適正な電圧が印加されていない。従って、エンハンスメント型ＦＥＴ２１ａは、まだオフである。 In a state before the start of power supply to the load circuit 52, the standby signal SG1off is input from the control circuit 4 to the booster circuit 3 and the load circuit 52. Therefore, an appropriate voltage for turning on the enhancement type FET 21a is not applied to the gate of the enhancement type FET 21a. Therefore, the enhancement type FET 21a is still off.
　次に、負荷回路５２への電源供給を開始するため、制御回路４から昇圧回路３及び負荷回路５２にスタンバイ解除信号ＳＧ１ｏｎが入力される。制御回路４から昇圧回路３及び負荷回路５２にスタンバイ解除信号ＳＧ１ｏｎが入力された後の状態を図４（ｂ）に示す。昇圧回路３からは、７．６Ｖの倍の電圧である１５．２Ｖが出力され、エンハンスメント型ＦＥＴ２１ａのゲートＧ３に印加される。１５．２ＶがゲートＧ３に印加されれば、エンハンスメント型ＦＥＴ２１ａがオンし、出力端子１２には、エンハンスメント型ＦＥＴ２１ａを介して電圧が出力される。尚、エンハンスメント型ＦＥＴ２１ａがオンした後では、その電圧降下が０．４Ｖであるため、出力端子１２には、７．６Ｖが出力される。 Next, in order to start power supply to the load circuit 52, the standby release signal SG1on is input from the control circuit 4 to the booster circuit 3 and the load circuit 52. FIG. 4B shows a state after the standby release signal SG1on is input from the control circuit 4 to the booster circuit 3 and the load circuit 52. The booster circuit 3 outputs 15.2V, which is twice the voltage of 7.6V, and is applied to the gate G3 of the enhancement type FET 21a. When 15.2 V is applied to the gate G3, the enhancement type FET 21a is turned on, and a voltage is output to the output terminal 12 via the enhancement type FET 21a. Note that, after the enhancement type FET 21a is turned on, the voltage drop is 0.4V, so 7.6V is output to the output terminal 12.
　エンハンスメント型ＦＥＴ２１ａがオンした後に、デプレッション型ＦＥＴ２２ａをオフとする動作については、入力端子１１における電圧が１２Ｖの時と同様であるため、説明を省略する。 Since the operation to turn off the depletion type FET 22a after the enhancement type FET 21a is turned on is the same as when the voltage at the input terminal 11 is 12V, the description is omitted.
　このように、本発明の電源供給装置２００は、バッテリ５１からの電圧が、９Ｖまで低下した場合においても、出力端子１２における出力電圧Ｖｏｕｔは、昇圧回路３が動作可能な電圧である７．６Ｖとすることができる。従って、バッテリ５１からの電圧が、９Ｖまで低下した場合においても、バッテリ５１のからの電圧が１２Ｖの時と同様の動作を期待できる。尚、本発明の電源供給装置２００では、例として、昇圧回路３が動作可能な電圧が７Ｖ以上であるとして話を進めてきた。しかし、昇圧回路３の動作電圧が、例えば、もっと低い電圧からであった場合、バッテリ５１からの電圧についても、より低い電圧に対応できることは勿論である。 As described above, in the power supply device 200 of the present invention, even when the voltage from the battery 51 is reduced to 9V, the output voltage Vout at the output terminal 12 is 7.6V, which is the voltage at which the booster circuit 3 can operate. It can be. Therefore, even when the voltage from the battery 51 drops to 9V, the same operation as when the voltage from the battery 51 is 12V can be expected. In the power supply device 200 of the present invention, as an example, the discussion has been made assuming that the voltage at which the booster circuit 3 can operate is 7 V or more. However, when the operating voltage of the booster circuit 3 is from a lower voltage, for example, the voltage from the battery 51 can of course correspond to a lower voltage.
　このように、本発明の第２実施形態の電源供給装置２００は、バッテリ５１からの電圧が低下した場合においても、負荷回路５２への電源を、安定して供給することができる。 As described above, the power supply apparatus 200 according to the second embodiment of the present invention can stably supply power to the load circuit 52 even when the voltage from the battery 51 decreases.
　これまで、バッテリ５１のからの電圧が通常時に１２Ｖの場合、及び９Ｖまで低下した場合についての説明をした。しかし、バッテリ５１のからの電圧は、通常時においても、１２Ｖを超えて、約１６Ｖまで上昇する可能性がある。例えば、エンジンを始動した時には、バッテリには充電が行なわれるため、その出力電圧が上昇する。また、最近のハイブリッドカー等の車両では、減速時にも充電が行なわれ、バッテリの出力電圧が上昇する。 So far, the case where the voltage from the battery 51 is normally 12V and the case where the voltage is lowered to 9V has been described. However, the voltage from the battery 51 may rise over 12V to about 16V even in normal times. For example, when the engine is started, since the battery is charged, its output voltage rises. In recent vehicles such as hybrid cars, charging is performed even during deceleration, and the output voltage of the battery increases.
　本発明の第１実施形態及び２の電源供給装置１００及び２００においても、バッテリの出力電圧が上昇した場合、出力端子１２には、規定の１３Ｖを超える可能性がある。しかし、電源供給装置２００に設けたような保護回路３１によって、所定の出力電圧以上の電圧が負荷回路５２に供給されないようにすることができる。保護回路３１では、トランジスタ（図示せず）と、ツェナーダイオード（図示せず）で構成されており、ツェナーダイオードのツェナー電圧を適切な値に設定することで、出力端子１２における出力電圧が、規定の電圧値（１３Ｖ）を超えないように構成されている。 Also in the power supply devices 100 and 200 of the first embodiment and the second embodiment of the present invention, when the output voltage of the battery rises, the output terminal 12 may exceed the specified 13V. However, the protection circuit 31 provided in the power supply device 200 can prevent a voltage higher than a predetermined output voltage from being supplied to the load circuit 52. The protection circuit 31 includes a transistor (not shown) and a Zener diode (not shown). By setting the Zener voltage of the Zener diode to an appropriate value, the output voltage at the output terminal 12 is regulated. The voltage value (13V) is not exceeded.
　このように、保護回路３１を設けることにより、負荷回路５２へ、所定電圧を超えるような過大な電圧が供給されることを防止することができる。 Thus, by providing the protection circuit 31, it is possible to prevent an excessive voltage exceeding a predetermined voltage from being supplied to the load circuit 52.
　これまで説明してきた本発明の電源供給装置２００は、バッテリ５１が車両に搭載されていることを前提として説明している。そのため、このように構成された電源供給装置２００は、低温時においても車両内の電子機器を支障なく動作させることができる。しかし、本発明の電源供給装置２００は、車両に搭載されたバッテリに留まらず、車両以外の種々の機器に搭載されているバッテリにも適用できることは言うまでもない。 The power supply device 200 of the present invention described so far has been described on the assumption that the battery 51 is mounted on the vehicle. Therefore, the power supply device 200 configured in this way can operate the electronic devices in the vehicle without any trouble even at low temperatures. However, it goes without saying that the power supply device 200 of the present invention is not limited to a battery mounted on a vehicle, but can be applied to a battery mounted on various devices other than the vehicle.
　以上説明したように、本発明の第１実施形態の電源供給装置１００、又は第２実施形態の電源供給装置２００は、バッテリ５１から出力される電圧が低下した場合においても、昇圧回路３へ供給する電圧を十分高い電圧にすることができる。そのため、バッテリ５１から出力される電圧が低下した場合においても、負荷回路５２を駆動するための電源を安定して供給することができる。 As described above, the power supply device 100 according to the first embodiment of the present invention or the power supply device 200 according to the second embodiment supplies the booster circuit 3 even when the voltage output from the battery 51 decreases. To a sufficiently high voltage. Therefore, even when the voltage output from the battery 51 is reduced, the power for driving the load circuit 52 can be stably supplied.
　１　　　　第１ＦＥＴ回路
　１ａ　　　エンハンスメント型ＦＥＴ
　１ｂ　　　抵抗
　２　　　　第２ＦＥＴ回路
　２ａ　　　デプレッション型ＦＥＴ
　２ｂ　　　抵抗
　３　　　　昇圧回路
　４　　　　制御回路
　１１　　　入力端子
　１２　　　出力端子
　２１　　　第３ＦＥＴ回路
　２１ａ　　エンハンスメント型ＦＥＴ
　２１ｂ　　抵抗
　２１ｃ　　ダイオード　２１ｄ　　ダイオード
　２２　　　第４ＦＥＴ回路
　２２ａ　　デプレッション型ＦＥＴ
　２２ｂ　　抵抗
　２２ｃ　　ツェナーダイオード
　３１　　　保護回路
　５１　　　バッテリ
　５２　　　負荷回路
　２００　　電源供給装置 1 1st FET circuit 1a Enhancement type FET
1b resistor 2 second FET circuit 2a depletion type FET
2b Resistance 3 Booster circuit 4 Control circuit 11 Input terminal 12 Output terminal 21 Third FET circuit 21a Enhancement type FET
21b resistor 21c diode 21d diode 22 4th FET circuit 22a depletion type FET
22b Resistor 22c Zener diode 31 Protection circuit 51 Battery 52 Load circuit 200 Power supply device

Claims (6)

  1. 　バッテリから電源が供給される入力端子と、負荷回路が接続される出力端子と、前記入力端子にドレインが接続され、前記出力端子にソースが接続された第１ＦＥＴと、前記出力端子に接続され、前記出力端子からの出力電圧を昇圧する昇圧回路と、前記昇圧回路及び前記負荷回路に接続された制御回路と、を備え、
    　前記第１ＦＥＴは、前記第１ＦＥＴのドレインとゲートに同一電圧が供給されている状態ではオフとなっている素子であり、前記昇圧回路によって昇圧された電圧を前記第１ＦＥＴのゲートに印加して前記第１ＦＥＴをオンさせることによって前記負荷回路に電源を供給する電源供給装置であって、
    　前記制御回路により制御可能とされる第２ＦＥＴを設け、前記第２ＦＥＴのドレインを前記第１ＦＥＴのドレインに接続すると共に、前記第２ＦＥＴのソースを前記第１ＦＥＴのソースに接続し、
    　前記第２ＦＥＴは、前記第２ＦＥＴのドレインとゲートに同一電圧が供給されている状態ではオンとしておくことが可能な素子であり、
    　前記負荷回路への電源供給開始時より前に、前記第２ＦＥＴをオンとしておくと共に、前記電源供給開始時に、前記第２ＦＥＴを介して前記昇圧回路に電圧を供給するようにしたことを特徴とする電源供給装置。     An input terminal to which power is supplied from a battery, an output terminal to which a load circuit is connected, a drain connected to the input terminal, a first FET having a source connected to the output terminal, and a connection to the output terminal, A booster circuit for boosting an output voltage from the output terminal, and a control circuit connected to the booster circuit and the load circuit,
    The first FET is an element that is turned off when the same voltage is supplied to the drain and the gate of the first FET, and the voltage boosted by the booster circuit is applied to the gate of the first FET. A power supply device that supplies power to the load circuit by turning on a first FET,
    Providing a second FET that can be controlled by the control circuit, connecting the drain of the second FET to the drain of the first FET, and connecting the source of the second FET to the source of the first FET;
    The second FET is an element that can be turned on when the same voltage is supplied to the drain and gate of the second FET,
    The second FET is turned on before the start of power supply to the load circuit, and the voltage is supplied to the booster circuit via the second FET at the start of power supply. Power supply device.
  2. 　前記負荷回路への電源供給開始時より前に、前記第１ＦＥＴ及び前記第２ＦＥＴに前記バッテリから電圧が供給されていて、
    　前記負荷回路への電源供給開始時に、前記制御回路からの第１制御信号によって前記昇圧回路を動作させて前記第１ＦＥＴをオンすると共に、前記負荷回路を動作可能としたことを特徴とする請求項１記載の電源供給装置。     Before the start of power supply to the load circuit, the voltage is supplied from the battery to the first FET and the second FET,
    2. The power supply circuit to the load circuit, wherein the boost circuit is operated by a first control signal from the control circuit to turn on the first FET, and the load circuit is operable. The power supply device according to 1.
  3. 　前記第１ＦＥＴがオンした後に、前記制御回路からの第２制御信号によって前記第２ＦＥＴをオフするようにしたことを特徴とする請求項１又は請求項２に記載の電源供給装置。 The power supply device according to claim 1 or 2, wherein the second FET is turned off by a second control signal from the control circuit after the first FET is turned on.
  4. 　前記第１ＦＥＴはエンハンスメント型ＦＥＴであり、前記第２ＦＥＴはデプレッション型ＦＥＴであって、
    　前記エンハンスメント型ＦＥＴのドレインとゲートが抵抗を介して接続されており、前記デプレッション型ＦＥＴのドレインとゲートが抵抗を介して接続されていることを特徴とする請求項１乃至請求項３のいずれかに記載の電源供給装置。     The first FET is an enhancement type FET, and the second FET is a depletion type FET,
    The drain and gate of the enhancement type FET are connected via a resistor, and the drain and gate of the depletion type FET are connected via a resistor. The power supply device described in 1.
  5. 　前記デプレッション型ＦＥＴは、ＭＯＳ・ＦＥＴであることを特徴とする請求項４に記載の電源供給装置。 The power supply device according to claim 4, wherein the depletion type FET is a MOS-FET.
  6. 　車両に搭載されたバッテリに接続されていることを特徴とする請求項１乃至請求項５のいずれかに記載の電源供給装置。 The power supply device according to any one of claims 1 to 5, wherein the power supply device is connected to a battery mounted on the vehicle.
PCT/JP2013/085190 2012-12-28 2013-12-27 Power supply device WO2014104332A1 (en)

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JP2012-287165 2012-12-28
JP2012287165A JP2016033691A (en) 2012-12-28 2012-12-28 Power supply device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109286237A (en) * 2018-11-12 2019-01-29 艾体威尔电子技术(北京)有限公司 A kind of circuit for controlling the access of low-power consumption backup battery or being detached from

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Publication number Priority date Publication date Assignee Title
JP2003108243A (en) * 2001-09-11 2003-04-11 Semikron Elektron Gmbh Circuit apparatus for voltage control
JP2007082374A (en) * 2005-09-16 2007-03-29 Denso Corp Protection circuit on reverse connection of power supply
JP2009199435A (en) * 2008-02-22 2009-09-03 Nec Corp Regulator circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003108243A (en) * 2001-09-11 2003-04-11 Semikron Elektron Gmbh Circuit apparatus for voltage control
JP2007082374A (en) * 2005-09-16 2007-03-29 Denso Corp Protection circuit on reverse connection of power supply
JP2009199435A (en) * 2008-02-22 2009-09-03 Nec Corp Regulator circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109286237A (en) * 2018-11-12 2019-01-29 艾体威尔电子技术(北京)有限公司 A kind of circuit for controlling the access of low-power consumption backup battery or being detached from
CN109286237B (en) * 2018-11-12 2024-03-22 艾体威尔电子技术(北京)有限公司 Circuit for controlling low-power-consumption backup battery to be connected or disconnected

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