WO2014188570A1

WO2014188570A1 - Semiconductor device

Info

Publication number: WO2014188570A1
Application number: PCT/JP2013/064411
Authority: WO
Inventors: 佳史安田; 亀山　悟
Original assignee: トヨタ自動車株式会社
Priority date: 2013-05-23
Filing date: 2013-05-23
Publication date: 2014-11-27

Abstract

This semiconductor device has a semiconductor substrate that is provided with a main region, and a sense region for detecting a current flowing in the main region. The main region and the sense region of the semiconductor substrate have a same element structure. Furthermore, the sense region of the semiconductor substrate has: a conductive first region electrically connected to a first portion of the semiconductor device; a conductive second region electrically connected to a second portion of the semiconductor device, said second portion being different from the first portion; and an insulating film, which is disposed between the first region and the second region, and which separates the second region from the first region.

Description

Semiconductor device

The technology disclosed in this specification relates to a semiconductor device in which a main region and a sense region are formed on the same semiconductor substrate.

In order to prevent an overcurrent from flowing through the semiconductor device, a semiconductor device having a sense region for detecting a current flowing through the semiconductor device has been developed. Japanese Patent Publication No. 10-326897 discloses a semiconductor device in which a main region and a sense region are formed on the same semiconductor substrate. In this semiconductor device, IGBTs are formed in the main region and the sense region. In this semiconductor device, the current flowing through the main region can be detected by detecting the current flowing through the sense region.

In this type of semiconductor device, the area of the sense region is extremely small compared to the main region. For this reason, the electrostatic tolerance of the sense region is smaller than that of the main region, and the electrostatic tolerance of the semiconductor device is determined by the electrostatic tolerance of the sense region. As a result, the electrostatic resistance of the semiconductor device is lower than that of a semiconductor device that does not include a sense region.

This specification discloses a technique capable of improving the electrostatic resistance of a semiconductor device in which a main region and a sense region are formed on the same semiconductor substrate.

The semiconductor device disclosed in this specification includes a semiconductor substrate including a main region and a sense region for detecting a current flowing in the main region. Each of the main region and the sense region of the semiconductor substrate has the same element structure. In addition to the element structure, the sense region of the semiconductor substrate further includes a conductive first region, a conductive second region, and an insulating film. The first region is electrically connected to the first part of the semiconductor device. The second region is electrically connected to a second part different from the first part of the semiconductor device. The insulating film is disposed between the first region and the second region, and isolates the second region from the first region.

In this semiconductor device, a conductive first region, a conductive second region, and an insulating film are formed in the sense region, and a capacitor is constituted by these. The first region and the second region are electrically connected to different parts of the semiconductor device, and different potentials can be applied. For this reason, when different potentials are applied to the first region and the second region, charges are stored in the capacitor constituted by the first region, the second region, and the insulating film. Accordingly, the capacitance of the sense region can be increased, and the electrostatic resistance of the semiconductor device can be improved.

FIG. 2 is a plan view showing a part of the semiconductor device according to the first embodiment. II-II sectional view of the semiconductor device shown in FIG. FIG. 2 is a diagram showing a circuit equivalent to the semiconductor device shown in FIG. 1. Sectional drawing of the semiconductor device which concerns on the modification of 1st Example. Sectional drawing of the semiconductor device which concerns on the other modification of 1st Example. Sectional drawing of the semiconductor device which concerns on the other modification of 1st Example. FIG. 7 is a sectional view taken along line VII-VII in FIG. 6. Sectional drawing of the semiconductor device of 2nd Example. FIG. 9 illustrates a circuit equivalent to the semiconductor device illustrated in FIG. 8. Sectional drawing of the semiconductor device which concerns on the modification of 2nd Example.

The semiconductor device disclosed in the present specification further includes a main electrode disposed on the main region of the upper surface of the semiconductor substrate, and a sense electrode disposed on the sense region of the upper surface of the semiconductor substrate. Also good. At least a part of the first region and the second region may be located below the sense electrode. According to such a configuration, the semiconductor substrate can be effectively used by forming a part of the first region and the second region below the sense electrode. As a result, an increase in size of the semiconductor device can be suppressed.

In the semiconductor device disclosed in this specification, the first region may be a semiconductor layer exposed on the upper surface of the semiconductor substrate. In this case, at least one trench extending downward from the upper surface of the semiconductor substrate may be formed in the first region. The second region may be a conductor disposed in the trench. The insulating film may be disposed between the wall surface of the trench and the second region. According to such a configuration, by disposing the conductor (second region) and the insulating film in the trench formed in the first region, the capacitance of the capacitor configured by the first region, the second region, and the insulating film. Can be increased efficiently.

In the semiconductor device disclosed in this specification, the element structure of the main region has a first conductivity type main drift region, a second conductivity type main body region in contact with the main drift region, and a main body region. And a first conductivity type main contact region separated from the main drift region by the main body region, and a main body region in a range separating the main contact region and the main drift region through the gate insulating film And a main gate electrode. Further, the element structure of the sense region is in contact with the first conductivity type sense drift region, the second conductivity type sense body region in contact with the sense drift region, and the sense body region. A sense contact electrode of a first conductivity type separated from the region; a sense body region in a range separating the sense contact region and the sense drift region; You may have. A main electrode that contacts the main contact region may be disposed on the main region of the upper surface of the semiconductor substrate. A sense electrode in contact with the sense contact region may be disposed on the sense region in the upper surface of the semiconductor substrate. In this semiconductor device, switching elements are formed in the main region and the sense region, and the current flowing through the main region can be detected by the current flowing through the sense region.

In the above semiconductor device, the first region may be electrically connected to the main electrode, and the second region may be electrically connected to the sense electrode. According to such a configuration, the sense electrode and the main electrode are connected by the capacitor. For this reason, even if electrostatic discharge occurs in the sense electrode, it is possible to suppress application of an overvoltage to the sense electrode. As a result, an overvoltage is suppressed from being applied to the gate insulating film that covers the sense gate electrode, and this gate insulating film can be protected.

Alternatively, in the above semiconductor device, the first region may be electrically connected to the sense electrode, and the second region may be electrically connected to the main gate electrode or the sense gate electrode. According to such a configuration, the sense electrode and the sense gate electrode are connected by the capacitor. For this reason, even if electrostatic discharge occurs in the sense electrode, it is possible to suppress application of an overvoltage to the sense electrode. As a result, an overvoltage is suppressed from being applied to the gate insulating film that covers the sense gate electrode, and this gate insulating film can be protected.

First Example Hereinafter, a semiconductor device 10 of a first example will be described with reference to the drawings. As shown in FIGS. 1 and 2, the semiconductor device 10 includes a semiconductor substrate 12,

insulating films

36, 44, 46, 62 and

electrodes

38, 64 formed on the upper surface of the semiconductor substrate 12, and a lower surface of the semiconductor substrate 12. The formed electrode 40 is provided. The semiconductor substrate 12 has a main region 20, a sense region 50, and an isolation region 80. That is, the main region 20 and the sense region 50 are formed on the same semiconductor substrate 12. The isolation region 80 is disposed between the main region 20 and the sense region 50. As apparent from FIG. 1, the sense region 50 is smaller than the main region 20. As the semiconductor substrate 12, a known substrate (for example, a silicon substrate (Si substrate), a silicon carbide substrate (SiC substrate), or the like) can be used. In this specification, a region where a main emitter electrode 38 (described later) is formed is referred to as a main region 20, and a region where a sense emitter electrode 64 (described later) is formed is referred to as a sense region 50.

(Main area 20)
First, the main area 20 will be described. As shown in FIG. 2, an emitter region 34, a body region 26, a drift region 24, and a collector region 22 are formed in the main region 20 of the semiconductor substrate 12. The emitter region 34 is an n ⁺ type semiconductor region and is formed in a range facing the upper surface of the semiconductor substrate 12. A plurality of emitter regions 34 are formed at intervals in the x direction. Each emitter region 34 is formed in an island shape extending in the y direction.

The body region 26 is a p ⁻ type semiconductor region and is formed below the emitter region 34. The body region 26 is in contact with the lower surface and the side surface of the emitter region 34. A part of the body region 26 is located between adjacent emitter regions 34 and exposed on the upper surface of the semiconductor substrate 12.

The drift region 24 is an n ⁻ type semiconductor region and is formed below the body region 26. The drift region 24 is in contact with the lower surface of the body region 26. The drift region 24 is separated from the emitter region 34 by the body region 26. The drift region 24 is formed on the entire surface of the semiconductor substrate 12. Therefore, the drift region 24 is also formed in the sense region 50 and the isolation region 80.

The collector region 22 is a p ⁺ type semiconductor region and is formed in a range facing the lower surface of the semiconductor substrate 12. The collector region 22 is in contact with the lower surface of the drift region 24. The collector region 22 is separated from the body region 26 by the drift region 24. The collector region 22 is formed on the entire surface of the semiconductor substrate 12. Therefore, the collector region 22 is also formed in the sense region 50 and the isolation region 80.

A plurality of gate trenches 28 are formed in the main region 20 described above. The gate trenches 28 extend in the y direction and are arranged at intervals in the x direction. The gate trench 28 penetrates the emitter region 34 and the body region 26, and its lower end extends to the drift region 24. A gate electrode 32 is formed in the gate trench 28. The gate electrode 32 is formed so that the lower end thereof is slightly deeper than the lower surface of the body region 26. For example, polysilicon or the like can be used as the material of the gate electrode 32. An insulating film 30 is filled between the wall surface of the gate trench 28 and the gate electrode 32. For this reason, the gate electrode 32 faces the body region 26 and the emitter region 24 with the insulating film 30 interposed therebetween. An insulating film 36 is formed on the gate electrode 32. The gate electrode 32 is insulated from the main emitter electrode 38 by the insulating film 36.

A collector electrode 40 is formed on the lower surface of the semiconductor substrate 12. The collector electrode 40 is in ohmic contact with the collector region 22. The collector electrode 40 is formed on the entire surface of the semiconductor substrate 12. Therefore, the collector electrode 40 is formed not only in the main region 20 but also in the sense region 50 and the isolation region 80.

A main emitter electrode 38 is formed on the upper surface of the semiconductor substrate 12. The main emitter electrode 38 is formed so as to cover the insulating film 36 and is insulated from the gate electrode 32. The main emitter electrode 38 is in ohmic contact with the emitter region 34 and the body region 26. The main emitter electrode 38 is formed on the main region 20 of the semiconductor substrate 12.

As is apparent from the above, a vertical IGBT (Insulated Gate Bipolar Transistor) is formed in the main region 20 of the semiconductor substrate 12. The IGBT formed in the main region 20 is surrounded by the diffusion layer 42. The diffusion layer 42 is a p + type semiconductor region and is formed in a range facing the upper surface of the semiconductor substrate 12. The diffusion layer 42 is in contact with the body region 26 and the drift region 24 and surrounds the body region 26. The diffusion layer 42 is formed to a position deeper than the lower end of the gate trench 28. As shown in FIG. 1, a part of the diffusion layer 42 is located in the main region 20 (below the main emitter electrode 38), and in the isolation region 80 and the sense region 50 (that is, below the sense emitter electrode 64). Is also located. An insulating film 44 is formed on the upper surface of the diffusion layer 42. This prevents the diffusion layer 42 from coming into direct contact with the main emitter electrode 38 and the sense emitter electrode 64.

(Sense region 50)
Next, the sense region 50 will be described. An IGBT having the same structure as that of the main region 20 is also formed in the sense region 50. That is, an n ⁺ type emitter region 60, a p ⁻ type body region 52, an n ⁻ type drift region 24, and a p ⁺ type collector region 22 are formed in the sense region 50 of the semiconductor substrate 12. Yes. A plurality of gate trenches 54 are also formed in the sense region 50, and a gate electrode 58 and an insulating film 56 are formed in the gate trench 54. The emitter region 60, the body region 52, the drift region 24, the collector region 22, the gate electrode 58 and the insulating film 56 form an IGBT. As apparent from FIG. 1, the area of the IGBT formed in the sense region 50 is much smaller than the area of the IGBT formed in the main region 20.

Also in the sense region 50, a collector electrode 40 is formed on the lower surface of the semiconductor substrate 12. On the other hand, in the sense region 50, a sense emitter electrode 64 is formed on the upper surface of the semiconductor substrate 12. The sense emitter electrode 64 is formed so as to cover the insulating

films

62 and 44 and is insulated from the gate electrode 58. The sense emitter electrode 64 is in ohmic contact with the emitter region 60 and the body region 52.

The IGBT formed in the sense region 50 is surrounded by the diffusion layer 76. The diffusion layer 76 is a p + type semiconductor region and is formed in a range facing the upper surface of the semiconductor substrate 12. The diffusion layer 76 is in contact with the body region 52 and the drift region 24 and is formed to a position deeper than the lower end of the gate trench 54 (that is, the gate trench 28 of the main region 20). As shown in FIG. 1, the diffusion layer 76 surrounds the body region 52. The drift region 24 is disposed between the diffusion layer 76 and the diffusion layer 42, and the diffusion layer 76 is surrounded by the drift region 24. Thereby, the diffusion layer 76 is separated from the diffusion layer 42. An insulating film 44 is also formed on the upper surface of the diffusion layer 76. The insulating film 44 is also formed on the upper surface of the drift region 24 in a range that separates the diffusion layer 76 and the diffusion layer 42.

A diffusion layer 42 is further formed in the sense region 50 of the semiconductor substrate 12. That is, the diffusion layer 42 surrounding the IGBT in the main region 20 is formed up to the lower side of the sense emitter electrode 64. As apparent from FIG. 2, in the sense region 50, a plurality of trenches 68 are formed in the diffusion layer 42. The plurality of trenches 68 are formed in the entire portion of the diffusion layer 42 located below the sense electrode 64. That is, the trench 68 extends from one end to the other end in the y direction of the sense electrode 64 (see FIG. 1), and one end in the x direction of the sense electrode from the boundary between the drift region 24 and the diffusion layer 42 (lower end in FIG. 1). Are arranged at intervals in the x direction. Note that the interval between the adjacent trenches 68 is narrower than the interval between the

gate trenches

54 and 28. Each trench 68 extends downward from the upper surface of the semiconductor substrate 12, and its lower end is located in the diffusion layer 42. That is, the lower end of the trench 68 does not reach the drift region 24. The depth of the trench 68 is the same as the depth of the

gate trenches

54 and 28. A conductor 72 is formed in the trench 68. For example, polysilicon or the like can be used as the material of the conductor 72. An insulating film 70 is filled between the wall surface of the trench 68 and the conductor 72. Therefore, the conductor 72 is opposed to the diffusion layer 42 with the insulating film 70 interposed therebetween.

The upper end of the conductor 72 in each trench 68 is connected to the conductive layer 74. The conductive layer 74 is disposed in the insulating film 44. An opening is formed in the insulating film 44 at a position (not shown), and the conductive layer 74 and the sense emitter electrode 64 are connected through this opening.

(Separation region 80)
Next, the separation region 80 will be described. As shown in FIG. 1, the isolation region 80 is a region that separates the main region 20 and the sense region 50 and is formed so as to surround the sense region 50. As shown in FIG. 2, in the isolation region 80, a diffusion layer 42, a drift region 24, and a diffusion layer 76 are formed in a range facing the upper surface of the semiconductor substrate 12 (see FIG. 2). An insulating film 44 and an insulating film 46 are formed on the upper surface of the drift region 24. The insulating film 46 is formed up to the main emitter electrode 38 and the sense emitter electrode 64. Also in the isolation region 80, the collector region 22 is formed below the drift region 24.

Next, the operation of the semiconductor device 10 will be described. With the main emitter electrode 38 and the sense emitter electrode 64 connected to the ground potential and the collector electrode 12 connected to the power supply potential, the

gate electrodes

32 and 58 have an ON potential (a potential higher than the potential necessary for forming a channel). ) Is applied, the semiconductor device 10 is turned on. That is, by applying an ON potential to the

gate electrodes

32 and 58, channels are formed in the

body regions

26 and 52 in a range in contact with the insulating

films

30 and 56. Then, in the main region 20, a current flows from the collector electrode 40 to the main emitter electrode 38, and in the sense region 50, a current flows from the collector electrode 40 to the sense emitter electrode 64. Here, the ratio of the current flowing through the main region 20 and the current flowing through the sense region 50 (so-called sense ratio) is determined by the area ratio between the main region 20 and the sense region 50 and is a substantially constant value. Therefore, by detecting the current flowing through the sense region 50, the current value flowing through the main region 20 can be calculated from the detected current value and the sense ratio.

Further, in the semiconductor device 10 of this embodiment, the trench 68 is formed in the diffusion layer 42 of the sense region 50, and the conductor 72 and the insulating film 70 are disposed in the trench 68. The diffusion layer 42 is electrically connected to the main emitter electrode 38 via the body region 26, and the conductor 72 is electrically connected to the sense emitter electrode 64 via the conductive layer 74. That is, the same potential as that applied to the main emitter electrode 38 is applied to the diffusion layer 42, and the same potential as that applied to the sense emitter electrode 64 is applied to the conductor 72. Therefore, in the semiconductor device 10 of this embodiment, as shown in FIG. 3, a capacitor 76 is constituted by the diffusion layer 42, the insulating film 70, and the conductor 72, and one end of the capacitor 76 is connected to the main emitter electrode 38. On the other hand, the other end of the capacitor 76 is connected to the sense emitter electrode 64. Therefore, even if electrostatic discharge occurs in the sense emitter electrode 64, the capacitor 76 between the sense emitter electrode 64 and the main emitter electrode 38 and the capacitor between the sense emitter electrode 64 and the gate electrode 58 (the gate electrode 58 and the insulating film) The electric charge is stored in a capacitor constituted by 56 and the body region 52. As a result, application of an excessive voltage to the insulating film 56 is suppressed, and the electrostatic resistance of the sense region 50 can be improved.

Further, in the semiconductor device 10 of the present embodiment, since the capacitor 76 is only formed between the sense emitter electrode 64 and the main emitter electrode 38, a current path for releasing charges due to electrostatic discharge is not required. For this reason, a leak current due to the current path does not occur, and it is not necessary to consider that the parasitic resistance of the current path is lowered to quickly release the charge.

In the semiconductor device 10 of this embodiment, the capacitor 76 is formed on the semiconductor substrate 12 below the sense emitter electrode 64. Therefore, the formation of the capacitor 76 does not increase the size of the semiconductor substrate 12, and the size of the semiconductor device 10 does not increase. A trench 68 is formed in the entire sense emitter electrode 64 (excluding the region where the IGBT is formed), and the interval between the trenches 68 is also shorter than the interval between the

gate trenches

28 and 54. Therefore, the capacitance of the capacitor 76 can be effectively increased, and the electrostatic resistance of the sense region 50 can be effectively increased. Further, by disposing the conductive layer 74 in the insulating film 44, the conductive layer 74, the insulating film 44, and the diffusion layer 42 also constitute a capacitor. This also increases the capacitance component of the sense region 50 and increases the electrostatic resistance.

Further, in the semiconductor device 10 of this embodiment, the diffusion layer 42 in the sense region 50 is separated from the body region 52 by the drift region 24 and the diffusion layer 76. For this reason, the holes from the collector electrode 40 are suppressed from flowing to the sense emitter electrode 64 through the diffusion layer 42. For this reason, the accuracy of the sense current flowing through the sense region 50 (the accuracy of the sense ratio) is improved, and the current flowing through the main region 20 can be detected with high accuracy.

In the semiconductor device 10 of the first embodiment described above, the conductive layer 74 is electrically connected to the sense emitter electrode 64 in the opening formed in the insulating film 44. However, the structure for electrically connecting the conductive layer and the sense emitter electrode is not limited to such a form. For example, unlike the semiconductor device 10a shown in FIG. 4, the upper surface of the conductive layer 74a connected to the conductor 72 is not covered with the insulating film 44a, and the entire upper surface of the conductive layer 74a is in contact with the sense emitter electrode 64a. You may do it. Also with such a configuration, the conductor 72 can be electrically connected to the sense emitter electrode 64a, and the same effect as the first embodiment can be obtained. In the semiconductor device 10a shown in FIG. 4, portions having the same configuration as those of the semiconductor device 10 shown in FIGS. (Similarly, in the semiconductor device of FIGS. 5 to 7, the same reference numerals are given to the parts having the same configuration as the semiconductor device 10 shown in FIGS. 1 and 2.)

In the semiconductor device 10 of the first embodiment described above, the p ⁺ -type diffusion layer 42 is formed below the sense emitter electrode 64, and the trench 68 and the like are formed in the diffusion layer 42. However, a p ⁻ -type diffusion region 78 may be formed below the sense emitter electrode 64 as in the semiconductor device 10b shown in FIG. In this case, the diffusion region 78 is in contact with the diffusion region 42 and is electrically connected to the main emitter electrode 38 via the diffusion region 42 and the body region 26. Even with such a configuration, the same operational effects as the semiconductor device 10 of the first embodiment can be obtained. If the depth and concentration of the diffusion region 78 are the same as those of the

body regions

26 and 52, the

body regions

26 and 52 and the diffusion region 78 can be formed by the same process. Further, when the diffusion region 78 has the same depth as the

body regions

26 and 52, the trench 68 penetrates the diffusion region 78 and the lower end thereof reaches the drift region 24.

In the semiconductor device 10 of the first embodiment described above, the conductor 72 protrudes upward from the trench 68 and is connected to the conductive film 74 in the insulating film 44. However, like the semiconductor device 10 c shown in FIG. 6, the conductor 72 a may be disposed only in the trench 68 as with the

gate electrodes

32 and 58. In this case, as shown in FIG. 7, an opening 45 is formed in the insulating film 44 at the end in the longitudinal direction of the conductor 72a, and the conductor 72a and the sense emitter electrode 64 are electrically connected through the opening 45. May be. Even with such a configuration, the same operational effects as the semiconductor device 10 of the first embodiment can be obtained. The

gate electrodes

32 and 58 and the conductor 72a can be formed by the same process.

Second Embodiment Unlike the semiconductor device 10 of the first embodiment, the semiconductor device 100 of the second embodiment is different in that a capacitor is formed between the sense emitter electrode 64 and the

gate electrodes

32 and 58. However, since other configurations are the same as those of the semiconductor device 10 of the first embodiment, the description thereof is omitted. In addition, the same code | symbol is attached | subjected to the site | part which becomes the structure similar to the semiconductor device 10 of 1st Example.

In the semiconductor device 100 shown in FIG. 8, in the sense region 120, the body region 52 and the p ⁺ type diffusion layer 102 are in contact with each other, and the diffusion layer 102 is electrically connected to the sense emitter electrode 64 through the body region 52. ing. As a result, the same potential as that of the sense emitter electrode 64 is applied to the diffusion layer 102. The diffusion layer 102 surrounds the body region 52, and the diffusion layer 102 and the diffusion layer 42 are separated by the drift region 24. For this reason, the diffusion layer 102 is not electrically connected to the main emitter electrode 38 via the diffusion layer 42 and the body region 26.

The diffusion layer 102 is formed in a range facing the upper surface of the semiconductor substrate 12, and is formed up to a position deeper than the lower end of the gate trench 54. The diffusion layer 102 is formed on the entire area below the sense emitter electrode 64. That is, when viewed in plan, the diffusion layer 102 is formed over the entire sense emitter electrode 64. A plurality of trenches 104 are formed in the diffusion layer 102. The plurality of trenches 104 are formed in the entire diffusion layer 102. The plurality of trenches 104 extend in the y direction and are arranged at intervals in the x direction. The trench 104 is formed in the same manner as the trench 68 of the first embodiment, and a conductor 108 and an insulating film 106 are formed therein. For this reason, the conductor 108 faces the diffusion layer 102 with the insulating film 106 interposed therebetween.

The upper end of the conductor 108 in each trench 104 is connected to the conductive layer 110. The conductive layer 110 is disposed in the insulating film 44. An opening is formed in the insulating film 44 at a position not shown, and the conductive layer 110 is electrically connected to a gate wiring (not shown) through this opening. For this reason, the conductor 108 is electrically connected to the gate wiring through the conductive layer 110, and the same potential as that of the

gate electrodes

32 and 58 is applied.

In the semiconductor device 100 of this embodiment, the trench 104 is formed in the diffusion layer 102 of the sense region 120, and the conductor 108 and the insulating film 106 are disposed in the trench 104. The diffusion layer 102 is electrically connected to the sense emitter electrode 64 via the body region 52, and the conductor 108 is electrically connected to the

gate electrodes

32 and 58 via the conductive layer 110. That is, the same potential as that applied to the sense emitter electrode 64 is applied to the diffusion layer 102, and the same potential as that applied to the

gate electrodes

32 and 58 is applied to the conductor 108. Therefore, in the semiconductor device 100 of this embodiment, as shown in FIG. 9, a capacitor 112 is constituted by the diffusion layer 102, the insulating film 106, and the conductor 108, and one end of the capacitor 112 is connected to the sense emitter electrode 64. On the other hand, the other end of the capacitor 112 is connected to the

gate electrodes

32 and 58. Therefore, even if electrostatic discharge occurs in the sense emitter electrode 64, the capacitor 112 between the sense emitter electrode 64 and the

gate electrodes

32 and 58 and the capacitor between the sense emitter electrode 64 and the gate electrode 58 (insulated from the gate electrode 58) Charge is stored in a capacitor formed by the film 56 and the body region 52. As a result, application of an excessive voltage to the insulating film 56 is suppressed, and the electrostatic resistance of the sense region 50 can be improved.

Further, in the semiconductor device 100, the configuration of the trench 104, the insulating film 106, and the conductor 108 can be made substantially the same as the configuration of the gate trench 54, the insulating film 56, and the gate electrode 58. Therefore, these can be formed by the same process, and the semiconductor device 100 can be easily manufactured.

In the second embodiment described above, the diffusion layer 102 is brought into contact with the body region 52, and the trench 104, the conductor 108, and the insulating film 106 are formed in the diffusion layer 102. However, the configuration of the capacitor 112 formed in the sense region 120 is not limited to such a configuration. For example, as in the semiconductor device 10 of the first embodiment shown in FIG. 1, the diffusion layer in which the trench 104, the conductor 108 and the insulating film 106 are formed may be separated from the body region 52 by the drift region 24. When such a configuration is adopted, an opening may be formed in the insulating film formed on the upper surface of the diffusion layer, and the diffusion layer and the sense emitter electrode 64 may be electrically connected via the opening.

Further, the conductor 108 disposed in the trench 104 may be configured to bury the conductor 108 in the trench 104 as in the semiconductor device 10c shown in FIG. Further, as in the semiconductor device 100a shown in FIG. 10, the trench 104 is formed in the body region 52a of the sense region 120a separately from the gate trench 54, and the conductor 108 and the insulating film 106 are formed in the trench 104. It may be. Even with such a configuration, the capacitor component of the sense region 120a can be increased, and the electrostatic resistance can be improved. In the semiconductor device 100a, the upper ends of the two trenches 104a adjacent to the gate trench 54 functioning as the IGBT (the gate trench in contact with the emitter region 60) are closed with the insulating film 44c, and the insulating film 44c includes the adjacent trench 104a. No opening is formed between them. As a result, the holes are suppressed from flowing to the sense emitter electrode 64b through other than the element portion, and the accuracy of the sense current (the accuracy of the sense ratio) is improved.

As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

For example, in each of the embodiments described above, capacitors (trench, conductor, insulating film) are formed in the

sense regions

50, 120, but a capacitor (trench, conductor, insulating film) may be formed in the main region 20. . Even with such a configuration, the capacitance components of the

sense regions

50 and 120 can be increased, and the electrostatic resistance can be improved.

Further, in each of the above-described embodiments, a vertical semiconductor element (specifically, an IGBT) is formed on the semiconductor substrate 12, but a horizontal semiconductor element may be formed on the semiconductor substrate 12. Further, the semiconductor element formed on the semiconductor substrate 12 is not limited to the IGBT, and may be another semiconductor element (for example, MOS).

The technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

Claims

A semiconductor device,
A semiconductor substrate having a main region and a sense region for detecting a current flowing in the main region;
The main region and the sense region of the semiconductor substrate have the same element structure,
In addition to the element structure, the sense region of the semiconductor substrate further includes:
A conductive first region electrically connected to the first portion of the semiconductor device;
A conductive second region electrically connected to a second part different from the first part of the semiconductor device;
A semiconductor device having an insulating film disposed between the first region and the second region and isolating the second region from the first region;
A main electrode disposed on the main region of the upper surface of the semiconductor substrate;
A sense electrode disposed on the sense region of the upper surface of the semiconductor substrate, and
The semiconductor device according to claim 1, wherein at least part of the first region and the second region is located below the sense electrode.
The first region is a semiconductor layer exposed on the upper surface of the semiconductor substrate,
In the first region, at least one trench extending downward from the upper surface of the semiconductor substrate is formed,
The second region is a conductor disposed in the trench,
The semiconductor device according to claim 1, wherein the insulating film is disposed between the wall surface of the trench and the second region.
The element structure of the main region is
A main drift region of a first conductivity type;
A second conductivity type main body region in contact with the main drift region;
A main contact region of a first conductivity type in contact with the main body region and separated from the main drift region by the main body region;
A main body region in a range separating the main contact region and the main drift region, and a main gate electrode facing the gate insulating film,
The element structure of the sense region is
A sense drift region of a first conductivity type;
A second conductivity type sense body region in contact with the sense drift region;
A sense contact region of a first conductivity type in contact with the sense body region and separated from the sense drift region by the sense body region;
A sense body region in a range separating the sense contact region and the sense drift region, and a sense gate electrode facing the gate insulating film,
A main electrode disposed on the main region of the upper surface of the semiconductor substrate and in contact with the main contact region;
The semiconductor device according to any one of claims 1 to 3, further comprising a sense electrode disposed on the sense region of the upper surface of the semiconductor substrate and in contact with the sense contact region.
The first region is electrically connected to the main electrode,
The semiconductor device according to claim 4, wherein the second region is electrically connected to the sense electrode.
The first region is electrically connected to the sense electrode;
The semiconductor device according to claim 4, wherein the second region is electrically connected to the main gate electrode or the sense gate electrode.