WO2014021252A1

WO2014021252A1 - Semiconductor device and production method therefor

Info

Publication number: WO2014021252A1
Application number: PCT/JP2013/070448
Authority: WO
Inventors: 安弘小原; 原田　光徳; 聖中原
Original assignee: シャープ株式会社
Priority date: 2012-08-02
Filing date: 2013-07-29
Publication date: 2014-02-06
Also published as: US9496287B2; JPWO2014021252A1; US20150162348A1; JP5964967B2

Abstract

A semiconductor device (100A) is provided with: a transparent conductive layer (3); an insulating layer (5) that is formed so as to cover the transparent conductive layer (3) and that comprises an opening (5u) that at least partially overlaps with the transparent conductive layer (3); a metal layer (7d) that is formed on the insulating layer (5) and within the opening (5u); and a contact section (90) that connects the transparent conductive layer (3) and the metal layer (7d). A nitride layer (20) comprising a metal that has a high melting point is arranged at the contact section (90) between the transparent conductive layer (3) and the part of the metal layer (7d) that is positioned within the opening (5u). The nitride layer (20) comprising a metal that has a high melting point is in contact with the upper surface of the transparent conductive layer (3).

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof.

An active matrix substrate used for a liquid crystal display device or the like includes a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel. Conventionally, as such a switching element, a TFT having an amorphous silicon film as an active layer (hereinafter referred to as “amorphous silicon TFT”) or a TFT having a polycrystalline silicon film as an active layer (hereinafter referred to as “polycrystalline silicon TFT”). Is widely used. In recent years, it has also been proposed to use an oxide semiconductor instead of amorphous silicon or polycrystalline silicon as a material for the active layer of a TFT. Such a TFT is referred to as an “oxide semiconductor TFT”. An oxide semiconductor has higher mobility than amorphous silicon. For this reason, the oxide semiconductor TFT can operate at a higher speed than the amorphous silicon TFT. In addition, since the oxide semiconductor film is formed by a simpler process than the polycrystalline silicon film, the oxide semiconductor film can be applied to a device that requires a large area.

In an active matrix substrate used for a display device, a TFT is provided for each pixel and functions as a switching element. The drain electrode of each TFT is connected to the pixel electrode. For example, Patent Document 1 discloses an active matrix substrate used for an IPS (In-Plane Switching) type liquid crystal display device. In the active matrix substrate disclosed in Patent Document 1, a pixel electrode and a drain electrode of a TFT are connected in a contact hole formed in an interlayer insulating layer.

JP 2007-328210 A

As described above, in a semiconductor device such as an active matrix substrate (TFT substrate) provided with a TFT, for example, a contact portion for connecting a transparent conductive layer such as a pixel electrode and a metal layer such as a drain electrode is provided.

As a result of investigations by the present inventors, it has been found that, in the contact portion between the transparent conductive layer and the metal layer, the contact resistance may be increased or the adhesion may be lowered depending on the configuration of the contact portion and the material of each layer. . This is a finding that the present inventor has found in various configurations of semiconductor devices such as an active matrix substrate. Detailed description will be described later.

When the resistance of the contact portion is increased, desired characteristics may not be obtained. Further, the reliability of the semiconductor device may not be ensured due to a decrease in adhesion between the metal layer and the transparent conductive layer in the contact portion.

In view of the above circumstances, an object of an embodiment of the present invention is to suppress an increase in resistance and a decrease in adhesion in a contact portion in a semiconductor device including a contact portion between a transparent conductive layer and a metal layer.

A semiconductor device according to an embodiment of the present invention includes a substrate, a transparent conductive layer supported by the substrate, and an opening formed to cover the transparent conductive layer and at least partially overlaps the transparent conductive layer. An insulating layer; a metal layer formed on the insulating layer and in the opening; and a contact portion that connects the transparent conductive layer and the metal layer. In the contact portion, the transparent conductive layer and the metal A refractory metal nitride layer is disposed between the layer and the portion located in the opening, and the refractory metal nitride layer is in contact with the upper surface of the transparent conductive layer.

In one embodiment, the shape of the refractory metal nitride layer is different from the shape of the metal layer when viewed from the normal direction of the substrate.

In one embodiment, the refractory metal nitride layer is in contact with a portion of the metal layer located in the opening.

In one embodiment, the semiconductor device further includes a thin film transistor supported by the substrate, and the thin film transistor includes a semiconductor layer including a channel region, a gate electrode, and a gate formed between the gate electrode and the semiconductor layer. An insulating layer, and a source electrode and a drain electrode electrically connected to the semiconductor layer, wherein the metal layer is an electrode layer electrically connected to the drain electrode or the drain electrode of the thin film transistor; The insulating layer includes the gate insulating layer, and the transparent conductive layer functions as a pixel electrode.

In one embodiment, the gate electrode includes a first gate layer formed of the same metal nitride film as the refractory metal nitride layer.

In one embodiment, the gate electrode further includes a second gate layer disposed on the first gate layer, and the second gate layer is formed of a material different from that of the first gate layer. ing.

In one embodiment, the semiconductor device further includes a conductive layer formed of the same conductive film as the second gate layer, between the refractory metal nitride layer and the metal layer.

In one embodiment, the semiconductor device further includes an insulating layer between the gate electrode, the transparent conductive layer, and the insulating layer.

In one embodiment, the semiconductor device has a base insulating layer between the substrate, the gate electrode, and the transparent conductive layer.

In one embodiment, at least a part of the upper surface of the nitride layer is in contact with the insulating layer.

A semiconductor device according to another embodiment of the present invention connects a substrate, a transparent conductive layer supported by the substrate, a metal layer formed on the transparent conductive layer, and the transparent conductive layer and the metal layer. A refractory metal nitride layer is disposed between the transparent conductive layer and the metal layer in the contact portion, and the refractory metal nitride layer is transparent. The refractory metal nitride layer is in contact with the upper surface of the conductive layer and viewed from the normal direction of the substrate, and the refractory metal nitride layer is disposed in a region where the metal layer and the transparent conductive layer overlap. The shape of the nitride layer is different from the shape of the metal layer.

In one embodiment, the refractory metal nitride layer is disposed over the entire region where the metal layer and the transparent conductive layer overlap when viewed from the normal direction of the substrate.

In one embodiment, the semiconductor device further includes a thin film transistor supported by the substrate, and the thin film transistor includes a semiconductor layer including a channel region, a gate electrode, and a gate formed between the gate electrode and the semiconductor layer. An insulating layer; and a source electrode and a drain electrode electrically connected to the semiconductor layer, wherein the metal layer and the transparent conductive layer are disposed on the gate insulating layer, and the metal layer includes: The drain electrode of the thin film transistor or an electrode layer electrically connected to the drain electrode, and the transparent conductive layer functions as a pixel electrode.

In one embodiment, the semiconductor device includes a protective layer formed on the source electrode and the drain electrode, and a common electrode disposed so as to overlap at least part of the transparent conductive layer with the protective layer interposed therebetween. And further.

In one embodiment, the semiconductor layer is an oxide semiconductor layer.

In one embodiment, the oxide semiconductor layer contains In, Ga, and Zn.

In one embodiment, the oxide semiconductor layer has crystallinity.

A method for manufacturing a semiconductor device according to an embodiment of the present invention is the above-described method for manufacturing a semiconductor device, wherein after forming the transparent conductive layer on the substrate, before forming the gate electrode and the insulating layer, The nitride layer is formed.

The method of manufacturing a semiconductor device according to another embodiment of the present invention includes a step (a) of preparing a substrate, a step (b) of forming a transparent conductive layer on a part of the surface of the substrate, and the step of forming the substrate. A step (c) of forming a metal nitride film made of a refractory metal nitride and a conductive film made of a material different from the metal nitride film in this order on the surface and the transparent conductive layer; and halftone exposure By patterning the metal nitride film and the conductive film from one photomask by the method, the metal nitride film and the conductive film are formed on the surface of the substrate where the transparent conductive layer is not formed. A step (d) of forming a nitride layer from the metal nitride film on the transparent conductive layer, covering the gate electrode, the transparent conductive layer, and the nitride layer; and A step (e) of forming an insulating layer having an opening exposing at least a part of the surface of the nitride layer, a step (f) of forming a semiconductor layer on the insulating layer, the semiconductor layer, Forming a metal film on the insulating layer and in the opening; and patterning the metal film to form a source electrode and a drain electrode, wherein the drain electrode is nitrided in the opening. A step (h) in contact with the physical layer.

According to still another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: preparing a substrate; forming a gate electrode on a part of the surface of the substrate; and forming a gate insulating layer on the gate electrode. A step (b) of forming a semiconductor layer, a step (c) of forming a transparent conductive film and a metal nitride film made of a refractory metal nitride on the gate insulating layer and the semiconductor layer, By patterning the transparent conductive film and the metal nitride film from one photomask by a halftone exposure method, the transparent conductive film is transparent to the surface of the substrate where the gate electrode is not formed. Forming a conductive layer and forming a nitride layer from the metal nitride film on a part of the transparent conductive layer; and the semiconductor layer, the transparent conductive layer, and the nitride layer. A step (e) of forming a metal film, and a step of patterning the metal film to form a source electrode and a drain electrode, wherein the drain electrode is in contact with the nitride layer (f). To do.

In one embodiment, the semiconductor layer is an oxide semiconductor layer.

In one embodiment, the oxide semiconductor layer contains In, Ga, and Zn.

In one embodiment, the oxide semiconductor layer has crystallinity.

In the embodiment of the present invention, in the contact portion that connects the transparent conductive layer and the metal layer formed on the transparent conductive layer, the upper surface of the transparent conductive layer is in contact between the transparent conductive layer and the metal layer. A refractory metal nitride layer is interposed between the two layers. Thereby, resistance between a transparent conductive layer and a metal layer can be restrained low. Moreover, the fall of the characteristic and reliability resulting from the low adhesiveness of a metal layer and a transparent conductive layer can be suppressed.

(A) is a schematic plan view of the TFT substrate 100A of the first embodiment according to the present invention, and (b) is a schematic cross-sectional view of the TFT substrate 100A along the line AA ′ of (a). (C) is a schematic cross-sectional view of the TFT substrate 100A along the line BB ′ of (a), and (d) is an enlarged cross-sectional view of the contact portion. It is a block diagram for demonstrating an example of the manufacturing method of TFT substrate 100A. (A)-(g) is typical sectional drawing for demonstrating an example of the manufacturing method of TFT substrate 100A, respectively. It is typical sectional drawing of TFT substrate 100B of 2nd Embodiment by this invention. It is a block diagram for demonstrating an example of the manufacturing method of TFT substrate 100B. (A)-(g) is typical sectional drawing for demonstrating an example of the manufacturing method of TFT substrate 100B, respectively. (A)-(e) is typical sectional drawing for demonstrating the other example of the manufacturing method of TFT substrate 100B, respectively. It is typical sectional drawing of TFT substrate 100C of 3rd Embodiment by this invention. It is a block diagram for demonstrating an example of the manufacturing method of TFT substrate 100C. (A)-(f) is typical sectional drawing for demonstrating an example of the manufacturing method of TFT substrate 100C, respectively. It is typical sectional drawing of TFT substrate 100D of 4th Embodiment by this invention. It is a block diagram for demonstrating an example of the manufacturing method of TFT substrate 100D. (A)-(f) is typical sectional drawing for demonstrating an example of the manufacturing method of TFT substrate 100D, respectively. (A) and (b) are schematic cross-sectional views of a TFT substrate 100E according to a fifth embodiment of the present invention, respectively, and (a) is an AA ′ view of the plan view shown in FIG. 1 (a). The cross-sectional structure along the line is shown, and (b) shows the cross-sectional structure along the line BB ′ of the plan view shown in FIG. It is a block diagram for demonstrating an example of the manufacturing method of TFT substrate 100E. (A)-(h) is typical sectional drawing for demonstrating an example of the manufacturing method of TFT substrate 100E, respectively. (A) and (b) are schematic cross-sectional views of a TFT substrate 100F according to a sixth embodiment of the present invention, respectively, and (a) is an AA ′ in the plan view shown in FIG. 1 (a). The cross-sectional structure along the line is shown, and (b) shows the cross-sectional structure along the line BB ′ of the plan view shown in FIG. (A) is a typical top view of TFT substrate 100G of 7th Embodiment by this invention, (b) is typical sectional drawing of TFT substrate 100G along the AA 'line of (a). (C) is a schematic cross-sectional view of the TFT substrate 100G along the line BB ′ of (a), and (d) is an enlarged cross-sectional view of the contact portion. It is a block diagram for demonstrating an example of the manufacturing method of TFT substrate 100G. (A)-(g) is typical sectional drawing for demonstrating an example of the manufacturing method of TFT substrate 100G, respectively. (A)-(e) is typical sectional drawing for demonstrating the other example of the manufacturing method of TFT substrate 100G, respectively. It is typical sectional drawing which shows an example of the contact part 90 of embodiment by this invention. It is typical sectional drawing of the contact part 80 of a comparative example.

The inventor has studied a configuration in which, for example, in an active matrix substrate, a transparent conductive layer functioning as a pixel electrode is disposed below the TFT drain electrode. As a result, it has been found that there is a problem that contact resistance increases or adhesion decreases between the transparent conductive layer and the metal layer which is the drain electrode. It has also been found that the same problem can occur not only in the contact portion between the pixel electrode and the drain electrode but also in the contact portion connecting the transparent conductive layer and the metal layer such as an electrode or wiring thereover.

On the other hand, in the contact portion in which the transparent conductive layer is disposed on the metal layer, the increase in contact resistance and the decrease in adhesion do not occur so significantly. From this, it is surmised that the above problem is caused by the characteristics of the outermost surface of the transparent conductive layer.

Furthermore, it has been found that the above problem is particularly remarkable in the configuration in which the metal layer and the transparent conductive layer are brought into contact with each other in the contact hole provided in the insulating layer. This is presumably because the characteristics of the upper surface of the transparent conductive layer may be greatly degraded by the formation of contact holes.

Further, the process is not limited to the contact hole formation process, and in the semiconductor device process, the outermost surface of the transparent conductive layer is modified by various treatments performed after the transparent conductive layer is formed. There was also a tendency for the contact resistance to become more unstable.

In addition, the said problem arises in the contact part in which a transparent conductive layer is lower (board | substrate side) than a metal layer, and is a problem which was not recognized conventionally.

As a result of intensive investigations to solve the above problems, the present inventor has arranged a refractory metal nitride layer between the transparent conductive layer and the metal layer, thereby increasing contact resistance and adhesion. The inventors have found that the reduction can be suppressed and have arrived at the present invention.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings. The semiconductor device of this embodiment includes an oxide semiconductor TFT. In addition, the semiconductor device of this embodiment should just be provided with the oxide semiconductor TFT, and includes an active matrix substrate, various display apparatuses, an electronic device, etc. widely.

The semiconductor device according to the embodiment of the present invention has a contact portion that electrically connects a transparent conductive layer and a metal layer formed thereon.

FIG. 22 is a cross-sectional view schematically showing the contact portion 90 in the semiconductor device of this embodiment. For comparison, FIG. 23 shows a configuration of a contact portion 80 that directly contacts the transparent conductive layer 3 and the metal layer 7d.

As shown in FIG. 22, the semiconductor device of this embodiment includes a substrate 2, a transparent conductive layer 3 supported by the substrate 2, an insulating layer 5 formed so as to cover the transparent conductive layer 3, and a metal layer 7d. And have. The semiconductor device is provided with a contact portion 90 for electrically connecting the metal layer 7 d and the transparent conductive layer 3. In the contact portion 90, the insulating layer 5 is provided with an opening (contact hole) 5 u located on a part of the upper surface of the transparent conductive layer 3. The opening part 5u should just be arrange | positioned so that it may overlap with the transparent conductive layer 3 at least partially. The metal layer 7d is formed on the insulating layer 5 and in the opening 5u. Further, in the contact portion 90, a refractory metal nitride layer 20 is disposed between the transparent conductive layer 3 and a portion of the metal layer 7d located in the opening 5u. The nitride layer 20 is provided in contact with the upper surface of the transparent conductive layer 3.

In the illustrated example, the nitride layer 20 is in contact with the portion located in the opening 5u of the metal layer 7d. A further conductive layer may be formed between the portion of the metal layer 7d located in the opening 5u and the nitride layer 20.

If the contact portion 90 shown in FIG. 22 is provided, the following effects can be obtained.

As described above, in the contact portion 80 of the comparative example, there is a problem that the resistance increases between the transparent conductive layer 3 and the metal layer 7d, and the adhesion between the upper surface of the transparent conductive layer 3 and the metal layer 7d is low. These problems are particularly remarkable when an indium oxide material is used as the transparent conductive layer. On the other hand, according to the present embodiment, since the nitride layer 20 is interposed between the transparent conductive layer 3 and the metal layer 7d, the resistance of the contact portion can be kept low. Further, by covering the upper surface of the transparent conductive layer 3 with the nitride layer 20, it is possible to suppress a decrease in adhesion due to the characteristics of the upper surface of the transparent conductive layer 3.

As will be described later, if the nitride layer 20 is formed on the upper surface of the transparent conductive layer 3 immediately after forming the transparent conductive layer 3, the upper surface of the transparent conductive layer 3 is altered in the manufacturing process, and the contact portion 90 It can suppress more effectively that resistance becomes high or adhesiveness falls.

In the illustrated example, the nitride layer 20 is disposed only at a part of the interface between the metal layer 7d and the transparent conductive layer 3, and the metal layer 7d is formed between the nitride layer 20 and the transparent conductive layer 3 in the opening 5u. It is in contact with both. The nitride layer 20 may be disposed on the entire interface between the metal layer 7d and the transparent conductive layer 3. For example, when viewed from the normal direction of the substrate 2, the opening 5 u may be disposed inside the nitride layer 20. In that case, the metal layer 7d is not in direct contact with the transparent conductive layer 3 in the opening 5u, but is connected to the transparent conductive layer 3 through the nitride layer 20.

This embodiment can be applied to a TFT substrate used for a liquid crystal display device, for example. In that case, the transparent conductive layer 3 may be a pixel electrode, and the metal layer 7d may be a drain electrode 7d of the TFT or an electrode layer electrically connected to the drain electrode 7d. The insulating layer 5 may include a gate insulating layer of the TFT.

Note that the semiconductor device of the present embodiment only needs to have a contact portion 90 that electrically connects the transparent conductive layer 3 and the metal layer 7d. Such a contact portion 90 is a contact between the TFT and the pixel electrode. It does not have to be a part. For example, a terminal part or a connection part for connecting wirings may be used.

Hereinafter, the configuration of the semiconductor device according to the present embodiment will be described more specifically with reference to the TFT substrate.

FIG. 1A is a schematic plan view of a TFT substrate 100A according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of the TFT substrate 100A along the line AA ′ in FIG. 1A, and FIG. 1C is the line BB ′ in FIG. It is typical sectional drawing of TFT substrate 100A along. FIG. 1D is an enlarged plan view in which a region including the contact portion in the TFT substrate 100A is enlarged.

As shown in FIGS. 1A to 1D, a TFT substrate 100A includes a substrate 2, a gate electrode 4 and a pixel electrode (transparent conductive layer) 3 formed on the substrate 2, a gate electrode 4 and Insulating layer 5 formed on pixel electrode 3, semiconductor layer 6 overlapping gate electrode 4 with insulating layer 5 interposed therebetween, source electrode 7s and drain electrode (metal layer) 7d electrically connected to semiconductor layer 6 In addition, a contact portion 90 that electrically connects the drain electrode 7d and the pixel electrode 3 is provided.

In the contact portion 90, a refractory metal nitride layer 20 is disposed between a portion of the metal layer 7 d located in the opening 5 u provided in the insulating layer 5 and the upper surface of the transparent conductive layer 3. . The configuration of the contact portion 90 is the same as that described above with reference to FIG. Since the TFT substrate 100A includes such a contact portion 90, the resistance between the pixel electrode 3 and the drain electrode 7d can be kept low, and the adhesion between them can be increased.

In this embodiment, as can be seen from FIGS. 1A and 1D, the shape of the nitride layer 20 and the shape of the drain electrode (metal layer) 7d are different when viewed from the normal direction of the substrate 2. ing. As described above, by separately patterning the nitride layer 20 and the drain electrode 7d, the nitride layer 20 can be disposed only in a necessary region, so that the manufacturing cost can be reduced.

Further, it is preferable to form the nitride layer 20 after forming the pixel electrode 3 and before forming the insulating layer 5. If the insulating layer 5 is formed before the nitride layer 20, a portion of the upper surface of the pixel electrode 3 exposed at the opening 5 u of the insulating layer 5 may be damaged by the patterning process of the insulating layer 5. On the other hand, when the nitride layer 20 is formed before the formation of the insulating layer 5, the upper surface of the pixel electrode 3 is protected by the nitride layer 20 when the insulating layer 5 is patterned. An increase in resistance and a decrease in adhesion can be more effectively suppressed. When the nitride layer 20 is formed before the insulating layer 5, if the shape of the nitride layer 20 is larger than the opening 5 u, at least a part of the upper surface of the nitride layer 20 is in contact with the insulating layer 5. .

Subsequently, the planar shape of the contact portion 90 will be described in more detail with reference to FIG. When viewed from the normal direction of the substrate 2, the nitride layer 20 may be disposed so as to overlap at least a part of the opening 5 u of the insulating layer 5. For example, as illustrated, a part of the nitride layer 20 may overlap the opening 5u, and the other part may be located in a region around the opening 5u. As described above, when the configuration in which the nitride layer 20 is disposed over a part of the opening 5u is employed, the nitride layer 20 is compared with the configuration in which the nitride layer 20 is disposed so as to overlap the entire opening 5u. The pattern size can be further reduced, and the size of the opening 5u can also be reduced. Therefore, the restriction on the design of the contact portion 90 is also eased.

The TFT substrate 100A may include a protective layer 8 formed on the source electrode 7s and the drain electrode 7d, and a common electrode 9 that overlaps at least a part of the pixel electrode 3 with the protective layer 8 interposed therebetween. Thereby, an auxiliary capacitor having the protective layer 8 as a dielectric layer can be formed. Further, when the pixel electrode 3 and the common electrode 9 are formed of a transparent electrode material (for example, ITO (Indium Tin Oxide)), it is possible to suppress a decrease in the aperture ratio of the pixel. An auxiliary capacity formed of a transparent material may be referred to as a “transparent auxiliary capacity”. The common electrode 9 may not be separated for each pixel. For example, it may be provided so as to cover substantially the entire display area. Note that the above-described opening 5u is closer to the substrate 2 than the common electrode 9 is.

In the example shown in FIG. 1A, the TFT substrate 100A has source wirings 7 (m) and 7 (m + 1) electrically connected to the source electrode 7s of the corresponding pixel. Source wirings 7 (m) and 7 (m + 1) are formed on the insulating layer 5. Further, a gate wiring 14 is formed between the pixel electrodes 3 (m) and 3 (m + 1) of adjacent pixels. The pixel electrodes 3 (m) and 3 (m + 1) and the gate wiring 14 are all formed between the substrate 2 and the insulating layer 5.

In the TFT substrate 100A, the pixel electrode 3 is formed closer to the substrate 2 than the gate insulating layer (here, the insulating layer 5), and the contact hole (opening 5u) for connecting the drain electrode 7d and the pixel electrode 3 is connected. Is formed in the insulating layer 5. For this reason, the upper surface of the protective layer 8 formed on the TFT can be made substantially flat. Therefore, the shape of the contact hole hardly affects the liquid crystal alignment of the liquid crystal layer disposed on the protective layer 8 and hardly causes display failure. On the other hand, for example, in the configuration in which the pixel electrode is disposed on the TFT via the protective layer, a contact hole for connecting the pixel electrode and the drain electrode is formed in the protective layer. For this reason, since the vicinity of the contact hole on the upper surface of the protective layer does not become flat, the shape of the contact hole may affect the liquid crystal alignment of the liquid crystal layer disposed on the protective layer.

In the TFT substrate 100A, the drain electrode 7d formed above the insulating layer 5 and the nitride layer 20 formed below the insulating layer 5 are brought into contact with each other in the opening 5u of the insulating layer 5. However, as will be described later, an insulating layer may not be formed between the nitride layer 20 and the drain electrode 7d. However, if the insulating layer 5 is formed and the contact portion 90 is formed in the opening 5u, the aperture ratio of the pixel can be further increased. The reason for this will be described later.

Next, each component of the TFT substrate 100A will be described in detail.

The substrate 2 is typically a transparent substrate, for example, a glass substrate. In addition to a glass substrate, a plastic substrate can also be used. The plastic substrate includes a substrate formed of a thermosetting resin or a thermoplastic resin, and a composite substrate of these resins and inorganic fibers (for example, glass fibers or glass fiber nonwoven fabrics). Examples of the heat-resistant resin material include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), acrylic resin, and polyimide resin. In addition, when used in a reflective liquid crystal display device, a silicon substrate can be used as the substrate 2.

The pixel electrodes 3 (m), 3 (m + 1) and the common electrode 9 are transparent conductive layers such as indium oxide and zinc oxide, respectively. For example, an ITO (Indium Tin Oxide) or IZO (registered trademark) (Indium Zinc Oxide) layer may be used. The thicknesses of the pixel electrodes 3 (m), 3 (m + 1) and the common electrode 9 may be, for example, 20 nm or more and 200 nm or less (for example, about 100 nm).

The refractory metal nitride layer 20 may be, for example, a molybdenum nitride (MoN) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, or the like. The thickness of the nitride layer 20 is preferably 5 nm or more, for example. Thereby, the increase in resistance of the contact part 90 can be suppressed more reliably. Further, the thickness of the nitride layer 20 is preferably, for example, equal to or less than the thickness of the insulating layer 5 (for example, 400 nm or less).

The gate electrode 4 may be formed integrally with the gate wiring 14. The gate electrode 4 and the gate wiring 14 are, for example, elements selected from Mo (molybdenum), Al (aluminum), Ti (titanium), W (tungsten), Ta (tantalum), Cu (copper), or these elements. It may be formed from a metal film such as an alloy or a metal nitride. Moreover, you may have the structure where those metal films were laminated | stacked. The thickness of the gate electrode 4 and the gate wiring 14 may be about 50 nm or more and 600 nm or less (for example, about 420 nm).

For example, the insulating layer 5 includes SiO ₂ (silicon oxide), SiN _x (silicon nitride), SiO _x N _y (silicon oxynitride, x> y), SiN _x O _y (silicon nitride oxide, x> y), Al _2. A single layer or a stack formed from O ₃ (aluminum oxide) or tantalum oxide (Ta ₂ O ₅ ) can be used. The thickness of the insulating layer 5 is, for example, about 50 nm or more and 600 nm or less. In order to form the dense insulating layer 5 with little gate leakage current at a low temperature, the insulating layer 5 is preferably formed using a rare gas such as Ar (argon).

The semiconductor layer 6 may be a silicon-based semiconductor layer such as an amorphous silicon (a-Si) layer, a polysilicon (p-Si) layer, or a microcrystalline silicon (μ-Si) layer. Alternatively, the semiconductor layer 6 may be an oxide semiconductor layer. The thickness of the semiconductor layer 6 is, for example, about 30 nm to 100 nm (for example, about 50 nm).

In the case where an oxide semiconductor layer is used as the semiconductor layer 6, since the TFT having the oxide semiconductor layer has high mobility as described above, the size of the TFT can be reduced and reduction in the aperture ratio of the pixel can be suppressed. It becomes possible. In addition, since the oxide semiconductor layer can be formed at a lower temperature than the silicon-based semiconductor layer, a substrate having low heat resistance can be used. For example, a semiconductor device applicable to a flexible display can be manufactured by forming an oxide semiconductor layer on a plastic substrate or a film substrate.

The oxide semiconductor layer is formed of, for example, an In—Ga—Zn—O based semiconductor film containing In (indium), Ga (gallium), and Zn (zinc) at a ratio of 1: 1: 1. The ratio of In, G, and Zn can be selected as appropriate.

If an amorphous In—Ga—Zn—O based semiconductor film is used as the In—Ga—Zn—O based semiconductor film, it can be manufactured at a low temperature and high mobility can be realized. However, instead of the amorphous In—Ga—Zn—O-based semiconductor film, an In—Ga—Zn—O-based semiconductor film that exhibits crystallinity with respect to a predetermined crystal axis (C-axis) may be used.

The semiconductor layer 6 may be formed using another oxide semiconductor film instead of the In—Ga—Zn—O-based semiconductor film. For example, Zn—O based semiconductor (ZnO) film, In—Zn—O based semiconductor (IZO) film, Zn—Ti—O based semiconductor (ZTO) film, Cd—Ge—O based semiconductor film, Cd—Pb—O based film A semiconductor film, CdO (cadmium oxide), Mg—Zn—O based semiconductor film, or the like may be used. Further, as an oxide semiconductor layer, an amorphous ZnO film to which one or a plurality of impurity elements of Group 1 element, Group 13 element, Group 14 element, Group 15 element, Group 17 element and the like are added is added. A state, a polycrystalline state, a microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a state in which no impurity element is added can be used.

The source electrode 7s, the drain electrode 7d, and the source wirings 7 (m) and 7 (m + 1) are, for example, Mo (molybdenum), Al (aluminum), Ti (titanium), W (tungsten), Ta (tantalum), You may form from metal films, such as an element chosen from Cu (copper), or an alloy which uses these elements as a component. Moreover, you may have the structure where those metal films were laminated | stacked. The thicknesses of the source electrode 7s, the drain electrode 7d, and the source wirings 7 (m) and 7 (m + 1) are each preferably about 50 nm to 600 nm. The thickness of the source electrode 7s, the drain electrode 7d, and the source wirings 7 (m) and 7 (m + 1) is, for example, about 350 nm.

The protective layer 8 is formed on the source electrode 7s, the drain electrode 7d, and the source wirings 7 (m) and 7 (m + 1). Examples of the protective layer 8 include Si-based nitrides such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy; x> y) film, and a silicon nitride oxide (SiNxOy; x> y) film. Alternatively, an inorganic insulating film (passivation film) containing an oxide can be used. Alternatively, an Al ₂ O ₃ (aluminum oxide) or Ta ₂ O ₅ (tantalum oxide) film may be used.

In the illustrated example, a protective layer 8 is disposed between the common electrode 9 and the pixel electrode 3. Accordingly, a transparent auxiliary capacitor is formed in which the protective layer 8 is a dielectric layer and the transparent common electrode 9 and the pixel electrode 3 are capacitor electrodes. Thereby, when the TFT substrate 100A is used for a display panel, a display panel having a high aperture ratio can be manufactured. The thickness of the protective layer 8 is preferably about 50 nm to 300 nm (for example, about 200 nm), for example.

The TFT substrate 100A is used for, for example, a fringe field switching (FFS) mode liquid crystal display device. At this time, a display signal voltage is supplied to the pixel electrode 3, and a common voltage or a counter voltage is supplied to the upper common electrode 9. The common electrode 9 is provided with at least one or more slits 19 (see FIGS. 1A and 1D).

Next, an example of a manufacturing method of the TFT substrate 100A will be described with reference to FIGS. FIG. 2 is a block diagram for explaining a manufacturing method of the TFT substrate 100A. 3 (a) to 3 (g) are schematic cross-sectional views for explaining a manufacturing method of the TFT substrate 100A.

As shown in FIG. 2, the manufacturing method of the TFT substrate 100A includes a pixel electrode forming step PX, a refractory metal nitride layer forming step IM, a gate electrode forming step GT, a gate insulating layer / semiconductor layer forming step GI / PS, It has a source / drain electrode forming step SD, a protective layer forming step PAS, and a common electrode forming step CT, and the process proceeds in this order.

A specific manufacturing process will be described with reference to FIGS. 3 (a) to 3 (g). Note that the cross-sectional views shown in FIGS. 3A to 3G correspond to the cross-sectional view shown in FIG.

As shown in FIG. 3A, in the pixel electrode formation step PX, a conductive film (not shown) (for example, a transparent conductive film such as an ITO film) is formed on the substrate 2 by sputtering, for example, The conductive film is patterned by wet etching or the like to form the pixel electrode 3. In addition, after patterning of the pixel electrode 3, the resist (not shown) used for patterning is peeled off.

3B, in the refractory metal nitride layer forming step IM, a refractory metal nitride film is formed so as to cover the pixel electrode 3 by sputtering, for example, in a nitrogen atmosphere. . Thereafter, the nitride film is patterned by a photolithography method and a wet etching method to form a nitride layer 20 on a part of the pixel electrode 3. Thereafter, the resist (not shown) is peeled off.

Next, as shown in FIG. 3C, in the gate electrode formation step GT, after forming a conductive film on the substrate 2 by, for example, sputtering, the conductive film is formed by photolithography and wet or dry etching. The gate electrode 4 is formed by patterning. Note that the gate electrode 4 is formed so as not to be electrically connected to the pixel electrode 3. Further, when the gate electrode 4 is patterned, the difference between the conductive film for forming the gate electrode 4 and the nitride layer 20 is used to leave the nitride layer 20 without being removed. The film is selectively etched. After patterning the gate electrode 4, the resist (not shown) used for patterning is peeled off.

Next, as shown in FIG. 3D, in the gate insulating layer / semiconductor layer forming step GI / PS, an insulating film (not shown) is formed on the gate electrode 4 and the pixel electrode 3 by, for example, a CVD (Chemical Vapor Deposition) method. And so on. Next, the insulating film is patterned by a photolithography method, a dry etching method, or the like to form the insulating layer 5 having the opening 5u. The opening 5 u is arranged so as to at least partially overlap with the region where the pixel electrode 3 and the nitride layer 20 overlap when viewed from the normal direction of the substrate 2. Preferably, the opening 5u is formed so that the entire opening 5u is positioned on the pixel electrode 3. A part (or all) of the upper surface of the nitride layer 20 is exposed by the opening 5u. Thereafter, the resist (not shown) used for patterning is peeled off.

Next, a semiconductor film (not shown) (for example, an In—Ga—Zn—O-based semiconductor film) is formed on the insulating layer 5 by, for example, a sputtering method, and this semiconductor film is formed by a photolithography method, a dry etching method, or the like. The semiconductor layer 6 is formed by patterning. The semiconductor layer 6 is formed so as to overlap the gate electrode 4 with the insulating layer 5 interposed therebetween. After patterning of the semiconductor layer 6, the resist (not shown) used for patterning is peeled off.

Next, as shown in FIG. 3E, in the source / drain electrode formation step SD, a metal film (not shown) is formed on the semiconductor layer 6, the insulating layer 5, and the opening 5u by, for example, sputtering. To do. Thereafter, the metal film is patterned by a photolithography method, a wet etching method, or the like to form the source electrode 7s and the drain electrode 7d. After patterning the source electrode 7s and the drain electrode 7d, the resist (not shown) used for patterning is stripped.

The source electrode 7s and the drain electrode 7d are electrically connected to the semiconductor layer 6, respectively. Of the semiconductor layer 6, a portion in contact with the source electrode 7 s is a source contact region, a portion in contact with the drain electrode 7 d is a drain contact region, and a portion sandwiched between the source contact region and the drain contact region is a channel region. The drain electrode 7d is also in contact with the nitride layer 20 in the opening 5u. You may contact both the nitride layer 20 and the pixel electrode 3 in the opening 5u. In this way, a contact portion 90 that connects the drain electrode 7d and the pixel electrode 3 is obtained.

Next, as shown in FIG. 3F, in the protective layer forming step PAS, an insulating film (not shown) is formed on the source electrode 7s and the drain electrode 7d by, for example, the CVD method. Next, the insulating film is patterned by a photolithography method, a dry etching method, or the like to form the protective layer 8. After patterning of the protective layer 8, the resist (not shown) used for patterning is peeled off.

Next, as shown in FIG. 3G, in the common electrode formation step CT, a conductive film (not shown) (for example, a transparent conductive film) is formed on the protective layer 8 by sputtering, for example, and photolithography and wet processing are performed. The conductive film is patterned by an etching method or the like to form the common electrode 9. After patterning the common electrode 9, the resist (not shown) used for patterning is peeled off.

In this example, the common electrode 9 is formed so as to overlap a part of the pixel electrode 3 with the insulating layer 5 and the protective layer 8 interposed therebetween. As a result, a transparent auxiliary capacitor having the insulating layer 5 and the protective layer 8 as dielectric layers can be formed.

As described above, according to the above method, since the nitride layer 20 is formed after the pixel electrode 3 is formed and before the insulating layer 5 is formed, the upper surface of the pixel electrode 3 is damaged by the patterning of the insulating layer 5. This can be suppressed.

In the above method, the nitride layer 20 is formed after the pixel electrode 3 is formed and before the gate electrode 4 is formed. However, the nitride layer 20 can be formed after the gate electrode 4 is formed. . However, if the nitride layer 20 is formed before the gate electrode 4 is formed, the surface of the pixel electrode 3 is modified by the gate insulating layer forming step GI and subsequent processes, and deterioration of the characteristics of the contact portion 90 can be suppressed. . In particular, when the nitride layer 20 is formed immediately after the formation of the pixel electrode 3 and a part of the upper surface of the pixel electrode 3 (portion constituting the contact portion 90) is covered (capped), the upper surface of the pixel electrode 3 is more effectively obtained. Can be suppressed.

When an electrode layer made of an ITO polycrystal is formed as the pixel electrode 3, it is preferable to use wet etching for patterning the gate electrode 4 and patterning the nitride layer 20 after the pixel electrode 3 is formed. It can be suppressed that the characteristics of the upper surface of the pixel electrode 3 are deteriorated by dry etching, which causes a decrease in adhesion and an increase in contact resistance.

(Second Embodiment)
Hereinafter, a second embodiment of the semiconductor device according to the present invention will be described. The semiconductor device of this embodiment is a TFT substrate of a display device.

FIG. 4 is a schematic cross-sectional view of the TFT substrate 100B of the present embodiment. For a plan view of the TFT substrate 100B and an enlarged plan view of the contact portion, refer to FIGS. 1A and 1D, respectively. FIG. 4 shows a cross-sectional structure along the line A-A ′ of FIG. Constituent elements similar to those of the TFT substrate 100A shown in FIG.

As shown in FIG. 4, in the TFT substrate 100B, the gate electrode 4 (and the gate wiring 14) includes a first gate layer 20a formed of the same metal nitride film as the nitride layer 20, and a first gate layer. It has a stacked structure including the second gate layer 4a formed on 20a. The second gate layer 4a is formed of a conductive material different from that of the first gate layer 20a. As the second gate layer 4a, for example, a metal film containing an element selected from Mo (molybdenum), Al (aluminum), Ti (titanium), W (tungsten), Ta (tantalum), and Cu (copper) is used. Also good. Other configurations and the thicknesses and materials of the respective components are the same as those of the TFT substrate 100A.

According to the present embodiment, since the nitride layer 20 is interposed between the drain electrode (metal layer) 7d and the pixel electrode (transparent conductive layer) 3 in the contact portion 90, the contact resistance is increased as in the first embodiment. And the fall of adhesiveness can be suppressed. Furthermore, since the first gate layer 20a made of a refractory metal nitride is disposed under the second gate layer 4a, hillocks in the second gate layer 4a can be suppressed. Further, since the first gate layer 20a functions as a buffer, the adhesion between the gate electrode 4 and its base layer can be improved as compared with the case where the gate electrode is formed only by the second gate layer 4a.

Further, as will be described in detail later, when a part of the metal nitride film is left as the lower layer of the gate electrode 4, the gate electrode 4 and the nitride layer 20 can be formed from one photomask. . Therefore, the number of photomasks can be reduced and manufacturing costs can be reduced.

Next, an example of a manufacturing method of the TFT substrate 100B will be described in detail with reference to FIGS. FIG. 5 is a block diagram for explaining an example of a manufacturing method of the TFT substrate 100B. 6A to 6G are schematic cross-sectional views for explaining an example of the manufacturing method of the TFT substrate 100B, and correspond to FIG.

As shown in FIG. 5, the manufacturing method of the TFT substrate 100B includes a pixel electrode forming step PX, a refractory metal nitride layer and first gate layer forming step IM, a second gate layer forming step GT, and a gate insulating layer. / Semiconductor layer forming step GI / PS, source / drain electrode forming step SD, protective layer forming step PAS and common electrode forming step CT, and the process proceeds in this order.

First, as shown in FIG. 6A, the pixel electrode 3 is formed on the substrate 2. The formation method of the pixel electrode 3 is the same as the method described above with reference to FIG.

Next, as shown in FIG. 6B, a refractory metal nitride film (not shown) is formed on the substrate 2 and is patterned to form a nitride located on a part of the pixel electrode 3. A layer 20 and a first gate layer 20a located on a region where the pixel electrode 3 is not formed are formed. The first gate layer 20a is provided in a region where a gate electrode and a gate wiring are formed. The method for forming the nitride film is the same as the method described above with reference to FIG.

Next, as shown in FIG. 6C, the second gate layer 4a is formed on the first gate layer 20a, and the gate electrode 4 is obtained. The method for forming the second gate layer 4a is the same as the method for forming the gate electrode 4 described above with reference to FIG. In the illustrated example, the pattern of the second gate layer 4a and the pattern of the first gate layer 20a are matched, but the second gate layer 4a overlaps at least a part of the first gate layer 20a. It only has to be.

In the present embodiment, the entire gate electrode 4 and the gate wiring may have a stacked structure including the first gate layer 20a and the second gate layer 4a. Alternatively, only a part of the gate electrode and the gate wiring may have such a stacked structure, and the other part may be configured by only one of the first gate layer 20a or the second gate layer 4a. .

Thereafter, as shown in FIGS. 6D to 6G, the insulating layer 5, the semiconductor layer 6, the source and

drain electrodes

7s and 7d, the protective layer 8, and the common electrode 9 are formed. These forming methods are the same as those described above with reference to FIGS. 3 (d) to 3 (g). In this way, the TFT substrate 100B is obtained.

In the above method, after the pixel electrode 3 is formed and before the second gate layer 4a is formed, the nitride layer 20 is formed to cover a part of the upper surface of the pixel electrode 3. Accordingly, it is possible to prevent the upper surface of the pixel electrode 3 from being modified during the manufacturing process and the characteristics of the contact portion 90 from being deteriorated.

The manufacturing method of the TFT substrate 100B is not limited to the above method. For example, as shown in FIGS. 7A to 7E, a refractory metal nitride layer and first gate layer forming step IM shown in FIG. The gate layer forming step GT can be performed using one photomask.

First, as shown in FIG. 7A, a refractory metal nitride film (metal nitride film) 20 ′ is formed on the substrate 2 on which the pixel electrode 3 is formed, and on the metal nitride film 20 ′. A conductive film 4 ′ for forming the second gate layer is formed.

Next, as shown in FIG. 7B, resist films R1 and R2 having different thicknesses are formed on the conductive film 4 'by a halftone exposure method using a single photomask (halftone mask). Form into shape. A resist film R1 is formed in a region where the contact portion on the pixel electrode 3 is formed, and a resist film R3 thicker than the resist film R1 is formed in a region where the gate electrode and the gate wiring are formed.

Next, as shown in FIG. 7C, the metal nitride film 20 'and the conductive film 4' in a region not covered with the resist films R1 and R2 are patterned by a wet etching method. By this patterning, the nitride layer 20 is formed from the metal nitride film 20 'and the conductive layer (etched layer) 4b is formed from the conductive film 4' in the region defined by the resist film R1. Further, the first gate layer 20a is formed from the metal nitride film 20 'and the second gate layer 4a is formed from the conductive film 4' in the region defined by the resist film R2. The first gate layer 20a and the second gate layer 4a constitute the gate electrode 4.

Next, as shown in FIG. 7D, the resist film R1 is removed by a dry etching method. By this dry etching method, a part of the resist film R2 is scraped to obtain a resist film R2 'having a smaller thickness than the resist film R2.

Subsequently, the resist film R2 'and the conductive layer 4b are removed by a further dry etching method. The second gate layer 4a under the resist film R2 'remains without being removed.

Thereafter, although not shown, as described with reference to FIGS. 6D to 6G, the gate insulating layer / semiconductor layer forming step GI / PS, the source / drain electrode forming step SD, and the protective layer forming Through the process PAS and the common electrode formation process CT, the TFT substrate 100B is obtained.

According to this method, since the nitride layer 20 and the gate electrode 4 can be formed from one photomask, the number of photomasks can be reduced, and the manufacturing cost can be reduced.

As will be described later, the nitride layer 20 and the drain electrode 7d can be connected via the conductive layer 4b, leaving the conductive layer 4b without being removed. However, when an Al layer or Cu layer is used as the second gate layer 4a, an oxide film is formed on the surface, so that the connection with the upper drain electrode 7d becomes unstable, and the effective connection area may be reduced. There is. Therefore, in such a case, it is preferable to remove the conductive layer 4b and bring the nitride layer 20 and the drain electrode 7d into direct contact as in this embodiment.

(Third embodiment)
Hereinafter, a third embodiment of a semiconductor device according to the present invention will be described. The semiconductor device of this embodiment is a TFT substrate of a display device.

FIG. 8 is a schematic cross-sectional view of the TFT substrate 100C of this embodiment. For a plan view of the TFT substrate 100C and an enlarged plan view of the contact portion, refer to FIG. 1 (a) and FIG. 1 (d), respectively. FIG. 8 shows a cross-sectional structure along the line A-A ′ of FIG. Constituent elements similar to those of the TFT substrate 100A shown in FIG.

The TFT substrate 100C is different from the above-described TFT substrate 100A (FIG. 1) in that the gate electrode 4 (20a) and the gate wiring 14 are formed using the same metal nitride film as the nitride layer 20. Other configurations and the thicknesses and materials of the respective components are the same as those of the TFT substrate 100A.

In this embodiment, since the gate electrode 4 (20a) and the gate wiring and the nitride layer 20 are formed as a single layer of the same metal nitride film, the resistance of the contact portion 90 can be increased and the number of manufacturing steps can be increased. Decrease in adhesion can be suppressed. Further, when the nitride layer 20 and the gate electrode 4 are formed as separate layers, the nitride layer 20 may be etched when the gate electrode 4 is etched. Although it becomes unstable, according to this embodiment, such instability can be improved and the stability of the process can be improved.

Next, an example of a manufacturing method of the TFT substrate 100C will be described in detail with reference to FIGS. FIG. 9 is a block diagram for explaining an example of a manufacturing method of the TFT substrate 100C. FIGS. 10A to 10F are schematic cross-sectional views for explaining an example of the manufacturing method of the TFT substrate 100C, and correspond to FIG.

As shown in FIG. 9, the manufacturing method of the TFT substrate 100C includes a pixel electrode forming step PX, a refractory metal nitride layer and gate electrode forming step IM, a gate insulating layer / semiconductor layer forming step GI / PS, and a source / drain. It has an electrode forming step SD, a protective layer forming step PAS, and a common electrode forming step CT, and the process proceeds in this order.

First, as shown in FIG. 10A, the pixel electrode 3 is formed on the substrate 2. The formation method of the pixel electrode 3 is the same as the method described above with reference to FIG.

Next, as shown in FIG. 10B, a refractory metal nitride film (not shown) is formed on the substrate 2 and is patterned to form a nitride located on a part of the pixel electrode 3. The layer 20 and the gate electrode 4 (20a) located on the region where the pixel electrode 3 is not formed are formed. The method for forming and patterning the metal nitride film is the same as that described above with reference to FIG.

Next, as shown in FIGS. 10C to 10F, the insulating layer 5, the semiconductor layer 6, the source and

drain electrodes

7s and 7d, the protective layer 8, and the common electrode 9 are formed to obtain the TFT substrate 100C. These forming methods are the same as those described above with reference to FIGS. 3 (d) to 3 (g).

According to the above method, the number of photomasks can be reduced because the gate electrode forming step GT can be reduced as compared with the manufacturing method of the TFT substrate 100A described above with reference to FIGS. In addition, since the nitride layer 20 is formed on the pixel electrode 3 after the pixel electrode 3 is formed and before the insulating layer 5 is formed, the contact portion 90 is formed during the insulating layer 5 forming process and the subsequent processes. It can suppress that the upper surface of the pixel electrode 3 located is improved.

(Fourth embodiment)
FIG. 11 is a schematic cross-sectional view of the TFT substrate 100D of the present embodiment. For a plan view of the TFT substrate 100D and an enlarged plan view of the contact portion, refer to FIG. 1 (a) and FIG. 1 (d), respectively. FIG. 11 shows a cross-sectional structure along the line AA ′ in FIG. Constituent elements similar to those of the TFT substrate 100A shown in FIG.

In the TFT substrate 100D, as in the TFT substrate 100B (FIG. 4), the gate electrode 4 (and the gate wiring 14) includes the first gate layer 20a formed of the same metal nitride film as the nitride layer 20, and the first gate layer 20a. And a second gate layer 4a formed on the first gate layer 20a. The second gate layer 4a is formed of a conductive material different from that of the first gate layer 20a. In addition, the TFT substrate 100D includes a conductive layer 4b formed of the same conductive film as the second gate layer 4a between the nitride layer 20 and the drain electrode 7d. Conductive layer 4b is in contact with nitride layer 20 and in contact with the portion of drain electrode 7d located at opening 5u. Other configurations and the thicknesses and materials of the respective components are the same as those of the TFT substrate 100A.

In the present embodiment, the gate electrode 4 and the gate wiring, and the conductor layer formed between the nitride layer 20 and the drain electrode 7d in the contact portion 90 are formed of the same two films (metal nitride film and conductive film). ) Are simultaneously formed by patterning. For this reason, it is possible to suppress an increase in resistance and a decrease in adhesion of the contact portion 90 without increasing the number of manufacturing steps. Further, when the nitride layer 20 and the gate electrode 4 are formed as separate layers, the nitride layer 20 may be etched when the gate electrode 4 is etched. Although it becomes unstable, according to this embodiment, such instability can be improved and the stability of the process can be improved.

Next, an example of a manufacturing method of the TFT substrate 100D will be described in detail with reference to FIGS. FIG. 12 is a block diagram for explaining an example of a manufacturing method of the TFT substrate 100D. FIGS. 13A to 13F are schematic cross-sectional views for explaining an example of the manufacturing method of the TFT substrate 100D, and correspond to FIG.

As shown in FIG. 12, the manufacturing method of the TFT substrate 100D includes a pixel electrode forming step PX, a refractory metal nitride layer and gate electrode forming step IM / GT, a gate insulating layer / semiconductor layer forming step GI / PS, and a source. A drain electrode forming step SD, a protective layer forming step PAS, and a common electrode forming step CT, and the process proceeds in this order.

First, as shown in FIG. 13A, the pixel electrode 3 is formed on the substrate 2. The formation method of the pixel electrode 3 is the same as the method described above with reference to FIG.

Next, as shown in FIG. 13B, a refractory metal nitride film (not shown) and a conductive film (not shown) are formed on the substrate 2 in this order. Next, by simultaneously patterning these films, a nitride layer 20 formed of a nitride film and a conductive layer 4b formed of a conductive film are formed on a part of the pixel electrode 3. In addition, a first gate layer 20a formed of a nitride film and a second gate layer 4a formed of a conductive film are formed on a region where the pixel electrode 3 is not formed.

Next, as shown in FIGS. 13C to 13F, the insulating layer 5, the semiconductor layer 6, the source and

drain electrodes

7s and 7d, the protective layer 8, and the common electrode 9 are formed to obtain the TFT substrate 100D. These forming methods are the same as those described above with reference to FIGS. 3 (d) to 3 (g). In the present embodiment, the drain electrode 7d is formed in contact with the conductive layer 4b in the opening 5u.

According to the above method, since the gate electrode 4 and the nitride layer 20 can be formed by one photomask, the number of steps (number of photomasks) can be reduced as compared with the manufacturing method of the TFT substrate 100A. Also in this embodiment, since the nitride layer 20 is formed on the upper surface of the pixel electrode 3 after the pixel electrode 3 is formed and before the insulating layer 5 is formed, the insulating layer 5 is formed during or after the forming process. The upper surface of the pixel electrode 3 located in the contact portion 90 can be prevented from being modified.

(Fifth embodiment)
Hereinafter, a fifth embodiment of the semiconductor device according to the present invention will be described. The semiconductor device of this embodiment is a TFT substrate of a display device.

FIGS. 14A and 14B are schematic cross-sectional views of the TFT substrate 100E of the present embodiment, respectively. For a plan view of the TFT substrate 100E and an enlarged plan view of the contact portion, refer to FIG. 1 (a) and FIG. 1 (d), respectively. FIGS. 14A and 14B show cross-sectional structures taken along lines A-A ′ and B-B ′ of FIG. Constituent elements similar to those of the TFT substrate 100A shown in FIG.

The TFT substrate 100E is different from the TFT substrate 100A in that a further insulating layer 5a is formed between the gate electrode 4, the insulating layer 5, and the pixel electrode 3.

In the TFT substrate 100E, the gate insulating layer has a two-layer structure including the insulating layer 5 and the insulating layer 5a, and the pixel electrode 3 is provided between these two layers. In the present embodiment, the insulating layer 5a is referred to as a “first gate insulating layer”, and the insulating layer 5 in which the opening 5u is formed is referred to as a “second gate insulating layer”.

The first gate insulating layer 5a and the second gate insulating layer 5 are made of, for example, SiO ₂ (silicon oxide), SiN _x (silicon nitride), SiO _x N _y (silicon oxynitride, x> y), SiN _x O _y (nitriding). It can be formed from silicon oxide, x> y), Al ₂ O ₃ (aluminum oxide) or tantalum oxide (Ta ₂ O ₅ ).

Further, in order to prevent diffusion of impurities from the substrate 2 and reduce the processing time of the manufacturing process, the lower first gate insulating layer 5a is formed of SiN _x or SiN _x O _y (silicon nitride oxide, x> y). May be. Since the insulating layer formed from the silicon nitride film has a high etching rate, the processing time can be shortened. The first gate insulating layer 5a may be provided on substantially the entire display region (see FIG. 14B).

As the lower first gate insulating layer 5a, a silicon nitride layer, a silicon nitride oxide layer, or the like is formed to prevent diffusion of impurities and the like from the substrate 2, and insulation is ensured on the upper layer (upper layer). Therefore, a silicon oxide layer, a silicon oxynitride layer, or the like may be formed.

Note that the configuration of the gate electrode 4 and the contact portion 90 is not limited to the configuration shown in FIG. In the example shown in FIG. 14, the first gate insulating layer 5a is provided on the TFT substrate 100A (FIG. 1), but the first gate insulating layer 5a may be provided on the other TFT substrates 100B to 100D.

According to the present embodiment, in the contact portion 90, by increasing the nitride layer 20 between the drain electrode 7d and the pixel electrode 3, an increase in resistance and a decrease in adhesion of the contact portion 90 can be suppressed. In addition, since the gate electrode 4, the pixel electrode 3, and the nitride layer 20 are formed as separate layers with the insulating layer 5a interposed therebetween, the gate electrode 4 may be affected when the pixel electrode 3 and the nitride layer 20 are processed. The nitride layer 20 can be prevented from being affected during the processing of the gate electrode 4, and the process stability can be improved.

The present embodiment can be suitably applied when an oxide semiconductor layer is used as the semiconductor layer 6. In the oxide semiconductor TFT, in order to maintain the characteristics of the oxide semiconductor layer (in order to suppress a reduction in resistance), as the second gate insulating layer 5 serving as a layer in contact with the oxide semiconductor layer among the gate insulating layers, A layer containing oxygen (eg, an oxide insulating film such as SiO ₂ or SiO _x N _y (x> y)) is preferably used. Accordingly, when oxygen vacancies occur in the oxide semiconductor layer, the oxygen vacancies can be recovered by oxygen contained in the oxide layer. Accordingly, oxygen vacancies in the oxide semiconductor layer can be reduced and reduction in resistance of the oxide semiconductor layer can be suppressed. On the other hand, the formation of such an oxide insulating film has a problem that the etching rate is slow and processing tact is required. On the other hand, when the first gate insulating layer 5a located on the gate electrode side in the gate insulating layer is formed of an insulating film other than the oxide insulating film (for example, a nitride film such as SiNx), the insulation with respect to the entire thickness of the gate insulating layer is achieved. The thickness ratio (film thickness occupancy) of the oxide film can be reduced. As a result, it is possible to suppress the processing tact while suppressing the resistance reduction of the oxide semiconductor layer. As described above, when this embodiment is applied to a semiconductor device including an oxide semiconductor TFT having a gate insulating layer having a two-layer structure, the above effect is achieved by using two layers of the gate insulating layer while ensuring high TFT characteristics. (Improvement of process stability) can be obtained.

Next, an example of a manufacturing method of the TFT substrate 100E according to the embodiment of the present invention will be described with reference to FIGS.

FIG. 15 is a block diagram for explaining a manufacturing method of the TFT substrate 100E. 16 (a) to 16 (h) are schematic cross-sectional views for explaining a manufacturing method of the TFT substrate 100E. 16 (a) to 16 (h) show a cross-sectional structure corresponding to FIG. 14 (a).

As shown in FIG. 15, the manufacturing method of the TFT substrate 100E includes the gate electrode forming step GT, the first gate insulating layer step GI-1, the pixel electrode forming step PX, the refractory metal nitride layer forming step IM, It has a gate insulating layer / semiconductor layer forming step GI-2 / PS, a source / drain electrode forming step SD, a protective layer forming step PAS, and a common electrode forming step CT, and the process proceeds in this order.

First, as shown in FIG. 16A, in the gate electrode formation step GT, the gate electrode 4 is formed by the same method as described above with reference to FIG.

Next, as shown in FIG. 16B, in the first gate insulating layer step GI-1, after forming an insulating film (not shown) on the gate electrode 4 by, for example, CVD, photolithography and wet or The insulating film is patterned by a dry etching method or the like to form the first gate insulating layer 5a. Further, after the patterning of the first gate insulating layer 5a, the resist (not shown) used for the patterning is peeled off.

Next, as shown in FIG. 16C, in the pixel electrode formation step PX, the pixel electrode 3 is formed on the gate insulating layer 5a by the same method as described above with reference to FIG. To do.

Next, as shown in FIG. 16D, in the refractory metal nitride layer forming step IM, the same method as described above with reference to FIG. The nitride layer 20 is formed by this method.

Subsequently, as shown in FIG. 16E, in the second gate insulating layer / semiconductor layer forming step GI-2 / PS, the second gate insulating layer 5 and the first gate insulating layer 5 are formed on the first gate insulating layer 5a and the pixel electrode 3. A semiconductor layer 6 is formed. The method for forming the second gate insulating layer 5 and the semiconductor layer 6 is the same as the method for forming the insulating layer 5 and the semiconductor layer 6 described above with reference to FIG.

Next, after the source / drain electrode formation step SD, the protective layer formation step PAS, and the common electrode formation step CT shown in FIGS. 16 (f) to 16 (h), the source electrode 7s, the drain electrode 7d, the protective layer 8 and A common electrode 9 is formed. These forming methods are the same as those described above with reference to FIGS. 3 (e) to 3 (g). In this way, the TFT substrate 100E is obtained.

When an electrode layer made of an ITO polycrystal is formed as the pixel electrode 3, in the above method, wet etching is used for patterning the nitride layer 20 and patterning the source and drain electrodes performed after the pixel electrode 3 is formed. preferable. It can be suppressed that the characteristics of the upper surface of the pixel electrode 3 are deteriorated by dry etching, which causes a decrease in adhesion and an increase in contact resistance.

(Sixth embodiment)
The sixth embodiment of the semiconductor device according to the present invention will be described below. The semiconductor device of this embodiment is a TFT substrate of a display device.

FIGS. 17A and 17B are schematic cross-sectional views of the TFT substrate 100F of the present embodiment, respectively. For a plan view of the TFT substrate 100F and an enlarged plan view of the contact portion, refer to FIG. 1 (a) and FIG. 1 (d), respectively. FIGS. 17A and 17B show cross-sectional structures taken along lines A-A ′ and B-B ′ of FIG. Constituent elements similar to those of the TFT substrate 100A shown in FIG.

The TFT substrate 100F is different from the TFT substrate 100A in that a base insulating layer (buffer layer) 15 is formed on the substrate 2 and a gate electrode 4 and a pixel electrode 3 are formed on the base insulating layer 15.

According to this embodiment, the same effect as the TFT substrate 100A of the first embodiment can be obtained. Further, depending on the metal material constituting the gate electrode 4, the adhesion to the substrate 2 may be low, but by forming the base insulating layer 15 on the substrate 2, the adhesion of the gate electrode 4 can be improved. . In addition, since the base insulating layer 15 functions as a protective layer for the substrate 2, it is possible to use a substrate that can cause ion elution, such as alkali glass, as the substrate 2. Furthermore, as the substrate 2, a plastic substrate such as an acrylic resin or a film base material such as PET can be used. Thus, since the board | substrate other than an alkali free glass can also be widely used as the board | substrate 2, the selectivity of the board | substrate 2 becomes high.

When using a plastic or film base material having low heat resistance as the substrate 2, it is preferable to use an oxide semiconductor layer as the semiconductor layer 6. Since an oxide semiconductor can be processed at a lower temperature than a Si-based semiconductor, an oxide semiconductor film can be formed and patterned on a plastic or a film substrate. Therefore, when a plastic or film substrate is used as the substrate 2 and the oxide semiconductor TFT is formed after the base insulating layer 15 is formed on the surface thereof, a semiconductor device that can be suitably applied to, for example, a flexible display can be manufactured.

As the base insulating layer 15, for example, SiO ₂ (silicon oxide), SiN _x (silicon nitride), SiO _x N _y (silicon oxynitride, x> y), SiN _x O _y (silicon nitride oxide, x> y), Al A single layer or a laminate formed of ₂ O ₃ (aluminum oxide) or tantalum oxide (Ta ₂ O ₅ ) can be used. The thickness of the base insulating layer 15 is, for example, not less than about 50 nm and not more than 600 nm.

The configurations of the gate electrode 4 and the contact portion 90 are not limited to the configuration shown in FIG. In FIG. 17, the base insulating layer 15 is formed on the TFT 100A (FIG. 1), but the base insulating layer 15 may be applied to other TFT substrates 100B to 100D.

The TFT substrate 100F can be manufactured as follows. First, the base insulating layer 15 is formed on the substrate 2 by a CVD method or the like (buffer layer forming step BU). Subsequently, pixel electrode formation step PX, gate electrode formation step GT, refractory metal nitride layer formation step IM, gate insulating layer / semiconductor layer formation step GI / PS, source / drain electrode formation step SD, protective layer formation step PAS and common electrode forming step CT are performed. Each process after the formation of the base insulating layer 15 is the same as the process described above with reference to FIGS.

(Seventh embodiment)
Hereinafter, a seventh embodiment of the semiconductor device of the present invention will be described. The semiconductor device of this embodiment is different from the above-described embodiment in that an insulating layer is not formed between the transparent conductive layer and the metal layer.

The semiconductor device of this embodiment has a contact portion that connects the transparent conductive layer and the metal layer. In the contact portion, a refractory metal nitride layer is disposed between the transparent conductive layer and the metal layer, and the refractory metal nitride layer is in contact with the upper surface of the transparent conductive layer. Further, when viewed from the normal direction of the substrate, the refractory metal nitride layer is disposed in a region where the metal layer and the transparent conductive layer overlap, and the shape of the refractory metal nitride layer and the metal layer The shape is different. The metal layer is, for example, a drain electrode or an electrode layer electrically connected to the drain electrode, and the transparent conductive layer is, for example, a pixel electrode. Note that the semiconductor device of the present embodiment only needs to have a contact portion configured as described above, and such a contact portion is not limited to the contact portion between the TFT and the pixel electrode, but a terminal portion or a connection portion. It may be.

FIG. 18A is a schematic plan view of a TFT substrate 100G according to an embodiment of the present invention. 18B is a schematic cross-sectional view of the TFT substrate 100G along the line AA ′ in FIG. 18A, and FIG. 18B is a line BB ′ in FIG. It is typical sectional drawing of the TFT substrate 100G along. FIG. 18D is an enlarged plan view in which a region including the contact portion in the TFT substrate 100G is enlarged. Constituent elements similar to those of the TFT substrate 100A shown in FIG.

As shown in FIGS. 18A to 18D, the TFT substrate 100G includes a substrate 2, a gate electrode 4 formed on the substrate 2, an insulating layer 5 covering the gate electrode 4, and an insulating layer 5 A pixel electrode (transparent conductive layer) 3 formed thereon, a semiconductor layer 6 overlapping with the gate electrode 4 through the insulating layer 5, and a source electrode 7s and a drain electrode (metal layer) electrically connected to the semiconductor layer 6 ) 7d. The TFT substrate 100G is provided with a contact portion 90 that electrically connects the drain electrode 7d and the pixel electrode 3.

In the contact portion 90, the nitride layer 20 is disposed between the pixel electrode 3 and the drain electrode 7d. The nitride layer 20 is in contact with a part of the upper surface of the pixel electrode 3. Further, when viewed from the normal direction of the substrate 2, the shape of the nitride layer 20 and the shape of the drain electrode 7 d are different. In the present embodiment, the insulating layer 5 is a gate insulating layer, and the pixel electrode 3 and the nitride layer 20 are provided above the insulating layer 5.

Since the TFT substrate 100G of this embodiment has the nitride layer 20 between the drain electrode 7d and the pixel electrode 3, the resistance between the pixel electrode 3 and the drain electrode 7d can be kept low, And these adhesiveness can be improved. The shape of the nitride layer 20 is different from the shape of the drain electrode 7d. Thus, since the nitride layer 20 and the drain electrode 7d are separately patterned, the nitride layer 20 can be disposed only in a necessary region, and the manufacturing cost can be kept low.

In the illustrated example, when viewed from the normal direction of the substrate 2, the nitride layer 20 is disposed over the entire region where the drain electrode 7 d and the pixel electrode 3 overlap. For this reason, the upper surface of the pixel electrode 3 is not in direct contact with the drain electrode 7d. With such a configuration, a decrease in adhesion and an increase in resistance due to the characteristics of the upper surface of the pixel electrode 3 can be more effectively suppressed. For example, as can be seen from FIG. 18 (d), when viewed from the normal direction of the substrate 2, the above configuration can be realized more reliably by making the width of the nitride layer 20 larger than the width of the drain electrode 7d. .

In the first to sixth embodiments described above, the contact portion is formed in the contact hole of the insulating layer, so that the contact area is limited to the area of the contact hole. On the other hand, in this embodiment, since an insulating layer is not formed between the drain electrode 7d and the pixel electrode 3, the drain electrode 7d and the nitride layer 20 (or the nitride layer 20 and the pixel electrode 3) in the contact portion The contact area can be increased. Therefore, the display quality can be further stabilized.

Further, in the example shown in FIG. 18, since the width of the nitride layer 20 is made larger than the width of the drain electrode 7d, the opening area of the pixel is reduced accordingly. However, according to the present embodiment, it is possible to suppress the length of the portion of the drain electrode 7d that overlaps the pixel electrode 3 while ensuring the same contact area as compared with the first to sixth embodiments. is there. Therefore, by suppressing the length of the drain electrode 7d, the aperture ratio can be kept high even if the width of the drain electrode 7d is increased.

Next, an example of a manufacturing method of the TFT substrate 100G will be described with reference to FIGS. FIG. 19 is a block diagram for explaining a manufacturing method of the TFT substrate 100G. 20 (a) to 20 (g) are schematic cross-sectional views for explaining a manufacturing method of the TFT substrate 100G.

As shown in FIG. 19, the manufacturing method of the TFT substrate 100G includes a gate electrode formation step GT, a gate insulating layer / semiconductor layer formation step GI / PS, a pixel electrode formation step PX, a refractory metal nitride layer formation step IM, It has a source / drain electrode forming step SD, a protective layer forming step PAS, and a common electrode forming step CT, and the process proceeds in this order.

Specific manufacturing steps will be described with reference to FIGS. 20 (a) to 20 (g). Note that the cross-sectional structure shown in FIGS. 20A to 20G corresponds to the cross-sectional structure shown in FIG. The formation method and patterning method of each film are the same as those described above with reference to FIG.

As shown in FIG. 20A, in the gate electrode formation step GT, after forming a conductive film on the substrate 2 by, for example, sputtering, the conductive film is patterned to form the gate electrode 4.

Next, as shown in FIG. 20B, in the gate insulating layer / semiconductor layer forming step GI / PS, an insulating film (not shown) is formed by, for example, a CVD method so as to cover the gate electrode 4. Next, the insulating film 5 is formed by patterning this insulating film. Thereafter, a semiconductor film (not shown) (for example, an In—Ga—Zn—O-based semiconductor film) is formed on the insulating layer 5 by, for example, sputtering, and the semiconductor film is patterned to form the semiconductor layer 6. To do. The semiconductor layer 6 is formed so as to overlap the gate electrode 4 with the insulating layer 5 interposed therebetween.

Next, as shown in FIG. 20C, in the pixel electrode formation step PX, a conductive film (not shown) (for example, a transparent conductive film such as an ITO film) is formed on the insulating layer 5, and then the conductive film is formed. Is patterned to form the pixel electrode 3.

Subsequently, as shown in FIG. 20D, in the refractory metal nitride layer forming step IM, a refractory metal nitride film is formed so as to cover the pixel electrode 3 by sputtering in a nitrogen atmosphere, for example. . Next, the nitride film is patterned to form a nitride layer 20 on a part of the upper surface of the pixel electrode 3.

Next, as shown in FIG. 20E, in the source / drain electrode formation step SD, a metal film (not shown) is formed on the semiconductor layer 6, the insulating layer 5, and the nitride layer 20 by, for example, sputtering. Form. Thereafter, the metal film is patterned by a photolithography method, a wet etching method, or the like to form the source electrode 7s and the drain electrode 7d.

The source electrode 7s and the drain electrode 7d are electrically connected to the semiconductor layer 6, respectively. Of the semiconductor layer 6, a portion in contact with the source electrode 7 s is a source contact region, a portion in contact with the drain electrode 7 d is a drain contact region, and a portion sandwiched between the source contact region and the drain contact region is a channel region. The drain electrode 7 d is also electrically connected to the pixel electrode 3 through the nitride layer 20. The drain electrode 7d may be in contact with both the nitride layer 20 and the pixel electrode 3. In this way, a contact portion 90 that connects the drain electrode 7d and the pixel electrode 3 is obtained.

Next, as shown in FIGS. 20 (f) and 20 (g), the protective layer forming step PAS and the common electrode forming step CT are performed to form the protective layer 8 and the common electrode 9. These forming methods are the same as those described above with reference to FIGS. 3 (f) and 3 (g). In this way, the TFT substrate 100G is obtained.

According to the above method, after the pixel electrode 3 is formed, the nitride layer 20 is formed before the source and

drain electrodes

7s and 7d are formed, so that the upper surface of the pixel electrode 3 can be protected. For this reason, it is possible to suppress the upper surface of the pixel electrode 3 from being modified in the source and drain electrode formation step and the subsequent steps, and thus it is possible to suppress an increase in resistance of the contact portion and a decrease in reliability.

The manufacturing method of the TFT substrate 100G is not limited to the above method. For example, the pixel electrode forming step PX and the refractory metal nitride layer forming step IM in the above method can be performed simultaneously.

FIGS. 21A to 21E are views for explaining another example of the manufacturing method of the TFT substrate 100G, and a process PX for simultaneously forming the pixel electrode and the refractory metal nitride layer. It is sectional drawing which shows / IM.

First, the gate electrode 4 and the insulating layer 5 are formed on the substrate 2 by the same method as described above.

Next, as shown in FIG. 21A, a transparent conductive film 3 ′ is formed on the insulating layer 5, and a refractory metal nitride film (metal nitride film) 20 ′ is formed on the transparent conductive film 3 ′. Form.

Next, as shown in FIG. 21B, resist films R3 and R4 having different thicknesses are formed on the metal nitride film 20 ′ by a halftone exposure method using a single photomask (halftone mask). Form in pattern shape. Here, a resist film R3 is formed in a region where a nitride layer is to be formed, and a resist film R4 thinner than the resist film R3 is formed in a region where a pixel electrode is to be formed (other than a region where nitride is to be formed). Form.

Next, as shown in FIG. 21C, the transparent conductive film 3 'and the metal nitride film 20' in a region not covered with the resist films R3 and R4 are patterned by a wet etching method. By this patterning, the pixel electrode 3 is formed from the transparent conductive film 3 ′, and the nitride layer 20 is formed from the metal nitride film 20 ′.

Next, as shown in FIG. 21D, the resist film R4 is removed by a dry etching method. In addition, by this dry etching method, a part of the resist film R3 is removed to form a resist film R3 'having a smaller thickness than the resist film R3. Thereafter, as shown in FIG. 21E, the resist film R3 'is removed by a known method.

Thereafter, as described with reference to FIGS. 3E to 3G, the source / drain electrode forming step SD, the protective layer forming step PAS, and the common electrode forming step CT are shown in FIG. A TFT substrate 100G is obtained.

When the halftone exposure method is used as in the above method, the pixel electrode 3 and the nitride layer 20 can be formed from one photomask, so that the number of photomasks can be reduced and the manufacturing cost can be reduced.

In the first to sixth embodiments described above, the insulating layer 5 is formed between the nitride layer 20 and the drain electrode 7d, and the contact portion 90 is formed in the contact hole of the insulating layer 5. In the seventh embodiment, no insulating layer is provided between the nitride layer 20 and the drain electrode 7d. As described above, according to the seventh embodiment, there is an advantage that the contact area between the drain electrode 7d and the nitride layer 20 in the contact portion 90 and between the nitride layer 20 and the pixel electrode 3 can be increased. On the other hand, if the contact portion 90 is formed in the contact hole of the insulating layer 5 as in the first to sixth embodiments, the aperture ratio of the pixel can be further increased. Hereinafter, this reason will be described with reference to the drawings.

According to the configuration in which the insulating layer is not formed between the nitride layer 20 and the drain electrode 7d (seventh embodiment), as shown in FIG. 18D, the source wiring 7 (m) and 7 (m + 1) and the pixel electrode 3 (m) are formed. The pixel electrode 3 (m) is formed between adjacent source lines 7 (m) and 7 (m + 1). In this case, the distance between the pixel electrode 3 and the source wirings 7 (m) and 7 (m + 1) is set to 5 μm or more, for example. This is because if the distance between the pixel electrode 3 and the source wiring 7 is too small (for example, less than 5 μm), there is a possibility of short circuit between them.

On the other hand, according to the configuration in which the insulating layer 5 is formed between the nitride layer 20 and the drain electrode 7d (first to sixth embodiments), as shown in FIG. m) and 7 (m + 1) and the pixel electrode 3 (m) are formed in different layers. Therefore, when viewed from the normal direction of the substrate 2, the distance between the pixel electrode 3 and the source wiring 7 is, for example, less than 5 μm. Even if the pixel electrode 3 and the source line 7 are arranged so as to overlap each other by about 1 μm at the maximum, the possibility of short circuit between them is low. Therefore, the distance between the source wirings 7 (m) and 7 (m + 1) and the pixel electrode 3 when viewed from the normal direction of the substrate 2 can be kept small or can be arranged so as to overlap. Become.

Note that, contrary to the above, the gate wiring 14 and the pixel electrode 3 are formed in different layers in the configuration shown in FIG. 18, and are formed in the same layer in the configuration shown in FIG. For this reason, the configuration shown in FIG. 18 can reduce the distance between the gate wiring 14 and the pixel electrode 3. In general, for example, one pixel of a liquid crystal display device has a length in a direction (column direction) parallel to the extending direction of the source lines 7 (m) and 7 (m + 1) in a direction perpendicular to the column direction (row direction). ) (For example, length in the column direction: length in the row direction = 3: 1). Therefore, the distance between the gate wiring 14 and the pixel electrodes 3 (m) and 3 (m + 1) is reduced when the distance between the source wirings 7 (m) and 7 (m + 1) and the pixel electrode 3 is reduced. The effect of increasing the area of the effective opening region v of the pixel is greater than this. Therefore, as shown in FIG. 1D, the pixel aperture ratio can be more effectively improved by adopting the configuration in which the insulating layer 5 is formed between the nitride layer 20 and the drain electrode 7d.

The embodiment of the semiconductor device according to the present invention only needs to have a contact portion having a transparent conductive layer, a metal layer on the transparent conductive layer, and a nitride layer disposed between them, and the TFT substrate described above is provided. The present invention is not limited and can be applied to various semiconductor devices. Further, the manufacturing process, the material of each component, the thickness, and the like are not limited to the above-described example. Furthermore, the structure of the TFT is not limited to the above-described example. For example, when an oxide semiconductor TFT is formed, an etch stop layer may be provided so as to be in contact with the channel region. By reducing the resistance of part of the oxide semiconductor film, the oxide semiconductor layer and the pixel electrode can be formed from the same oxide semiconductor film. Even in that case, by forming a nitride layer in contact with the upper surface of the pixel electrode between the pixel electrode (transparent oxide layer) and the drain electrode, the resistance of the contact portion is increased and the adhesion is decreased. The effect of suppressing is obtained.

The TFT substrates 100A to 100G of the above-described embodiments can be applied to display devices in operation modes other than the FFS mode. For example, the present invention may be applied to a vertical electric field drive type display device such as a VA (Vertical Alignment) mode. In that case, the common electrode 9 may not be provided. Alternatively, instead of the common electrode 9, a transparent conductive layer that functions as an auxiliary capacitance electrode may be provided to face the pixel electrode 3, and a transparent auxiliary capacitance may be formed in the pixel.

Embodiments of the present invention can be widely applied to various semiconductor devices including a contact portion that connects a transparent conductive layer and a metal layer. For example, circuit boards such as active matrix substrates, liquid crystal display devices, display devices such as organic electroluminescence (EL) display devices and inorganic electroluminescence display devices, imaging devices such as image sensor devices, image input devices, fingerprint readers, etc. It can also be applied to other electronic devices.

2 Substrate 3, 3 (m), 3 (m + 1) Pixel electrode (transparent conductive layer)
4 Gate electrode 5 Insulating layer 5u Opening 6 Semiconductor layer 7s Source electrode 7d Drain electrode (metal layer)
7 (m), 7 (m + 1) Source wiring 8 Protective layer 9 Common electrode 14 Gate wiring 15 Base insulating layer 19 Slit 20 Nitride layer 100A to 100G Semiconductor device (TFT substrate)

Claims

A substrate,
A transparent conductive layer supported by a substrate;
An insulating layer formed to cover the transparent conductive layer and having an opening at least partially overlapping the transparent conductive layer;
A metal layer formed on the insulating layer and in the opening;
A contact portion connecting the transparent conductive layer and the metal layer;
In the contact portion, a refractory metal nitride layer is disposed between the transparent conductive layer and a portion of the metal layer located in the opening,
The semiconductor device in which the nitride layer of the refractory metal is in contact with the upper surface of the transparent conductive layer.
2. The semiconductor device according to claim 1, wherein the shape of the refractory metal nitride layer is different from the shape of the metal layer when viewed from the normal direction of the substrate.
3. The semiconductor device according to claim 1, wherein the refractory metal nitride layer is in contact with a portion of the metal layer located in the opening.
Further comprising a thin film transistor supported on the substrate,
The thin film transistor includes a semiconductor layer including a channel region, a gate electrode, a gate insulating layer formed between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode electrically connected to the semiconductor layer. Including
The metal layer is an electrode layer electrically connected to the drain electrode or the drain electrode of the thin film transistor,
The insulating layer includes the gate insulating layer;
The semiconductor device according to claim 1, wherein the transparent conductive layer functions as a pixel electrode.
5. The semiconductor device according to claim 4, wherein the gate electrode includes a first gate layer formed of the same metal nitride film as the refractory metal nitride layer.
6. The gate electrode further includes a second gate layer disposed on the first gate layer, and the second gate layer is formed of a material different from that of the first gate layer. A semiconductor device according to 1.
The semiconductor device according to claim 6, further comprising a conductive layer formed of the same conductive film as the second gate layer, between the refractory metal nitride layer and the metal layer.
8. The semiconductor device according to claim 4, further comprising an insulating layer between the gate electrode and the transparent conductive layer and the insulating layer.
The semiconductor device according to claim 4, further comprising a base insulating layer between the substrate and the gate electrode and the transparent conductive layer.
7. The semiconductor device according to claim 1, wherein at least a part of the upper surface of the nitride layer is in contact with the insulating layer.
A substrate,
A transparent conductive layer supported by a substrate;
A metal layer formed on the transparent conductive layer;
A contact portion connecting the transparent conductive layer and the metal layer;
In the contact portion, a refractory metal nitride layer is disposed between the transparent conductive layer and the metal layer,
The refractory metal nitride layer is in contact with the upper surface of the transparent conductive layer,
When viewed from the normal direction of the substrate, the refractory metal nitride layer is disposed in a region where the metal layer and the transparent conductive layer overlap, and the shape of the refractory metal nitride layer and the metal A semiconductor device that differs from the shape of the layer.
12. The semiconductor device according to claim 11, wherein the refractory metal nitride layer is disposed in an entire region where the metal layer and the transparent conductive layer overlap when viewed from the normal direction of the substrate.
Further comprising a thin film transistor supported on the substrate,
The thin film transistor includes a semiconductor layer including a channel region, a gate electrode, a gate insulating layer formed between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode electrically connected to the semiconductor layer. Including
The metal layer and the transparent conductive layer are disposed on the gate insulating layer,
The metal layer is an electrode layer electrically connected to the drain electrode or the drain electrode of the thin film transistor,
The semiconductor device according to claim 11, wherein the transparent conductive layer functions as a pixel electrode.
A protective layer formed on the source electrode and the drain electrode;
The semiconductor device according to claim 4, further comprising a common electrode disposed so as to overlap at least a part of the transparent conductive layer with the protective layer interposed therebetween.
The semiconductor device according to any one of claims 4 to 9, 13, and 14, wherein the semiconductor layer is an oxide semiconductor layer.
The semiconductor device according to claim 15, wherein the oxide semiconductor layer contains In, Ga, and Zn.
A method of manufacturing a semiconductor device according to claim 4 or 13,
A method of manufacturing a semiconductor device, wherein the nitride layer is formed after forming the transparent conductive layer on the substrate and before forming the gate electrode and the insulating layer.
Preparing a substrate (a);
Forming a transparent conductive layer on a part of the surface of the substrate (b);
Forming a metal nitride film made of a refractory metal nitride on the surface of the substrate and the transparent conductive layer, and a conductive film made of a material different from the metal nitride film in this order (c); ,
By patterning the metal nitride film and the conductive film from one photomask by a halftone exposure method, the metal nitride film and the part of the surface of the substrate where the transparent conductive layer is not formed are formed. Forming a gate electrode made of a conductive film and forming a nitride layer from the metal nitride film on the transparent conductive layer;
Forming an insulating layer that covers the gate electrode, the transparent conductive layer, and the nitride layer, and has an opening that exposes at least a portion of the surface of the nitride layer; and
Forming a semiconductor layer on the insulating layer (f);
Forming a metal film on the semiconductor layer, on the insulating layer and in the opening;
A method of manufacturing a semiconductor device, comprising: patterning the metal film to form a source electrode and a drain electrode, wherein the drain electrode is in contact with the nitride layer in the opening.
Preparing a substrate (a);
Forming a gate electrode on a part of the surface of the substrate, and forming a semiconductor layer on the gate electrode via a gate insulating layer; and
Forming a transparent conductive film and a metal nitride film made of a refractory metal nitride on the gate insulating layer and the semiconductor layer;
By patterning the transparent conductive film and the metal nitride film from one photomask by a halftone exposure method, the transparent conductive film is transparent to the surface of the substrate where the gate electrode is not formed. Forming a conductive layer and forming a nitride layer from the metal nitride film on a part of the transparent conductive layer;
Forming a metal film that covers the semiconductor layer, the transparent conductive layer, and the nitride layer; and
A method of manufacturing a semiconductor device, comprising: forming a source electrode and a drain electrode by patterning the metal film, wherein the drain electrode is in contact with the nitride layer (f).
The semiconductor device according to claim 16, wherein the oxide semiconductor layer has crystallinity.
20. The method of manufacturing a semiconductor device according to claim 18, wherein the semiconductor layer is an oxide semiconductor layer.
The method of manufacturing a semiconductor device according to claim 21, wherein the oxide semiconductor layer contains In, Ga, and Zn.
The method for manufacturing a semiconductor device according to claim 22, wherein the oxide semiconductor layer has crystallinity.