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WO2014089795A1 - 一种垂直沟道型三维半导体存储器件及其制备方法 - Google Patents

一种垂直沟道型三维半导体存储器件及其制备方法 Download PDF

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Publication number
WO2014089795A1
WO2014089795A1 PCT/CN2012/086511 CN2012086511W WO2014089795A1 WO 2014089795 A1 WO2014089795 A1 WO 2014089795A1 CN 2012086511 W CN2012086511 W CN 2012086511W WO 2014089795 A1 WO2014089795 A1 WO 2014089795A1
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WO
WIPO (PCT)
Prior art keywords
channel
memory device
semiconductor memory
hollow
dimensional semiconductor
Prior art date
Application number
PCT/CN2012/086511
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English (en)
French (fr)
Inventor
霍宗亮
刘明
Original Assignee
中国科学院微电子研究所
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Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to PCT/CN2012/086511 priority Critical patent/WO2014089795A1/zh
Publication of WO2014089795A1 publication Critical patent/WO2014089795A1/zh
Priority to US14/581,990 priority patent/US9437609B2/en
Priority to US15/214,372 priority patent/US9613981B2/en

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    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Definitions

  • the present invention relates to the field of microelectronic devices and memory technologies, and in particular, to a nonvolatile ultra-high density vertical channel type three-dimensional semiconductor memory device and a preparation method thereof .
  • NAND-type flash memory technology with high data storage capacity has become the focus of research.
  • NAND-type flash memory technology focuses on high-density, low-cost research on non-volatile flash memory technology. Since the advent of NAND-type flash memory, increasing the storage capacity by increasing the size of memory cells has been the main way of technological development.
  • FIG. 1 Different from the traditional method of reducing the storage unit size to increase the storage density, realizing the vertical cascading of storage units to realize three-dimensional storage (Fig. 1) is becoming the main idea of the development of flash memory technology, and has also attracted widespread attention in the industry. The technology has gradually emerged since 2006. In IEDM in 2006, South Korea's Samsung Electronics demonstrated the storage array structure of a two-layer planar channel using an epitaxial process. In 2007, Toshiba reported on the VLSI a vertical channel BiCS memory array implemented by the "gate-first" process.
  • the basic memory cell (Fig. 2b) constituting the three-dimensional memory device is a polysilicon trench. Road material.
  • the grain size change of the polysilicon channel and the charge trap caused by the grain gap trap can significantly reduce the carrier mobility.
  • the carrier mobility of the polysilicon channel is generally l ⁇ 50cm 2 / VS , which is much lower than the traditional single.
  • the carrier mobility of crystalline silicon reduces the read current of the memory array string, and limits the access capability of peripheral circuits; on the other hand, the vertically stacked memory cells are etched by the etching process.
  • the limitation is such that the lower and upper memory cells of the memory string have different polysilicon channel thicknesses.
  • the top memory cell has a larger channel diameter (dl ⁇ d5) than the bottom memory cell, and the bottom trench When the channel enters the fully depleted state, the top channel may still be partially depleted, which also causes differences in storage performance (such as erasing speed and durability) and reduces the reliability of the three-dimensional memory.
  • the main purpose of the present invention is to propose a vertical channel type three-dimensional semiconductor memory around the polysilicon channel technology. And its preparation method to solve the technical problem of small open channel current caused by low carrier mobility of the conventional polysilicon channel, and improve the storage performance consistency and reliability of the vertical storage unit.
  • the present invention provides a vertical channel type three-dimensional semiconductor memory device, comprising: a substrate; a multilayer film structure formed by sequentially depositing an insulating layer and an electrode material layer on the substrate; etching a plurality of through holes formed in the multilayer film structure to the substrate, wherein the through holes are used Defining a channel region; depositing a plurality of gate stacks formed by a barrier layer, a memory layer, and a tunneling layer on the inner walls of the plurality of via holes; depositing channel material on a surface of the tunneling layer of the plurality of gate stacks a plurality of hollow channels formed; a drain line formed by the contact hole contact region on the hollow channel; and a source formed by the via hole and the substrate contact region under the hollow channel.
  • the present invention further provides a method for preparing a vertical channel type three-dimensional semiconductor memory device, comprising: sequentially depositing an insulating layer and an electrode material layer alternately on a substrate to form a multilayer film structure; a film structure to the substrate to form a plurality of via holes for defining a channel region; depositing a barrier layer, a memory layer and a tunneling layer on the inner wall of the plurality of via holes to form a plurality of gate stacks; Depositing a channel material on a tunneling layer surface of the plurality of gate stacks to form a plurality of hollow channels; forming a drain level on the hollow channel with a contact hole contact region; and forming a via hole and a liner under the hollow channel
  • the bottom contact region forms a source.
  • the present invention has the following beneficial effects:
  • the vertical channel type three-dimensional semiconductor memory device having the A ir -gap characteristic proposed by the present invention can effectively overcome the conventional method by reducing the channel stress in the channel crystallization process, reducing the back interface or the bulk lattice defect density, and the like.
  • the vertical channel type three-dimensional semiconductor memory device with the A ir -gap feature proposed by the present invention can improve the thickness control of the channel at various positions of the vertical storage string, thereby improving the storage performance of the vertical storage cells. Consistency and reliability.
  • FIG. 1 is a schematic diagram of evolution of a conventional planar flash memory array to a three-dimensional memory
  • FIG. 2a to FIG. 2c are top-view diagrams and singles of a conventional vertical three-dimensional memory
  • 2a is a top view of a three-dimensional memory of a columnar ring-gate structure
  • FIG. 2b is a structure of a basic memory cell of FIG. 2a
  • FIG. 2c is a top view of a three-dimensional memory of a strip-shaped planar gate structure
  • FIG. 3 is a structural view of a columnar memory array structure along a line A-A' in FIG. 2a and its different positions, and only the array strings are not given peripheral connections;
  • FIG. 4a is a memory cell junction of a hollow channel using the Air-gap concept according to the present invention.
  • FIG. 4b is a three-dimensional flash memory array structure having the memory cell shown in FIG. 4a according to the present invention, wherein the three-dimensional flash memory array structure is along the figure.
  • 5A to 5F are views showing an example of a process flow for preparing a hollow channel of a new storage structure along the line B-B' in Fig. 2a and in the direction perpendicular to the paper.
  • FIG. 1 A schematic diagram of the evolution of a conventional planar flash array to a three dimensional memory is shown in FIG.
  • NAND-type flash memory devices have improved storage capacity by reducing the size of memory cells to increase the number of memory cells per unit area.
  • Each string has two selection transistors and a plurality of memory cells connected in series.
  • the three-dimensional storage technique obtains a vertical storage string by vertically stacking a plurality of memory cells, and arranges the vertical storage strings in parallel to form a three-dimensional memory having a high density.
  • FIG. 2a to 2c are top-view sectional views and unit structure diagrams of a conventional vertical three-dimensional memory.
  • vertical channel three-dimensional memory is a research hotspot of high-density flash memory technology, in which polysilicon channel can be completed by deep hole or deep trench etching and filling.
  • the TCAT structure proposed by Samsung and the BiCS structure of Toshiba are both used in the columnar channel structure as shown in Fig. 2a and Fig. 2b.
  • the columnar channel forms a vertical annular gate electrode to control the erasing speed.
  • the strip-shaped vertical channel is similar to the double-gate structure, and multi-bit storage can be realized on each of the chip channels by controlling different gate electrodes.
  • FIG. 3 is a columnar ring-gate vertical three-dimensional memory shown in FIG. 2a as an example, showing a columnar memory array structure along AA' and a vertical paper direction in FIG. 2a and a structure diagram of a memory cell at different positions, where Only the array string is given without a peripheral connection. It can be seen that since it is difficult to obtain a deep hole etched at 90 degrees during deep hole etching, the top cell of the vertical string has a larger channel diameter than the bottom cell during the subsequent solid polysilicon channel formation process. This difference will cause a change in the erasing speed. At the same time, the depletion state of the channel in the read and write operations will also cause inconsistency in cell performance. Even the volume change during the conversion from amorphous silicon to polycrystalline silicon causes more defects and greater stress in the core structure, thereby reducing the mobility of carriers in the channel.
  • the main idea of the present invention is to improve the uniformity of the memory cells by obtaining the same polysilicon channel thickness, and to improve the carrier mobility by reducing the scattering of carriers by the polysilicon channel back interface defects. Based on this idea, the present invention will propose a hollow channel structure based on the A ir -gap concept and be used for a three-dimensional memory.
  • Figure 4a shows the memory cell structure based on the Air-gap concept
  • Figure 4b shows the vertical array structure of the three-dimensional memory with the hollow structure.
  • the hollowing of the memory cell channel can be automatically realized by controlling the deposition thickness during the channel deposition process, and the incomplete channel filling can ensure that the memory cells of the vertical memory string have the same thickness of the polysilicon film, so that the three-dimensional memory
  • the storage unit has good consistency.
  • the polysilicon film reduces the number of body defects in the die gap in the channel by thinning the thickness, thereby reducing the fluctuation of the threshold voltage between the memory cells.
  • the back interface of polysilicon can significantly reduce the interface trap density by means of post-annealing to reduce the scattering of carriers, thereby increasing the channel carrier mobility.
  • the presence of a hollow structure can effectively release the stress generated during the crystallization of amorphous silicon, and the change in channel stress can also improve the trench.
  • the mobility of the Tao is a process using amorphous silicon film deposition and subsequent annealing to form a polysilicon channel.
  • the present invention provides a vertical channel type three-dimensional semiconductor memory device, the three-dimensional
  • the semiconductor memory device includes: a substrate; a multilayer film structure formed by sequentially depositing an insulating layer and an electrode material layer on the substrate; etching the multilayer film structure to a plurality of via holes formed by the substrate, Through holes are used to define the channel region; a plurality of gate stacks formed by depositing a barrier layer, a memory layer and a tunneling layer, and a plurality of hollow trenches formed by depositing a channel material on a surface of the tunneling layer of the plurality of gate stacks; a drain line formed by the contact hole contact region on the hollow channel; and a source formed by the via hole and the substrate contact region under the hollow channel.
  • the hollow channel is a hollow cylindrical channel formed by introducing Air-gap, a hollow annular channel or a hollow band channel.
  • the channel material may be made of polysilicon, amorphous silicon, germanium silicon, germanium, GaAs or InGaAs.
  • the channel material is made of polysilicon material
  • the hollow channel is directly deposited on the surface of the tunneling layer.
  • the method is formed; when the channel material is made of an amorphous silicon material, the hollow channel is formed by depositing an amorphous silicon film on the surface of the tunneling layer and performing high temperature annealing.
  • the hollow surface portion can be subjected to different surface treatments for reducing the defect state such as dangling bonds of the surface.
  • the gate stack can be a charge trap type memory gate stack based on discrete charge storage or a floating gate memory gate stack based on a continuous memory medium.
  • the charge trap type memory gate stack uses a tunneling layer/discrete dielectric storage layer/barrier layer structure composed of SiN or a high-k dielectric material (such as HfO).
  • the floating gate memory gate stack employs a tunneling layer/storage layer/barrier layer structure composed of polysilicon, metal or a composite structure of both polysilicon and metal.
  • each vertical string of data listed in the example consists of two select transistors (SSL and GSL) and six memory cells.
  • SSL and GSL select transistors
  • For a NAND string it is a string consisting of multiple memory cells and GSL and SSL transistors.
  • the bit line is near the GSL and the ground is close to the SSL.
  • the new channel structure can be designed by introducing Air-gap to form any hollow channel structure such as hollow column, hollow ring, or hollow band.
  • the hollow part can be just The memory cell region of the NAND memory string may also include a select transistor region of the memory string, or a partial memory string channel region.
  • the formation of the hollow channel may be formed by deposition of polysilicon film, or by amorphous silicon deposition and high temperature annealing; and different surface treatments may be performed on the hollow surface portion (such as annealing in nitrogen). Etc.) used to reduce the surface of the dangling keys, etc.
  • the trapped state; the vertical channel material having a hollow structure will not be limited to polysilicon, but may be a material which can be used as a channel material such as amorphous silicon, germanium silicon, germanium, GaAs, InGaAs or the like.
  • the vertical memory cell may be a vertical planar gate structure, a vertical double gate structure or a vertical ring gate structure based on different hollow channel structures; a source-drain region of the vertical NAND memory string formed by such vertical cells (ie, a NAND string)
  • the SL and BL contact regions in the middle can be doped with the same type (same as N-type or P-type doping), and different types of doping can be used (such as source region N-type doping, drain region P-type).
  • Doping may also be a source-drain region of a different material (such as a material such as a metal silicide different from the channel in the contact of the BL region); and the gate stack of such a memory cell may be based on discrete charge storage.
  • a charge trapping memory gate stack (such as a tunnel dielectric/SiN discrete dielectric storage layer/barrier structure), or a continuous memory medium based floating gate memory gate stack (such as tunneling layer/polysilicon, metal, or both) The storage structure/barrier structure of the composite structure).
  • the tunneling layer, the storage layer and the barrier layer constituting the gate stack may all be located in the etched deep holes/grooves; may not be in the deep holes/grooves, but only after the polysilicon channel is formed, using the Gate-Last process before the gate electrode deposition Complete gate stack deposition; or it may be partially located in the etched deep hole/groove, such as by completing the tunneling layer before deep hole/slot polysilicon deposition and using the Gate-Last process to complete the memory and barrier layers before gate electrode deposition Together, the deposition of the gate stack is achieved.
  • the hollow channel structure based on this concept can be used for a variety of vertical channel type three-dimensional flash memory devices using a gate-last process (such as BiCS structure, p-BiCS structure, SCP-NAND structure), or can be used for adoption.
  • a gate-last process such as BiCS structure, p-BiCS structure, SCP-NAND structure
  • a variety of vertical channel type 3D flash devices in the Gate-First process such as TCAT structure).
  • the present invention also provides a method of fabricating a vertical channel type three-dimensional semiconductor memory device, the method comprising the following steps:
  • Step 1 depositing an insulating layer and an electrode material layer alternately on the substrate to form a multilayer film.
  • Step 2 etching the multilayer film structure to the substrate to form a plurality of via holes, the through holes are defined Out of the channel area;
  • Step 3 depositing a barrier layer, a storage layer and a tunneling layer on the inner wall of the plurality of through holes Multiple gate stacks;
  • Step 4 depositing a channel material on a surface of a tunneling layer of the plurality of gate stacks to form a plurality of hollow channels;
  • Step 5 Surface treating the plurality of hollow channels to reduce the defect state of the hollow channel surface; wherein the surface treatment may be annealed in nitrogen to reduce the hanging bonds of the hollow channel surface.
  • Step 6 forming a drain level in the contact line contact region of the azimuth line connection on the hollow channel.
  • Step 7 forming a source between the via hole and the substrate contact region under the hollow channel.
  • FIG. 5A to FIG. 5F illustrate an implementation of implementing a hollow channel by taking a gate-first process as an example, specifically including:
  • a multilayer film having an insulating layer/electrode material such as SiO/PolySi is deposited, thereby completing the gate electrode preparation of the vertical memory string;
  • sequential deposition of the barrier/storage layer/tunneling layer is performed to obtain a gate stack of the memory cell; where the memory layer may be a continuous storage medium or a discrete medium;
  • the amorphous silicon thin layer deposition is completed, and the hollow structure is formed by incomplete filling;
  • the polysilicon channel is annealed, and the hollow surface is treated to reduce the defect state
  • a three-dimensional memory array having a hollow vertical channel can be effectively realized.
  • the implementation of the polysilicon channel can also be achieved by skipping the incomplete deposition of thin film polysilicon directly from the steps shown in Figures 5D and 5E to obtain a hollow polysilicon channel. For the deformation based on this idea, there will be no more details here.
  • the hollow channel is used, even if the etching angle of the deep hole is not very vertical, the same can be obtained by controlling the deposition time of the film in the channel region.
  • the thickness of the polysilicon channel film reduces the difficulty of the etching process; in addition, the structure also avoids the problem of high quality filling of the original solid channel. Therefore, the preparation process is relatively simple, the manufacturing cost can also be reduced, and it is convenient for industrial application and promotion.
  • a columnar polysilicon channel structure is formed by filling or epitaxial and auxiliary annealing.
  • a hollow columnar, hollow ring or hollow strip-shaped polysilicon channel can be formed by introducing Air-gap.
  • the three-dimensional memory device with the vertical channel of the Air-gap feature can effectively overcome the channel stress during channel crystallization, increase the thickness uniformity of the channel, and reduce the back interface or bulk lattice defect density.
  • the technical problem of small open-state channel current caused by low carrier mobility of conventional polysilicon channel is beneficial to improve the consistency and reliability of storage performance of vertical storage cells, and to effectively reduce vertical channel. Manufacturing difficulty and cost.
  • the application of the hollow Air-gap concept in the present invention is not limited to polysilicon channels, and can also be applied to the formation of vertical hollow electrodes in a three-dimensional cross-array type resistance-switching type memory structure, for example, a three-dimensional vertical cross based on a resistive memory concept.
  • the vertical electrode of the -Bar type resistive memory can also adopt a hollow structure.

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Abstract

一种垂直沟道型三维半导体存储器件及其制备方法，该三维半导体存储器件包括：衬底；在该衬底上依次交替淀积绝缘层和电极材料层形成的多层膜结构；刻蚀该多层膜结构至该衬底形成的多个通孔；在该多个通孔内壁依次淀积阻挡层、存储层和隧穿层形成的多个栅堆栈；在该多个栅堆栈的隧穿层表面淀积沟道材料而形成的多个空心沟道；在该空心沟道上方位线连接用接触孔接触区形成的漏极；以及在该空心沟道下方通孔与衬底接触区形成的源极。该半导体存储器件及其制备方法克服了传统多晶硅沟道低载流子迁移率所带来的小的开态沟道电流的技术难题，并提高了垂直向各存储单元存储性能的一致性和可靠性，降低了垂直沟道的制造难度和成本。

Description

一种垂直沟道型三维半导体存储器件及其制备方法 技术领域 本发明属于微电子器件及存储器技术领域， 尤其涉及一种非易失性 超高密度垂直沟道型三维半导体存储器件及其制备方法。
背景技术 半导体存储技术是微电子技术领域的关键技术之一。 随着信息技术 从以网络和计算为核心转入以存储为核心， 存储技术的研究成为了信息 技术研究的重要方向。特别是具有高数据存储能力的 NAND型闪存技术 成为了研究的重点， 当前 NAND型闪存技术的研究主要集中在高密度、 低成本的非易失性闪存技术研究上面。 自 NAND型闪存问世以来，通过 提高工艺技术缩小存储单元的尺寸来实现存储容量的增加一直是其技 术发展的主要途径。 随着器件尺寸的不断缩小， 传统的基于多晶硅浮栅 的 FLASH技术在存储单元尺寸进入到 20纳米节点以后面临着越来越严 重的来自于成本控制、 物理和工艺技术等方面的挑战， 比如严重的单元 间串扰、 昂贵的 EUV技术等， 因而难以适应后 20纳米结点的存储技术 的发展要求。 因此， 发展新的存储技术成为存储技术实现大容量需求的 必然选择。
不同于传统的通过缩小存储单元尺寸来提高存储密度的方法， 实现 存储单元的垂直向层叠实现三维存储 （如图 1 ) 正成为目前闪存技术发 展的主要思路， 也引起了业界的广泛关注。 该技术从 2006 年开始逐渐 兴起。 2006年在 IEDM上， 韩国三星电子利用外延工艺演示了双层平面 沟道的存储阵列结构； 2007 年日本东芝公司在 VLSI 上报道了采用 "gate-first"工艺实现的垂直沟道的 BiCS存储阵列技术； 之后三星电子在 2009年 VLSI上报道了采用 "gate-last"工艺实现的垂直沟道 TCAT存储阵 列技术和 VS AT ( Vertical Stacked Array Transistor ) 存储结构； 台湾旺宏 电子也在 2010年的 VLSI上报道了具有多层平面沟道的 VG-NAND三维 存储技术。 ITRS2011指出，三维存储技术正成为闪存技术发展的主流技 术。
尽管三维存储技术的研究已经取得了很大的进展， 但来自于可靠性 等方面的问题仍然是该技术走向应用的主要瓶颈。 以基于垂直沟道的三 维存储器为例，无论是采用柱状沟道（图 2a)还是采用条状垂直沟道（图 2c), 其构成三维存储器件的基本存储单元 （图 2b) 均采用多晶硅沟道 材料。 多晶硅沟道的晶粒大小变化及晶粒间隙陷阱引起的电荷陷落会显 著降低载流子的迁移率，多晶硅沟道的载流子迁移率一般在 l~50cm2/VS， 远低于传统单晶硅的载流子迁移率， 过低的载流子迁移率使得存储阵列 串的读取电流降低， 限制了外围电路的访问能力； 另一方面， 垂直向层 叠的存储单元因为刻蚀工艺的限制使得存储串下部和上部的存储单元 具有不同的多晶硅沟道厚度， 以图 3所示为例， 顶部存储单元相较底部 存储单元具有更大的沟道直径（dl<d5)， 在底部沟道进入全耗尽状态时 顶部沟道可能还处在部分耗尽状态， 这同样会造成存储性能 （如擦写速 度及耐久性等） 的差异， 降低三维存储器的可靠性。
发明内容
(一） 要解决的技术问题
针对三维存储技术存在的诸如深孔刻蚀技术、 多层介质沉积技术、 多晶硅沟道技术等技术难题， 本发明的主要目的在于围绕其中的多晶硅 沟道技术提出一种垂直沟道型三维半导体存储器件及其制备方法， 以解 决传统多晶硅沟道低载流子迁移率所带来的小开态沟道电流的技术难 题， 并提高垂直向存储单元存储性能一致性和可靠性。
(二） 技术方案
为达到上述目的， 本发明提供了一种垂直沟道型三维半导体存储器 件， 包括： 一衬底； 在该衬底上依次交替淀积绝缘层和电极材料层形成 的多层膜结构； 刻蚀该多层膜结构至该衬底形成的多个通孔， 该通孔用 以定义出沟道区域； 在该多个通孔内壁依次淀积阻挡层、 存储层和隧穿 层形成的多个栅堆栈； 在该多个栅堆栈的隧穿层表面淀积沟道材料而形 成的多个空心沟道； 在该空心沟道上方位线连接用接触孔接触区形成的 漏级； 以及在该空心沟道下方通孔与衬底接触区形成的源极。
为达到上述目的， 本发明还提供了一种制备垂直沟道型三维半导体 存储器件的方法， 包括： 在衬底上依次交替淀积绝缘层和电极材料层 形成多层膜结构； 刻蚀该多层膜结构至该衬底形成多个通孔， 该通孔用 以定义出沟道区域； 在该多个通孔内壁依次淀积阻挡层、 存储层和隧穿 层形成多个栅堆栈； 在该多个栅堆栈的隧穿层表面淀积沟道材料形成多 个空心沟道； 在该空心沟道上方位线连接用接触孔接触区形成漏级； 以 及在该空心沟道下方通孔与衬底接触区形成源极。
(三） 有益效果
从上述技术方案可以看出， 本发明具有以下有益效果：
1、本发明提出的具有 Air-gap特怔的垂直沟道型三维半导体存储器 件， 通过降低沟道结晶过程中的沟道应力、 减少背界面或者体晶格缺陷 密度等， 可以有效克服传统多晶硅沟道低载流子迁移率所带来的小开态 沟道电流的技术难题。
2、本发明提出的具有 Air-gap特怔的垂直沟道型三维半导体存储器 件， 可以提高垂直向存储串各个位置上沟道的厚度控制， 从而有益于提 高垂直向各存储单元存储性能的一致性和可靠性。
3、本发明提出的具有 Air-gap特怔的垂直沟道型三维半导体存储器 件， 其中的空心沟道可以通过控制沟道的沉积时间来形成不完全填充， 降低了原有实心沟道填充的难度， 同时可以放松对于深孔刻蚀角度的要 求， 有力的降低了三维存储器的制造难度和成本。
附图说明 图 1为常规的平面型闪存阵列向三维存储器的演化示意图； 图 2a至图 2c为传统垂直向三维存储器的俯视 （Top-View) 图及单 元结构； 其中， 图 2a为柱状环栅结构三维存储器的俯视图， 图 2b为图 2a中基本存储单元的结构， 图 2c为条状平面栅结构三维存储器的俯视 图；
图 3为在沿图 2a中 A-A'且垂直纸面方向柱状存储器阵列结构及其 不同位置存储单元结构图， 此处只给出阵列串未给出外围连线；
图 4a为本发明提出的采用 Air-gap概念的空心沟道的存储单元结 图 4b为本发明提出的具有图 4a所示的存储单元的三维闪存阵列结 构， 其中该三维闪存阵列结构是沿图 2a中 A-A'垂直纸面方向；
图 5A至图 5F为本发明沿图 2a中 B-B'且垂直纸面方向新存储结构 空心沟道的制备工艺流程的一个实例。
具体实施方式 为使本发明的目的、 技术方案和优点更加清楚明白， 以下结合具体 实施例， 并参照附图， 对本发明进一歩详细说明。
在图 1中给出了常规平面型闪存阵列向三维存储器的演化示意图。 传统上 NAND 型闪存器件通过缩小存储单元的尺寸来提高单位面积上 的存储单元数目完成存储容量的提升。 每个存储串有两个选择晶体管和 多个存储单元串连构成。 为了提高密度， 三维存储技术就是通过垂直层 叠多个存储单元获得垂直向存储串， 并把这些垂直存储串平行排列而形 成具有高密度的三维存储器。
图 2a至图 2c为传统垂直向三维存储器的 Top- View截面图及单元结 构示意图。 目前垂直沟道三维存储器是高密度闪存技术的研究热点， 其 中多晶硅沟道可以通过深孔或深槽刻蚀并填充来完成。 三星提出的 TCAT结构和东芝的 BiCS结构都是采用的如图 2a和图 2b中的柱状沟道 结构， 这种柱状沟道形成了垂直环状栅电极有益于控制擦写速度。 而从 提高提成密度出发， 条状垂直沟道类似于双栅结构， 通过控制不同的栅 电极可以在每一个片状沟道上实现多位存储。 图 3是以图 2a示出的柱状环栅垂直三维存储器为例，示出了在沿图 2a 中 A-A'且垂直纸面方向柱状存储器阵列结构及其不同位置存储单元 结构图， 此处只给出阵列串未给出外围连线。 可以看出， 由于在深孔刻 蚀时候很难获得刻蚀为 90度的深孔， 因此在随后的实心多晶硅沟道形 成过程中， 垂直串的顶部单元比底部单元具有更大的沟道直径， 这种差 异会引起擦写速度的变化， 同时在读写操作中沟道的耗尽状态不同也会 造成单元性能的不一致。 甚至于在从无定形硅向多晶硅转化过程中的体 积变化因为其实心结构造成更多的缺陷和更大的应力， 从而降低载流子 在沟道的迁移率。
本发明的主要思路是通过获得相同的多晶硅沟道厚度来提高存储 单元的一致性， 通过降低多晶硅沟道背界面缺陷对载流子的散射来提高 载流子的迁移率。 基于这一思路， 本发明将提出基于 Air-gap概念的空 心沟道结构并用于三维存储器。
图 4a给出了基于 Air-gap概念的存储单元结构， 图 4b给出了具有 该空心结构的三维存储器的垂直阵列结构。 这里， 沟道沉积过程中通过 控制沉积厚度可以自动实现存储单元沟道的空心化， 这种不完全的沟道 填充可以确保垂直存储串的存储单元都具有相同的多晶硅薄膜的厚度， 使得三维存储器的存储单元具有很好的一致性。 同时这种多晶硅薄膜通 过减薄厚度降低了沟道中晶粒间隙的体缺陷数目从而可以降低存储单 元间阈值电压的波动。 更为重要的是， 多晶硅的背界面可以通过后退火 处理等手段显著降低界面陷阱密度从而降低对载流子的散射， 从而提高 沟道载流子迁移率。 当然， 对于采用无定型硅薄膜沉积并随后退火来形 成多晶硅沟道的工艺方法来说， 空心结构的存在， 可以有效释放无定型 硅晶化时产生的应力， 沟道应力的改变同样可以提高沟道的迁移率。
基于图 4a及图 4b所示的采用 Air-gap概念的空心沟道的存储单元 结构以及具有该存储单元的三维闪存阵列结构， 本发明提供了一种垂直 沟道型三维半导体存储器件， 该三维半导体存储器件包括： 一衬底； 在 该衬底上依次交替淀积绝缘层和电极材料层形成的多层膜结构； 刻蚀该 多层膜结构至该衬底形成的多个通孔， 该通孔用以定义出沟道区域； 在 该多个通孔内壁依次淀积阻挡层、 存储层和隧穿层形成的多个栅堆栈； 在该多个栅堆栈的隧穿层表面淀积沟道材料而形成的多个空心沟道； 在 该空心沟道上方位线连接用接触孔接触区形成的漏级； 以及在该空心沟 道下方通孔与衬底接触区形成的源极。
其中， 该空心沟道是通过引入 Air-gap形成的空心柱状沟道、 空心 环状沟道或空心带状沟道。 该沟道材料可以采用多晶硅、 无定型硅、 锗 硅、 锗、 GaAs或 InGaAs等多种材料， 当沟道材料采用多晶硅材料时， 该空心沟道采用在该隧穿层表面直接淀积多晶硅薄膜的方式形成； 当沟 道材料采用无定形硅材料时， 该空心沟道采用在该隧穿层表面淀积无定 形硅薄膜并进行高温退火的方式形成。 同时， 还可以对该空心表面部分 进行不同方式的表面处理用于减少表面的悬挂键等缺陷态。
该栅堆栈可以是基于分立电荷存储的电荷俘获型存储器栅堆栈， 也 可以是基于连续存储媒质的浮栅存储器栅堆栈。 其中， 电荷俘获型存储 器栅堆栈采用隧穿层 /分立介质存储层 /阻挡层结构， 该分立介质存储层 由 SiN或高 K介质材料（如 HfO)构成。浮栅存储器栅堆栈采用隧穿层 /存储层 /阻挡层结构， 该存储层由多晶硅、 金属或者多晶硅与金属两者 的复合结构构成。
应该指出的是， 图 4a及图 4b中的空心状单元及阵列结构只是本发 明的一个简单示例。 本发明提出的思路将不仅限于我们在实例中所列出 的每个垂直存储串由两个选择晶体管（SSL和 GSL)和六个存储单元所 构成的串结构。 对于 NAND存储串来说， 是由多个存储单元以及 GSL 和 SSL晶体管共同构成的一个串，靠近 GSL的为位线引出端，靠近 SSL 的为接地端。基于这一思路， 新型沟道结构的设计可以通过引入 Air-gap 以形成空心柱状、 空心环状、 或者空心带状等任何空心沟道结构， 对于 垂直存储串来说， 该空心部分可以只是在 NAND存储串的存储单元区， 也可以包括存储串的选择管区域， 或者部分存储串沟道区域。 该空心沟 道的形成可以是采用多晶硅薄膜沉积的方式形成， 也可以通过采用无定 形硅沉积并进行高温退火的方式形成； 同时对于该空心表面部分可以进 行不同方式的表面处理 （如氮气中退火等） 用于减少表面的悬挂键等缺 陷态； 具有空心结构的垂直沟道材料将不限于多晶硅， 还可以是无定型 硅、 锗硅、 锗、 GaAs、 InGaAs等可以作为沟道材料的材料。
基于不同的空心沟道结构， 其垂直存储单元可以是采用垂直平面栅 结构、 垂直双栅结构或者垂直环栅结构； 由此类垂直单元构成的垂直型 NAND存储串的源漏区 （即 NAND串中的 SL和 BL接触区） 可以是采 用同类型掺杂 （同为 N型或者同为 P型掺杂）， 可以是采用不同类型的 掺杂 （比如源区 N型掺杂， 漏区 P型掺杂， 或者相反）， 也可以是异种 材料的源漏区 （比如 BL区域接触处采用与沟道不同的金属硅化物等材 料）； 同时此类存储单元的栅堆栈可以是基于分立电荷存储的电荷俘获 型存储器栅堆栈 （如隧穿层 /SiN等分立介质存储层 /阻挡层结构）， 也可 以是基于连续存储媒质的浮栅存储器栅堆栈 （如隧穿层 /多晶硅、 金属、 或者两者的复合结构构成的存储层 /阻挡层结构）。构成栅堆栈的隧穿层、 存储层和阻挡层可以全部位于刻蚀的深孔 /槽中； 可以不在深孔 /槽中， 只是在形成多晶硅沟道后采用 Gate-Last工艺在栅电极沉积前完成栅堆 栈沉积； 也可以是部分位于刻蚀深孔 /槽中， 比如通过在深孔 /槽多晶硅 沉积前完成隧穿层和采用 Gate-Last工艺在栅电极沉积前完成存储层和 阻挡层来共同实现栅堆栈的沉积。
另外，基于该概念的空心沟道结构既可以用于采用 gate-last工艺（如 BiCS结构、 p-BiCS结构、 SCP-NAND结构） 的多种垂直沟道型三维闪 存器件， 也可以用于采用 Gate-First工艺 （如 TCAT结构） 的多种垂直 沟道型三维闪存器件。
基于上述本发明提供的垂直沟道型三维半导体存储器件， 本发明还 提供了一种制备垂直沟道型三维半导体存储器件的方法， 该方法包括以 下歩骤：
歩骤 1 : 在衬底上依次交替淀积绝缘层和电极材料层形成多层膜结 歩骤 2: 刻蚀该多层膜结构至该衬底形成多个通孔， 该通孔用以定 义出沟道区域；
歩骤 3: 在该多个通孔内壁依次淀积阻挡层、 存储层和隧穿层形成 多个栅堆栈；
歩骤 4: 在该多个栅堆栈的隧穿层表面淀积沟道材料形成多个空心 沟道；
歩骤 5: 对该多个空心沟道进行表面处理， 以减少空心沟道表面的 缺陷态； 其中表面处理可以为在氮气中退火， 以减少空心沟道表面的悬 挂键。
歩骤 6: 在该空心沟道上方位线连接用接触孔接触区形成漏级。 歩骤 7: 在该空心沟道下方通孔与衬底接触区形成源极。
在实际应用中， 为了制备具有新结构的三维存储阵列， 可以采用多 种制备流程。 为了对于基于该新结构的存储器件的制备有一个直观的认 识，图 5A至图 5F以 gate-first工艺为例给出了实现空心沟道的一种实现 方式， 具体包括：
如图 5A所示， 进行 SiO/PolySi等具有绝缘层 /电极材料的多层膜沉 积， 从而完成垂直存储串的栅电极制备；
如图 5B所示， 通孔刻蚀， 完成沟道区域的定义；
如图 5C所示， 进行阻挡层 /存储层 /隧穿层的顺序沉积， 获得存储单 元的栅堆栈； 此处存储层可以是连续存储媒质或者分立介质；
如图 5D所示， 完成无定形硅薄层沉积， 通过不完全填充形成空心 结构；
如图 5E所示， 退火形成多晶硅沟道， 对空心表面进行处理减小缺 陷态；
如图 5F所示， 完成空心沟道的漏接触区的封口和漏结的形成； 最 后完成绝缘层介质淀积， 外围金属连线等后端工艺。
通过采用上述歩骤， 具有空心垂直沟道的三维存储阵列能够有效实 现。当然， 多晶硅沟道的实现也可以跳过图 5D和图 5E所示歩骤直接进 行薄膜多晶硅的不完全沉积来获得空心的多晶硅沟道。 对于基于该思路 的变形较多， 此处不再一一赘述。
由上述工艺流程可以看出， 由于采用了空心沟道， 即使深孔的刻蚀 角度不十分垂直， 但是通过控制沟道区薄膜的沉积时间也可以获得相同 厚度的多晶硅沟道薄膜， 所以降低了对于刻蚀工艺的难度； 另外， 该结 构也避免了原有实心沟道的高质量填充的难题。 因此其制备工艺相对简 单、 制造成本也可以得以降低， 便于工业应用和推广。
图 5中的工艺流程的示例中只示出了具有两个选择管和六个存储单 元的垂直阵列结构， 更多层存储单元堆栈结构也将被本发明所涵盖。
因此， 在常规垂直沟道型三维存储器中， 通过深孔刻蚀后定义沟道 区域后， 采用填充或者外延并辅助退火的方式形成柱状多晶硅沟道结 构。 在本发明中， 通过引入 Air-gap可以形成空心柱状、 空心环状或者 空心带状的多晶硅沟道。 所述具有 Air-gap特怔的垂直沟道的三维存储 器件通过降低沟道结晶过程中的沟道应力、 提高沟道的厚度一致性、 减 少背界面或者体晶格缺陷密度等特点可以有效克服传统多晶硅沟道低 载流子迁移率所带来的小的开态沟道电流的技术难题， 并有益于提高垂 直向各存储单元存储性能的一致性和可靠性， 同时有力的降低垂直沟道 的制造难度和成本。
另外， 本发明中空心 Air-gap概念的应用将不限于多晶硅沟道， 也 可以应用于三维交叉阵列型电阻转变类存储结构中垂直空心电极的形 成， 比如对于基于阻变存储概念的三维垂直 Cross-Bar型阻变存储器的 垂直电极也可以采用空心结构。
以上所述的具体实施例， 对本发明的目的、 技术方案和有益效果进 行了进一歩详细说明， 所应理解的是， 以上所述仅为本发明的具体实施 例而已， 并不用于限制本发明， 凡在本发明的精神和原则之内， 所做的 任何修改、 等同替换、 改进等， 均应包含在本发明的保护范围之内。

Claims

权利要求
1、 一种垂直沟道型三维半导体存储器件， 其特征在于， 包括： 一衬底；
在该衬底上依次交替淀积绝缘层和电极材料层形成的多层膜结构； 刻蚀该多层膜结构至该衬底形成的多个通孔， 该通孔用以定义出沟 道区域；
在该多个通孔内壁依次淀积阻挡层、 存储层和隧穿层形成的多个栅 堆栈；
在该多个栅堆栈的隧穿层表面淀积沟道材料而形成的多个空心沟 道；
在该空心沟道上方位线连接用接触孔接触区形成的漏级； 以及 在该空心沟道下方通孔与衬底接触区形成的源极。
2、 根据权利要求 1 所述的垂直沟道型三维半导体存储器件， 其特 征在于，所述空心沟道为空心柱状沟道、空心环状沟道或空心带状沟道。
3、 根据权利要求 1 所述的垂直沟道型三维半导体存储器件， 其特 征在于，所述沟道材料采用多晶硅、无定型硅、锗硅、锗、 GaAs或 lnGaAs。
4、 根据权利要求 3 所述的垂直沟道型三维半导体存储器件， 其特 征在于， 所述沟道材料为多晶硅时， 该空心沟道采用在该隧穿层表面直 接淀积多晶硅薄膜的方式形成。
5、 根据权利要求 3 所述的垂直沟道型三维半导体存储器件， 其特 征在于， 所述沟道材料为无定形硅时， 该空心沟道采用在该隧穿层表面 淀积无定形硅薄膜并进行高温退火的方式形成。
6、 根据权利要求 1 所述的垂直沟道型三维半导体存储器件， 其特 征在于， 所述栅堆栈是基于分立电荷存储的电荷俘获型存储器栅堆栈， 或者是基于连续存储媒质的浮栅存储器栅堆栈。
7、 根据权利要求 6 所述的垂直沟道型三维半导体存储器件， 其特 征在于， 所述电荷俘获型存储器栅堆栈采用隧穿层 /分立介质存储层 /阻 挡层结构。
8、 根据权利要求 7 所述的垂直沟道型三维半导体存储器件， 其特 征在于， 所述分立介质存储层由 SiN或高 K介质材料 HfO构成。
9、 根据权利要求 6 所述的垂直沟道型三维半导体存储器件， 其特 征在于， 所述浮栅存储器栅堆栈采用隧穿层 /存储层 /阻挡层结构。
10、 根据权利要求 9所述的垂直沟道型三维半导体存储器件， 其特 征在于， 所述存储层由多晶硅或金属构成， 或者由多晶硅与金属两者的 复合结构构成。
11、 一种制备权利要求 1至 10中任一项所述垂直沟道型三维半导 体存储器件的方法， 其特征在于， 包括：
在衬底上依次交替淀积绝缘层和电极材料层形成多层膜结构； 刻蚀该多层膜结构至该衬底形成多个通孔， 该通孔用以定义出沟道 区域；
在该多个通孔内壁依次淀积阻挡层、 存储层和隧穿层形成多个栅堆 栈；
在该多个栅堆栈的隧穿层表面淀积沟道材料形成多个空心沟道； 在该空心沟道上方位线连接用接触孔接触区形成漏级； 以及 在该空心沟道下方通孔与衬底接触区形成源极。
12、 根据权利要求 11 所述的制备垂直沟道型三维半导体存储器件 的方法， 其特征在于， 所述空心沟道为空心柱状沟道、 空心环状沟道或 空心带状沟道。
13、 根据权利要求 11 所述的制备垂直沟道型三维半导体存储器件 的方法， 其特征在于， 所述沟道材料采用多晶硅、 无定型硅、 锗硅、 锗、 GaAs或 lnGaAs。
14、 根据权利要求 13 所述的制备垂直沟道型三维半导体存储器件 的方法， 其特征在于， 所述沟道材料为多晶硅时， 该空心沟道采用在该 隧穿层表面直接淀积多晶硅薄膜的方式形成。
15、 根据权利要求 13 所述的制备垂直沟道型三维半导体存储器件 的方法， 其特征在于， 所述沟道材料为无定形硅时， 该空心沟道采用在 该隧穿层表面淀积无定形硅薄膜并进行高温退火的方式形成。
16、 根据权利要求 11 所述的制备垂直沟道型三维半导体存储器件 的方法， 其特征在于， 所述栅堆栈是基于分立电荷存储的电荷俘获型存 储器栅堆栈， 或者是基于连续存储媒质的浮栅存储器栅堆栈。
17、 根据权利要求 16所述的制备垂直沟道型三维半导体存储器件 的方法， 其特征在于， 所述电荷俘获型存储器栅堆栈采用隧穿层 /分立介 质存储层 /阻挡层结构。
18、 根据权利要求 17 所述的制备垂直沟道型三维半导体存储器件 的方法， 其特征在于， 所述分立介质存储层由 SiN或高 K介质材料 HfO 构成。
19、 根据权利要求 16所述的制备垂直沟道型三维半导体存储器件 的方法， 其特征在于， 所述浮栅存储器栅堆栈采用隧穿层 /存储层 /阻挡 层结构。
20、 根据权利要求 19所述的制备垂直沟道型三维半导体存储器件 的方法， 其特征在于， 所述存储层由多晶硅或金属构成， 或者由多晶硅 与金属两者的复合结构构成。
21、 根据权利要求 11 所述的制备垂直沟道型三维半导体存储器件 的方法， 其特征在于， 所述形成多个空心沟道之后， 还包括： 对该多个 空心沟道进行表面处理， 以减少空心沟道表面的缺陷态。
22、 根据权利要求 21 所述的制备垂直沟道型三维半导体存储器件 的方法， 其特征在于， 所述表面处理为在氮气中退火， 以减少空心沟道 表面的悬挂键。
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