WO2014084667A1 - Group iii nitride semiconductor laminate - Google Patents

Abstract

The present disclosure relates to a group III nitride semiconductor laminate comprising: an m-plane substrate; a growth prevention region which is formed on the m-plane substrate and which has a plurality of windows for the growth of group III nitride semiconductor; a seed layer formed on the m-plane substrate at least in the region of the plurality of windows; and a group III nitride semiconductor layer which is grown from the seed layer and deployed in an a-axis direction and c-axis direction and coalesced, wherein the group III nitride semiconductor layer cooperates with the group III nitride semiconductor that is deployed in the c-axis direction in a single window so as to be deployed over the growth prevention region and deployed in a-axis direction in the neighboring window, so as to form a cavity.

Description

Group III nitride semiconductor laminate

This disclosure relates generally to Group III nitride semiconductor laminates, and more particularly to Group III nitride semiconductor laminates having cavities.

Here, the group III nitride semiconductor means a compound semiconductor layer made of Al (x) Ga (y) In (1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). The light emitting device may be used for manufacturing a light emitting device such as a light emitting diode and a light receiving device such as a photodiode, and may be applied to various fields such as the manufacture of diodes, transistors, and electrical devices in addition to optical devices.

This section provides background information related to the present disclosure which is not necessarily prior art.

1 is a view showing an example of a group III nitride semiconductor light emitting device shown in US Patent Publication No. 2003-0057444, in which the group III nitride semiconductor light emitting device is grown on a substrate 100 and the substrate 100. The group nitride semiconductor layer 300 includes an active layer 400 grown on the n-type group III nitride semiconductor layer 300 and a p-type group III nitride semiconductor layer 500 grown on the active layer 400. The protrusions 110 are formed on the substrate 100, and the protrusions 110 improve the grain quality of the group III nitride semiconductor layers 300, 400, and 500 grown on the substrate 100, and at the active layer 400. It functions as a scattering surface to improve the efficiency of emitting the generated light to the outside of the light emitting device.

2 and 3 are diagrams illustrating an example of the group III nitride semiconductor light emitting device shown in International Patent Publication No. 2010-110608, wherein the group III nitride semiconductor light emitting device is grown on the substrate 100 and the substrate 100. The n-type group III nitride semiconductor layer 300, the active layer 400 grown on the n-type group III nitride semiconductor layer 300, and the p-type group III nitride semiconductor layer 500 grown on the active layer 400 are included. A protrusion 120 is formed on the substrate 100, and a cavity 130 (cavity) is formed by growing the group III nitride semiconductor layers 300, 400, and 500 on the upper surface of the protrusion 120. By using the cavity 130 (the refractive index of air is 1), the scattering surface between the group III nitride semiconductor layers 300, 400, 500 and the substrate 100 (approximately 1.7 in the case of the sapphire substrate) is increased. It's a skill. However, as shown in FIG. 3, the group III nitride semiconductor layers 300, 400, and 500 actually grown on the protrusions 120, unlike the expectation, merely form the scattering surface 131 having a very small curvature. Meanwhile, in addition to using the cavity 130 thus formed as a scattering surface, the substrate 100 and the group III nitride semiconductor layers 300, 400, and 500 are used as a channel into which an etchant is input during separation by wet etching, or by laser separation. In the case of lift-off, the separation surface by the laser is reduced, and the impact caused by the group III nitride semiconductor layers 300, 400, and 500 can be reduced by using it as a movement path of the gas generated during the laser separation.

4 is a diagram illustrating an example of a group III nitride semiconductor laminate disclosed in US Patent Publication No. 2005-0156175, wherein the group III nitride semiconductor laminate includes a c-plane sapphire substrate 100 and a c-plane sapphire substrate 100. A Group III nitride semiconductor template 210 previously formed thereon, a growth prevention film 150 made of SiO ₂ formed on the Group III nitride semiconductor template 210, and a Group III nitride semiconductor layer 310 selectively grown thereon. ). The group III nitride semiconductor template 210 is conventionally formed by a method of growing a group III nitride semiconductor on the c-plane sapphire substrate 100. That is, a seed layer is formed at a growth temperature of about 550 ° C. and a hydrogen atmosphere, and then formed to a thickness of 1 to 3 μm by a method of growing GaN at a growth temperature of 1050 ° C. Reference numeral 180 denotes defects, and development of defects under the growth prevention film 150 is blocked, resulting in an improvement in crystallinity as a whole. However, this method requires the growth of the group III nitride semiconductor template 210 before the formation of the growth barrier film 150, and the lattice constant and thermal expansion coefficient between the group III nitride semiconductor template 210 and the c-plane sapphire substrate 100. This results in substrate bending due to the difference. This substrate warpage then interferes with the photolithography process required to form the growth barrier film 150, and is typically on the c-side sapphire substrate 100 having diameters of 2 inches, 4 inches, 6 inches, and 8 inches. There is a problem that makes it difficult to uniformly proceed the process. This attempt on m-plane substrates has been described in P. de Mierry et al., Improved semipolar (11-22) GaN quality using asymmetric lateral epitaxy, Applied Physics Letters 94, 191903 (2009).

5 is a view showing another example of the group III nitride semiconductor laminate disclosed in US Patent Publication No. 2005-0156175, wherein the group III nitride semiconductor laminate is a c-plane sapphire substrate 100, a c-plane sapphire substrate 100 A growth prevention film 150 made of SiO ₂ formed on the substrate), and a group III nitride semiconductor layer 310 selectively grown thereon. Since the group III nitride semiconductor layer 310 grown at about 1050 ° C. cannot be grown on the c-plane sapphire substrate 100 and the growth preventing film 150, the group III nitride semiconductor layer 310 is 550 ° C. as in the group III nitride semiconductor template 210 of FIG. 4. At the growth temperature of the first seed layer 200 (commonly referred to as buffer layer) must be formed. However, if the seed layer 200 is formed at a temperature much lower than the growth temperature of the Group III nitride semiconductor (in the case of GaN, in general, 1000 ° C. or more), the material forming the seed layer 200 may also be formed on the growth barrier 150. Mainly, GaN) polycrystals are formed, which makes it difficult to form the group III nitride semiconductor layer 310 having excellent crystallinity.

This is described later in the section titled 'Details of the Invention.'

This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all, provided that this is a summary of the disclosure. of its features).

According to one aspect of the present disclosure (According to one aspect of the present disclosure), an m-plane substrate; a growth prevention region on the m-plane substrate and having a plurality of windows for growth of the group III nitride semiconductor; A seed layer formed on the m-plane substrate in an area corresponding to at least a plurality of windows; And a group III nitride semiconductor layer that is grown from the seed layer and developed in the a-axis direction and the c-axis direction to coalesce, wherein the group III nitride semiconductor that is developed in one window in the c-axis direction is over the growth prevention region. A group III nitride semiconductor laminate is provided, including a group III nitride semiconductor layer that is formed to form a cavity with a group III nitride semiconductor that is developed in an a-axis direction in a neighboring window.

This is described later in the section titled 'Details of the Invention.'

1 is a view showing an example of a group III nitride semiconductor light emitting device shown in US Patent Publication No. 2003-0057444;

2 and 3 are views showing an example of a group III nitride semiconductor light emitting device shown in International Publication No. 2010-110608;

4 is a view showing an example of a group III nitride semiconductor laminate shown in US Patent Publication No. 2005-0156175,

5 is a view showing still another example of the group III nitride semiconductor laminate shown in US Patent Publication No. 2005-0156175,

6 is a view showing an example of a group III nitride semiconductor laminate according to the present disclosure;

7 is a view showing an example of a method of growing a group III nitride semiconductor on the seed layer in accordance with the present disclosure,

8 illustrates another example of a method for growing a group III nitride semiconductor over a seed layer in accordance with the present disclosure;

9 shows another example of the group III nitride semiconductor laminate according to the present disclosure;

10 is a view showing still another example of the group III nitride semiconductor laminate according to the present disclosure;

11 is a view showing still another example of the group III nitride semiconductor laminate according to the present disclosure;

12 is a cross-sectional image of the group III nitride semiconductor laminate of FIG. 6 grown in the structure of FIG.

FIG. 13 is a cross-sectional image of the group III nitride semiconductor laminate of FIG. 6 grown with the structure of FIG. 8, FIG.

14 is a photograph showing the seed layer grown at a low temperature and the seed layer grown in a hydrogen atmosphere,

15 is a photograph showing a seed layer grown in accordance with the present disclosure;

16 and 17 illustrate an example of a method for growing a group III nitride semiconductor according to the present disclosure.

The present disclosure will now be described in detail with reference to the accompanying drawing (s).

FIG. 6 is a diagram illustrating an example of a group III nitride semiconductor laminate according to the present disclosure, wherein the group III nitride semiconductor laminate is positioned on an m-plane substrate 10 and an m-plane substrate 10. A growth prevention film 15 having a plurality of windows 16a and 16b for growth, a seed layer 20 formed on the m surface substrate 10 in a region corresponding to the plurality of windows 16a and 16b, and a seed A Group III nitride semiconductor layer 31 which is grown from the layer 20 and developed in the a-axis direction and the c-axis direction and coalesces, and is developed in the c-axis direction in one window 16a. A group III nitride semiconductor layer 31 which forms a cavity 13 with the group III nitride semiconductor 31b that is developed above the growth preventing film 15 and extends in the a-axis direction in the adjacent window 16b. It includes.

A representative material of the m-plane substrate 10 is hexagonal sapphire. When the c plane is (0001), the m plane is (1-100) and the a plane is (11-20). Here, the a axis is defined as an axis perpendicular to the a plane, and the c axis is defined as an axis perpendicular to the c plane. Preferably an accurate m-plane substrate 10 is used, but a substrate cut at an angle slightly off from the m-plane can be used, here collectively referred to as m-plane substrate 10. In addition to sapphire, Group III nitride semiconductors (eg, GaN, InGaN, AlGaN, InN, AlN, InGaAlN) can be grown, and m-plane materials can be used. The group III nitride semiconductor may be doped with a material such as Si and Mg.

SiO ₂ is mainly used as the growth prevention film 15, but SiN _x and TiO ₂ may be used, and any material may be used as long as it is a material for preventing the growth of the group III nitride semiconductor. It is also possible to form the growth preventing film 15 in a DBR structure of SiO ₂ / TiO ₂ . For example, a SiO ₂ film of 100 nm to 300 nm thickness may be used. The growth prevention film 15 may be formed as a stripe in the a plane direction of the m surface sapphire substrate, and the gap between the growth prevention film 15 and the window 16a may be appropriately adjusted. The present inventors experimented using the mask (unit is um) of 17: 1, 16: 2, 13: 1, 14: 2, 7: 3, 6: 2 for the space | interval of the growth prevention film 15 and the window 16a. Even in the case of 17 um where the growth prevention film 15 is the widest, the planarization of the group III nitride semiconductor layer 31 (GaN) is performed at 7 μm or less (that is, the height of the cavity 13 is 7 μm or less). . Therefore, according to the group III nitride semiconductor growth method according to the present disclosure, the group III nitride semiconductor layer 31 can be planarized before an excessive height (for example, 10 μm).

The seed layer 20 (eg, GaN) is formed at a high temperature of 650 ° C. or higher, preferably 800 ° C. or higher, unlike a GaN buffer layer formed at about 500 ° C. (eg, 550 ° C.). Generally not well formed. It is possible to form a better seed layer 20 at a temperature above 800 ° C., but to grow at a temperature above 900 ° C. for rapid transfer to growth conditions for the Group III nitride semiconductor layer 31 grown at a higher temperature. In this regard, it is desirable to grow at a temperature of 900 ℃ or more. As the carrier gas, N ₂ is used instead of H _{2 which} is conventionally used. As pointed out above, by using the same method as the conventional buffer layer, polycrystals are formed on the growth prevention film 15, which makes it difficult to obtain the Group 3 nitride semiconductor layer 31 having good crystallinity. Therefore, it can be seen that the seed layer 20 of the present embodiment differs from the concept of formation of the buffer layer used for the growth of the group III nitride semiconductor layer. FIG. 14 is a photograph showing seed layers grown at a low temperature and seed layers grown at a hydrogen atmosphere. When grown at a low temperature as shown in (a), the polycrystals cover the growth prevention layer, and (b) When grown in a hydrogen atmosphere at high temperatures as shown in FIG. 1, the growth is poor and some very large nuclei are formed. 15 is a photograph showing a seed layer grown according to the present disclosure, and it can be seen that the seed layer 20 is formed only in the window 16a. Since the growth of the seed layer 20 is performed in the narrow window 16a region, the growth of the seed layer 20 may be formed too quickly in the window 16a using growth conditions without the growth barrier 15. Therefore, it is necessary to adjust the growth rate in accordance with the size of the window 16a. The seed layer 20 is a compound semiconductor of Al (x) Ga (y) In (1-xy) N (0 = x = 1, 0 = y = 1, 0 = x + y = 1), preferably Made of GaN. In FIG. 15, the growth conditions of the seed layer 20 were as follows. After m-sapphire substrates were organically cleaned, SiO ₂ was deposited by PECVD, and then grown using MOCVD. The atmosphere gas in the MOCVD reactor was changed to N ₂ , and then injected into the reactor with a NH ₃ flow rate of 8000 sccm (Standard Cubic Cm per Min.) From 450 ° C., and the temperature was increased to 1050 ° C. This was for the nitriding treatment of the sapphire surface. GaN nuclei were grown at a rate of 0.5 nm / sec using TMGa at 1050 ° C. At this time, the pressure of the reactor was 100 mbar.

FIG. 7 is a view showing an example of a method for growing a group III nitride semiconductor on a seed layer according to the present disclosure, wherein the group III nitride semiconductor 31a and the group III nitride semiconductor 31b are joined to a junction. Explain the example. As shown in the left side of FIG. 7, the group III nitride semiconductor 31e grown on the seed layer 20 of the m-plane substrate 10 is grown clockwise, having the c plane, the a plane, and the -c plane. Can be. Depending on the growth conditions, either side can be made wider or one side can be omitted, but the lateral development in the a-axis direction is basically suppressed relative to the lateral development in the c-axis direction. And as shown in the middle figure, crystal defects 32 (exactly stacking faults) develop in the a-axis direction. Therefore, the crystal is developed in the a-axis direction until the point 33 at which the group III nitride semiconductor 31a grown in the window 16a and the group III nitride semiconductor 31b grown in the adjacent window 16b is joined is determined. The region n in which the defects 32 are formed is developed in the c-axis direction and formed narrower than the region m in which the crystal defects 32 are not formed, so that the crystals in the entire group III nitride semiconductors 31a and 31b are formed. The defects can be reduced. For the bonding, the a surface of the group III nitride semiconductors 31a and 31b, which are developed in the a-axis direction, is gradually reduced, and optimum point bonding is achieved. Further, the group III nitride semiconductor developed in the a-axis direction is reduced by reducing the c plane of the group III nitride semiconductor 31a developed in the c-axis direction up to the point 33 to be joined, so that the point bonding is optimally performed. It helps to join or planarize the 31- nitride semiconductor 31a and 31b which are developed in the c-axis direction. At the point 33 to be bonded, when the -c surface of the group III nitride semiconductor 31b and the c surface of the group III nitride semiconductor 31a meet, the bonding thereof is not easy or is not bonded, and growth is performed in parallel. . Preferably, the group III nitride semiconductors 31a and 31b have a growth prevention region because the lateral growth development of the group III nitride semiconductor developed in the c-axis direction is faster than the lateral growth development of the group III nitride semiconductor developed in the a-axis direction. The growth-developed sub-group III nitride semiconductor chunks 31f and 31g and / or both the a-plane and the c-plane are preliminarily formed and then grown. In the case of making an inverted trapezoidal group III nitride semiconductor from the beginning of growth, since the height of the semiconductor can be too high up to the point 33 to be joined, the sub group III nitride semiconductor previously developed on the growth prevention film 15. It is good to make a mass (31f, 31g). In addition, since it is not easy to join group III nitride semiconductors 31a and 31b in an inverted trapezoid, it is preferable to make subgroup III nitride semiconductor agglomerates 31f and 31g in advance as a preliminary form for forming such a form. As described above, according to the method for growing a group III nitride semiconductor according to the present disclosure, even when the width of the growth prevention film 15 and the window 16a is set to 17: 1, the group III nitride semiconductor layer 31 is thick. Coalescence may be performed at 7 μm or less, where subgroup III nitride semiconductor agglomerates 31f and 31g are one useful tool for achieving this. After growing the seed layer 20, the atmosphere gas is changed to hydrogen. Subsequently, the subgroup III nitride semiconductor agglomerates 31f and 31g of 500 nm to 1300 nm are grown at a rate of 4000 sccm, NH ₃ at 100 mbar, temperature at 1050 ° C., and growth rate at 0.6 nm / sec. Thereafter, the temperature was lowered to 920 ° C., the pressure was 250 mbar, and NH ₃ was grown to 12,000 sccm. For example, by growing the subgroup III nitride semiconductor agglomerates 31f and 31g at 500 nm, a structure as shown in FIG. 7 is formed, and the crystal defect 32 is formed by allowing the region n to have only about 5% of the entire surface. Can be significantly reduced. Further, by growing the sub-group III nitride semiconductor agglomerates 31f and 31g by 1300 nm, a structure as shown in FIG. 8 to be described later is formed, and the crystal defects 32 can be prevented from penetrating the surface. Comparing the growth conditions of the two layers, when the subgroup III nitride semiconductor chunks 31f and 31g are grown at relatively low pressure and high temperature, the group III nitride after the subgroup III nitride semiconductor chunks 31f and 31g grow. In the case of the semiconductors 31a and 31b, the growth was relatively less sensitive to temperature.

8 is a view showing another example of a method for growing a group III nitride semiconductor on a seed layer according to the present disclosure, wherein the group III nitride semiconductor 31a and the group III nitride semiconductor 31b are different from each other until the junction. Explain the example. The crystal defect 32 of the group III nitride semiconductor 31b developed in the a-axis direction is blocked by the group III nitride semiconductor 31a. Similarly, by reducing the c plane of the group III nitride semiconductor 31a developed in the c-axis direction until the point at which the bonding is completed, the point 3 is developed in the a-axis direction by optimum point bonding. The bonding or planarization of the group nitride semiconductor 31a and the group III nitride semiconductor 31a developed in the c-axis direction is assisted, and the development of the defect 32 is prevented.

9 is a view illustrating another example of the group III nitride semiconductor laminate according to the present disclosure. Unlike the group III nitride semiconductor laminate illustrated in FIG. 6, the seed layer 20 includes the growth prevention layer 15 and the m surface substrate. It is located between 10. That is, the seed layer 20 is first formed before the growth barrier 15 is formed. In the case of forming the semiconductor layer first, there may be a problem pointed out in relation to FIG. 4, but by limiting the height of the seed layer 20, it is possible to solve this problem. In the case of this embodiment, the seed layer 20 may be formed of a conventional buffer layer.

FIG. 10 is a view showing another example of the group III nitride semiconductor laminate according to the present disclosure, and unlike the group III nitride semiconductor laminate shown in FIG. 6, prior to the growth of the group III nitride semiconductor 31, a growth prevention film (15) is removed. Therefore, the region 15a of the m surface substrate 10 on which the seed layer 20 is not formed serves as a growth prevention region. Since there is no seed layer 20 in the region 15a, growth of the group III nitride semiconductor layer 31 does not occur. Therefore, the group III nitride semiconductor layer 31 is grown from the seed layer 20 as in FIG. That is, the group III nitride semiconductor 31a that is developed in the c-axis direction in the window 16a is developed above the region 15a, and the group III nitride semiconductor 31b that is developed in the a-axis direction in the adjacent window 16b. (13; Cavity) grows. Prior to the growth of the group III nitride semiconductor layer 31, the growth prevention film 15 is removed, so that even when polycrystals are formed in the formation process of the seed layer 20 on the growth prevention film 15, the group III nitride semiconductor is not problematic. It is possible to grow the layer 31.

FIG. 11 is a view showing another example of the group III nitride semiconductor laminate according to the present disclosure, wherein the group III nitride semiconductor laminate has an additional growth prevention film 17, and has a cavity (on the additional growth prevention film 17). 13) is formed. The growth of the group III nitride semiconductor 31c is stopped on the seed layer 20, and an additional growth prevention layer 17 is formed so that the surface 31d of the group III nitride semiconductor 31c developed in the c-axis direction is exposed again. Thereafter, the group III nitride semiconductor 31a and the group III nitride semiconductor 31b are grown from the surfaces 31d and 31d to form the cavity 13. As described above and later, the region where the Group III nitride semiconductor 31c is developed in the c-axis direction on the growth prevention film 15 is a region where there are almost no defects (see FIG. 12), and therefore the Group III nitride semiconductor layer formed thereon ( The crystal defect in 31 can be greatly reduced.

12 is a cross-sectional image of the group III nitride semiconductor laminate of FIG. 6 grown in the structure of FIG. 8, the right side is a Scanning Transmission Electronic Microscope (STEM) image, and the left side is a Transmission Electronic Microscope (TEM) image. In the STEM image, it can be seen that the defect developed in the group III nitride semiconductor 31b is blocked by the group III nitride semiconductor 31a based on the bonding surface A, while the group III nitride semiconductor 31a, In other words, it can be seen that the Group III nitride semiconductor developed in the c-axis direction has almost no crystal defects. This property can be used for growth of the group III nitride semiconductor laminate shown in FIG. Through the TEM image, the blocking of defects can be seen better.

FIG. 13 is a cross-sectional image of the group III nitride semiconductor laminate of FIG. 6 grown in the structure of FIG. 8, (a) is a cathode luminescence (CL) image, (b) is a scanning electron microscope (SEM) image, and c) is an optical microscope image. In the CL image, what appears to be a groove tilted upwards is a defect, and you can see that it no longer develops. The cavity is well shown in the SEM image and is formed across the substrate. What appears to be a defect in the upper right corner of the cavity is scratching while cutting the cross section. In the light microscope image, the bright side is the cavity, and the surface is clean so that the inside of the group III nitride semiconductor layer can be seen.

16 and 17 illustrate an example of a method for growing a group III nitride semiconductor according to the present disclosure. When the group III nitride semiconductor 311 is referenced, the group III nitride semiconductor 312 has a plane a. The growth is possible by making the growth rates in the direction and c plane direction similar, and making these growth rates relatively faster than the growth rates in the (11-22) plane direction. The group III nitride semiconductor 313 can be grown by adjusting the growth rate in the order of (11-22) plane direction> c plane direction> a plane direction. The group III nitride semiconductor 314 can be grown by controlling the growth rate in the order of (11-22) plane direction> a plane direction> c plane direction. The group III nitride semiconductor 315 adjusts the growth rate in the order of c plane direction> (11-22) plane direction> a plane direction, but increases the growth rate in the c plane direction than the growth rate in the (11-22) plane direction. You can grow by controlling it slightly faster The group III nitride semiconductor 316 is controlled in the order of c plane direction> a plane direction> (11-22) plane direction, but growth is possible by controlling the growth rate in the c plane direction slightly faster than the growth rate in the a plane direction. . FIG. 17 shows a process of incorporating a group III nitride semiconductor 312, a group III nitride semiconductor 315, and a group III nitride semiconductor 316 having a (11-22) plane which is easy to planarize. In the case of 315, the c surface remains after the coalescence, and therefore, it can be seen that the group III nitride semiconductor 312 and the group III nitride semiconductor 316 can be planarized at a low height. Further, by forming the group III nitride semiconductor 312 and then growing the group III nitride semiconductor 315, that is, forming the region n shown in FIG. 7 to be narrower than the region m, and then It is also possible to block (n).

According to one group III nitride semiconductor laminate according to the present disclosure, it is possible to form a group III nitride semiconductor laminate having a cavity. When a light emitting diode is made of a group III nitride semiconductor laminate, this cavity can function as a scattering surface for scattering light. By forming the cavity in the form of an elongated channel, the substrate can be easily separated from the group III nitride semiconductor through wet etching or using a laser. In particular, in the case of constituting the group III nitride semiconductor laminate as shown in FIG. 10, since the substrate and the group III nitride semiconductor are mostly separated from each other, separation can be performed more easily. Also in the case of constituting a group III nitride semiconductor laminate as in the embodiment of FIG. 6, after the growth prevention film is removed by wet etching, separation can be easily performed similarly. In addition, since the substrate is separated and exposed to the (11-22) surface, the surface is wet etched (wet etching) well, so that it is easier to make a rough surface than the c-plane vertical structure LED.

Further, according to another group III nitride semiconductor laminate according to the present disclosure, it is possible to grow a group III nitride semiconductor having excellent crystallinity on the m-plane substrate.

In the present disclosure, the formation of a seed layer, the formation of sub-group III nitride semiconductor mass, the formation of a group III nitride semiconductor, the incorporation of a group III nitride semiconductor, the formation of a cavity, a method of reducing crystal defects, a method of planarization at a low height Should be understood to individually form the spirit of the present disclosure. That is, when someone implements the seed layer in a different way than the method of forming the seed layer according to the present disclosure, other technical ideas according to the present disclosure may be combined with this other seed layer individually and / or in combination. It will be understood by those skilled in the art. In this regard, the present disclosure relates to the following.

(1) A method of forming a seed layer on an m surface substrate on which a growth prevention film is formed, and a group III nitride semiconductor laminate comprising the same

(2) A method of incorporating or planarizing a group III nitride semiconductor layer on an m surface substrate having a growth prevention film formed thereon, and a group III nitride semiconductor laminate using the same.

(3) A method of growing a group III nitride semiconductor having reduced crystal defects on an m surface substrate having a growth prevention film formed thereon, and a group III nitride semiconductor laminate using the same.

(4) A method of growing a group III nitride semiconductor with a cavity on an m-plane substrate on which a growth prevention film is formed, and a group III nitride semiconductor laminate using the same, in particular, having an excessive thickness until forming a cavity, until planarization Unshaven and / or cavities with reduced crystal defects.

(5) Combination of the above method and laminate

(6) An element using the method, the laminate, or a combination thereof. In particular, semiconductor devices using pn junctions (e.g. vertical structure LEDs, semiconductor devices described in the prior art mentioned in connection with FIGS.

Claims (13)

1. m surface substrate;

   a growth prevention region on the m-plane substrate and having a plurality of windows for growth of the group III nitride semiconductor;

   A seed layer formed on the m-plane substrate in an area corresponding to at least a plurality of windows; And,

   A group III nitride semiconductor layer that is grown from the seed layer and that is coalesced in the a-axis direction and the c-axis direction, wherein the group III nitride semiconductor developed in the c-axis direction in one window is expanded over the growth prevention region; A group III nitride semiconductor laminate comprising a; group III nitride semiconductor layer forming a cavity with a group III nitride semiconductor that extends in an a-axis direction from a neighboring window.
2. The method according to claim 1,

   A group III nitride semiconductor laminate, wherein the growth prevention film is provided in the growth prevention region.
3. The method according to claim 2,

   A group III nitride semiconductor laminate, wherein the seed layer is located between the growth prevention region and the m-plane substrate.
4. The method according to claim 1,

   The growth prevention region is a group III nitride semiconductor laminate, characterized in that the m-plane substrate region without a seed layer formed.
5. The method according to claim 1,

   An additional growth barrier layer positioned on the plurality of windows;

   A cavity is formed on an additional growth preventing film, Group III nitride semiconductor laminate.
6. The method according to claim 1,

   The a surface of the group III nitride semiconductor developed in the a-axis direction is reduced to coalescence. The group III nitride semiconductor laminate.
7. The method according to claim 1,

   A group III nitride semiconductor laminate, wherein defects of the group III nitride semiconductor developed in the a-axis direction are blocked by the group III nitride semiconductor developed in the c-axis direction.
8. The method according to claim 1,

   The c plane of the group III nitride semiconductor developed in the c-axis direction is reduced to coalescence.
9. The method according to claim 6,

   The c plane of the group III nitride semiconductor developed in the c-axis direction is reduced to coalescence.
10. The method according to claim 7,

    The c plane of the group III nitride semiconductor developed in the c-axis direction is reduced to coalescence.
11. The method according to any one of claims 1 to 10,

    The group III nitride semiconductors grown in one window and the group III nitride semiconductors grown in a neighboring window each include a group III nitride semiconductor in which the lateral growth development of the group III nitride semiconductors developed in the c-axis direction is developed in the a-axis direction. A group III nitride semiconductor laminate comprising a sub-group III nitride semiconductor mass that is grown and developed over a growth prevention region faster than the lateral growth development of.
12. The method according to claim 1,

    A group III nitride semiconductor laminate, wherein the m-plane substrate is made of sapphire.
13. The method according to claim 9,

    The group III nitride semiconductor laminate according to claim 1, wherein defects of the group III nitride semiconductor developed in the a-axis direction are blocked by the group III nitride semiconductor developed in the c-axis direction.

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