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WO2014076797A1 - Variable output amplifier - Google Patents

Variable output amplifier Download PDF

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Publication number
WO2014076797A1
WO2014076797A1 PCT/JP2012/079656 JP2012079656W WO2014076797A1 WO 2014076797 A1 WO2014076797 A1 WO 2014076797A1 JP 2012079656 W JP2012079656 W JP 2012079656W WO 2014076797 A1 WO2014076797 A1 WO 2014076797A1
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WO
WIPO (PCT)
Prior art keywords
variable
transistor
output amplifier
transistors
matching circuit
Prior art date
Application number
PCT/JP2012/079656
Other languages
French (fr)
Japanese (ja)
Inventor
堀口　健一
勝也 嘉藤
正和 廣部
直子 新田
森　一富
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2012/079656 priority Critical patent/WO2014076797A1/en
Priority to TW102104152A priority patent/TW201419751A/en
Publication of WO2014076797A1 publication Critical patent/WO2014076797A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/226—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with junction-FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics

Definitions

  • the present invention relates to a variable output amplifier applied to a mobile phone system or the like.
  • FIG. 1 is a block diagram showing a conventional amplifier.
  • 1 and 2 are RF input terminals
  • 3 and 4 are amplifiers
  • 5 and 6 are RF output terminals
  • 7 and 8 are transistors
  • 9 to 12 are matching circuits.
  • a dedicated amplifier is prepared for each communication mode such as W-CDMA and GSM (registered trademark / hereinafter, omitted), or for each frequency band, and an RF signal is amplified.
  • the RF signal A input from the RF input terminal 1 is amplified by the amplifier 3 and output from the RF output terminal 5.
  • the RF signal B input from the RF input terminal 2 is amplified by the amplifier 4 and output from the RF output terminal 6.
  • the transmission power from the terminal and the gain of the terminal are different. Further, since the devices constituting the amplifier have frequency characteristics, the saturation output and gain of the amplifier change when the frequency changes. For this reason, the conventional amplifier requires a dedicated amplifier for each transmission power, communication mode, or frequency, and there is a problem that the module size of the amplifier increases.
  • the present invention has been made to solve the above-described problems, and an object thereof is to obtain a miniaturized variable output amplifier.
  • a variable output amplifier includes a plurality of first transistors connected in parallel, a variable matching circuit that is connected to a subsequent stage of the plurality of first transistors and makes impedance variable, and output power of the variable output amplifier And a control circuit for controlling the impedance of the variable matching circuit as well as controlling the number of parallel combinations of the first transistors that amplify the high-frequency signal.
  • the number of parallel composites of the first transistors that amplify the high-frequency signal is controlled according to the magnitude of the output power of the variable output amplifier, and the impedance of the variable matching circuit is controlled so that after amplification. Different output power can be obtained. For this reason, there is an effect that the variable output amplifier can be reduced in size as compared with the conventional method in which a dedicated amplifier is used depending on the magnitude of the output power.
  • FIG. 1 is a configuration diagram illustrating a variable output amplifier according to a first embodiment of the present invention. It is a block diagram which shows the variable output amplifier by Embodiment 2 of this invention.
  • FIG. FIG. 2 is a block diagram showing a variable output amplifier according to the first embodiment of the present invention.
  • 21 is an RF input terminal
  • 22 is a matching circuit
  • 23 and 24 are grounded source transistors (second transistors)
  • 25 and 26 are grounded gate transistors (first transistors)
  • 27 is an output combining point
  • 28 is A matching circuit with a switch (variable matching circuit)
  • 29 is an RF output terminal
  • 30 is a bias control circuit (control circuit).
  • Reference numerals 31 to 34 are DC blocking capacitors.
  • Common source transistors 23 and 24 and common gate transistors 25 and 26 are composed of FET (Field Effect Transistor).
  • the common source transistors 23 and 24 provided in front of the common gate transistors 25 and 26 have a function for amplifying the driver, and the common source transistors 23 and 24 and the common gate transistors 25 and 26 constitute a cascode amplifier.
  • an RF signal (high frequency signal) input from the RF input terminal 21 is amplified using both the source grounded transistors 23 and 24. Thereafter, amplification is performed using both or one of the gate-grounded transistors 25 and 26 according to transmission power (output power of the variable output amplifier). At this time, the matching circuit with switch 28 matches the output impedance of the variable output amplifier, but controls the impedance according to the transmission power.
  • the current flowing through the drain is controlled by the gate control voltage (second bias control voltage) from the bias control circuit 30.
  • the parallel common integer for amplifying the RF signal is controlled by the gate control voltage (first bias control voltage) of the grounded gate transistors 25 and 26 from the bias control circuit 30.
  • the matching circuit with switch 28 switches the switch by the switch control signal from the bias control circuit 30, and the impedance is controlled.
  • an RF signal is amplified using either one of the grounded gate transistors 25 and 26, and the load when the matching circuit 28 with a switch at the subsequent stage is viewed from the output combining point 27.
  • the matching circuit with switch 28 is controlled so that the impedance ZL becomes high.
  • the current flowing through the drains of the common source transistors 23 and 24 is controlled to be small.
  • the RF signal is amplified using both of the grounded gate transistors 25 and 26 so that the load impedance ZL when the matching circuit 28 with the switch at the subsequent stage is viewed from the output combining point 27 becomes low.
  • the matching circuit 28 with a switch is controlled.
  • the current flowing through the drains of the common source transistors 23 and 24 is controlled to increase.
  • variable output amplifier can be reduced in size as compared with the conventional method in which a dedicated amplifier is used depending on the magnitude of transmission power.
  • the switch-equipped matching circuit 28 when the transmission power is small, the switch-equipped matching circuit 28 is controlled so that the load impedance ZL viewed from the output combining point 27 when the switch-equipped matching circuit 28 is viewed is increased.
  • the current flowing through the transistor during operation can be suppressed, the saturation power of the variable output amplifier can be suppressed, and the efficiency at the time of low output can be increased.
  • the impedance of the grounded gate transistors 25 and 26 viewed from the output combining point 27 is increased.
  • reflection loss due to mismatch with the load impedance ZL increased by the matching circuit 28 with switch can be suppressed, and the gain can be increased.
  • the saturation power of the variable output amplifier is increased to control the switching matching circuit 28 so that the load impedance ZL when the switching matching circuit 28 at the subsequent stage is viewed from the output combining point 27 is lowered. Can be made.
  • the impedance of the common gate transistors 25 and 26 viewed from the output combining point 27 is lowered.
  • reflection loss due to mismatch with the load impedance ZL lowered by the matching circuit 28 with switch can be suppressed, and the gain can be increased.
  • the parallel combined integer of the grounded-gate transistors 25 and 26 and the load impedance of the matching circuit 28 with a switch are controlled according to the magnitude of the transmission power.
  • the parallel combined integers of the gate-grounded transistors 25 and 26 and the load impedance of the matching circuit 28 with a switch are set. You may control.
  • the parallel integers of the grounded-gate transistors 25 and 26 and the load impedance of the matching circuit 28 with a switch may be controlled in accordance with changes in the transmission frequency (the output frequency of the variable output amplifier).
  • a common source transistor may be used instead of the common gate transistors 25 and 26.
  • the current flowing through the drain of the common source transistors 23 and 24 is controlled by the gate control voltage from the bias control circuit 30 according to the magnitude of the transmission power.
  • the common source integers for amplifying the RF signal may be controlled by the common source transistors 23 and 24 by the gate control voltage from the bias control circuit 30.
  • the grounded source transistors 23 and 24 are connected in parallel, and the grounded gate transistors 25 and 26 are connected in parallel.
  • three or more parallel grounded source transistors and three or more parallel grounded gate transistors may be connected.
  • the number of switching of the load impedance of the matching circuit 28 with a switch may be three or more according to three or more parallel gate-grounded transistors.
  • FIG. 3 is a block diagram showing a variable output amplifier according to Embodiment 2 of the present invention.
  • 41 is a matching circuit with a switch
  • 42 is a matching circuit with a switch (variable matching circuit)
  • 43 and 44 are switches
  • 45 and 46 are matching circuits
  • 47 and 48 are transistors (third transistors)
  • 49 is a bias.
  • It is a control circuit (control circuit).
  • the matching circuit 45 is set to have a higher impedance than the matching circuit 46.
  • the transistor 47 is set to have a smaller gate width than the transistor 48.
  • the common source transistors 23 and 24 and the common gate transistors 25 and 26 are formed of Si devices, and the transistors 47 and 48 are formed of GaAs devices.
  • the bias control circuit 49 outputs a switch control signal to the switches 43 and 44 of the matching circuit 41 with switch and the matching circuit 42 with switch to control the switching of the switches.
  • the control of the common source transistors 23 and 24 and the common gate transistors 25 and 26 by the bias control circuit 49 is the same as in the first embodiment.
  • the switched matching circuit 41 is controlled so that the RF signal of the first communication mode input from the RF input terminal 1 is input to the source grounded transistors 23 and 24.
  • the switches 43 and 43 of the matching circuit with switch 42 are arranged so that the RF signal of the first communication mode is input to the transistor 47 having a small gate width size via the common gate transistors 25 and 26 and the output combining point 27. 44 is controlled.
  • the switched matching circuit 41 is controlled so that the RF signal of the second communication mode input from the RF input terminal 2 is input to the source grounded transistors 23 and 24. Further, the switches 43, 43 of the switched matching circuit 42 are arranged so that the RF signal in the second communication mode is input to the transistor 48 having a large gate width size via the common gate transistors 25, 26 and the output combining point 27. 44 is controlled.
  • the transistor 43 having a small gate width size is controlled through the matching circuit 45 in which the switch 43 of the matching circuit with switch 42 is turned on and the switch 44 is turned off and the impedance is set high. 47.
  • the load impedance ZL viewed from the output combining point 27 and the matching circuit 42 with the switch at the subsequent stage becomes a high impedance, suppresses the saturation power of the variable output amplifier, and increases the efficiency at the time of low output.
  • the switch 43 of the matching circuit with switch 42 is turned off and the switch 44 is turned on, and is supplied to the transistor 48 having a large gate width size through the matching circuit 46 having a low impedance. .
  • the load impedance ZL viewed from the output combining point 27 and the matching circuit 42 with the switch at the subsequent stage becomes a low impedance, and the saturation power of the variable output amplifier is increased.
  • the parallel combined integers of the gate-grounded transistors 25 and 26, the load impedance of the switched matching circuit 42, and the transistors 45 having different gate width sizes are different.
  • 46 can be controlled to obtain different outputs after amplification.
  • the variable output amplifier can be reduced in size as compared with the conventional method in which a dedicated amplifier is used depending on the magnitude of transmission power.
  • by optimizing each of the subsequent transistors 47 and 48 that are dominant in performance while obtaining the effect of miniaturization by sharing the former transistors high performance as a whole variable output amplifier can be obtained. Can do.
  • control is performed according to the magnitude of transmission power.
  • the connection of the parallel-connected integers of the grounded-gate transistors 25 and 26, the load impedance of the matching circuit with switch 42, and the transistors 47 and 48 having different gate width sizes may be controlled.
  • the matching circuit with switch 42 and the transistors 47 and 48 having different gate width sizes are connected in parallel with each other.
  • three or more matching circuits with switches 42 and transistors having different gate width sizes may be connected in parallel.
  • variable output amplifier includes a plurality of first transistors connected in parallel, a variable matching circuit that is connected to a subsequent stage of the plurality of first transistors, and that makes the impedance variable, and a variable output
  • the number of parallel combination of the first transistors that amplify the high frequency signal is controlled, and the control circuit for controlling the impedance of the variable matching circuit is provided. Suitable for use in systems and the like.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The present invention is configured so that the number of first transistors com bined in parallel and used for amplifying a high frequency signal are controlled, and so that the impedance of a variable matching circuit is controlled, according to the magnitude of the output power of a variable output amplifier; therefore, the variable output amplifier can be reduced in size by a great er amount than possible in a conventional method which requires using dedicated amplifiers for respectively different purposes depending on the magnitude of the output power.

Description

可変出力増幅器Variable output amplifier
　この発明は、携帯電話システムなどに適用される可変出力増幅器に関する。 The present invention relates to a variable output amplifier applied to a mobile phone system or the like.
　図１は従来の増幅器を示す構成図である。
　図において、１，２はＲＦ入力端子、３，４は増幅器、５，６はＲＦ出力端子、７，８はトランジスタ、９～１２は整合回路である。 FIG. 1 is a block diagram showing a conventional amplifier.
In the figure, 1 and 2 are RF input terminals, 3 and 4 are amplifiers, 5 and 6 are RF output terminals, 7 and 8 are transistors, and 9 to 12 are matching circuits.
　従来の増幅器では、Ｗ－ＣＤＭＡやＧＳＭ（登録商標／以下、記載を省略する）などの通信モード、または周波数バンド毎に専用の増幅器を用意してＲＦ信号の増幅を行う。
　ＲＦ入力端子１から入力したＲＦ信号Ａは、増幅器３で増幅されてＲＦ出力端子５から出力される。
　また、ＲＦ入力端子２から入力したＲＦ信号Ｂは、増幅器４で増幅されてＲＦ出力端子６から出力される。 In a conventional amplifier, a dedicated amplifier is prepared for each communication mode such as W-CDMA and GSM (registered trademark / hereinafter, omitted), or for each frequency band, and an RF signal is amplified.
The RF signal A input from the RF input terminal 1 is amplified by the amplifier 3 and output from the RF output terminal 5.
The RF signal B input from the RF input terminal 2 is amplified by the amplifier 4 and output from the RF output terminal 6.
　現代の携帯電話システム、例えば、Ｗ－ＣＤＭＡやＧＳＭでは、端末からの送信電力や端末の利得が異なる。
　また、増幅器を構成するデバイスには周波数特性があるため、周波数が変わると増幅器の飽和出力や利得が変わってくる。
　このため、従来の増幅器では、送信電力、通信モードまたは周波数毎に専用の増幅器が必要とされ、増幅器のモジュールサイズが大型化する課題があった。 In modern mobile phone systems such as W-CDMA and GSM, the transmission power from the terminal and the gain of the terminal are different.
Further, since the devices constituting the amplifier have frequency characteristics, the saturation output and gain of the amplifier change when the frequency changes.
For this reason, the conventional amplifier requires a dedicated amplifier for each transmission power, communication mode, or frequency, and there is a problem that the module size of the amplifier increases.
　この発明は、前記のような課題を解決するためになされたもので、小型化した可変出力増幅器を得ることを目的とする。 The present invention has been made to solve the above-described problems, and an object thereof is to obtain a miniaturized variable output amplifier.
　この発明に係る可変出力増幅器は、並列接続された複数の第一のトランジスタと、複数の第一のトランジスタの後段に接続され、インピーダンスを可変にする可変整合回路と、当該可変出力増幅器の出力電力の大きさに応じて、高周波信号を増幅する第一のトランジスタの並列合成数を制御するとともに、可変整合回路のインピーダンスを制御する制御回路とを備えた。 A variable output amplifier according to the present invention includes a plurality of first transistors connected in parallel, a variable matching circuit that is connected to a subsequent stage of the plurality of first transistors and makes impedance variable, and output power of the variable output amplifier And a control circuit for controlling the impedance of the variable matching circuit as well as controlling the number of parallel combinations of the first transistors that amplify the high-frequency signal.
　この発明によれば、可変出力増幅器の出力電力の大きさに応じて、高周波信号を増幅する第一のトランジスタの並列合成数を制御するとともに、可変整合回路のインピーダンスを制御することで、増幅後に異なる出力電力を得ることができる。
　このため、出力電力の大きさに応じて、専用の増幅器をそれぞれ使い分ける従来法と比較して、可変出力増幅器の小型化を図ることができる効果がある。 According to the present invention, the number of parallel composites of the first transistors that amplify the high-frequency signal is controlled according to the magnitude of the output power of the variable output amplifier, and the impedance of the variable matching circuit is controlled so that after amplification. Different output power can be obtained.
For this reason, there is an effect that the variable output amplifier can be reduced in size as compared with the conventional method in which a dedicated amplifier is used depending on the magnitude of the output power.
従来の増幅器を示す構成図である。It is a block diagram which shows the conventional amplifier. この発明の実施の形態１による可変出力増幅器を示す構成図である。1 is a configuration diagram illustrating a variable output amplifier according to a first embodiment of the present invention. この発明の実施の形態２による可変出力増幅器を示す構成図である。It is a block diagram which shows the variable output amplifier by Embodiment 2 of this invention.
以下、この発明をより詳細に説明するために、この発明を実施するための形態について、添付の図面に従って説明する。
実施の形態１．
　図２はこの発明の実施の形態１による可変出力増幅器を示す構成図である。
　図中、従来技術と同一のものには同一符号を付して説明する。
　図において、２１はＲＦ入力端子、２２は整合回路、２３，２４はソース接地トランジスタ（第二のトランジスタ）、２５，２６はゲート接地トランジスタ（第一のトランジスタ）、２７は出力合成点、２８はスイッチ付き整合回路（可変整合回路）、２９はＲＦ出力端子、３０はバイアス制御回路（制御回路）である。
　なお、３１～３４は直流阻止コンデンサである。 Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 2 is a block diagram showing a variable output amplifier according to the first embodiment of the present invention.
In the figure, the same components as those in the prior art will be described with the same reference numerals.
In the figure, 21 is an RF input terminal, 22 is a matching circuit, 23 and 24 are grounded source transistors (second transistors), 25 and 26 are grounded gate transistors (first transistors), 27 is an output combining point, 28 is A matching circuit with a switch (variable matching circuit), 29 is an RF output terminal, and 30 is a bias control circuit (control circuit).
Reference numerals 31 to 34 are DC blocking capacitors.
　ソース接地トランジスタ２３，２４およびゲート接地トランジスタ２５，２６は、ＦＥＴ（Field Effect Transistor）からなる。
　ゲート接地トランジスタ２５，２６の前段に設けられるソース接地トランジスタ２３，２４は、ドライバ増幅用としての機能を有し、ソース接地トランジスタ２３，２４およびゲート接地トランジスタ２５，２６は、カスコード増幅器を構成する。 Common source transistors 23 and 24 and common gate transistors 25 and 26 are composed of FET (Field Effect Transistor).
The common source transistors 23 and 24 provided in front of the common gate transistors 25 and 26 have a function for amplifying the driver, and the common source transistors 23 and 24 and the common gate transistors 25 and 26 constitute a cascode amplifier.
　この実施の形態１では、ＲＦ入力端子２１から入力したＲＦ信号（高周波信号）を、ソース接地トランジスタ２３，２４の両方を用いて増幅する。
　その後、送信電力（可変出力増幅器の出力電力）に応じて、ゲート接地トランジスタ２５，２６の両方または一方を用いて増幅する。
　このとき、スイッチ付き整合回路２８は、可変出力増幅器の出力インピーダンスの整合を取るものだが、送信電力に応じて、インピーダンスを制御する。 In the first embodiment, an RF signal (high frequency signal) input from the RF input terminal 21 is amplified using both the source grounded transistors 23 and 24.
Thereafter, amplification is performed using both or one of the gate-grounded transistors 25 and 26 according to transmission power (output power of the variable output amplifier).
At this time, the matching circuit with switch 28 matches the output impedance of the variable output amplifier, but controls the impedance according to the transmission power.
　ソース接地トランジスタ２３，２４は、バイアス制御回路３０からのゲート制御電圧（第二のバイアス制御電圧）により、ドレインに流れる電流が制御される。
　ゲート接地トランジスタ２５，２６は、バイアス制御回路３０からのゲート制御電圧（第一のバイアス制御電圧）により、ＲＦ信号を増幅する並列合整数が制御される。
　スイッチ付き整合回路２８は、バイアス制御回路３０からのスイッチ制御信号により、スイッチを切り替え、インピーダンスが制御される。 In the common source transistors 23 and 24, the current flowing through the drain is controlled by the gate control voltage (second bias control voltage) from the bias control circuit 30.
The parallel common integer for amplifying the RF signal is controlled by the gate control voltage (first bias control voltage) of the grounded gate transistors 25 and 26 from the bias control circuit 30.
The matching circuit with switch 28 switches the switch by the switch control signal from the bias control circuit 30, and the impedance is controlled.
　この実施の形態１では、送信電力が小さい場合には、ゲート接地トランジスタ２５，２６のどちらか一方を用いてＲＦ信号を増幅し、出力合成点２７から後段のスイッチ付き整合回路２８を見た負荷インピーダンスＺＬが高くなるようにスイッチ付き整合回路２８を制御する。
　加えて、ソース接地トランジスタ２３，２４のドレインに流れる電流を小さくなるように制御する。 In the first embodiment, when the transmission power is small, an RF signal is amplified using either one of the grounded gate transistors 25 and 26, and the load when the matching circuit 28 with a switch at the subsequent stage is viewed from the output combining point 27. The matching circuit with switch 28 is controlled so that the impedance ZL becomes high.
In addition, the current flowing through the drains of the common source transistors 23 and 24 is controlled to be small.
　一方、送信電力が大きい場合には、ゲート接地トランジスタ２５，２６の両方を用いてＲＦ信号を増幅し、出力合成点２７から後段のスイッチ付き整合回路２８を見た負荷インピーダンスＺＬが低くなるようにスイッチ付き整合回路２８を制御する。
　加えて、ソース接地トランジスタ２３，２４のドレインに流れる電流を大きくなるように制御する。 On the other hand, when the transmission power is large, the RF signal is amplified using both of the grounded gate transistors 25 and 26 so that the load impedance ZL when the matching circuit 28 with the switch at the subsequent stage is viewed from the output combining point 27 becomes low. The matching circuit 28 with a switch is controlled.
In addition, the current flowing through the drains of the common source transistors 23 and 24 is controlled to increase.
　以上のように、この実施の形態１によれば、送信電力の大きさに応じて、ゲート接地トランジスタ２５，２６の並列合整数およびスイッチ付き整合回路２８の負荷インピーダンスを制御することで、増幅後に異なる出力を得ることができる。
　このため、送信電力の大きさに応じて、専用の増幅器をそれぞれ使い分ける従来法と比較して、可変出力増幅器の小型化を図ることができる。 As described above, according to the first embodiment, by controlling the parallel combined integers of the gate-grounded transistors 25 and 26 and the load impedance of the switched matching circuit 28 in accordance with the magnitude of the transmission power, after amplification, Different outputs can be obtained.
For this reason, the variable output amplifier can be reduced in size as compared with the conventional method in which a dedicated amplifier is used depending on the magnitude of transmission power.
　また、この実施の形態１によれば、送信電力が小さい場合に、出力合成点２７から後段のスイッチ付き整合回路２８を見た負荷インピーダンスＺＬが高くなるようにスイッチ付き整合回路２８を制御するため、動作中のトランジスタに流れる電流を抑え、可変出力増幅器の飽和電力を抑制し、低出力時の効率を高めることができる。 Further, according to the first embodiment, when the transmission power is small, the switch-equipped matching circuit 28 is controlled so that the load impedance ZL viewed from the output combining point 27 when the switch-equipped matching circuit 28 is viewed is increased. The current flowing through the transistor during operation can be suppressed, the saturation power of the variable output amplifier can be suppressed, and the efficiency at the time of low output can be increased.
　加えて、ゲート接地トランジスタ２５，２６の並列合整数を減らすことで、出力合成点２７からゲート接地トランジスタ２５，２６を見たインピーダンスが高くなる。
　これにより、スイッチ付き整合回路２８により高くした負荷インピーダンスＺＬとの間で不整合による反射損失が抑えられ、利得を増加させることができる。 In addition, by reducing the parallel integer of the grounded gate transistors 25 and 26, the impedance of the grounded gate transistors 25 and 26 viewed from the output combining point 27 is increased.
As a result, reflection loss due to mismatch with the load impedance ZL increased by the matching circuit 28 with switch can be suppressed, and the gain can be increased.
　一方、送信電力が大きい場合に、出力合成点２７から後段のスイッチ付き整合回路２８を見た負荷インピーダンスＺＬが低くなるようにスイッチ付き整合回路２８を制御するため、可変出力増幅器の飽和電力を増大させることができる。 On the other hand, when the transmission power is large, the saturation power of the variable output amplifier is increased to control the switching matching circuit 28 so that the load impedance ZL when the switching matching circuit 28 at the subsequent stage is viewed from the output combining point 27 is lowered. Can be made.
　加えて、ゲート接地トランジスタ２５，２６の並列合整数を増やすことで、出力合成点２７からゲート接地トランジスタ２５，２６を見たインピーダンスが低くなる。
　これにより、スイッチ付き整合回路２８により低くした負荷インピーダンスＺＬとの間で不整合による反射損失が抑えられ、利得を増加させることができる。 In addition, by increasing the parallel integer of the common gate transistors 25 and 26, the impedance of the common gate transistors 25 and 26 viewed from the output combining point 27 is lowered.
As a result, reflection loss due to mismatch with the load impedance ZL lowered by the matching circuit 28 with switch can be suppressed, and the gain can be increased.
　なお、前記実施の形態１では、送信電力の大きさに応じて、ゲート接地トランジスタ２５，２６の並列合整数およびスイッチ付き整合回路２８の負荷インピーダンスを制御した。
　その他、異なる出力や利得が要求される複数の通信モード、例えば、Ｗ－ＣＤＭＡやＧＳＭなどを切り替えることを目的として、ゲート接地トランジスタ２５，２６の並列合整数およびスイッチ付き整合回路２８の負荷インピーダンスを制御しても良い。
　また、送信周波数（可変出力増幅器の出力周波数）の変化に合わせてゲート接地トランジスタ２５，２６の並列合整数およびスイッチ付き整合回路２８の負荷インピーダンスを制御しても良い。
　さらに、ゲート接地トランジスタ２５，２６の代わりに、ソース接地トランジスタを用いても良い。 In the first embodiment, the parallel combined integer of the grounded-gate transistors 25 and 26 and the load impedance of the matching circuit 28 with a switch are controlled according to the magnitude of the transmission power.
In addition, for the purpose of switching a plurality of communication modes that require different outputs and gains, such as W-CDMA and GSM, the parallel combined integers of the gate-grounded transistors 25 and 26 and the load impedance of the matching circuit 28 with a switch are set. You may control.
Further, the parallel integers of the grounded-gate transistors 25 and 26 and the load impedance of the matching circuit 28 with a switch may be controlled in accordance with changes in the transmission frequency (the output frequency of the variable output amplifier).
Further, a common source transistor may be used instead of the common gate transistors 25 and 26.
　また、前記実施の形態１では、送信電力の大きさに応じて、ソース接地トランジスタ２３，２４は、バイアス制御回路３０からのゲート制御電圧により、ドレインに流れる電流が制御された。
　その他、送信電力の大きさに応じて、ソース接地トランジスタ２３，２４は、バイアス制御回路３０からのゲート制御電圧により、ＲＦ信号を増幅する並列合整数が制御されるようにしても良い。 In the first embodiment, the current flowing through the drain of the common source transistors 23 and 24 is controlled by the gate control voltage from the bias control circuit 30 according to the magnitude of the transmission power.
In addition, according to the magnitude of the transmission power, the common source integers for amplifying the RF signal may be controlled by the common source transistors 23 and 24 by the gate control voltage from the bias control circuit 30.
　さらに、前記実施の形態１では、ソース接地トランジスタ２３，２４を２並列、ゲート接地トランジスタ２５，２６を２並列に接続した。
　その他、ソース接地トランジスタを３並列以上、ゲート接地トランジスタを３並列以上に接続しても良い。
　この場合、３並列以上のゲート接地トランジスタに応じて、スイッチ付き整合回路２８の負荷インピーダンスの切り替え数を３段以上にすれば良い。 Furthermore, in the first embodiment, the grounded source transistors 23 and 24 are connected in parallel, and the grounded gate transistors 25 and 26 are connected in parallel.
In addition, three or more parallel grounded source transistors and three or more parallel grounded gate transistors may be connected.
In this case, the number of switching of the load impedance of the matching circuit 28 with a switch may be three or more according to three or more parallel gate-grounded transistors.
実施の形態２．
　図３はこの発明の実施の形態２による可変出力増幅器を示す構成図である。
　図中、従来技術または実施の形態１と同一のものには同一符号を付して説明する。
　図において、４１はスイッチ付き整合回路、４２はスイッチ付き整合回路（可変整合回路）、４３，４４はスイッチ、４５，４６は整合回路、４７，４８はトランジスタ（第三のトランジスタ）、４９はバイアス制御回路（制御回路）である。 Embodiment 2. FIG.
3 is a block diagram showing a variable output amplifier according to Embodiment 2 of the present invention.
In the figure, the same components as those in the prior art or the first embodiment will be described with the same reference numerals.
In the figure, 41 is a matching circuit with a switch, 42 is a matching circuit with a switch (variable matching circuit), 43 and 44 are switches, 45 and 46 are matching circuits, 47 and 48 are transistors (third transistors), and 49 is a bias. It is a control circuit (control circuit).
　なお、整合回路４５は、整合回路４６よりもインピーダンスが高く設定される。
　また、トランジスタ４７は、トランジスタ４８よりもゲート幅サイズが小さく設定される。
　さらに、ソース接地トランジスタ２３，２４およびゲート接地トランジスタ２５，２６は、Ｓｉデバイスにより構成され、トランジスタ４７，４８は、ＧａＡｓデバイスにより構成される。 The matching circuit 45 is set to have a higher impedance than the matching circuit 46.
The transistor 47 is set to have a smaller gate width than the transistor 48.
Further, the common source transistors 23 and 24 and the common gate transistors 25 and 26 are formed of Si devices, and the transistors 47 and 48 are formed of GaAs devices.
　この実施の形態２では、第一の通信モードのＲＦ信号を増幅する場合には、ＲＦ入力端子１よりＲＦ信号を入力し、ＲＦ出力端子５からＲＦ信号を出力する。
　また、第二の通信モードのＲＦ信号を増幅する場合には、ＲＦ入力端子２よりＲＦ信号を入力し、ＲＦ出力端子６からＲＦ信号を出力する。
　このとき、バイアス制御回路４９は、スイッチ付き整合回路４１およびスイッチ付き整合回路４２のスイッチ４３，４４にスイッチ制御信号を出力し、スイッチを切り替え制御する。
　なお、バイアス制御回路４９によるソース接地トランジスタ２３，２４およびゲート接地トランジスタ２５，２６の制御については、前記実施の形態１と同様である。 In the second embodiment, when an RF signal in the first communication mode is amplified, the RF signal is input from the RF input terminal 1 and the RF signal is output from the RF output terminal 5.
Further, when the RF signal in the second communication mode is amplified, the RF signal is input from the RF input terminal 2 and the RF signal is output from the RF output terminal 6.
At this time, the bias control circuit 49 outputs a switch control signal to the switches 43 and 44 of the matching circuit 41 with switch and the matching circuit 42 with switch to control the switching of the switches.
The control of the common source transistors 23 and 24 and the common gate transistors 25 and 26 by the bias control circuit 49 is the same as in the first embodiment.
　例えば、第一の通信モードにおける送信電力が、第二の通信モードにおける送信電力よりも小さい場合について説明する。
　この場合、ＲＦ入力端子１から入力した第一の通信モードのＲＦ信号がソース接地トランジスタ２３，２４に入力されるように、スイッチ付き整合回路４１が制御される。
　また、ゲート接地トランジスタ２５，２６および出力合成点２７を介して第一の通信モードのＲＦ信号が、ゲート幅サイズの小さいトランジスタ４７へと入力されるように、スイッチ付き整合回路４２のスイッチ４３，４４が制御される。 For example, a case where the transmission power in the first communication mode is smaller than the transmission power in the second communication mode will be described.
In this case, the switched matching circuit 41 is controlled so that the RF signal of the first communication mode input from the RF input terminal 1 is input to the source grounded transistors 23 and 24.
Further, the switches 43 and 43 of the matching circuit with switch 42 are arranged so that the RF signal of the first communication mode is input to the transistor 47 having a small gate width size via the common gate transistors 25 and 26 and the output combining point 27. 44 is controlled.
　一方、ＲＦ入力端子２から入力した第二の通信モードのＲＦ信号は、ソース接地トランジスタ２３，２４に入力されるように、スイッチ付き整合回路４１が制御される。
　さらに、ゲート接地トランジスタ２５，２６および出力合成点２７を介して第二の通信モードのＲＦ信号が、ゲート幅サイズの大きいトランジスタ４８へと入力されるように、スイッチ付き整合回路４２のスイッチ４３，４４が制御される。 On the other hand, the switched matching circuit 41 is controlled so that the RF signal of the second communication mode input from the RF input terminal 2 is input to the source grounded transistors 23 and 24.
Further, the switches 43, 43 of the switched matching circuit 42 are arranged so that the RF signal in the second communication mode is input to the transistor 48 having a large gate width size via the common gate transistors 25, 26 and the output combining point 27. 44 is controlled.
　この実施の形態１では、送信電力が小さい場合に、スイッチ付き整合回路４２のスイッチ４３がオン、スイッチ４４がオフに制御され、インピーダンスが高く設定された整合回路４５を通じて、ゲート幅サイズの小さいトランジスタ４７に供給される。
　これにより、出力合成点２７から後段のスイッチ付き整合回路４２を見た負荷インピーダンスＺＬは高インピーダンスとなり、可変出力増幅器の飽和電力を抑制し、低出力時の効率を高める。 In the first embodiment, when the transmission power is small, the transistor 43 having a small gate width size is controlled through the matching circuit 45 in which the switch 43 of the matching circuit with switch 42 is turned on and the switch 44 is turned off and the impedance is set high. 47.
As a result, the load impedance ZL viewed from the output combining point 27 and the matching circuit 42 with the switch at the subsequent stage becomes a high impedance, suppresses the saturation power of the variable output amplifier, and increases the efficiency at the time of low output.
　一方、送信電力が大きい場合に、スイッチ付き整合回路４２のスイッチ４３がオフ、スイッチ４４がオンに制御され、インピーダンスが低く設定された整合回路４６を通じて、ゲート幅サイズの大きいトランジスタ４８に供給される。
　これにより、出力合成点２７から後段のスイッチ付き整合回路４２を見た負荷インピーダンスＺＬは低インピーダンスとなり、可変出力増幅器の飽和電力を増大させる。 On the other hand, when the transmission power is large, the switch 43 of the matching circuit with switch 42 is turned off and the switch 44 is turned on, and is supplied to the transistor 48 having a large gate width size through the matching circuit 46 having a low impedance. .
As a result, the load impedance ZL viewed from the output combining point 27 and the matching circuit 42 with the switch at the subsequent stage becomes a low impedance, and the saturation power of the variable output amplifier is increased.
　以上のように、この実施の形態２によれば、送信電力の大きさに応じて、ゲート接地トランジスタ２５，２６の並列合整数、スイッチ付き整合回路４２の負荷インピーダンスおよびゲート幅サイズの異なるトランジスタ４５，４６の接続を制御することで、増幅後に異なる出力を得ることができる。
　このため、送信電力の大きさに応じて、専用の増幅器をそれぞれ使い分ける従来法と比較して、可変出力増幅器の小型化を図ることができる。
　また、前段のトランジスタの共用化による小型化の効果を得ながら、性能に対して支配的となる後段のトランジスタ４７，４８の個々を最適化することで、可変出力増幅器全体として高い性能を得ることができる。 As described above, according to the second embodiment, according to the magnitude of the transmission power, the parallel combined integers of the gate-grounded transistors 25 and 26, the load impedance of the switched matching circuit 42, and the transistors 45 having different gate width sizes are different. , 46 can be controlled to obtain different outputs after amplification.
For this reason, the variable output amplifier can be reduced in size as compared with the conventional method in which a dedicated amplifier is used depending on the magnitude of transmission power.
Further, by optimizing each of the subsequent transistors 47 and 48 that are dominant in performance while obtaining the effect of miniaturization by sharing the former transistors, high performance as a whole variable output amplifier can be obtained. Can do.
　なお、前記実施の形態２では、送信電力の大きさに応じて制御した。
　その他、送信周波数や通信モードに応じて、ゲート接地トランジスタ２５，２６の並列合整数、スイッチ付き整合回路４２の負荷インピーダンスおよびゲート幅サイズの異なるトランジスタ４７，４８の接続を制御しても良い。 In the second embodiment, control is performed according to the magnitude of transmission power.
In addition, in accordance with the transmission frequency and the communication mode, the connection of the parallel-connected integers of the grounded-gate transistors 25 and 26, the load impedance of the matching circuit with switch 42, and the transistors 47 and 48 having different gate width sizes may be controlled.
　さらに、前記実施の形態２では、スイッチ付き整合回路４２およびゲート幅サイズの異なるトランジスタ４７，４８を、それぞれ２並列に接続した。
　その他、スイッチ付き整合回路４２およびゲート幅サイズの異なるトランジスタを、３並列以上接続しても良い。 Furthermore, in the second embodiment, the matching circuit with switch 42 and the transistors 47 and 48 having different gate width sizes are connected in parallel with each other.
In addition, three or more matching circuits with switches 42 and transistors having different gate width sizes may be connected in parallel.
　なお、本願発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .
　以上のように、この発明に係る可変出力増幅器は、並列接続された複数の第一のトランジスタと、複数の第一のトランジスタの後段に接続され、インピーダンスを可変にする可変整合回路と、可変出力増幅器の出力電力の大きさに応じて、高周波信号を増幅する第一のトランジスタの並列合成数を制御するとともに、可変整合回路のインピーダンスを制御する制御回路とを備えるように構成したので、携帯電話システムなどに用いるのに適している。 As described above, the variable output amplifier according to the present invention includes a plurality of first transistors connected in parallel, a variable matching circuit that is connected to a subsequent stage of the plurality of first transistors, and that makes the impedance variable, and a variable output In accordance with the magnitude of the output power of the amplifier, the number of parallel combination of the first transistors that amplify the high frequency signal is controlled, and the control circuit for controlling the impedance of the variable matching circuit is provided. Suitable for use in systems and the like.
　１，２，２１　ＲＦ入力端子、２２，４５，４６　整合回路、２３，２４　ソース接地トランジスタ（第二のトランジスタ）、２５，２６　ゲート接地トランジスタ（第一のトランジスタ）、２７　出力合成点、２８，４２　スイッチ付き整合回路（可変整合回路）、５，６，２９　ＲＦ出力端子、３０，４９　バイアス制御回路（制御回路）、３１～３４　直流阻止コンデンサ、４１　スイッチ付き整合回路、４３，４４　スイッチ、４７，４８　トランジスタ（第三のトランジスタ）。 1, 2, 21 RF input terminal, 22, 45, 46 Matching circuit, 23, 24 Common source transistor (second transistor), 25, 26 Common gate transistor (first transistor), 27 Output composite point, 28, 42 Matching circuit with switch (variable matching circuit), 5, 6, 29 RF output terminal, 30, 49 Bias control circuit (control circuit), 31-34 DC blocking capacitor, 41 Matching circuit with switch, 43, 44 switch, 47 48 transistors (third transistor).

Claims (14)

  1. 　並列接続された複数の第一のトランジスタと、
    　前記複数の第一のトランジスタの後段に接続され、インピーダンスを可変にする可変整合回路と、
    　当該可変出力増幅器の出力電力の大きさに応じて、高周波信号を増幅する前記第一のトランジスタの並列合成数を制御するとともに、前記可変整合回路のインピーダンスを制御する制御回路とを備えた可変出力増幅器。     A plurality of first transistors connected in parallel;
    A variable matching circuit that is connected to a subsequent stage of the plurality of first transistors and makes the impedance variable;
    A variable output comprising a control circuit for controlling the number of parallel combinations of the first transistors for amplifying a high-frequency signal and controlling the impedance of the variable matching circuit according to the magnitude of the output power of the variable output amplifier amplifier.
  2. 　複数の第一のトランジスタの前段に、ドライバ増幅用として第二のトランジスタを備えたことを特徴とする請求項１記載の可変出力増幅器。 2. The variable output amplifier according to claim 1, wherein a second transistor is provided for driver amplification in front of the plurality of first transistors.
  3. 　第二のトランジスタは、
    　並列接続された複数からなることを特徴とする請求項２記載の可変出力増幅器。     The second transistor is
    3. The variable output amplifier according to claim 2, comprising a plurality of units connected in parallel.
  4. 　第一のトランジスタおよび第二のトランジスタは、
    　ＦＥＴからなることを特徴とする請求項３記載の可変出力増幅器。     The first transistor and the second transistor are
    4. The variable output amplifier according to claim 3, wherein the variable output amplifier is an FET.
  5. 　第一のトランジスタは、
    　ゲート接地に構成され、
    　第二のトランジスタは、
    　ソース接地に構成されたことを特徴とする請求項４記載の可変出力増幅器。     The first transistor is
    Configured to gate ground,
    The second transistor is
    5. The variable output amplifier according to claim 4, wherein the variable output amplifier is configured as a common source.
  6. 　第一のトランジスタと第二のトランジスタにより、カスコード増幅器を構成することを特徴とする請求項５記載の可変出力増幅器。 6. The variable output amplifier according to claim 5, wherein the first transistor and the second transistor constitute a cascode amplifier.
  7. 　制御回路は、
    　当該可変出力増幅器の出力電力の大きさに応じて、第一のトランジスタに印加する第一のバイアス制御電圧により、高周波信号を増幅する前記第一のトランジスタの並列合成数を制御するとともに、
    　当該可変出力増幅器の出力電力の大きさに応じて、第二のトランジスタに印加する第二のバイアス制御電圧により、前記第二のトランジスタに流れる電流を制御することを特徴とする請求項２記載の可変出力増幅器。     The control circuit
    According to the magnitude of the output power of the variable output amplifier, the first bias control voltage applied to the first transistor controls the number of parallel combinations of the first transistors that amplify the high-frequency signal,
    3. The current flowing through the second transistor is controlled by a second bias control voltage applied to the second transistor in accordance with the magnitude of the output power of the variable output amplifier. Variable output amplifier.
  8. 　制御回路は、
    　当該可変出力増幅器の出力電力の大きさに応じて、第一のトランジスタに印加する第一のバイアス制御電圧により、高周波信号を増幅する前記第一のトランジスタの並列合成数を制御するとともに、
    　当該可変出力増幅器の出力電力の大きさに応じて、第二のトランジスタに印加する第二のバイアス制御電圧により、高周波信号を増幅する前記第二のトランジスタの並列合成数を制御することを特徴とする請求項２記載の可変出力増幅器。     The control circuit
    According to the magnitude of the output power of the variable output amplifier, the first bias control voltage applied to the first transistor controls the number of parallel combinations of the first transistors that amplify the high-frequency signal,
    The number of parallel combinations of the second transistors that amplify the high-frequency signal is controlled by a second bias control voltage applied to the second transistor according to the magnitude of the output power of the variable output amplifier. The variable output amplifier according to claim 2.
  9. 　可変整合回路は、
    　スイッチの切り替えにより、インピーダンスを可変にするスイッチ付き整合回路からなり、
    　制御回路は、
    　当該可変出力増幅器の出力電力の大きさに応じて、前記スイッチ付き整合回路に出力するスイッチ制御信号により、インピーダンスを制御することを特徴とする請求項１記載の可変出力増幅器。     The variable matching circuit
    It consists of a matching circuit with a switch that makes the impedance variable by switching the switch,
    The control circuit
    The variable output amplifier according to claim 1, wherein the impedance is controlled by a switch control signal output to the matching circuit with a switch in accordance with a magnitude of output power of the variable output amplifier.
  10. 　制御回路は、
    　当該可変出力増幅器の出力電力が大きいときには、
    　第一のトランジスタの並列合成数を増加させるとともに、可変整合回路のインピーダンスを低くなるように制御し、
    　当該可変出力増幅器の出力電力が小さいときには、
    　前記第一のトランジスタの並列合成数を減少させるとともに、前記可変整合回路のインピーダンスを高くなるように制御することを特徴とする請求項１記載の可変出力増幅器。     The control circuit
    When the output power of the variable output amplifier is large,
    While increasing the number of parallel composites of the first transistor and controlling the impedance of the variable matching circuit to be low,
    When the output power of the variable output amplifier is small,
    2. The variable output amplifier according to claim 1, wherein the number of parallel combinations of the first transistors is reduced and the impedance of the variable matching circuit is controlled to be high.
  11. 　制御回路は、
    　当該可変出力増幅器の出力電力が大きいときには、
    　第一のトランジスタの並列合成数を増加させるとともに、第二のトランジスタに流れる電流が大きくなるように制御し、
    　当該可変出力増幅器の出力電力が小さいときには、
    　前記第一のトランジスタの並列合成数を減少させるとともに、前記第二のトランジスタに流れる電流が小さくなるように制御することを特徴とする請求項７記載の可変出力増幅器。     The control circuit
    When the output power of the variable output amplifier is large,
    While increasing the number of parallel composites of the first transistor, control to increase the current flowing through the second transistor,
    When the output power of the variable output amplifier is small,
    8. The variable output amplifier according to claim 7, wherein the number of parallel combinations of the first transistors is reduced and the current flowing through the second transistor is controlled to be small.
  12. 　制御回路は、
    　当該可変出力増幅器の出力周波数に応じて、第一のトランジスタの並列合成数を制御すると共に、可変整合回路のインピーダンスを制御することを特徴とする請求項１記載の可変出力増幅器。     The control circuit
    2. The variable output amplifier according to claim 1, wherein the number of parallel synthesis of the first transistors is controlled according to the output frequency of the variable output amplifier, and the impedance of the variable matching circuit is controlled.
  13. 　可変整合回路の後段に、ゲート幅サイズの異なる複数の第三のトランジスタを備え、
    　前記可変整合回路のインピーダンスが低くなるときは、
    　該可変整合回路を通過した高周波信号がゲート幅サイズの大きな前記第三のトランジスタに供給され、
    　前記可変整合回路のインピーダンスが高くなるときは、
    　該可変整合回路を通過した高周波信号がゲート幅サイズの小さな前記第三のトランジスタに供給されることを特徴とする請求項１記載の可変出力増幅器。     A plurality of third transistors having different gate width sizes are provided at the subsequent stage of the variable matching circuit,
    When the impedance of the variable matching circuit is low,
    The high-frequency signal that has passed through the variable matching circuit is supplied to the third transistor having a large gate width size,
    When the impedance of the variable matching circuit becomes high,
    2. The variable output amplifier according to claim 1, wherein the high-frequency signal that has passed through the variable matching circuit is supplied to the third transistor having a small gate width size.
  14. 　第一のトランジスタおよび第二のトランジスタは、
    　Ｓｉデバイスにより構成され、
    　第三のトランジスタは、
    　ＧａＡｓデバイスにより構成されたことを特徴とする請求項１３記載の可変出力増幅器。     The first transistor and the second transistor are
    Consists of Si devices,
    The third transistor is
    14. The variable output amplifier according to claim 13, comprising a GaAs device.
PCT/JP2012/079656 2012-11-15 2012-11-15 Variable output amplifier WO2014076797A1 (en)

Priority Applications (2)

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PCT/JP2012/079656 WO2014076797A1 (en) 2012-11-15 2012-11-15 Variable output amplifier
TW102104152A TW201419751A (en) 2012-11-15 2013-02-04 Amplifier featuring variable output

Applications Claiming Priority (1)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003087060A (en) * 2001-09-11 2003-03-20 Hitachi Ltd High-frequency amplifier, and transmitter/receiver
JP2004128704A (en) * 2002-09-30 2004-04-22 Toshiba Corp Amplifier and radio communication device using the same
JP2004134823A (en) * 2002-10-08 2004-04-30 Matsushita Electric Ind Co Ltd High frequency amplifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003087060A (en) * 2001-09-11 2003-03-20 Hitachi Ltd High-frequency amplifier, and transmitter/receiver
JP2004128704A (en) * 2002-09-30 2004-04-22 Toshiba Corp Amplifier and radio communication device using the same
JP2004134823A (en) * 2002-10-08 2004-04-30 Matsushita Electric Ind Co Ltd High frequency amplifier

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