WO2013132580A1

WO2013132580A1 - Multi-rate recovery device

Info

Publication number: WO2013132580A1
Application number: PCT/JP2012/055578
Authority: WO
Inventors: 巨生鈴木
Original assignee: 三菱電機株式会社
Priority date: 2012-03-05
Filing date: 2012-03-05
Publication date: 2013-09-12
Also published as: JP5924705B2; WO2013132716A1; JPWO2013132716A1

Abstract

A multi-rate recovery device includes an M[Hz]×N-phase sampling circuit (1) that oversamples input data, a phase group selection circuit (2) that outputs phase group data from N-phase sampling data, an N-phase data selection circuit (6) that outputs only optimum identification phase sampling data as optimum phase data from the phase group data selected by the phase group selection circuit (2), and data recovery circuits (9 and 10) that recover a signal having the bit rate of the optimum phase data. The phase group selection circuit (2) inputs data for one phase group from N×S phase sampling data to an optimum phase selection circuit (7), an edge phase detection circuit (3) detects an edge phase bit by bit from the N×S phase sampling data, and a phase group determination circuit (4) outputs from a selector circuit (5) one phase group on the basis of the results of edge detection. Therefore, a reduction in power consumption is achieved.

Description

Multi-rate playback device

The present invention relates to a multirate reproduction circuit using a multirate sampling circuit for oversampling input data bits and a data reproduction circuit, and more particularly to a clock extraction circuit for extracting a clock for timing reproduction from input data, and an extraction clock. The present invention relates to an improvement technique for a data reproduction circuit CDR (Clock and Data Recovery) that outputs retimed reproduction data.

As a recent FTTH (Fiber-to-the-Home) system, a PON (Passive Optical Networks) system has become mainstream (see, for example, Non-Patent Document 1).
In the PON system, an optical fiber is connected from an optical line terminal (OLT) to an optical network unit (ONU) on the subscriber side, and a large number of ONUs are connected by an OLT via an optical splitter. Is to be accommodated.

In the PON system described in Non-Patent Document 1, the input optical signal data having various data phases output from each ONU is burst (intermittently) input to the OLT in bursts. It is suitable for use in burst CDR that performs burst clock extraction and burst data reproduction.

The burst CDR circuit in the OLT optical receiver extracts frequency information and phase information as a clock signal at a high speed from the burst optical signal within a desired overhead time in the system, and uses the extracted clock as an input data signal. Are required to be retimed and played back.

For example, the CDR overhead time defined as a standard specification in Non-Patent Document 1 is 400 ns or less corresponding to a frequency and phase information amount of 500 bits or less with respect to an input data bit rate of 1.25 [Gbps]. In a general feedback control type PLL (Phase Locked Loop) circuit, it is difficult to accurately extract a clock signal from such a small amount of frequency and phase information.
Therefore, conventionally, a technique for extracting a clock signal from such a burst signal at high speed and reproducing the data has been proposed (for example, see Non-Patent Document 2).

The conventional burst CDR circuit disclosed in Non-Patent Document 2 is output from an optical receiver and a multi-phase clock generator that generates a multi-phase clock synchronized with the system clock in a PON system synchronized in frequency with the system clock. A data sampler for sampling the burst input data with a multi-phase clock, and an output circuit having a selector retiming DFF circuit.

The output circuit of Non-Patent Document 2 detects the data edge phase (the phase of the rising and falling change points of the data signal pulse) from the sampling output data sampled by each phase clock, and from the detection result of the data edge phase Data sampled with the clock whose phase margin is expected to be the most appropriate from the edge phase as the data identification phase is selected by the selector / retiming DFF circuit as retiming reproduction data and output by the system clock To do.

This makes it possible to always sample burst input data with a multi-phase continuous clock synchronized with the system clock, select the optimum output data from the sampling results, and output it as playback data. Burst clock extraction (extraction of phase information from frequency-synchronized multi-phase clocks) and data reproduction by extraction clock (selection and output of optimum clock phase sampling output data) are possible.

The conventional burst CDR circuit shown in Non-Patent Document 2 also discloses a pulse-wise detector circuit for determining the pulse width of input data. Even when input data is distorted, burst input data is also disclosed. On the other hand, a circuit configuration that enables accurate and high-speed clock extraction and data reproduction has been proposed.
For example, by sampling with 8 phase clocks (1.25 [GHz] × 8 phase shift (45 degree shift) clocks) for 1 [Gbps] burst input data, up to ± 0.68 UI (Unit Interval) It has been shown that an accurate burst CDR operation can be achieved for a given input pulse width distortion.

In addition to the high-speed burst response operation, the burst CDR for the PON system needs to continuously accommodate conventional low-speed subscribers on the same optical access network. However, there is a demand for multi-rate operation that can be operated.
For example, experimental results for multi-rate operation corresponding to different bit rate input conditions of 10.3 [Gbps] and 1.25 [Gbps] are also shown (for example, see Non-Patent Document 3).

The technique disclosed in Non-Patent Document 3 uses an oversampling CDR technique using an 8-phase clock.
Unlike the CDR method based on the normal PLL system, the multi-phase sampling CDR method is a method of receiving input data bits by oversampling, and therefore the oversampling speed basically depends on the bit rate of the input data. In addition, by downsampling the sampling data in accordance with the input data bit rate, there is an advantage that a multirate operation can be easily realized.

For example, when 1.03 [Gbps] is input, 10.3 [GHz] × 8 phase sampling is equivalent to 1.03 [GHz] × 80 phase sampling. Only data will be thinned out.

The conventional multi-rate playback apparatus is capable of multi-rate operation in the example of the over-sampling burst CDR described in Non-Patent Document 3 above, while the sampling rate corresponding to the maximum input bit rate (for example, 10.3 [Gbps] is input when 10.3 [Gbps] is input, and when low-speed bit rate data is input, a part of the sampling data obtained by oversampling is discarded. Therefore, there is a problem that the circuit configuration is wasteful, the cost is increased when inputting a low bit rate, and the power consumption is excessive.

On the other hand, the use of all oversampling data can be expected to improve the sampling performance such as improving the pulse width distortion tolerance. However, as the sampling resolution increases, the number of detected edge phases increases. There is a problem that the number of combinations in the selection algorithm (optimum discrimination phase selection logic circuit) of the optimum clock phase sampling output data given as a table becomes enormous, the algorithm becomes very complicated, and as a result, circuit implementation becomes rapidly difficult. there were.
In particular, when the input pulse width is distorted, the pulse width distortion tolerance performance is improved by improving the sampling resolution, while the detection frequency of the edge phase assumed by the distortion spreads to all edges, so that the selection algorithm is further improved. There was a problem that a trade-off of becoming complicated occurred.

The present invention has been made to solve the above-described problems. In the oversampling CDR, when low-speed data is input, the sampling performance corresponding to the oversampling resolution corresponding to the high-speed bit rate (pulse width distortion tolerance). ) While ensuring optimum clock phase sampling output data optimum identification phase selection logic circuit (hereinafter abbreviated as “optimum phase selection circuit”), and providing a means for enabling easy circuit mounting An object of the present invention is to obtain a multi-rate playback device that realizes low power consumption for a CDR circuit having sampling performance equivalent to that of a conventional system.

A multirate playback apparatus according to the present invention is provided in a master station apparatus of an optical access system, and is a multirate playback apparatus that uses the same sampling clock for a plurality of bit rate signals. An M [Hz] × N-phase sampling circuit that oversamples data and outputs N-phase sampling data, an edge phase detection circuit, a phase group determination circuit, and a selector circuit, and converts the N-phase sampling data to the bit rate of the input data A phase group selection circuit that assigns the required number of phase groups according to the output and outputs one phase group, an optimum phase selection circuit that extracts the phase of the data sampled with the optimum identification phase from the N phase sampling data, and a phase From the phase group data selected by the group selection circuit, the optimum phase selected by the optimum phase selection circuit is selected. An N phase data selection circuit that outputs only the identification phase sampling data as optimum phase data; and a data reproduction circuit that reproduces and outputs the bit rate of the optimum phase data to a required bit rate signal, and M [Hz] When the input data has a maximum bit rate M [bps] that can be input in synchronization with the system reference frequency, the × N phase sampling circuit generates an N phase clock of M [Hz] and converts the input data to N Phase oversampling is performed, and input data is obtained from M / S [bps] bit rate data of 1 / S of M [bps] (S = 2 ^ (x), x = 0, 1, 2,...). In this case, the input data is subjected to N × S phase oversampling, and the phase group selection circuit performs N × S phase oversampling when M / S [bps] data is input as input data. N × S phase sampling data by ring is assigned to S phase groups, and only sampling data for N phases of M / S [bps] out of S phase group data is set as one phase group data. When the M / S [bps] data is input as the input data, the edge phase detection circuit inputs the phase to the optimum phase selection circuit, and the phase of the rising edge and the falling edge for each bit from the N × S phase sampling data. The phase group determining circuit outputs one phase group from the selector circuit based on the detection result of the rising edge and the falling edge.

With this configuration, the present invention can realize low power consumption for a CDR circuit having sampling performance equivalent to that of a conventional system.

It is a block diagram which shows the multi-rate reproducing | regenerating apparatus concerning Embodiment 1 of this invention. It is explanatory drawing which shows operation | movement of the edge phase detection circuit by Embodiment 1 of this invention. It is explanatory drawing which shows operation | movement of the phase group determination circuit by Embodiment 1 of this invention. It is a flowchart which shows the operation | movement of the phase group selection circuit by Embodiment 1 of this invention. It is explanatory drawing which shows the effect by Embodiment 1 of this invention. It is a block diagram which shows the multi-rate reproducing | regenerating apparatus concerning Embodiment 2 of this invention.

Embodiment 1 FIG.
Hereinafter, the first embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a block diagram of a multi-rate playback apparatus according to Embodiment 1 of the present invention.
In FIG. 1, the multi-rate playback apparatus includes an M [Hz] × N phase sampling circuit 1, a phase group selection circuit 2, an N phase data selection circuit 6, an N phase optimum phase selection circuit 7, and a bit accumulation number. A decision circuit 8, an M / S [bps] data reproduction circuit 9, and an M [bps] data reproduction circuit 10 are provided.

The phase group selection circuit 2 includes an edge phase detection circuit 3, a phase group determination circuit 4, and a selector circuit 5 including selector elements 5a to 5n corresponding to the N phases.
The M / S [bps] data reproduction circuit 9 and the M [bps] data reproduction circuit 10 cooperate with the N phase data selection circuit 6 and the optimum phase selection circuit 7 to change the bit rate of the optimum phase data to a required bit. A data reproduction circuit that reproduces and outputs a rate signal is configured.

The M [Hz] × N phase sampling circuit 1 receives 1 / S (S = 2 ^ (x), x = M = bps) as input data from an optical receiver (not shown) of the master station device. M / S [bps] data having different bit rates consisting of 0, 1, 2, 3,...) Are input, but the M [Hz] × N phase sampling circuit 1 outputs a plurality of different bit rate signals. On the other hand, the same sampling clock is used.
The multi-rate playback device (for example, burst data playback device) in FIG. 1 is provided in a master station device (optical receiver) of an optical access system (not shown) such as a PON system.

Hereinafter, the operation of the multirate playback apparatus according to Embodiment 1 of the present invention shown in FIG. 1 will be described in detail.
First, input data of M / S [bps] output from the optical receiver is input to the M [Hz] × N phase sampling circuit 1.
The M [Hz] × N phase sampling circuit 1 samples and outputs input data using the M [Hz] × N phase clock as a sampling clock.

Here, M [Hz] × N phase clock is phase # 0 to phase #N shifted by 1 / N phase with respect to 1 bit width of M [bps] input data from the reference clock frequency-synchronized with the system clock. Is the clock.
Therefore, from the M [Hz] × N phase sampling circuit 1, the frequency is synchronized with the system clock, and the phase is shifted by 1 / (N × S) phase from # 0 to # (N−1) × S. Data sampling results (<0>, <1>,..., <N-1>) are output as N × S phase clock sampling data (hereinafter referred to as “N × S phase sampling data”).

The N × S phase sampling data output from the M [Hz] × N phase sampling circuit 1 is input to the phase group selection circuit 2.
In the phase group selection circuit 2, the edge phase detection circuit 3 detects the data edge phase from the input N × S phase sampling data and inputs the detection result to the phase group determination circuit 4.

Here, the data edge phase is one bit of N × S phase sampling data, and sampling data between adjacent phases is “... 0 → 1...” Or “... 1 → 0. ”Is detected as the change point phase.
The 1-bit width includes one or less of the rising edge phase or the falling edge phase according to any one of “0 → 1”, “1 → 0”, “1 → 1”, and “0 → 0”. Therefore, in the edge phase detection with 1 bit width, the edge phase is uniquely determined. If the edge phase is not detected, the edge phase detection circuit 3 latches and outputs the previous detection result.

Next, the operation of the phase group selection circuit 2 (edge phase detection circuit 3, phase group determination circuit 4 and selector circuit 5) will be described with reference to FIGS.
2 and 3 are explanatory diagrams showing the operations of the edge phase detection circuit 3 and the phase group determination circuit 4. FIG. 4 is a flowchart showing an operation sequence of the phase group selection circuit 2 (edge phase detection circuit 3, phase group determination circuit 4 and selector circuit 5).
In FIGS. 2 and 3, as an example for facilitating the description, the variables M, S, M / S, and N are represented by M = 10 [Gbps], S = 4, and M / S =, respectively. In this example, 2.5 [Gbps], N = 8 phases, and N × S = 32 phases are shown.

In FIG. 2, the rising edge of the input data from “0” (Low) to “1” (High) coincides with the timing of the phase group C of the four phase groups A to D (see the broken line arrow). Shows the case.
FIG. 3 shows a case where the center phase of the input data obtained by time-integrating a plurality of data coincides with the timing of the phase group C (see the broken line arrow) among the four phase groups A to D.

When data of M / S = 2.5 [Gbps] is input to the multi-rate playback device of FIG. 1, “2.5 [Gbps] × 32 phase sampling”, which is 32 times oversampling of the input data Is done.
Here, as shown in FIG. 2 and FIG. 3, four phase groups A, B, C, and D having sampling data for 8 phases with a set of phases for every 4 phases are assigned.
Hereinafter, an operation will be described for the case where 2.5 [Gbps] × 32 phase sampling is performed.

In FIG. 4, first, the edge phase detection circuit 3 detects the rising edge phase number <a> and the falling edge phase number <b> for each bit from 2.5 [Gbps] × 32 phase sampling data. (Step ST1).
Subsequently, the phase group determination circuit 4 determines a phase group from the edge phase extraction result in step ST1 according to the following equation (1) with the center phase number <c> as an average value (step ST2).

<C> = (<a> + <b>) / 2 (1)

If the edge phase is only one or no edge phase exists, the center phase number <c> (average value) cannot be extracted, so the previous detection result (phase group) is latched and used. Since the latch value is updated each time new data is detected, the latest value is stored.

Next, the phase group determination circuit 4 outputs the determination results of the phase groups A, B, C, and D to which the center phase belongs determined in step ST2 by the bit integration number set by the bit integration number determination circuit 8 (bits). Accumulated (at several intervals) (step ST3), and according to the majority rule, the most frequent phase group is determined as the optimum phase group (step ST4).
In step ST4, when there are a plurality of the same number of phase groups and they are not uniquely determined by majority decision, the previous determination result (optimum phase group) is latched and used.
Finally, the selector circuit 5 selects and outputs only the data of the phase group determined by the phase group determination circuit 4 (step ST5), and ends the processing routine of FIG.

In FIG. 1, the phase group data selected by the selector circuit 5 is input to the N phase data selection circuit 6 and buffered.
Here, a case where sampling data for 8 phases (N = 8) is output from the selector circuit 5 is shown.

Next, the optimum phase selection circuit (N phase) 7 extracts an optimum identification phase as a sampling phase from the phase group data determined by the phase group determination circuit 4.
In this case, the optimum phase selection circuit (N phase) 7 determines the edge phase of the input 8-phase data (N = 8). In determining the edge phase, an edge phase histogram is created for each bit integration number designated by the bit integration number determination circuit 8, and the most frequent phase is extracted as the edge phase.

Also, the optimum phase selection circuit (N phase) 7 determines the optimum identification phase based on the extracted edge phase information. The method for determining the optimum discrimination phase is described in Non-Patent Document 1 and other known documents (for example, Japanese Patent Application Laid-Open No. 10-327136), and will not be described in detail here.

Next, the N phase data selection circuit 6 outputs the data sampled at the optimum phase extracted by the optimum phase selection circuit (N phase) 7 to the M / S [bps] data reproduction circuit 9 as optimum phase data. . The M / S [bps] data recovery circuit 9 outputs M / S [bps] data that is timing-recovered with an M / S [Hz] clock generated inside the circuit in synchronization with the system clock.

Next, an operation when M [bps] (S = 1) bit rate data is input in FIG. 1 will be described.
When M [bps] data is input, the selector circuit 5 outputs all the phase group data and pauses the phase group determination operation.
All the phase group data is output as M [bps] data from the M [bps] data reproduction circuit 10.
Thereafter, the reproduction of M [bps] data can be performed by the same operation.

Next, effects of the first embodiment of the present invention will be described with reference to FIG.
FIG. 5 is an explanatory diagram showing a first effect according to the first embodiment of the present invention, and shows a sampling operation for distorted input data.
According to the first embodiment of the present invention, as a first effect, by realizing a sampling performance corresponding to high-speed sampling resolution, as shown in FIG. It becomes possible to arrange the identification phase in the bit opening.

That is, in FIG. 5, even when the timing of 8-phase sampling does not place the identification phase in the bit opening portion of the distorted input data and it becomes difficult to identify the bit opening and generates a penalty, By arranging the sampling clock phase in the bit opening portion of the input data distorted as indicated by the solid line arrow, it becomes possible to identify the bit opening, and to improve the pulse width distortion resistance substantially corresponding to 32 resolution. Can do.

Also, according to the first embodiment of the present invention, as a second effect, the optimum phase selection operation that complicates the circuit operation is performed in the phase group selection circuit 2 by a small number of inputs collected by the phase group selection operation. Since it is realizable only from phase sampling data, it has the effect that the circuit scale can be reduced while ensuring the sampling performance of the pulse width distortion tolerance.

Also, the phase group selection operation in the phase group selection circuit 2 converges the input sampling phase into the phase group, so that the combination conditions can be reduced and the selection operation can be simplified. Thereby, low power consumption can be easily realized for a circuit having equivalent sampling performance.

For example, as described above, taking 2.5 [Gbps] × 32 phase sampling as an example, in the conventional optimum phase selection operation, a maximum of 2 ³² (= 2 ^ (S × N)) edge phase combinations. Need to be considered. However, according to the first embodiment of the present invention, by selecting a phase group, a maximum of 2 ³² (= 2 ^ (S × N)) or less corresponding to the 32 phase sampling operation is selected. It is possible to make a combination of “operation + 8 phase optimum phase selection operation after selection”. As a result, it is possible to easily realize the proposal of the operation of the optimum phase selection circuit 7 and the reduction in power consumption for a circuit having equivalent sampling performance.

As described above, the multirate reproducing apparatus according to Embodiment 1 (FIGS. 1 to 5) of the present invention is provided in the master station apparatus (optical receiver) of the optical access system, and a plurality of bit rate signals are An M [Hz] × N-phase sampling circuit 1 that oversamples input data from a master station device and outputs N-phase sampling data, and an edge phase detection A phase group selection circuit 2 which includes a circuit 3, a phase group determination circuit 4 and a selector circuit 5, and which assigns N phase sampling data to a required number of phase groups corresponding to the bit rate of input data and outputs one phase group; , An optimum phase selection circuit 7 for extracting the phase of the data sampled with the optimum discrimination phase from the N phase sampling data, and a phase group selection circuit 2 N phase data selection circuit 6 for outputting only optimum discrimination phase sampling data selected by optimum phase selection circuit 7 from the selected phase group data as optimum phase data, and the bit rate of optimum phase data as a required bit And a data reproduction circuit (each data reproduction circuit 9, 10) that reproduces and outputs the rate signal.

The M [Hz] × N phase sampling circuit 1 generates an N phase clock of M [Hz] when the input data has a maximum bit rate M [bps] that can be input in synchronization with the system reference frequency. To N-phase oversample the input data.
Further, the M [Hz] × N phase sampling circuit 1 has an input data of 1 / S of M [bps] (S = 2 ^ (x), x = 0, 1, 2,...) M / When the bit rate data is S [bps], the input data is subjected to N × S phase oversampling.

When M / S [bps] data is input as input data, the phase group selection circuit 2 assigns N × S phase sampling data by N × S phase oversampling to S phase groups, and outputs S data. Among the phase group data, only sampling data for N phases of M / S [bps] is input to the optimum phase selection circuit as one phase group data.

When M / S [bps] data is input as input data, the edge phase detection circuit 3 detects the phase of the rising edge and the falling edge for each bit from the N × S phase sampling data, and determines the phase group The circuit 4 outputs one phase group from the selector circuit 5 based on the detection result of the rising edge and the falling edge.
Specifically, when M / S [bps] data is input as input data, the phase group determination circuit 4 extracts one phase group to which the center phase belongs from each phase of the rising edge and the falling edge. Then, only the center phase detected by one phase group is selected and output.

When M [bps] data is input as input data, the phase group selection circuit 2 passes N phase sampling data from the M [Hz] × N phase sampling circuit as one phase group data.
When the bit rate of the input data is M [bps], the data reproduction circuit uses the M [bps] data reproduction circuit 10 to reproduce M [bps] data.
Further, when the bit rate of the input data is M / S [bps], the data reproduction circuit reproduces M / S [bps] data by the M / S [bps] data reproduction circuit 9.

In addition, the multirate reproducing apparatus according to Embodiment 1 of the present invention includes a bit integration number determination circuit 8 that sets the bit integration number for the phase group determination circuit 4 and the optimum phase selection circuit 7, and includes a phase group The determination circuit 4 integrates the detection results of the edge phase detection circuit 3 by the number of bit integrations, determines the most frequent phase group as the optimal phase group, and the optimal phase selection circuit 7 sets the edge phase for each bit integration number. The most frequent phase is extracted as the edge phase.
Further, the optical access system is composed of a PON system, and the input data is composed of burst data.

As described above, in the oversampling CDR, when the low-speed data is input, the optimum discrimination phase of the optimum clock phase sampling output data while ensuring the sampling performance (pulse width distortion tolerance) corresponding to the oversampling resolution corresponding to the high-speed bit rate. By providing a means for simplifying the selection logic circuit (hereinafter abbreviated as “optimum phase selection circuit”) and enabling circuit mounting easily, it is possible to reduce the cost of the CDR circuit having the sampling performance equivalent to that of the conventional system. Power consumption can be realized.

Embodiment 2. FIG.
In the first embodiment (FIG. 1), the N phase data selection circuit 6 and the optimum phase selection circuit 7 are used. However, when there is almost no distortion or jitter in the input data, as shown in FIG. The functions of the N phase data selection circuit 6 and the optimum phase selection circuit 7 may be included in the functions in the phase group selection circuit 12 to simplify the overall circuit configuration.
Hereinafter, a multi-rate playback apparatus according to Embodiment 2 of the present invention will be described with reference to FIG.

FIG. 6 is a block diagram showing a multi-rate playback apparatus according to Embodiment 2 of the present invention.
In FIG. 6, the circuits 11 to 20 correspond to the circuits 1 to 10 described above (see FIG. 1).

The multi-rate playback device according to the second embodiment of the present invention is 1 / S (S = 2 ^ (x), x = 0, 1, 2, 3,...) With a bit rate of M [bps]. An M [Hz] × N phase sampling circuit 11 to which M / S [bps] data is input, a phase group selection circuit 12, a bit integration number determination circuit 18, an M / S [bps] data reproduction circuit 19, And an M [bps] data reproduction circuit 20.

The phase group selection circuit 12 includes an edge phase detection circuit 13, a phase group determination circuit 14, and a selector circuit 15.
The selector circuit 15 includes selector elements 15a to 15n corresponding to each of the N phases, and a selector element 16 that selects N phase data from the outputs of the selector elements 15a to 15n.
The selector element 16 includes the functions of the N phase data selection circuit 6 and the optimum phase selection circuit 7 described above (FIG. 1).

Next, the operation of the multirate playback apparatus according to Embodiment 2 of the present invention shown in FIG. 6 will be described in detail.
First, M / S [bps] data input from an optical receiver (not shown) is input to the M [Hz] × N phase sampling circuit 11, and the M [Hz] × N phase sampling circuit 11 Input data is sampled and output using [Hz] × N phase clock as a sampling clock.

Here, the M [Hz] × N phase clock is a phase # 0 to a phase # (shifted by 1 / N phase with respect to one bit width of M [bps] input data from a reference clock frequency-synchronized with the system clock. N-1) clock.
Therefore, from the M [Hz] × N phase sampling circuit 11, the frequency is synchronized with the system clock, and the phase is shifted by 1 / (N × S) phase from # 0 to # (N−1) × S. The data sampling result is output as N × S phase sampling data.

The N × S phase sampling data from the M [Hz] × N phase sampling circuit 11 is input to the phase group selection circuit 12.
In the phase group selection circuit 12, the edge phase detection circuit 13 detects the data edge phase from the input N × S phase sampling data and inputs it to the phase group determination circuit 14.

At this time, as described above, the data edge phase is one of the N × S phase sampling data for 1 bit, and the sampling data between adjacent phases is “... 0 → 1. In this case, the edge phase is uniquely determined in the edge phase detection with a 1-bit width.
If the edge phase is not detected, the edge phase detection circuit 13 latches and outputs the previous detection result.

As shown in FIGS. 2 and 3, the edge phase detection circuit 13 and the phase group determination circuit 14 have four phase groups A, B, and C having sampling data for eight phases each having a set of four phases. , Assign D.
For example, the edge phase detection circuit 13 detects the edge phase as shown in FIG. 2, and the phase group determination circuit 14 determines the phase group as shown in FIG.

Next, the operation of the phase group selection circuit 12 (edge phase detection circuit 13, phase group determination circuit 14 and selector circuit 15) will be described with reference to FIG.
In FIG. 4, the edge phase detection circuit 13 first detects the rising edge phase number <a> and the falling edge phase number <b> for each bit from 2.5 [Gbps] × 32 phase sampling data ( Step ST1).

Subsequently, the phase group determination circuit 14 extracts the center phase number <c> as an average value from the edge phase extraction result according to the above-described equation (1) (step ST2).
If the edge phase does not exist, the previous detection result is latched and used.

Next, the phase group determination circuit 14 integrates the determination results of the phase groups A, B, C, and D to which the determined center phase belongs by the number of bit integrations set by the bit integration number determination circuit 8 (step ST3) The phase group with the highest frequency is determined as the optimum phase group (step ST4).

In step ST4, when there are a plurality of the same number of phase groups and the majority is not decided by the majority decision, the phase group decision circuit 14 latches and uses the previous decision result.
Finally, the phase group determination circuit 14 notifies the selector circuit 15 only of the extracted data of the center phase number <c> (step ST5), and ends the processing routine of FIG.

As a result, the selector element 16 in the selector circuit 15 inputs the optimum phase data sampled at the optimum phase to the M / S [bps] data reproduction circuit 19.
The M / S [bps] data recovery circuit 19 outputs M / S [bps] data that is synchronized with the system clock and is timing-recovered by the M / S [Hz] clock generated inside the circuit.

Next, an operation when M [bps] bit rate data is input in FIG. 6 will be described.
When M [bps] data is input, the selector circuit 15 outputs all the phase group data, extracts only the center phase number <c> by the phase group determination operation (step ST5), and M [bps] data. The reproduction circuit 20 outputs only the center phase number data.
Thereafter, M [bps] data can be reproduced by the same operation as described above.

As described above, according to the second embodiment (FIG. 6) of the present invention, when there is almost no distortion or jitter in the input data, only the phase group determination circuit 14 in the phase group selection circuit 12 is used. By omitting the above-described optimum phase selection circuit 7 (FIG. 1), in addition to the above-described effects, the circuit scale can be further simplified and the power consumption can be reduced.

1, 11 M [Hz] × N phase sampling circuit, 2, 12 phase group selection circuit, 3, 13 edge phase detection circuit, 4, 14 phase group determination circuit, 5, 15 selector circuit, 6 N phase data selection circuit, 7 Optimal phase selection circuit, 8, 18 bit integration number determination circuit, 9, 19 M / S [bps] data reproduction circuit, 10, 20 M [bps] data reproduction circuit, 16 selector elements.

Claims

A multi-rate playback device that is provided in a master station device of an optical access system and uses the same sampling clock for a plurality of bit rate signals,
An M [Hz] × N-phase sampling circuit that oversamples input data from the master station device and outputs N-phase sampling data;
A phase group selection circuit including an edge phase detection circuit, a phase group determination circuit, and a selector circuit, which assigns the N phase sampling data to a required number of phase groups according to the bit rate of the input data and outputs one phase group When,
An optimum phase selection circuit for extracting a phase of data sampled at an optimum discrimination phase from the N phase sampling data;
An N-phase data selection circuit that outputs only optimum identification phase sampling data selected by the optimum phase selection circuit from the phase group data selected by the phase group selection circuit, as optimum phase data;
A data reproduction circuit that reproduces and outputs the bit rate of the optimum phase data to a required bit rate signal,
The M [Hz] × N phase sampling circuit is
When the input data has a maximum bit rate M [bps] that can be input in synchronization with a system reference frequency, an N-phase clock of M [Hz] is generated to oversample the input data by N-phase;
When the input data is composed of M / S [bps] bit rate data of 1 / S of M [bps] (S = 2 ^ (x), x = 0, 1, 2,...). , N × S phase oversampling the input data,
The phase group selection circuit assigns N × S phase sampling data by N × S phase oversampling to S phase groups when M / S [bps] data is input as the input data, Of the S phase group data, only sampling data for N phases of M / S [bps] is input as one phase group data to the optimum phase selection circuit,
The edge phase detection circuit detects a rising edge phase and a falling edge phase for each bit from the N × S phase sampling data when M / S [bps] data is input as the input data;
The multi-rate playback apparatus, wherein the phase group determination circuit causes the selector circuit to output one phase group based on the detection result of the rising edge and the falling edge.
The phase group determination circuit extracts one phase group to which a central phase belongs from each phase of the rising edge and the falling edge when M / S [bps] data is input as the input data, 2. The multi-rate reproducing apparatus according to claim 1, wherein only the center phase detected by the one phase group is selected and output.
The phase group selection circuit allows N phase sampling data from the M [Hz] × N phase sampling circuit to pass as one phase group data when M [bps] data is input as the input data. The multi-rate playback device according to claim 1, wherein:
The data reproduction circuit includes:
When the bit rate of the input data is M [bps], the data of M [bps] is reproduced, and when the bit rate of the input data is M / S [bps], the M / S [ 4. The multi-rate playback apparatus according to claim 1, wherein the multi-rate playback apparatus plays back the data of bps].
A bit integration number determination circuit for setting a bit integration number for the phase group determination circuit and the optimum phase selection circuit;
The phase group determination circuit integrates the detection results of the edge phase detection circuit by the number of bit integrations, and determines the most frequent phase group as the optimal phase group,
The said optimal phase selection circuit produces the histogram of an edge phase for every said bit integration number, and extracts the phase with the highest frequency as an edge phase, The any one of Claim 1 to 4 characterized by the above-mentioned. The multi-rate playback device described in 1.
The multi-rate playback apparatus according to any one of claims 1 to 5, wherein the optical access system is a PON system, and the input data is burst data.
The multi-rate playback device according to any one of claims 1 to 6, wherein the phase group selection circuit includes functions of the optimum phase selection circuit and the N phase data selection circuit.