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WO2013108706A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2013108706A1
WO2013108706A1 PCT/JP2013/050288 JP2013050288W WO2013108706A1 WO 2013108706 A1 WO2013108706 A1 WO 2013108706A1 JP 2013050288 W JP2013050288 W JP 2013050288W WO 2013108706 A1 WO2013108706 A1 WO 2013108706A1
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WO
WIPO (PCT)
Prior art keywords
lead frame
bonding
semiconductor device
bonding layer
semiconductor element
Prior art date
Application number
PCT/JP2013/050288
Other languages
English (en)
French (fr)
Inventor
藤野　純司
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to CN201380004427.2A priority Critical patent/CN104011843B/zh
Priority to US14/356,488 priority patent/US9142493B2/en
Priority to JP2013554280A priority patent/JP5657145B2/ja
Priority to KR1020147018045A priority patent/KR101609495B1/ko
Priority to DE112013000610.3T priority patent/DE112013000610B4/de
Publication of WO2013108706A1 publication Critical patent/WO2013108706A1/ja

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H01L2224/83825—Solid-liquid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a semiconductor device characterized by die bonding.
  • the power module is used in every scene from power generation / transmission to efficient use / regeneration of energy.
  • a silicon wafer on which a circuit has been formed is finely cut to form a Si chip (IC chip). This cut state is called a die.
  • the die is fixed at a predetermined position of the lead frame. This process is called die bonding.
  • Expensive equipment such as vacuum soldering equipment is used to suppress the occurrence of voids and unjoined parts in die bonding.
  • a process with a large number of steps such as scrubbing is also used, but the generation of voids has not been fundamentally solved.
  • the operating temperature becomes high, and therefore it is more important than ever to ensure heat dissipation at the die bond portion.
  • Patent Document 1 proposes a soldering method in which the bottom surface of a heat sink is processed into a pyramid shape to promote void removal during soldering. It is difficult to machine the back surface (die bond surface) on a brittle Si chip having a thickness of 100 ⁇ m, and even if it can, the processing strain affects the reliability.
  • Patent Document 2 proposes a method in which the solder is once pressed and spread to 50-90% of the joint area, and then the solder is melted and die-bonded. As long as the solder material as the joining material is completely melted as in the method disclosed herein, generation of large voids is inevitable even if scrubbing is performed.
  • Patent Document 3 proposes a method in which pads divided by slits are formed on a joint surface and high temperature solder is supplied to each pad.
  • the slit portion is completely unjoined.
  • the slit portion causes thermal damage.
  • Power modules are spreading in every product from transportation / industrial equipment to home appliances / information terminals.
  • power modules mounted on home appliances such as air conditioners are required not only for long-term reliability but also for miniaturization and high efficiency.
  • SiC semiconductors are expected to become the mainstream of future power modules in terms of high operating temperature and excellent efficiency. For this reason, development of the package form applicable also to a SiC semiconductor is calculated
  • the present invention has been made to solve these problems, and aims to improve the reliability of a die bond portion in a semiconductor device including a power module.
  • a semiconductor device is provided between a semiconductor element having a metallized layer formed on the back surface side, a metal lead frame disposed in parallel with the semiconductor element at an interval, and between the semiconductor element and the lead frame. And a first bonding layer bonded to the metallized layer, and a second bonding layer provided between the semiconductor element and the lead frame and bonding the first bonding layer and the lead frame. The central portion of the first bonding layer swells toward the lead frame.
  • the thickness of the die bond portion increases toward the outer edge due to the convex portion formed in the joint portion, so that voids generated in the joint material are positively discharged to the outside. As a result, the reliability of the die bond is improved.
  • FIG. 1 is a schematic configuration diagram showing a semiconductor device according to the present invention.
  • FIG. 3 is a conceptual diagram showing an initial step of a die bonding process according to the first embodiment.
  • FIG. 3 is a conceptual diagram showing a next step of the die bonding process according to the first embodiment.
  • FIG. 3 is a conceptual diagram showing a completed product of a die bonding process according to the first embodiment. It is a conceptual diagram which shows the void which generate
  • FIG. 10 is a conceptual diagram showing an initial step of a die bonding process according to a second embodiment. It is a conceptual diagram which shows the completed product of the die-bonding process by Embodiment 2.
  • FIG. 10 is a conceptual diagram showing an initial step of a die bonding process according to a second embodiment. It is a conceptual diagram which shows the completed product of the die-bonding process by Embodiment 2.
  • FIG. 10 is a conceptual diagram showing an initial step of a die bonding process according to a third embodiment.
  • FIG. 10 is a conceptual diagram showing a completed product of a die bond process according to a third embodiment. It is a conceptual diagram which shows the initial stage of the die-bonding process by Embodiment 4.
  • FIG. 10 is a conceptual diagram showing a completed product of a die bonding process according to a fourth embodiment.
  • FIG. 1 shows an overall configuration of a semiconductor device 100 called T-PM (transfer power mold).
  • the semiconductor device 100 includes a lead frame 4, a power element 11, a wire bond 12, a control element 13, an external lead 14, a mold resin 15, a heat sink 16, and the like.
  • the lead frame 4, the power element 11, the wire bond 12, the control element 13, and the heat sink 16 are resin-sealed with a mold resin 15.
  • the package type semiconductor device 100 is formed by setting a lead frame after bonding in a mold and pouring a thermosetting resin.
  • the power element 11 and the control element 13 may be formed of a wide band gap semiconductor having a band gap larger than that of silicon, in addition to those formed of silicon (Si).
  • the wide band gap semiconductor include silicon carbide (SiC), a gallium nitride material, and diamond.
  • FIG. 2 to 4 are conceptual diagrams showing a die bonding process of the semiconductor element according to the first embodiment.
  • a Si chip 1 having a size of 6 mm ⁇ 6 mm is used.
  • a metallized layer 2 is formed on the back surface of the Si chip 1 having a thickness of 0.2 mm, and a wire bond electrode 8 is formed on the front surface.
  • the configuration of the metallized layer 2 was Al / Ni / Au.
  • a solder paste of high-temperature solder (melting point: 240 ° C.) as a bonding material is printed on the surface of the metallized layer 2 (opening: 5 mm ⁇ 5 mm, thickness: 0.3 mm).
  • the solder paste Used to print and melt on a hot plate heated to 260 ° C.
  • the solder paste is obtained by kneading solder powder and flux.
  • the convex bonding layer 3 is formed on the back surface of the Si chip 1.
  • the composition of the convex bonding layer 3 is 95% Sn-5% Sb.
  • the convex bonding layer 3 has a gentle convex shape with a central thickness of about 0.2 mm.
  • a metal lead frame 4 is prepared.
  • a 0.6 mm thick Cu plate having a size of 10 mm ⁇ 10 mm was used for the lead frame 4.
  • solder paste 5 of low-temperature solder (melting point: 217 ° C.) as a bonding material onto the lead frame 4 using a printing mask (opening: 5 mm ⁇ 5 mm, thickness: 0.3 mm)
  • the Si chip 1 is mounted on the lead frame 4 with the convex bonding layer 3 facing down.
  • the solder paste 5 having a particle size of 15 to 25 ⁇ m and a flux content of 10 wt% was used.
  • the composition of the low-temperature solder is 96.5% Sn-3% Ag-0.5%.
  • the solder paste 5 of low-temperature solder is melted with a hot plate heated to 240 ° C. to form the concave bonding layer 6 (see FIG. 4).
  • the convex bonding layer 3 maintains a solid state. That is, the solidus temperature of the convex bonding layer 3 is higher than the solidus temperature of the concave bonding layer 6.
  • the Si chip 1 and the lead frame 4 are joined. Thereafter, the lead frame 4 is placed on the heat sink 16 and the wire bond electrode 8 of the Si chip 1 is connected to the external lead 14 and the like with a gold wire.
  • the wire-bonded Si chip 1 is molded with a mold resin 15.
  • the vaporized component in the flux of the solder paste 5 is gasified during heating to become bubbles. Since the liquid (molten solder) existing in the concave bonding layer 6 increases as the thickness of the concave bonding layer 6 increases toward the outer edge, the bubbles are positively discharged to the outside. This is because bubbles in the liquid tend to have a surface area as small as possible due to surface tension. If the bubbles have the same volume, the bubbles are changed to a state as close to a sphere as possible. As a result, a driving force that moves to the outer edge portion where the liquid has a large thickness acts on the bubbles.
  • the flat portion 74 was formed by pressing the apex portion of the convex bonding layer 3.
  • the flattening the central portion of the convex bonding layer 3 in a circular shape it is possible to suppress the inclination when the semiconductor element is mounted. If an inclination occurs at the time of joining, there is a concern about the occurrence of cracks associated with thermal stress in a portion where the joint height is small, but the occurrence of this crack is suppressed.
  • a flat void 72 remains in the vicinity of the apex of the convex bonding layer 3.
  • the flat void 72 is not only the thickness of the chip itself (0.2 mm) but also the thickness of the convex bonding layer 3 (0.2 mm) from the outermost surface where the heat generation of the Si chip 1 is the largest. It's far away. It is considered that the influence of the void 72 is small because the heat generation can be expected to spread sufficiently to reach that point. This effect can be expected to increase as the chip thickness decreases.
  • the convex surface of the convex bonding layer 3 has a spherical shape only in the vicinity of the center and the outer edge portion is a flat and low portion, the same effect can be obtained if a large void can be eliminated from the central portion where the temperature is highest. It is done. Further, a convex portion is formed by machining on the lead frame side on which the Si chip is mounted, and a further effect can be obtained if the joint portion can be inclined together with the convex portion of the Si chip.
  • the flat part 74 has a dimension of 5% or more of the entire bonding area, the inclination can be suppressed. When it becomes 50% or more of the entire bonding area, it becomes difficult to obtain a driving force for eliminating voids to the outside. Even if a void having the same area as the flat portion is generated, assuming that the thermal spread is 45 °, the thickness of the Si chip (0.2 mm) and the thickness of the convex bonding layer 3 (0.2 mm) are totaled. Since the thermal effect is almost negligible if it is less than a void having a diameter of 0.8 mm, which is twice the diameter of 0.4 mm, the dimension of the flat portion is preferably less than this.
  • the present application by using a high-temperature solder, it becomes easy to form the convex portion by the surface tension of the molten metal. Since the melting point is higher than that of the metal used for bonding, it is easy to ensure a situation in which the die bond portion becomes thicker toward the outer edge during the heating time for bonding.
  • high-temperature solder is supplied in advance, since it melts in an open state, voids having a diameter exceeding the thickness do not occur in principle. At the time of joining, the high-temperature solder does not melt, and voids generated in the melted low-temperature solder are rejected toward the outer edge having a wide gap.
  • solder paste of high temperature solder was used here, the same effect is acquired even if it supplies the solder and metal of a desired composition by plating, vapor deposition, dipping by immersion, etc. Moreover, the same effect is acquired by making it convex by remelting after metal supply.
  • SnSb was used as the high-temperature solder and SnAgCu solder was used as the low-temperature solder.
  • the same effect can be achieved by using a bonding material with a high refractory metal powder ratio as the high-temperature solder, and using a bonding material with the same or low refractory metal powder ratio or a bonding material that does not contain a refractory metal as the low-temperature solder.
  • the bonding material in which the high melting point metal powder and the low melting point metal powder are dispersed is a bonding material that has a small cohesive force due to a small amount of liquid components, and voids are unavoidable in closed joints.
  • the convex surface is formed in an open state, even if a bonding material made of a low melting point metal powder in which a high melting point metal powder is dispersed is used, there is almost no generation of large voids.
  • a bonding material made of a low melting point metal powder in which a high melting point metal powder is dispersed is used, there is almost no generation of large voids.
  • FIG. 6 and 7 are conceptual diagrams showing a die bonding process of a semiconductor device according to the second embodiment.
  • an aluminum jig 9 having a square pyramid opening 91 and an opening 92 is used.
  • the openings 91 and 92 are filled with solder paste of high-temperature solder, and the Si chip 1 is placed on the aluminum jig 9 with the metallized layer 2 facing down.
  • the solder paste of high-temperature solder filled in the openings 91 and 92 is melted to transfer the high-temperature solder to the metallized layer 2.
  • solder paste of low-temperature solder is printed and supplied to the lead frame 4 using a printing mask (opening: 5 mm ⁇ 5 mm, thickness: 0.3 mm), and the Si chip 1 is placed below the convex bonding layers 31 and 32. And placed on the lead frame 4.
  • solder paste 5 of low-temperature solder is melted with a hot plate heated to 240 ° C. to form the concave bonding layer 6 (see FIG. 7).
  • a convex convex bonding layer 31 having a smaller convex shape than the large convex convex bonding layer 32 at the center is formed on the back surface of the Si chip 1 corresponding to the wire bond electrode 8.
  • the convex bonding layer 31 suppresses the generation of voids directly under the wire bond electrode.
  • the capillary or tool used for the wire bond will step over the semiconductor element and be damaged. If the semiconductor element is thin, the rigidity is lowered, and if a void exists immediately below the wire bond electrode, the chip may be broken by the impact of the wire bond. A void can be excluded because the convex part of the convex joining layer 3 is located in the back surface.
  • FIG. 8 and 9 are conceptual diagrams showing a die bonding process of a semiconductor device according to the third embodiment.
  • an aluminum jig 9 having an opening in which an opening 91 and an opening 92 of a square weight are connected is used.
  • the openings 91 and 92 are filled with solder paste of high-temperature solder, and the Si chip 1 is placed on the aluminum jig 9 with the metallized layer 2 facing down.
  • the solder paste of high-temperature solder filled in the openings 91 and 92 is melted to transfer the high-temperature solder to the metallized layer 2.
  • solder paste of low-temperature solder is supplied by printing using a printing mask (opening: 5 mm ⁇ 5 mm, thickness: 0.3 mm), and the Si chip 1 is placed on the lead frame with the convex bonding layers 31 and 32 facing down. 4 is installed.
  • the solder paste of low-temperature solder is melted with a hot plate heated to 240 ° C. to form the concave bonding layer 6 (see FIG. 9).
  • the small convex convex bonding layer 31 and the central convex convex bonding layer 32 are connected. Since the metallized layer (Si chip electrode) 2 is not exposed during the formation of the concave bonding layer 6, even if voids are generated between the convex portions, the heat dissipation is hardly affected.
  • FIG. 10 and 11 are conceptual diagrams showing a die bonding process of a semiconductor device according to the fourth embodiment.
  • the solder paste 5 of low-temperature solder used for bonding is printed in 36 parts.
  • the solder paste 5 is heated at a temperature that maintains the shape as it is, and the solder paste 5 is bonded to the convex bonding layer 3.
  • the concave joining layer 6 of low-temperature solder is formed in a divided state (see FIG. 11). By allowing the gap 62 to remain in the concave bonding layer 6, it is possible to form a bonding portion that is more flexible and excellent in temperature cycle characteristics.
  • the convex bonding layer 3 is formed on the Si chip side, but an enclosure that limits the wet range with a solder resist or the like is formed on the lead frame side, and a convex surface of high-temperature solder is formed on the lead frame side or both surfaces.
  • the same effect can be obtained.
  • the high temperature solder was used as what forms a convex surface state, the same effect can be obtained even if the convex surface state is formed by pressing a mold by using an adhesive containing a metal filler such as an Ag paste.
  • the convex surface of the convex bonding layer 3 is ideally spherical, but even if a part of the apex is flat, the same effect can be obtained if the vicinity of the outer edge portion is gently reduced.
  • the semiconductor device 100 When SiC is used for the Si chip 1, the semiconductor device 100 is operated at a higher temperature than in the case of Si in order to take advantage of its characteristics. In a semiconductor device on which an SiC device is mounted, since higher reliability is required as a semiconductor device, the merit of the present invention for realizing a highly reliable semiconductor device becomes more effective.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

【課題】半導体装置におけるダイボンドの信頼性を向上することを目的にしている。 【解決手段】　裏面側にメタライズ層が形成されている半導体素子と、半導体素子と間隔を隔てて平行に配置された金属製のリードフレームと、半導体素子とリードフレームの間に設けられ、メタライズ層に接合されている第１の接合層と、半導体素子とリードフレームの間に設けられ、第１の接合層とリードフレームを接合する第２の接合層とを備えている半導体装置。第１の接合層は、リードフレームに向かって中央部が膨らんでいる。

Description

半導体装置および半導体装置の製造方法
　この発明は、ダイボンディングに特徴のある半導体装置に関する。
　パワーモジュールは発電・送電からエネルギーの効率的な利用・再生まであらゆる場面で利用されている。このような半導体装置を製造するには、先ず回路形成をしたシリコンウェハーを細かくカットして、Ｓｉチップ（ＩＣチップ）を形成する。このカットされた状態をダイスと呼ぶ。ダイスはリードフレームの所定の位置に固定される。この工程をダイボンディングという。
　パワーモジュールをはじめとする半導体素子では小型化が進んでいる。発熱密度が高くなるにつれて、ダイボンド部の品質（ボイドや未接合部の有無）が放熱性に大きな影響を与えるようになった。今後、高効率化のためＩＣチップの薄型化が進むと考えられている。半導体素子自体で熱を拡散することは難しいため、ダイボンド部の品質は放熱性により顕著な影響を与えるものと考えられる。
　ダイボンディングにおけるボイドや未接合部の発生を抑制するために、真空はんだ付け装置などの高額な装置が用いられている。スクラブを行うなど工程数の大きなプロセスも用いられているが、ボイドの発生は根本的には解決されていない。高性能なＳｉＣ半導体においては、動作温度が高くなるため、ダイボンド部における放熱性の確保がこれまで以上に重要になる。
　特許文献１には、ヒートシンクの底面を角錐状に加工し、はんだ付け時のボイドの抜けを促進するはんだ付け方法が提案されている。裏面（ダイボンド面）の機械加工を、薄さ１００μｍの脆いＳｉチップに対して行うことは困難で、できたとしても加工ひずみは信頼性に影響を与える。
　特許文献２では、はんだを一旦接合面積の５０-９０％までプレスして広げてから、そのはんだを溶融させてダイボンドする方法が提案されている。ここで開示される方法のように接合材料としてのはんだ材が全量溶融する限り、スクラブを行ったとしても大きなボイドの発生は避けられない。
　特許文献３は、接合面にスリットによって分割されたパッドを形成し、それぞれに高温はんだを供給する方法を提案している。スリット部分は完全に未接合部となる。発熱が大きく、チップの薄型化によって熱の拡散が期待できない場合には、スリット部が熱損傷の原因となる。
特開平０７－２９７３２９号公報 特開２００６－１１４６４９号公報 特開２００３－０６８９３０号公報
　輸送・産業機器から家電・情報端末に至るあらゆる製品でパワーモジュールの普及が進んでいる。特に、エアコンなどの家電に搭載されるパワーモジュールについては、長期信頼性だけではなく、小型化と高効率化が求められている。ＳｉＣ半導体は、動作温度が高く、効率に優れている点で、今後のパワーモジュールの主流になると予想されている。このためＳｉＣ半導体にも適用できるパッケージ形態の開発が求められている。
　この発明はこれらの課題を解決するためになされたものであり、パワーモジュールを含む半導体装置におけるダイボンド部の信頼性を向上することを目的にしている。
　本願に関わる半導体装置は、裏面側にメタライズ層が形成されている半導体素子と、半導体素子と間隔を隔てて平行に配置された金属製のリードフレームと、半導体素子とリードフレームの間に設けられ、メタライズ層に接合されている第１の接合層と、半導体素子とリードフレームの間に設けられ、第１の接合層とリードフレームを接合する第２の接合層とを備えている。第１の接合層は、リードフレームに向かって中央部が膨らんでいる。
　接合部に形成された凸部によって、ダイボンド部は外縁に行くほど厚さが大きくなるため、接合材料中に発生したボイドは積極的に外部に排斥される。この結果、ダイボンドの信頼性が向上する。
本発明にかかわる半導体装置を示す概略構成図である。 実施の形態1によるダイボンドプロセスの初期工程を示す概念図である。 実施の形態1によるダイボンドプロセスの次工程を示す概念図である。 実施の形態1によるダイボンドプロセスの完成品を示す概念図である。 ダイボンド部において発生するボイドを示す概念図である。 実施の形態２によるダイボンドプロセスの初期工程を示す概念図である。 実施の形態２によるダイボンドプロセスの完成品を示す概念図である。 実施の形態３によるダイボンドプロセスの初期工程を示す概念図である。 実施の形態３によるダイボンドプロセスの完成品を示す概念図である。 実施の形態４によるダイボンドプロセスの初期工程を示す概念図である。 実施の形態４によるダイボンドプロセスの完成品を示す概念図である。
実施の形態１．
　図１に、Ｔ－ＰＭ（トランスファーパワーモールド）と呼ばれている半導体装置１００の全体構成を示す。半導体装置１００は、リードフレーム４、パワー素子１１、ワイヤボンド１２、制御素子１３、外部リード１４、モールド樹脂１５、ヒートシンク１６などから構成されている。リードフレーム４、パワー素子１１、ワイヤボンド１２、制御素子１３、ヒートシンク１６はモールド樹脂１５で樹脂封止されている。パッケージタイプの半導体装置１００は、ボンディングの終わったリードフレームを金型にセットして、熱硬化性の樹脂を流し込んで成形される。
　リードフレーム４に、パワー素子１１などの半導体素子を接合するダイボンドプロセスを図２～図１１を用いて説明する。パワー素子１１および制御素子１３は、珪素（Ｓｉ）によって形成されたものの他、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成しても良い。ワイドバンドギャップ半導体としては、例えば、炭化珪素（ＳｉＣ）、窒化ガリウム系材料またはダイヤモンドがある。ワイドバンドギャップ半導体を用いた場合、許容電流密度が高く、電力損失も低いため、電力用半導体素子を用いた装置の小型化が可能となる。
　図２から図４は実施の形態１による半導体素子のダイボンドプロセスを示す概念図である。図２において、Ｓｉチップ1には６mm×６mmの大きさのものを使用している。厚さ０．２mmのＳｉチップ１の裏面にはメタライズ層２が、表面にはワイヤボンド電極８が形成されている。メタライズ層２の構成は、Ａｌ／Ｎｉ／Ａｕとした。Ｓｉチップ１の表面を下にして、接合材である高温はんだ（融点：２４０℃）のソルダペーストをメタライズ層２の表面に印刷マスク（開口部：５mm×５mm、厚さ：０．３mm）を用いて印刷供給し、２６０℃に加熱したホットプレートにて溶融させる。ソルダペーストは、ソルダパウダーとフラックスを混練したものである。その結果、Ｓｉチップ１の裏面に凸状接合層３が形成される。凸状接合層３の組成は９５％Ｓｎ-５％Ｓｂである。凸状接合層３は中央部の厚さが約０．２mmのなだらかな凸面形状を有する。
　次に図３に示すように、金属製のリードフレーム４を用意する。ここでは、リードフレーム４に、１０mm×１０mmの大きさを有する厚さ０．６mmのＣｕ板を使用した。リードフレーム４の上に、接合材である低温はんだ（融点：２１７℃）のソルダペースト５を、印刷マスク（開口部：５mm×５mm、厚さ：０．３mm）を用いて印刷供給したあと、Ｓｉチップ１を凸状接合層３を下にしてリードフレーム４に搭載する。ソルダペースト５は、粒径１５～２５μm、フラックス含有率１０ｗｔ％のものを用いた。低温はんだの組成は９６．５％Ｓｎ-３％Ａｇ-０．５％である。
　最後に、２４０℃に加熱したホットプレートにて、低温はんだのソルダペースト５を溶融させて凹状接合層６を形成する（図４参照）。低温はんだが溶融状態の場合でも、凸状接合層３は固体状態を保つ。すなわち、凸状接合層３の固相線温度は、凹状接合層６の固相線温度よりも高い。この工程で、Ｓｉチップ１とリードフレーム４が接合される。このあと、リードフレーム４はヒートシンク１６に載置され、Ｓｉチップ１のワイヤボンド電極８を金線で外部リード１４などと繋ぐ。ワイヤーボンディングされたＳｉチップ１はモールド樹脂１５でモールド成形される。
　ソルダペースト５のフラックス中の気化成分は、加熱中にガス化して気泡となる。凹状接合層６に存在する液体（溶融はんだ）は、凹状接合層６の厚さが外縁に行くに従って大きくなっているため、気泡は外部へ積極的に排斥される。これは、液体中の気泡は表面張力によってなるべく表面積が小さい状態になろうとするためである。気泡が同じ体積であればなるべく球形状に近い状態に変化する結果、気泡には、液体の厚みが大きい外縁部へ移動する駆動力が作用する。仮に気泡（ボイド）が凹状接合層６に残ったとしても、外縁部近傍に形成される球形ボイド７１がほとんどである（図５参照）。球形ボイド７１は、直径が凹状接合層６の厚さよりも十分に小さいため、接合部の厚さとほぼ同じ高さの円柱形状のボイドと比較すると放熱性に与える影響は極めて小さい。
　図５に示す凸状接合層３は、中央に直径０．８mmの平坦部７４を有する。平坦部７４は、凸状接合層３の頂点部分をプレス加工することによって形成した。凸状接合層３の中央部を円形に平坦化することで、半導体素子搭載時の傾きを抑制することが可能となる。接合時に傾きが生じると、接合部高さの小さい部分では熱応力に伴うクラックの発生などが懸念されるが、このクラックの発生が抑制される。
　仮に図５に示すように、凸状接合層３の頂点付近に扁平状のボイド７２が残存していたとする。扁平状のボイド７２は、Ｓｉチップ１の発熱の最も大きな最表面からは、チップ自体の厚さ（０．２mm）だけでなく、凸状接合層３の厚さ（０．２mm）の分だけ遠くはなれている。発熱はそこに至るまでに十分に広がりを期待できるため、ボイド７２の影響は小さいと考えられる。この効果は、チップ厚さが薄くなるほどに大きくなると期待できる。
　凸状接合層３の凸面は中央付近だけが球面状となっていて、外縁部は平坦な低い部分となっていても、最も温度が高くなる中心部から大きなボイドを排斥できれば同様の効果が得られる。また、Ｓｉチップを搭載するリードフレーム側に機械加工によって凸部が形成されており、Ｓｉチップの凸部とあわせて接合部に傾斜をつけることができればさらなる効果が得られる。
　平坦部７４の寸法としては、接合面積全体の５％以上あれば傾きの抑制が可能となる。接合面積全体の５０％以上になると外部へボイドを排斥する駆動力は得にくくなる。もし平坦部と同じ面積のボイドが発生したとしても、熱広がりを４５°と仮定すると、Ｓｉチップの厚さ（０．２mm）と、凸状接合層３の厚さ（０．２mm）を合計した０．４mmを２倍した０．８mmを直径とするボイド以下であれば、熱的な影響はほとんど無視できるため、平坦部の寸法としてはこれ以下が望ましい。
　本願によれば、高温はんだを用いることで、溶融した金属による表面張力で凸部の形成が容易となる。接合に用いる金属よりも融点が高いことで、ダイボンド部が外縁に行くほど厚くなる状況を接合のための加熱時間中に確保しやすい。あらかじめ高温はんだを供給する際には、開放された状態で溶融するため、原理的に厚さを超えるような直径のボイドは発生しない。接合時には高温はんだは溶融せず、溶融した低温はんだ内に発生したボイドは、隙間の広い外縁部に向かって排斥される。
　なお、ここでは高温はんだのソルダペーストを用いたが、所望の組成のはんだや金属を、めっきや蒸着、浸漬によるディップなどで供給しても、同様の効果が得られる。また、金属供給後に再溶融するなどして凸面状態にすることで同様の効果が得られる。ここでは高温はんだとしてＳｎＳｂ、低温はんだとしてＳｎＡｇＣｕはんだを用いたが、融点の温度差があるはんだの組み合わせであれば、ＳｎＡｇＣｕ（融点：２１７℃）／ＳｎＢｉ（融点：１４０℃）やＡｕＳｎ（融点：２８０℃）／ＳｎＳｂ（融点：２４０℃）などの組み合わせでも同様の効果が得られる。
　高融点金属粉を分散させた低融点金属粉からなる接合材料、例えば、旭化成イーマテリアルズ社のＡ-ＦＡＰを用いることが可能である。この接合材料は、一旦加熱して凝集すると、同じ温度まで加熱しても再溶融しないため、凸部形成に用いる接合材料と、接合に用いる接合材料が同じでも同様の効果が得られる。高温はんだとして、高融点金属粉比率の高い接合材料を用い、低温はんだとして、高融点金属粉比率が同じかまたは低い接合材料や、高融点金属を含まない接合材料を用いることで同様の効果を得ることができる。高融点金属粉と低融点金属粉を分散させた接合材料は、液体成分が少ないために凝集力が小さく、閉じられた接合部ではボイドの発生が不可避な接合材料である。実施の形態１によれば開放された状態で凸面を形成するため、高融点金属粉を分散させた低融点金属粉からなる接合材料を用いたとしても大きなボイドの発生がほとんどない。比較的ボイドの少ない高融点金属粉を少なく含む接合材料を用いて接合することで、接合部厚さに匹敵する厚さのボイド形成を抑制して、放熱性を確保することができる。
実施の形態２．
　図６と図７は実施の形態２による半導体素子のダイボンドプロセスを示す概念図である。実施の形態２では、図６に示すように、四角錘の開口部９１および開口部９２を有するアルミ製治具９を用いる。開口部９１、９２には高温はんだのソルダペーストを充填し、メタライズ層２を下にして、Ｓｉチップ１をアルミ製治具９に載置する。開口部９１、９２に充填した高温はんだのソルダペーストを溶融させてメタライズ層２に高温はんだを転写する。次いで、低温はんだのソルダペーストを、印刷マスク（開口部：５mm×５mm、厚さ：０．３mm）を用いてリードフレーム４に印刷供給し、Ｓｉチップ１を凸状接合層３１、３２を下にしてリードフレーム４に載置する。
　最後に、２４０℃に加熱したホットプレートにて、低温はんだのソルダペースト５を溶融させて凹状接合層６を形成する（図７参照）。ワイヤボンド電極８に対応したＳｉチップ１の裏面には、中央の大きな凸状の凸状接合層３２に比較して小さな凸状の凸状接合層３１が形成されている。凸状接合層３１はワイヤボンド電極直下に局所的にボイドが発生することを抑制する。
　ワイヤボンド部にボイドがあると、ワイヤボンドに使用するキャピラリやツールが半導体素子を踏み抜いて破損する懸念がある。半導体素子が薄くなることで剛性が低下し、ワイヤボンド電極の直下にボイドが存在すると、ワイヤボンドの衝撃によってチップが破断することも考えられる。凸状接合層３の凸部がその裏面に位置することでボイドを排除することができる。
実施の形態３．
　図８と図９は実施の形態３による半導体素子のダイボンドプロセスを示す概念図である。実施の形態３では、図８に示すように、四角錘の開口部９１と開口部９２が連結された開口部を有するアルミ製治具９を用いる。開口部９１、９２には高温はんだのソルダペーストを充填し、メタライズ層２を下にして、Ｓｉチップ１をアルミ製治具９に載置する。開口部９１、９２に充填した高温はんだのソルダペーストを溶融させてメタライズ層２に高温はんだを転写する。次いで、低温はんだのソルダペーストを、印刷マスク（開口部：５mm×５mm、厚さ：０．３mm）を用いて印刷供給し、Ｓｉチップ１を凸状接合層３１、３２を下にしてリードフレーム４に搭載する。
　最後に、２４０℃に加熱したホットプレートにて、低温はんだのソルダペーストを溶融させて凹状接合層６を形成する（図９参照）。アルミ製治具９の開口部を連結することで、小さな凸状の凸状接合層３１と中央の凸状の凸状接合層３２が連結される。凹状接合層６を形成中に、メタライズ層（Ｓｉチップ電極）２が露出しないため、凸部間にボイドが発生しても放熱性に影響が出にくい。
実施の形態４．
　図１０と図１１は実施の形態４による半導体素子のダイボンドプロセスを示す概念図である。実施の形態４では、図１０に示すように、接合に用いる低温はんだのソルダペースト５を、３６分割して印刷供給する。ソルダペースト５がそのままの形状を保つ温度で加熱して、ソルダペースト５を凸状接合層３に接合する。低温はんだの凹状接合層６は分割された状態で形成される（図１１参照）。凹状接合層６に隙間６２が残るようにすることで、より柔軟で温度サイクル性に優れた接合部を形成することが可能となる。この際、低温はんだのソルダペーストの液状成分を少なくしたり、高融点金属粉を分散させた低融点金属粉からなる接合材料を用いることで、接合前後の形状の変化を抑えることが可能である。
　なお、ここでは、凸状接合層３をＳｉチップ側に形成したが、リードフレーム側にソルダレジストなどでぬれ範囲を制限する囲いを形成し、リードフレーム側あるいは両面に高温はんだの凸面を形成しても、同様の効果が得られる。また、凸面状態を形成するものとして高温はんだを用いたが、Ａｇペーストなど金属フィラーを含んだ接着剤などを用い、型を押し付けるなどして凸面状態を形成しても、同様の効果が得られる。凸状接合層３の凸面は球面が理想的であるが、頂点の一部が平坦であっても、外縁部近傍がなだらかに高さが小さくなっていれば同様の効果が得られる。
　Ｓｉチップ１にＳｉＣを用いた場合、半導体装置１００はその特徴を生かすべくＳｉの時と比較してより高温で動作させることになる。ＳｉＣデバイスを搭載する半導体装置においては、半導体装置としてより高い信頼性が求められるため、高信頼の半導体装置を実現するという本発明のメリットはより効果的なものとなる。
　なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。
　１　Ｓｉチップ、２　メタライズ層、３　凸状接合層、
　４　リードフレーム、５　ソルダペースト、６　凹状接合層、
　７１～７３　ボイド、８　ワイヤボンド電極、９　アルミ製治具、
　１５　モールド樹脂、３１　凸状接合層、３２　凸状接合層、６２　隙間

Claims (11)

  1. 　裏面側にメタライズ層が形成されている半導体素子と、
    前記半導体素子と間隔を隔てて平行に配置された金属製のリードフレームと、
    前記半導体素子と前記リードフレームの間に設けられ、前記メタライズ層に接合されている第１の接合層と、
    前記半導体素子と前記リードフレームの間に設けられ、前記第１の接合層と前記リードフレームを接合する第２の接合層とを備え、
    前記第１の接合層は、前記リードフレームに向かって中央部が膨らんでいることを特徴とする半導体装置。
  2. 　前記第１の接合層は、前記第２の接合層よりも、融点が高いことを特徴とする請求項１に記載の半導体装置。
  3. 　前記半導体素子は、表面側にワイヤボンド電極が形成されていることを特徴とする請求項１に記載の半導体装置。
  4. 　前記第１の接合層は、前記ワイヤボンド電極と前記リードフレームに挟まれた部分が前記リードフレームに向かって膨らんでいることを特徴とする請求項３に記載の半導体装置。
  5. 　前記第１の接合層は、膨らんでいる中央部の頂部が平坦化されていることを特徴とする請求項１に記載の半導体装置。
  6. 　前記第２の接合層は、空隙によって複数の区画に分割されていることを特徴とする請求項１に記載の半導体装置。
  7. 　前記半導体素子は、ワイドバンドギャップ半導体により形成されていることを特徴とする請求項１に記載の半導体装置。
  8. 　前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料、ダイヤモンドのいずれかの半導体であることを特徴とする請求項７に記載の半導体装置。
  9. 　半導体素子の裏面側に形成されたメタライズ層にペースト状の第１の接合材を供給する工程と、
    前記第１の接合材が供給されたメタライズ層を下側にして前記半導体素子を加熱する工程と、
    金属製のリードフレームにペースト状の第２の接合材を供給する工程と、
    前記第２の接合材が供給されたリードフレームに前記加熱された半導体素子を裏面側を下向きにして載置する工程と、
    前記リードフレームに載置された前記半導体素子を加熱する工程とを備えている半導体装置の製造方法。
  10. 　前記第１の接合材は第１の金属粉を含んでなり、しかも、前記第２の接合材は前記第１の金属粉よりも融点の低い第２の金属粉を含んでなることを特徴とする請求項９に記載の半導体装置の製造方法。
  11. 　前記第１の接合材は、高融点金属粉を分散させた低融点金属粉を含んでなることを特徴とする請求項９に記載の半導体装置の製造方法。
PCT/JP2013/050288 2012-01-18 2013-01-10 半導体装置および半導体装置の製造方法 WO2013108706A1 (ja)

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Families Citing this family (7)

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WO2017006840A1 (ja) * 2015-07-07 2017-01-12 日立オートモティブシステムズ株式会社 半導体装置、力学量測定装置および半導体装置の製造方法
US9818677B2 (en) * 2015-07-24 2017-11-14 Semiconductor Components Industries, Llc Semiconductor component having group III nitride semiconductor device mounted on substrate and interconnected to lead frame
US9929066B1 (en) * 2016-12-13 2018-03-27 Ixys Corporation Power semiconductor device module baseplate having peripheral heels
IT201700039221A1 (it) * 2017-04-10 2018-10-10 Carel Ind Spa Metodo di saldatura di un componente di potenza su una piazzola di pcb
JP7017098B2 (ja) * 2018-03-06 2022-02-08 株式会社デンソー 半導体装置
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0319247A (ja) * 1989-06-15 1991-01-28 Mitsubishi Electric Corp 半導体装置製造時の半田付け方法
JP2002158238A (ja) * 2000-11-16 2002-05-31 Mitsubishi Electric Corp 電子部品の接合方法、電子装置の製造方法、及び電子装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297329A (ja) 1994-04-25 1995-11-10 Matsushita Electric Works Ltd ヒートシンク
JP3461632B2 (ja) 1995-08-28 2003-10-27 三菱電機株式会社 半導体レーザ装置
JP2003068930A (ja) 2001-08-27 2003-03-07 Mitsubishi Electric Corp 基板の接合構造およびその製造方法
JP2006114649A (ja) 2004-10-14 2006-04-27 Fuji Electric Device Technology Co Ltd 半導体装置の製造方法およびその製造装置
JP2010103206A (ja) 2008-10-22 2010-05-06 Panasonic Corp 半導体装置及びその製造方法
US8314473B2 (en) 2010-05-04 2012-11-20 Fairchild Semiconductor Corporation Die backside standoff structures for semiconductor devices
US9768120B2 (en) * 2012-11-21 2017-09-19 Infineon Technologies Austria Ag Semiconductor device assembly including a chip carrier, semiconductor wafer and method of manufacturing a semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0319247A (ja) * 1989-06-15 1991-01-28 Mitsubishi Electric Corp 半導体装置製造時の半田付け方法
JP2002158238A (ja) * 2000-11-16 2002-05-31 Mitsubishi Electric Corp 電子部品の接合方法、電子装置の製造方法、及び電子装置

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CN104011843A (zh) 2014-08-27
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US9142493B2 (en) 2015-09-22
US20140367701A1 (en) 2014-12-18
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JPWO2013108706A1 (ja) 2015-05-11
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