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WO2013157172A1 - Semiconductor package and method for producing same, semiconductor module, and semiconductor device - Google Patents

Semiconductor package and method for producing same, semiconductor module, and semiconductor device Download PDF

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Publication number
WO2013157172A1
WO2013157172A1 PCT/JP2013/000155 JP2013000155W WO2013157172A1 WO 2013157172 A1 WO2013157172 A1 WO 2013157172A1 JP 2013000155 W JP2013000155 W JP 2013000155W WO 2013157172 A1 WO2013157172 A1 WO 2013157172A1
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WO
WIPO (PCT)
Prior art keywords
lead frame
semiconductor
semiconductor element
semiconductor package
package according
Prior art date
Application number
PCT/JP2013/000155
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French (fr)
Japanese (ja)
Inventor
靖治 辛島
昌己 中川
則充 穗積
武 鈴木
中谷　誠一
崎山　一幸
Original Assignee
パナソニック株式会社
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Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2013157172A1 publication Critical patent/WO2013157172A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for individual devices of subclass H10D
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83205—Ultrasonic bonding
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a semiconductor element packaging technology, for example, a semiconductor package used for an inverter device for a motor, a power conditioner for solar power generation or wind power generation, a manufacturing method thereof, a semiconductor module, and a semiconductor device.
  • IGBTs Insulated Gate Bipolar Transistors
  • MOS-FETs Metal Oxide Semiconductor Semiconductor Field Effect Transistors
  • FIG. 18 is a perspective view showing the structure of a conventional semiconductor module.
  • the conventional semiconductor module includes an insulating substrate 101.
  • the insulating substrate 101 is composed of, for example, a laminate of an aluminum nitride (AlN) plate and a copper plate.
  • a power semiconductor element 102 is joined to one main surface of the insulating substrate 101 by soldering.
  • the power semiconductor element 102 is connected to an electrode of a component outside the semiconductor module through a wire or an external terminal 103.
  • a heat radiating plate 104 that releases heat generated from the power semiconductor element 102 through the insulating substrate 101 is joined to the other main surface of the insulating substrate 101 by solder.
  • a control circuit board 105 is disposed above one main surface of the insulating substrate 101.
  • the insulating substrate 101 and the control circuit substrate 105 are connected by wires or internal terminals 106.
  • a control component 107 for controlling the power semiconductor element 102 and the like are mounted on the control circuit board 105.
  • the parts are housed in the case 108.
  • the case 108 is filled with a sealing member such as silicone gel.
  • the case 108 is covered with a lid 109.
  • semiconductor modules mounted on hybrid cars and electric cars are required to be further miniaturized.
  • the semiconductor module is downsized, the amount of heat per unit area increases.
  • the thermal expansion coefficient of the power semiconductor element 102 is 3 ppm / K
  • the thermal expansion coefficient of the insulating substrate 101 is 4 to 5 ppm / K
  • the thermal expansion coefficient of the heat sink 104 is 17 ppm, for example. / K. That is, the coefficient of thermal expansion of each part is greatly different. For this reason, when the amount of heat generated in the semiconductor module increases, the thermal stress near the interface between these components increases, causing problems such as deformation or breakage of each component. Therefore, there is a demand for a semiconductor module that can improve heat dissipation performance and can reduce thermal stress.
  • the wiring connecting the semiconductor elements and the control circuit board becomes complicated and long. In this case, it is difficult to fix the wiring and it is easy to be affected by noise. For this reason, a semiconductor module capable of shortening the wiring is demanded.
  • Patent Document 1 Japanese Patent No. 4189666 discloses a semiconductor module having a structure in which a conductive portion for connecting electrodes to each other and a component storage hole for storing a semiconductor element are provided between a metal substrate portion and a control substrate portion. Is disclosed. According to the semiconductor module of Patent Document 1, the wiring can be shortened. However, in the semiconductor module of Patent Document 1, the heat of the semiconductor element is radiated through the metal substrate portion (that is, the heat radiation direction is one direction), and the heat of the semiconductor element cannot be sufficiently radiated. Moreover, no measures are taken for thermal stress. Therefore, the semiconductor module of Patent Document 1 still has room for improvement.
  • an object of the present invention is to solve the above-described conventional problems, and a semiconductor package, a manufacturing method thereof, and a semiconductor module capable of realizing improvement in heat dissipation capability, relaxation of thermal stress, and shortening of wiring. And providing a semiconductor device.
  • a semiconductor package includes: A first lead frame; A second lead frame arranged to face the first lead frame; A semiconductor element disposed between the first and second lead frames; A sealing member for sealing a gap between the first and second lead frames and the semiconductor element; A semiconductor package comprising: At least one of the first and second lead frames is formed such that the thickness in the vicinity of the portion connected to the semiconductor element is thinner than the thickness of the other portion.
  • the second lead frame includes a plurality of input / output terminals for inputting / outputting a plurality of signals to / from the semiconductor element, At least one of the plurality of input / output terminals protrudes from the second lead frame toward the first lead frame, and is inserted into a hole provided in the first lead frame. It is electrically connected to the first lead frame and is configured to maintain the relative position of the first and second lead frames.
  • a manufacturing method of a semiconductor package includes: A plurality of input / output terminals provided in the second lead frame are inserted into a plurality of holes provided in the first lead frame, and at least one of the plurality of input / output terminals is connected to the first lead frame. Connected to A semiconductor element is inserted into a space formed between the first lead frame and the second lead frame; Connecting the semiconductor element with a portion having a smaller thickness than the other portion provided on at least one of the first and second lead frames; Sealing a gap between the first and second lead frames and the semiconductor element with a sealing member; Partially etching the second lead frame; Including that.
  • the semiconductor package and the method for manufacturing the same by having the above-described configuration, it is possible to improve the heat dissipation capability, relax the thermal stress, and shorten the wiring.
  • FIG. 1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.
  • FIG. 2A is a cross-sectional view illustrating the method of manufacturing the semiconductor package according to the first embodiment of the present invention.
  • FIG. 2B is a cross-sectional view showing a step following FIG. 2A.
  • FIG. 2C is a cross-sectional view showing a step following FIG. 2B.
  • FIG. 2D is a cross-sectional view showing a step following FIG. 2C.
  • FIG. 2E is a cross-sectional view showing a step following FIG. 2D.
  • FIG. 1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.
  • FIG. 2A is a cross-sectional view illustrating the method of manufacturing the semiconductor package according to the first embodiment of the present invention.
  • FIG. 2B is a cross-sectional view showing a step following FIG. 2A.
  • FIG. 2C is a cross-section
  • FIG. 2F is a cross-sectional view showing a step following FIG. 2E.
  • FIG. 2G is a cross-sectional view showing a step following FIG. 2F.
  • FIG. 3 is a plan view showing a state where the upper and lower lead frames are connected to the semiconductor element
  • 4 is a cross-sectional view showing a state in which one of a plurality of input / output terminals connected to the upper lead frame is separated from the lower lead frame in the semiconductor package of FIG.
  • FIG. 5 is a cross-sectional view showing a configuration of a semiconductor module in which a heat sink is attached to the semiconductor package of
  • FIG. 6 is a cross-sectional view showing a configuration of a semiconductor module in which a control circuit board is attached to the semiconductor package of FIG.
  • FIG. 7 is a cross-sectional view showing a configuration of a semiconductor module in which a metal structure is attached to the semiconductor package of FIG.
  • FIG. 8A is a plan view schematically showing a configuration example of a semiconductor package including two semiconductor elements, and is a view of the lower half of the semiconductor package as viewed from above;
  • FIG. 8B is a plan view schematically showing a configuration example of a semiconductor package including two semiconductor elements, and is a plan view of the semiconductor package as viewed from above.
  • FIG. 9 is a cross-sectional view illustrating a configuration example of a semiconductor module including two semiconductor packages of FIG.
  • FIG. 10 is a cross-sectional view schematically showing the structure of the semiconductor package according to the second embodiment of the present invention.
  • FIG. 8A is a plan view schematically showing a configuration example of a semiconductor package including two semiconductor elements, and is a view of the lower half of the semiconductor package as viewed from above
  • FIG. 8B is a plan view schematically showing a configuration example of
  • FIG. 11A is a cross-sectional view illustrating a method of manufacturing the upper lead frame included in the semiconductor package of FIG.
  • FIG. 11B is a cross-sectional view showing a step following FIG. 11A
  • FIG. 12 is a cross-sectional view schematically showing the structure of the semiconductor package according to the third embodiment of the present invention.
  • 13A is a cross-sectional view illustrating a method for manufacturing a structure of a semiconductor element, an elastic member, and a conductive member included in the semiconductor package of FIG.
  • FIG. 13B is a cross-sectional view showing a step following FIG. 13A.
  • FIG. 13C is a cross-sectional view showing a step following FIG. 13B;
  • FIG. 13A is a cross-sectional view illustrating a method of manufacturing the upper lead frame included in the semiconductor package of FIG.
  • FIG. 11B is a cross-sectional view showing a step following FIG. 11A
  • FIG. 12 is a cross-sectional view schematically showing the structure
  • FIG. 14 is a cross-sectional view schematically showing the structure of the semiconductor package according to the fourth embodiment of the present invention.
  • 15A is a cross-sectional view showing a state before plating is performed on the upper and lower lead frames of the semiconductor package of FIG. 15B is a cross-sectional view showing a state in which the upper and lower lead frames of the semiconductor package of FIG. 14 are plated.
  • FIG. 16A is a cross-sectional view showing a first modification of the method for connecting the upper lead frame and the lower lead frame; 16B is a cross-sectional view showing a step that follows FIG. 16A.
  • FIG. 17A is a cross-sectional view showing a second modification of the method for connecting the upper lead frame and the lower lead frame;
  • FIG. 17B is a cross-sectional view showing a step following FIG. 17A;
  • FIG. 17C is a cross-sectional view showing a step following FIG. 17B;
  • FIG. 18 is an exploded perspective view showing the structure of a conventional
  • a first lead frame A second lead frame arranged to face the first lead frame; A semiconductor element disposed between the first and second lead frames; A sealing member for sealing the first and second lead frames and the semiconductor element; A semiconductor package comprising: At least one of the first and second lead frames is formed such that the thickness in the vicinity of the portion connected to the semiconductor element is thinner than the thickness of the other portion.
  • the second lead frame includes a plurality of input / output terminals for inputting / outputting a plurality of signals to / from the semiconductor element, At least one of the plurality of input / output terminals protrudes from the second lead frame toward the first lead frame, and is inserted into a hole provided in the first lead frame.
  • a semiconductor package is provided which is electrically connected to the first lead frame and maintains a relative position between the first and second lead frames.
  • the semiconductor package according to the first aspect of the present invention by having the above-described configuration, it is possible to realize improvement in heat dissipation capability, relaxation of thermal stress, and shortening of wiring.
  • the semiconductor package according to the first aspect wherein at least one of the first and second lead frames is composed of two or more metal members made of different materials. .
  • the metal member connected to the semiconductor element is made of a softer material than the other metal members, and an appropriate material is selected according to the place of use.
  • various effects such as improvement of the thermal stress relaxation function can be obtained.
  • the semiconductor package according to the second aspect wherein the vicinity of the portion connected to the semiconductor element is made of a metal member having a Young's modulus lower than that of other metal members. To do.
  • the metal member connected to the semiconductor element is made of a material having a Young's modulus lower than that of the metal member, thereby reducing the thermal stress of the first or second lead frame. Function can be improved.
  • an elastic member provided on the surface of the semiconductor element;
  • a conductive member that is inserted into a through hole provided in the elastic member and connects at least one of the first and second lead frames and the semiconductor element;
  • thermal stress can be further suppressed by elastically deforming the elastic member.
  • an insulating property is imparted to a portion connected to the input / output terminal of the first lead frame. I will provide a.
  • the terminal as the semiconductor package can be taken out from both the first and second lead frames.
  • the semiconductor package according to any one of the first to fifth aspects, wherein the semiconductor element is a power semiconductor element.
  • a semiconductor module comprising the semiconductor package according to any one of the first to sixth aspects.
  • the semiconductor module according to the seventh aspect of the present invention by having the above-described configuration, it is possible to realize improvement in heat dissipation capability, relaxation of thermal stress, and shortening of wiring.
  • the semiconductor module according to the seventh aspect comprising a metal structure that contacts an outer surface of at least one of the first and second lead frames of the semiconductor package.
  • the semiconductor module according to the eighth aspect of the present invention can dissipate heat through the metal structure, a semiconductor module with high heat dissipation performance can be realized.
  • a semiconductor device having two or more semiconductor modules according to the seventh or eighth aspect.
  • the plurality of input / output terminals provided in the second lead frame are inserted into the plurality of holes provided in the first lead frame, and the plurality of input / output terminals are connected.
  • a semiconductor element is inserted into a space formed between the first lead frame and the second lead frame;
  • a method for manufacturing a semiconductor package is inserted into the plurality of holes provided in the first lead frame, and the plurality of input / output terminals are connected.
  • the semiconductor package manufacturing method according to the tenth aspect, wherein the second lead frame is formed by half-etching or half-dicing a metal plate.
  • the first lead frame is formed by selectively etching two metal plates having different laminated materials. Provide a method.
  • the first lead frame and the second lead frame are joined by plating, a low melting point metal, or caulking.
  • a method of manufacturing the described semiconductor package is provided.
  • At least one of the first and second lead frames and the semiconductor element are bonded to each other by ultrasonic waves, a low melting point metal, or plating.
  • the manufacturing method of the semiconductor package as described in any one is provided.
  • FIG. 1 is a cross-sectional view schematically showing the structure of the semiconductor package according to the first embodiment of the present invention.
  • the semiconductor package 1 includes an upper lead frame 2 that is an example of a first lead frame and a second lead that is disposed so as to face the upper lead frame 2.
  • the lower lead frame 3 which is an example of a frame is provided.
  • the upper and lower lead frames 2 and 3 are made of, for example, gold, silver, copper, nickel, aluminum, tin, palladium, tungsten, or the like.
  • a semiconductor element 4 is arranged between the upper and lower lead frames 2 and 3.
  • the semiconductor element 4 is connected to each of the upper and lower lead frames 2 and 3.
  • a power semiconductor element made of silicon (Si), silicon carbide (SiC), gallium oxide (Ga2O3), gallium nitride (GaN), or the like can be used.
  • the upper and lower lead frames 2 and 3 are not auxiliary structural members such as linear or strip-shaped lead members, but function as main structural members that serve as the skeleton of the semiconductor package 1. At least one of the upper and lower lead frames 2 and 3 is formed to have a larger outer shape than the semiconductor element 4 so that a space for accommodating the semiconductor element 4 can be formed between them.
  • the upper lead frame 2 is formed so that the thickness in the vicinity of the portion connected to the semiconductor element 4 is thinner than the thickness of the other portions.
  • the said part is called the thin part 2a. Since the thin portion 2a of the upper lead frame 2 is thinner than the other portions, it is easily plastically deformed (including elastic deformation). When the thin-walled portion 2 a of the upper lead frame 2 is plastically deformed, the thermal stress generated due to the difference in thermal expansion coefficient between the semiconductor element 4 and the upper lead frame 2 when the semiconductor element 4 generates heat can be relieved.
  • the thin portion 2 a of the upper lead frame 2 is preferably provided so as to protrude from the region above the semiconductor element 4 in the vertical direction. That is, it is preferable that the thickness of the upper lead frame 2 located in the vertically upper region of the semiconductor element 4 is thinner than the thickness of the other portions. Thereby, the thermal stress can be further relaxed.
  • the thickness of the upper and lower lead frames 2 and 3 is, for example, 10 to 1000 ⁇ m, and preferably 100 to 500 ⁇ m from the viewpoint of current capacity and heat dissipation.
  • the thickness of the thin portion 2a of the upper lead frame 2 is, for example, 10 to 200 ⁇ m, and preferably 10 to 100 ⁇ m. Further, the thickness of the thin portion 2a of the upper lead frame 2 is desirably 1/2 to 1/10 of the thickness of other portions.
  • the length of the thin portion 2a of the upper lead frame 2 (the length in the left-right direction in FIG. 1) is, for example, a length obtained by adding 10 to 1000 ⁇ m to the length of the semiconductor element 4, and desirably the semiconductor element 4 The length is 10 to 200 ⁇ m added to the length.
  • the shape of the thin part 2a may be linear or plate-shaped.
  • the shape of the thin part 2a as shown in FIG. 1, since the one part bent is easy to plastically deform and the relaxation effect of a thermal stress is large, it is desirable.
  • the lower lead frame 3 is provided with a plurality of input / output terminals (vertical terminals) 3 a for inputting and outputting a plurality of signals to and from the semiconductor element 4. More specifically, the lower lead frame 3 is provided with a plurality of input / output terminals 3a for inputting / outputting a plurality of signals between the semiconductor element 4 and components outside the semiconductor package 1.
  • Each of the plurality of input / output terminals 3 a protrudes from the lower lead frame 3 toward the upper lead frame 2 and is fitted into a hole 2 b provided in the upper lead frame 2.
  • the upper and lower lead frames 2 and 3 are electrically connected to each other, and the relative positions of the upper and lower lead frames 2 and 3 are maintained.
  • the length of the input / output terminal 3a (the distance between the upper and lower lead frames 2 and 3) is, for example, the sum of the thickness of the semiconductor element 4 and the thickness of the junction between the semiconductor element 4 and the lower lead frame 3.
  • the thickness is 10 to 200 ⁇ m added to the thickness.
  • the length of the input / output terminal 3a is desirably a length obtained by adding 10 to 100 ⁇ m to the total thickness.
  • a sealing member 5 such as a resin.
  • 2A to 2G are cross-sectional views showing a method for manufacturing a semiconductor package according to the first embodiment.
  • the upper lead frame 2 including the thin portion 2a and the plurality of holes 2b is manufactured.
  • 2C is half-etched or half-diced to produce the second lead frame 3 having a plurality of input / output terminals 3a as shown in FIG. 2D.
  • the manufacturing order of the upper lead frame 2 and the lower lead frame 3 is not particularly limited, and either may be manufactured first.
  • both “half etching” and “half dicing” are processing methods that leave a part in the thickness direction of the material.
  • the manufacturing method of the upper and lower lead frames 2 and 3 of the present invention is not limited to these, and may be manufactured by other methods.
  • a plurality of input / output terminals 3 a provided in the lower lead frame 3 are fitted into a plurality of holes 2 b provided in the upper lead frame 2 using a holding jig (not shown). Combine. That is, the upper lead frame 2 and the lower lead frame 3 are joined by caulking.
  • FIG. 3 is a plan view showing a state in which the upper and lower lead frames 2 and 3 and the semiconductor element 4 are connected.
  • the upper and lower lead frames 2 and 3 and the semiconductor element 4 can be bonded by, for example, plating, a low melting point metal, ultrasonic waves, or the like.
  • the gap between the upper and lower lead frames 2, 3 and the semiconductor element 4 is sealed with a sealing member 5.
  • a sealing member 5 it is desirable to flatten the entire surface by grinding, dry etching, or the like.
  • the lower lead frame 3 is partially etched. Thereby, the semiconductor package 1 according to the first embodiment is manufactured.
  • the heat of the semiconductor element 4 can be radiated through the upper and lower lead frames 2 and 3. it can. That is, the heat dissipation direction can be two directions. Thereby, the heat dissipation performance of the semiconductor package 1 can be improved.
  • the thin portion 2a of the upper lead frame 2 and the semiconductor element 4 are connected, the thin portion 2a is plastically deformed so that the thermal stress can be reduced. it can.
  • the lower lead frame 3 includes the plurality of input / output terminals 3, and the plurality of input / output terminals 3a are connected to the upper lead frame 2, so that the wiring is conventionally provided. Can be shortened.
  • three or more terminals can be provided on the same surface.
  • the semiconductor element 4 has the function of a transistor having a collector terminal on the lower surface and an emitter terminal and a gate terminal on the upper surface
  • the collector terminal C from the lower lead frame 3 side (lower side in FIG. 1), All the terminals of the emitter terminal E and the gate terminal G can be taken out.
  • the lower lead frame 3 on the right side of FIG. 1 may be the emitter terminal E
  • the lower lead frame 3 in the center of FIG. 1 may be the collector terminal C
  • the present invention is not limited to the first embodiment, and can be implemented in various other modes.
  • one or more of the plurality of input / output terminals 3 a connected to the upper lead frame 2 may be separated from the lower lead frame 3.
  • three or more terminals can be taken out from either the upper lead frame 2 or the lower lead frame 3.
  • the semiconductor element 4 has the function of a transistor having a collector terminal on the lower surface and an emitter terminal and a gate terminal on the upper surface
  • the emitter terminal E and the gate terminal G are taken out from the lower lead frame 3 side
  • the upper lead The collector terminal C can be taken out from the frame 2 side.
  • the lower lead frame 3-1 and the lower lead frame 3-2 are connected.
  • the thin portion 2a is provided only on the upper lead frame 2, but the present invention is not limited to this.
  • a thin portion may be provided on at least one of the upper and lower lead frames 2 and 3. Thereby, thermal stress can be relieved.
  • the upper lead frame 2 is provided with a plurality of holes 2b and the lower lead frame 3 is provided with a plurality of input / output terminals 3a.
  • a plurality of holes may be provided in the lower lead frame 3, and a plurality of input / output terminals may be provided in the upper lead frame 2.
  • the lower lead frame 3 becomes the first lead frame
  • the upper lead frame 2 becomes the second lead frame.
  • the plurality of input / output terminals 3 a and the plurality of holes 2 b corresponding thereto may be provided in both the lower lead frame 3 and the upper lead frame 2.
  • a small semiconductor module that is resistant to thermal stress can be realized by attaching a heat sink 7 to the semiconductor package 1 via an insulating member 6.
  • control circuit board 8 by attaching the control circuit board 8 to the semiconductor package 1, a small semiconductor module in which the control circuit board 8 is integrated can be realized.
  • the semiconductor package 1 and the control circuit board 8 can be bonded by, for example, a low melting point metal such as solder, inductance coupling, or the like.
  • the metal structure 9 so as to be in contact with at least one outer surface of the upper and lower lead frames 2, 3, heat can be radiated through the metal structure 9. Thereby, a semiconductor module with high heat dissipation performance can be realized.
  • the upper and lower lead frames 2 and 3 and the metal structure 9 can be joined by, for example, a low melting point metal such as solder, pressure welding, gold bumps, or the like.
  • the semiconductor package can be provided with a circuit function by devising the patterns of the upper and lower lead frames 2 and 3 and providing a plurality of semiconductor elements 4.
  • 8A and 8B are plan views schematically showing a configuration example of a semiconductor package including two semiconductor elements 4.
  • FIG. 8A is a plan view of the lower half of the semiconductor package as viewed from above
  • FIG. 8B is a plan view of the semiconductor package as viewed from above.
  • 8A and 8B show the sealing member 5 in a transparent manner.
  • Each semiconductor element 4 in FIGS. 8A and 8B has a gate terminal and an emitter terminal on the upper surface, and a collector terminal on the lower surface.
  • P and “N” indicate DC terminals
  • AC indicates AC terminals
  • G indicates external terminals of the gate terminals.
  • 2ag indicates a thin portion of the upper lead frame 2 connected to the gate terminal of the semiconductor element 4
  • 2ae indicates a thin portion of the upper lead frame 2 connected to the emitter terminal of the semiconductor element 4.
  • a semiconductor module that functions as a half-bridge circuit (diode not shown) by connecting two semiconductor packages 1 via a structure 10 having a lead frame on the upper and lower surfaces. Can be realized.
  • FIG. 10 is a cross-sectional view schematically showing the structure of the semiconductor package according to the second embodiment of the present invention.
  • the semiconductor package of the second embodiment is different from the semiconductor package of the first embodiment in that the upper lead frame 2A is composed of two metal members 21 and 22 made of different materials.
  • the metal member 22 constituting the thin portion 2 a connected to the semiconductor element 4 is made of a material having a Young's modulus lower than that of the metal member 21.
  • the metal member 22 is made of aluminum, and the metal member 21 is made of copper.
  • the Young's modulus of aluminum is about 70 GPa and the Young's modulus of copper is about 120 GPa.
  • the upper lead frame 2A can be formed, for example, by selectively etching two metal plates A21 and A22 having different materials stacked as shown in FIG. 11A as shown in FIG. 11B. “Selective etching” is a method of performing etching for each material. However, the method of forming the upper lead frame 2A is not limited to this method, and other methods may be used.
  • examples of the material of the upper and lower lead frames 2 and 3 include gold, silver, copper, nickel, aluminum, tin, palladium, and tungsten.
  • the combination of the material of the upper lead frame 2 and the material of the lower lead frame 3 is not particularly limited, but is preferably a combination that can relieve thermal stress.
  • FIG. 12 is a cross-sectional view schematically showing the structure of the semiconductor package according to the third embodiment of the present invention.
  • the semiconductor package of the third embodiment is different from the semiconductor package of the first embodiment in that an elastic member 11 is provided on the surface of the semiconductor element 4 and a conductive member is provided in a through hole 11a provided in the elastic member 11. 12 is inserted.
  • the elastic member 11 is provided around the semiconductor element 4 so as to cover (seal) the semiconductor element 4.
  • the thermal stress can be further suppressed.
  • the material of the elastic member 11 include an elastomer.
  • the material of the elastic member 11 is not particularly limited, but is preferably a material that can relieve thermal stress. Further, the material of the elastic member 11 may be the same as the material of the sealing member 5.
  • the elastic member 11 is provided with a plurality of through holes 11a.
  • the conductive member 12 is inserted into each of the plurality of through holes 11 a so as to connect the upper lead frame 2 and the semiconductor element 4 and the upper lead frame 2 and the semiconductor element 4.
  • the height of the through hole 11a is, for example, 10 to 500 ⁇ m, and preferably 10 to 200 ⁇ m.
  • Examples of the material of the conductive member 12 include gold, silver, copper, nickel, aluminum, tin, palladium, and tungsten.
  • the structure of the semiconductor element 4, the elastic member 11, and the conductive member 12 can be manufactured as follows, for example.
  • an elastic member A11 is formed so as to cover the entire semiconductor element 4.
  • a plurality of through holes 11a are formed at a plurality of locations of the elastic member A11 to form the elastic member 11.
  • the plurality of through holes 11a can be formed by, for example, laser irradiation.
  • the conductive member 12 is formed in each of the plurality of through holes 11 a of the elastic member 11.
  • the conductive member 12 can be formed by, for example, plating or printing.
  • FIG. 14 is a cross-sectional view schematically showing the structure of the semiconductor package according to the fourth embodiment of the present invention.
  • the semiconductor package of the fourth embodiment is different from the semiconductor package of the third embodiment in that the upper lead frame 2A is composed of two metal members 21 and 22 made of different materials, and the upper and lower lead frames. 2A and 3 are plated 13.
  • the thickness of the plating 13 is, for example, 1 to 10 ⁇ m.
  • the plating 13 is made of copper, so that the upper and lower lead frames 2A and 3 are joined to the semiconductor element 4 (or the conductive member 12) with a low melting point metal such as solder. be able to. That is, according to this structure, it is possible to increase options for a method of joining the upper and lower lead frames 2A, 3 and the semiconductor element 4 (or the conductive member 12) such as joining with a low melting point metal such as solder. . Moreover, according to this structure, when the metal member 22 is comprised with aluminum, it can suppress that an internal fracture arises, for example.
  • the upper lead frame 2A is composed of two metal members 21 and 22 made of different materials, but the present invention is not limited to this.
  • the upper lead frame 2 shown in FIG. 1 may be used as the upper lead frame 2A.
  • the material of the upper lead frame 2 is copper, oxidation of the upper lead frame 2 can be prevented by using nickel or gold as the material of the plating 13.
  • the upper lead frame 2A and the lower lead frame 3 are illustrated as being joined by caulking, but the present invention is not limited to this.
  • the upper lead frame 2 ⁇ / b> A and the lower lead frame 3 may be joined by plating 13.
  • the hole 2b and the input / output so that a gap 30 is formed between the hole 2b and the input / output terminal 3a. Terminal 3a is formed.
  • the plating 13 is formed on the entire upper and lower lead frames 2 and 3.
  • the upper lead frame 2 ⁇ / b> A and the lower lead frame 3 can be joined by the plating 13 entering the gap 30.
  • the upper lead frame 2A and the lower lead frame 3 may be joined with a low melting point metal such as solder.
  • a low melting point metal such as solder.
  • the input / output terminals 3a of the lower lead frame 3 are connected to all of the plurality of holes 2b of the upper lead frame 2. However, the input / output terminals 3a are partially connected to the plurality of holes 2b. You may make it connect.
  • the diameter of the hole 2ba corresponding to the input / output terminal 3aa not connected to the upper lead frame 2 is made larger than that of the other holes 2b, and thereafter, as shown in FIG. 16B.
  • this can be realized by applying plating 13 to the upper lead frame 2.
  • plating 13 By not connecting a part of the input / output terminals 3aa of the lower lead frame 3 to the upper lead frame 2, it is possible to take out terminals as a semiconductor package from both the upper and lower lead frames 2 and 3.
  • the upper lead frame 2 and a part of the input / output terminal 3a can be prevented from being connected by the following manufacturing method.
  • a portion other than the hole 2bb corresponding to the input / output terminal 3aa not connected to the upper lead frame 2 is covered with a resist film.
  • an insulating region 15 is formed around the hole 2bb of the upper lead frame 2.
  • the upper lead frame 2 is made of aluminum
  • the surrounding portion becomes aluminum oxide and the insulating region 15 is formed.
  • insulation is imparted to the portion of the upper lead frame 2 connected to the input / output terminal 3aa.
  • the semiconductor package and the manufacturing method thereof, the semiconductor module, and the semiconductor device according to the present invention can realize improvement in heat dissipation capability, relaxation of thermal stress, and shortening of wiring, not only the application of power semiconductor elements. It can also be applied to three-dimensional mounting of LSI, CSP (Chip Scale Package), and the like.

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Abstract

This semiconductor package is provided with: a first lead frame; a second lead frame disposed in opposition to the first lead frame; a semiconductor element disposed between the first and second lead frames; and a sealing member for sealing the first and second lead frames and the semiconductor element, the semiconductor package being configured such that in at least one of the first and second lead frames, the thickness in proximity to the section that connects to the semiconductor element is formed thinner than the thickness of the other sections, and the second lead frame is provided with a plurality of input/output terminals, with at least one of the input/output terminals being connected to the first lead frame.

Description

半導体パッケージ及びその製造方法、半導体モジュール、並びに半導体装置Semiconductor package and method for manufacturing the same, semiconductor module, and semiconductor device
　本発明は、半導体素子のパッケージング技術に関し、例えば、モータ用インバータ装置、太陽光発電用又は風速発電用パワーコンディショナなどに用いられる半導体パッケージ及びその製造方法、半導体モジュール、並びに半導体装置に関する。 The present invention relates to a semiconductor element packaging technology, for example, a semiconductor package used for an inverter device for a motor, a power conditioner for solar power generation or wind power generation, a manufacturing method thereof, a semiconductor module, and a semiconductor device.
　従来、半導体モジュールとして、ＩＧＢＴ（Insulated Gate Bipolar Transistor）やＭＯＳ－ＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）などのパワー半導体素子を内蔵したものが知られている。 Conventionally, semiconductor modules incorporating power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOS-FETs (Metal Oxide Semiconductor Semiconductor Field Effect Transistors) are known.
　図１８は、従来の半導体モジュールの構造を示す斜視図である。図１８に示すように、従来の半導体モジュールは、絶縁基板１０１を備えている。絶縁基板１０１は、例えば、窒化アルミニウム（AlN）板と銅板の積層体等で構成されている。絶縁基板１０１の一方の主面には、パワー半導体素子１０２が半田により接合されている。パワー半導体素子１０２は、ワイヤや外部端子１０３を通じて半導体モジュールの外部の部品の電極と接続される。絶縁基板１０１の他方の主面には、パワー半導体素子１０２から発生した熱を、絶縁基板１０１を通じて放出する放熱板１０４が半田により接合されている。 FIG. 18 is a perspective view showing the structure of a conventional semiconductor module. As shown in FIG. 18, the conventional semiconductor module includes an insulating substrate 101. The insulating substrate 101 is composed of, for example, a laminate of an aluminum nitride (AlN) plate and a copper plate. A power semiconductor element 102 is joined to one main surface of the insulating substrate 101 by soldering. The power semiconductor element 102 is connected to an electrode of a component outside the semiconductor module through a wire or an external terminal 103. A heat radiating plate 104 that releases heat generated from the power semiconductor element 102 through the insulating substrate 101 is joined to the other main surface of the insulating substrate 101 by solder.
　絶縁基板１０１の一方の主面の上方には、制御回路基板１０５が配置されている。絶縁基板１０１と制御回路基板１０５とは、ワイヤや内部端子１０６により接続されている。制御回路基板１０５には、パワー半導体素子１０２を制御する制御部品１０７などが実装されている。 A control circuit board 105 is disposed above one main surface of the insulating substrate 101. The insulating substrate 101 and the control circuit substrate 105 are connected by wires or internal terminals 106. A control component 107 for controlling the power semiconductor element 102 and the like are mounted on the control circuit board 105.
　前記各部品は、ケース１０８内に収納されている。ケース１０８内には、シリコーンゲルなどの封止部材が充填されている。ケース１０８は、蓋１０９でカバーされている。 The parts are housed in the case 108. The case 108 is filled with a sealing member such as silicone gel. The case 108 is covered with a lid 109.
特許４１８９６６６号公報Japanese Patent No. 4189666
　例えば、ハイブリッド自動車や電気自動車に搭載される半導体モジュールにおいては、より一層の小型化が求められている。半導体モジュールを小型化すると、単位面積当たりの熱量が増大することになる。 For example, semiconductor modules mounted on hybrid cars and electric cars are required to be further miniaturized. When the semiconductor module is downsized, the amount of heat per unit area increases.
　前記従来の半導体モジュールにおいて、パワー半導体素子１０２の熱膨張率は例えば３ｐｐｍ／Ｋであり、絶縁基板１０１の熱膨張率は例えば４～５ｐｐｍ／Ｋであり、放熱板１０４の熱膨張率は例えば１７ｐｐｍ／Ｋである。すなわち、各部品の熱膨張率は大きく異なっている。このため、半導体モジュール内で発生する熱量が増大すると、それらの部品の界面付近の熱応力が増加し、各部品が変形又は破損するなどの問題が生じる。従って、放熱性能を向上させるとともに、熱応力を緩和することができる半導体モジュールが求められている。 In the conventional semiconductor module, the thermal expansion coefficient of the power semiconductor element 102 is 3 ppm / K, the thermal expansion coefficient of the insulating substrate 101 is 4 to 5 ppm / K, and the thermal expansion coefficient of the heat sink 104 is 17 ppm, for example. / K. That is, the coefficient of thermal expansion of each part is greatly different. For this reason, when the amount of heat generated in the semiconductor module increases, the thermal stress near the interface between these components increases, causing problems such as deformation or breakage of each component. Therefore, there is a demand for a semiconductor module that can improve heat dissipation performance and can reduce thermal stress.
　また、半導体モジュールにおいては、より一層の出力の増加が求められている。このため、１つの半導体モジュールに複数の半導体素子を内蔵するものが検討されている。 Further, in the semiconductor module, further increase in output is required. For this reason, a semiconductor module in which a plurality of semiconductor elements are incorporated has been studied.
　前記従来の半導体モジュールにおいて、半導体素子の数を増加させると、それらの半導体素子と制御回路基板とを接続する配線が複雑になり、長くなる。この場合、配線の固定が難しくなるとともに、ノイズの影響を受けやすくなる。このため、配線を短くすることができる半導体モジュールが求められている。 In the conventional semiconductor module, when the number of semiconductor elements is increased, the wiring connecting the semiconductor elements and the control circuit board becomes complicated and long. In this case, it is difficult to fix the wiring and it is easy to be affected by noise. For this reason, a semiconductor module capable of shortening the wiring is demanded.
　特許文献１（特許４１８９６６６号公報）には、金属基板部と制御基板部との間に、電極部同士を導通させる導通部と半導体素子を収納する部品収納孔とを設けた構造を有する半導体モジュールが開示されている。特許文献１の半導体モジュールによれば、配線を短くすることができる。しかしながら、特許文献１の半導体モジュールでは、半導体素子の熱は、金属基板部を通じて放熱されるもの（すなわち、放熱方向が一方向）であり、半導体素子の熱を十分に放熱することができない。また、熱応力については何ら対策がなされていない。従って、特許文献１の半導体モジュールは、未だ改善の余地がある。 Patent Document 1 (Japanese Patent No. 4189666) discloses a semiconductor module having a structure in which a conductive portion for connecting electrodes to each other and a component storage hole for storing a semiconductor element are provided between a metal substrate portion and a control substrate portion. Is disclosed. According to the semiconductor module of Patent Document 1, the wiring can be shortened. However, in the semiconductor module of Patent Document 1, the heat of the semiconductor element is radiated through the metal substrate portion (that is, the heat radiation direction is one direction), and the heat of the semiconductor element cannot be sufficiently radiated. Moreover, no measures are taken for thermal stress. Therefore, the semiconductor module of Patent Document 1 still has room for improvement.
　従って、本発明の目的は、前記従来の課題を解決することにあって、放熱能力の向上、熱応力の緩和、及び配線の短縮化を実現することができる半導体パッケージ及びその製造方法、半導体モジュール、並びに半導体装置を提供することにある。 Accordingly, an object of the present invention is to solve the above-described conventional problems, and a semiconductor package, a manufacturing method thereof, and a semiconductor module capable of realizing improvement in heat dissipation capability, relaxation of thermal stress, and shortening of wiring. And providing a semiconductor device.
　本発明の一態様にかかる半導体パッケージは、
　第１のリードフレームと、
　前記第１のリードフレームと対向するように配置された第２のリードフレームと、
　前記第１及び第２のリードフレーム間に配置された半導体素子と、
　前記第１及び第２のリードフレームと前記半導体素子との隙間を封止する封止部材と、
　を備える半導体パッケージであって、
　前記第１及び第２のリードフレームの少なくとも一方は、前記半導体素子と接続される部分の近傍の厚さがそれ以外の部分の厚さよりも薄く形成され、
　前記第２のリードフレームは、前記半導体素子に複数の信号を入出力するための複数の入出力端子を備え、
　前記複数の入出力端子の少なくとも１つは、前記第２のリードフレームから前記第１のリードフレームに向けて突設され、当該第１のリードフレームに設けられた穴に挿入されることにより、前記第１のリードフレームに電気的に接続されるとともに前記第１及び第２のリードフレームの相対位置を保持するように構成されている。 A semiconductor package according to one embodiment of the present invention includes:
A first lead frame;
A second lead frame arranged to face the first lead frame;
A semiconductor element disposed between the first and second lead frames;
A sealing member for sealing a gap between the first and second lead frames and the semiconductor element;
A semiconductor package comprising:
At least one of the first and second lead frames is formed such that the thickness in the vicinity of the portion connected to the semiconductor element is thinner than the thickness of the other portion.
The second lead frame includes a plurality of input / output terminals for inputting / outputting a plurality of signals to / from the semiconductor element,
At least one of the plurality of input / output terminals protrudes from the second lead frame toward the first lead frame, and is inserted into a hole provided in the first lead frame. It is electrically connected to the first lead frame and is configured to maintain the relative position of the first and second lead frames.
　本発明の一態様にかかる半導体パッケージの製造方法は、
　第１のリードフレームに設けられた複数の穴に、第２のリードフレームに設けられた複数の入出力端子を挿入して、当該複数の入出力端子の少なくとも１つを前記第１のリードフレームに接続し、
　前記第１のリードフレームと前記第２のリードフレームとの間に形成された空間に半導体素子を挿入し、
　前記第１及び第２のリードフレームの少なくとも一方に設けた他の部分よりも厚さが薄い部分と前記半導体素子とを接続し、
　前記第１及び第２のリードフレームと前記半導体素子との隙間を封止部材により封止し、
　前記第２のリードフレームを部分的にエッチングする、
　ことを含む。 A manufacturing method of a semiconductor package according to one embodiment of the present invention includes:
A plurality of input / output terminals provided in the second lead frame are inserted into a plurality of holes provided in the first lead frame, and at least one of the plurality of input / output terminals is connected to the first lead frame. Connected to
A semiconductor element is inserted into a space formed between the first lead frame and the second lead frame;
Connecting the semiconductor element with a portion having a smaller thickness than the other portion provided on at least one of the first and second lead frames;
Sealing a gap between the first and second lead frames and the semiconductor element with a sealing member;
Partially etching the second lead frame;
Including that.
　本発明の一態様にかかる半導体パッケージ及びその製造方法によれば、前記構成を有することにより、放熱能力の向上、熱応力の緩和、及び配線の短縮化を実現することができる。 According to the semiconductor package and the method for manufacturing the same according to one embodiment of the present invention, by having the above-described configuration, it is possible to improve the heat dissipation capability, relax the thermal stress, and shorten the wiring.
　本発明のこれらと他の目的と特徴は、添付された図面についての好ましい実施の形態に関連した次の記述から明らかになる。この図面においては、
図１は、本発明の第１実施形態にかかる半導体パッケージの断面図であり、 図２Ａは、本発明の第１実施形態にかかる半導体パッケージの製造方法を示す断面図であり、 図２Ｂは、図２Ａに続く工程を示す断面図であり、 図２Ｃは、図２Ｂに続く工程を示す断面図であり、 図２Ｄは、図２Ｃに続く工程を示す断面図であり、 図２Ｅは、図２Ｄに続く工程を示す断面図であり、 図２Ｆは、図２Ｅに続く工程を示す断面図であり、 図２Ｇは、図２Ｆに続く工程を示す断面図であり、 図３は、上側及び下側リードフレームと半導体素子とを接続した状態を示す平面図であり、 図４は、図１の半導体パッケージにおいて、上側リードフレームに接続されている複数の入出力端子の１つを下側リードフレームから切り離した状態を示す断面図であり、 図５は、図１の半導体パッケージにヒートシンクを取り付けた半導体モジュールの構成を示す断面図であり、 図６は、図１の半導体パッケージに制御回路基板を取り付けた半導体モジュールの構成を示す断面図であり、 図７は、図１の半導体パッケージに金属構造体を取り付けた半導体モジュールの構成を示す断面図であり、 図８Ａは、２つの半導体素子を備える半導体パッケージの構成例を模式的に示す平面図であって、当該半導体パッケージの下半分を上方から見た図であり、 図８Ｂは、２つの半導体素子を備える半導体パッケージの構成例を模式的に示す平面図であって、当該半導体パッケージを上方から見た平面図であり、 図９は、図１の半導体パッケージを２つ備える半導体モジュールの構成例を示す断面図であり、 図１０は、本発明の第２実施形態にかかる半導体パッケージの構造を模式的に示す断面図であり、 図１１Ａは、図１０の半導体パッケージが備える上側リードフレームの製造方法を示す断面図であり、 図１１Ｂは、図１１Ａに続く工程を示す断面図であり、 図１２は、本発明の第３実施形態にかかる半導体パッケージの構造を模式的に示す断面図であり、 図１３Ａは、図１２の半導体パッケージが備える半導体素子と弾性部材と導電性部材との構造体の製造方法を示す断面図であり、 図１３Ｂは、図１３Ａに続く工程を示す断面図であり、 図１３Ｃは、図１３Ｂに続く工程を示す断面図であり、 図１４は、本発明の第４実施形態にかかる半導体パッケージの構造を模式的に示す断面図であり、 図１５Ａは、図１４の半導体パッケージの上側及び下側リードフレームにめっきを施す前の状態を示す断面図であり、 図１５Ｂは、図１４の半導体パッケージの上側及び下側リードフレームにめっきを施した状態を示す断面図であり、 図１６Ａは、上側リードフレームと下側リードフレームとの接続方法の第１変形例を示す断面図であり、 図１６Ｂは、図１６Ａに続く工程を示す断面図であり、 図１７Ａは、上側リードフレームと下側リードフレームとの接続方法の第２変形例を示す断面図であり、 図１７Ｂは、図１７Ａに続く工程を示す断面図であり、 図１７Ｃは、図１７Ｂに続く工程を示す断面図であり、 図１８は、従来の半導体モジュールの構造を示す分解斜視図である。 These and other objects and features of the invention will become apparent from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings. In this drawing,
FIG. 1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention. FIG. 2A is a cross-sectional view illustrating the method of manufacturing the semiconductor package according to the first embodiment of the present invention. FIG. 2B is a cross-sectional view showing a step following FIG. 2A. FIG. 2C is a cross-sectional view showing a step following FIG. 2B. FIG. 2D is a cross-sectional view showing a step following FIG. 2C. FIG. 2E is a cross-sectional view showing a step following FIG. 2D. FIG. 2F is a cross-sectional view showing a step following FIG. 2E. FIG. 2G is a cross-sectional view showing a step following FIG. 2F. FIG. 3 is a plan view showing a state where the upper and lower lead frames are connected to the semiconductor element, 4 is a cross-sectional view showing a state in which one of a plurality of input / output terminals connected to the upper lead frame is separated from the lower lead frame in the semiconductor package of FIG. FIG. 5 is a cross-sectional view showing a configuration of a semiconductor module in which a heat sink is attached to the semiconductor package of FIG. 6 is a cross-sectional view showing a configuration of a semiconductor module in which a control circuit board is attached to the semiconductor package of FIG. FIG. 7 is a cross-sectional view showing a configuration of a semiconductor module in which a metal structure is attached to the semiconductor package of FIG. FIG. 8A is a plan view schematically showing a configuration example of a semiconductor package including two semiconductor elements, and is a view of the lower half of the semiconductor package as viewed from above; FIG. 8B is a plan view schematically showing a configuration example of a semiconductor package including two semiconductor elements, and is a plan view of the semiconductor package as viewed from above. FIG. 9 is a cross-sectional view illustrating a configuration example of a semiconductor module including two semiconductor packages of FIG. FIG. 10 is a cross-sectional view schematically showing the structure of the semiconductor package according to the second embodiment of the present invention. FIG. 11A is a cross-sectional view illustrating a method of manufacturing the upper lead frame included in the semiconductor package of FIG. FIG. 11B is a cross-sectional view showing a step following FIG. 11A; FIG. 12 is a cross-sectional view schematically showing the structure of the semiconductor package according to the third embodiment of the present invention. 13A is a cross-sectional view illustrating a method for manufacturing a structure of a semiconductor element, an elastic member, and a conductive member included in the semiconductor package of FIG. FIG. 13B is a cross-sectional view showing a step following FIG. 13A. FIG. 13C is a cross-sectional view showing a step following FIG. 13B; FIG. 14 is a cross-sectional view schematically showing the structure of the semiconductor package according to the fourth embodiment of the present invention. 15A is a cross-sectional view showing a state before plating is performed on the upper and lower lead frames of the semiconductor package of FIG. 15B is a cross-sectional view showing a state in which the upper and lower lead frames of the semiconductor package of FIG. 14 are plated. FIG. 16A is a cross-sectional view showing a first modification of the method for connecting the upper lead frame and the lower lead frame; 16B is a cross-sectional view showing a step that follows FIG. 16A. FIG. 17A is a cross-sectional view showing a second modification of the method for connecting the upper lead frame and the lower lead frame; FIG. 17B is a cross-sectional view showing a step following FIG. 17A; FIG. 17C is a cross-sectional view showing a step following FIG. 17B; FIG. 18 is an exploded perspective view showing the structure of a conventional semiconductor module.
　本発明の第１態様によれば、第１のリードフレームと、
　前記第１のリードフレームと対向するように配置された第２のリードフレームと、
　前記第１及び第２のリードフレーム間に配置された半導体素子と、
　前記第１及び第２のリードフレームと前記半導体素子とを封止する封止部材と、
　を備える半導体パッケージであって、
　前記第１及び第２のリードフレームの少なくとも一方は、前記半導体素子と接続される部分の近傍の厚さがそれ以外の部分の厚さよりも薄く形成され、
　前記第２のリードフレームは、前記半導体素子に複数の信号を入出力するための複数の入出力端子を備え、
　前記複数の入出力端子の少なくとも１つは、前記第２のリードフレームから前記第１のリードフレームに向けて突設され、当該第１のリードフレームに設けられた穴に挿入されることにより、前記第１のリードフレームに電気的に接続されるとともに前記第１及び第２のリードフレームの相対位置を保持する、半導体パッケージを提供する。 According to a first aspect of the present invention, a first lead frame;
A second lead frame arranged to face the first lead frame;
A semiconductor element disposed between the first and second lead frames;
A sealing member for sealing the first and second lead frames and the semiconductor element;
A semiconductor package comprising:
At least one of the first and second lead frames is formed such that the thickness in the vicinity of the portion connected to the semiconductor element is thinner than the thickness of the other portion.
The second lead frame includes a plurality of input / output terminals for inputting / outputting a plurality of signals to / from the semiconductor element,
At least one of the plurality of input / output terminals protrudes from the second lead frame toward the first lead frame, and is inserted into a hole provided in the first lead frame. A semiconductor package is provided which is electrically connected to the first lead frame and maintains a relative position between the first and second lead frames.
　本発明の第１態様にかかる半導体パッケージによれば、前記構成を有することにより、放熱能力の向上、熱応力の緩和、及び配線の短縮化を実現することができる。 According to the semiconductor package according to the first aspect of the present invention, by having the above-described configuration, it is possible to realize improvement in heat dissipation capability, relaxation of thermal stress, and shortening of wiring.
　本発明の第２態様によれば、前記第１及び第２のリードフレームの少なくとも一方は、互いに材料が異なる２以上の金属部材で構成されている、第１態様に記載の半導体パッケージを提供する。 According to a second aspect of the present invention, there is provided the semiconductor package according to the first aspect, wherein at least one of the first and second lead frames is composed of two or more metal members made of different materials. .
　本発明の第２態様にかかる半導体パッケージによれば、例えば半導体素子と接続される金属部材を他の金属部材よりも柔らかい材料で構成するなど、それぞれ用いる場所に応じて適切な材料を選択することで、熱応力緩和機能の向上など様々な効果を得ることができる。 According to the semiconductor package according to the second aspect of the present invention, for example, the metal member connected to the semiconductor element is made of a softer material than the other metal members, and an appropriate material is selected according to the place of use. Thus, various effects such as improvement of the thermal stress relaxation function can be obtained.
　本発明の第３態様によれば、前記半導体素子と接続される部分の近傍は、他の金属部材よりもヤング率が低い金属部材で構成されている、第２態様に記載の半導体パッケージを提供する。 According to a third aspect of the present invention, there is provided the semiconductor package according to the second aspect, wherein the vicinity of the portion connected to the semiconductor element is made of a metal member having a Young's modulus lower than that of other metal members. To do.
　本発明の第３態様にかかる半導体パッケージによれば、半導体素子と接続される金属部材を金属部材よりもヤング率の低い材料で構成することにより、第１又は第２のリードフレームの熱応力緩和機能を向上させることができる。 According to the semiconductor package of the third aspect of the present invention, the metal member connected to the semiconductor element is made of a material having a Young's modulus lower than that of the metal member, thereby reducing the thermal stress of the first or second lead frame. Function can be improved.
　本発明の第４態様によれば、前記半導体素子の表面に設けられた弾性部材と、
　前記弾性部材に設けられた貫通穴に挿入され、前記第１及び第２のリードフレームの少なくとも一方と前記半導体素子とを接続する導電性部材と、
　をさらに備える、第１～３態様のいずれか１つに記載の半導体パッケージを提供する。 According to the fourth aspect of the present invention, an elastic member provided on the surface of the semiconductor element;
A conductive member that is inserted into a through hole provided in the elastic member and connects at least one of the first and second lead frames and the semiconductor element;
The semiconductor package according to any one of the first to third aspects, further comprising:
　本発明の第４態様にかかる半導体パッケージによれば、弾性部材が弾性変形することにより、熱応力をより一層抑えることができる。 According to the semiconductor package of the fourth aspect of the present invention, thermal stress can be further suppressed by elastically deforming the elastic member.
　本発明の第５態様によれば、前記第１のリードフレームの前記入出力端子と接続される部分に絶縁性が付与されている、第１～４態様のいずれか１つに記載の半導体パッケージを提供する。 According to a fifth aspect of the present invention, in the semiconductor package according to any one of the first to fourth aspects, an insulating property is imparted to a portion connected to the input / output terminal of the first lead frame. I will provide a.
　本発明の第５態様にかかる半導体パッケージによれば、半導体パッケージとしての端子を、第１及び第２のリードフレームの両方から取り出すことが可能になる。 According to the semiconductor package of the fifth aspect of the present invention, the terminal as the semiconductor package can be taken out from both the first and second lead frames.
　本発明の第６態様によれば、前記半導体素子は、パワー半導体素子である、第１～５態様のいずれか１つに記載の半導体パッケージを提供する。 According to a sixth aspect of the present invention, there is provided the semiconductor package according to any one of the first to fifth aspects, wherein the semiconductor element is a power semiconductor element.
　本発明の第７態様によれば、第１～６態様のいずれか１つに記載の半導体パッケージを備える半導体モジュールを提供する。 According to a seventh aspect of the present invention, there is provided a semiconductor module comprising the semiconductor package according to any one of the first to sixth aspects.
　本発明の第７態様にかかる半導体モジュールによれば、前記構成を有することにより、放熱能力の向上、熱応力の緩和、及び配線の短縮化を実現することができる。 According to the semiconductor module according to the seventh aspect of the present invention, by having the above-described configuration, it is possible to realize improvement in heat dissipation capability, relaxation of thermal stress, and shortening of wiring.
　本発明の第８態様によれば、前記半導体パッケージの前記第１及び第２のリードフレームの少なくとも一方の外面と接触する金属構造体を備える、第７態様に記載の半導体モジュールを提供する。 According to an eighth aspect of the present invention, there is provided the semiconductor module according to the seventh aspect, comprising a metal structure that contacts an outer surface of at least one of the first and second lead frames of the semiconductor package.
　本発明の第８態様にかかる半導体モジュールによれば、金属構造体を通じて放熱することができるので、放熱性能の高い半導体モジュールを実現できる。 Since the semiconductor module according to the eighth aspect of the present invention can dissipate heat through the metal structure, a semiconductor module with high heat dissipation performance can be realized.
　本発明の第９態様によれば、第７又は８態様に記載の半導体モジュールを２つ以上有する半導体装置を提供する。 According to the ninth aspect of the present invention, there is provided a semiconductor device having two or more semiconductor modules according to the seventh or eighth aspect.
　本発明の第１０態様によれば、第１のリードフレームに設けられた複数の穴に、第２のリードフレームに設けられた複数の入出力端子を挿入して、当該複数の入出力端子の少なくとも１つを前記第１のリードフレームに接続し、
　前記第１のリードフレームと前記第２のリードフレームとの間に形成された空間に半導体素子を挿入し、
　前記第１及び第２のリードフレームの少なくとも一方に設けた他の部分よりも厚さが薄い部分と前記半導体素子とを接続し、
　前記第１及び第２のリードフレームと前記半導体素子との隙間を封止部材により封止し、
　前記第２のリードフレームを部分的にエッチングする、
　ことを含む、半導体パッケージの製造方法を提供する。 According to the tenth aspect of the present invention, the plurality of input / output terminals provided in the second lead frame are inserted into the plurality of holes provided in the first lead frame, and the plurality of input / output terminals are connected. Connecting at least one to the first lead frame;
A semiconductor element is inserted into a space formed between the first lead frame and the second lead frame;
Connecting the semiconductor element with a portion having a smaller thickness than the other portion provided on at least one of the first and second lead frames;
Sealing a gap between the first and second lead frames and the semiconductor element with a sealing member;
Partially etching the second lead frame;
A method for manufacturing a semiconductor package.
　本発明の第１０態様にかかる半導体パッケージの製造方法によれば、前記構成を有することにより、放熱能力の向上、熱応力の緩和、及び配線の短縮化を実現することができる。 According to the method of manufacturing a semiconductor package according to the tenth aspect of the present invention, by having the above-described configuration, it is possible to realize improvement in heat dissipation capability, relaxation of thermal stress, and shortening of wiring.
　本発明の第１１態様によれば、前記第２のリードフレームは、金属板をハーフエッチング又はハーフダイシングすることにより形成される、第１０態様に記載の半導体パッケージの製造方法を提供する。 According to an eleventh aspect of the present invention, there is provided the semiconductor package manufacturing method according to the tenth aspect, wherein the second lead frame is formed by half-etching or half-dicing a metal plate.
　本発明の第１２態様によれば、前記第１のリードフレームは、積層した材料の異なる２枚の金属板を選択エッチングすることにより形成される、第１０又は１１態様に記載の半導体パッケージの製造方法を提供する。 According to a twelfth aspect of the present invention, in the semiconductor package according to the tenth or eleventh aspect, the first lead frame is formed by selectively etching two metal plates having different laminated materials. Provide a method.
　本発明の第１３態様によれば、前記第１のリードフレームと第２のリードフレームとは、めっき、低融点金属、又は、かしめにより接合される、第１０～１２態様のいずれか１つに記載の半導体パッケージの製造方法を提供する。 According to a thirteenth aspect of the present invention, in any one of the tenth to twelfth aspects, the first lead frame and the second lead frame are joined by plating, a low melting point metal, or caulking. A method of manufacturing the described semiconductor package is provided.
　本発明の第１４態様によれば、前記第１及び第２のリードフレームの少なくとも一方と前記半導体素子とは、超音波、低融点金属、又は、めっきにより接合される、第１０～１３のいずれか１つに記載の半導体パッケージの製造方法を提供する。 According to a fourteenth aspect of the present invention, at least one of the first and second lead frames and the semiconductor element are bonded to each other by ultrasonic waves, a low melting point metal, or plating. The manufacturing method of the semiconductor package as described in any one is provided.
　以下、本発明の実施形態について、図面を参照しながら説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　《第１実施形態》
　図１は、本発明の第１実施形態にかかる半導体パッケージの構造を模式的に示す断面図である。 << First Embodiment >>
FIG. 1 is a cross-sectional view schematically showing the structure of the semiconductor package according to the first embodiment of the present invention.
　図１に示すように、本第１実施形態にかかる半導体パッケージ１は、第１のリードフレームの一例である上側リードフレーム２と、上側リードフレーム２と対向するように配置された第２のリードフレームの一例である下側リードフレーム３とを備えている。上側及び下側リードフレーム２、３は、例えば、金、銀、銅、ニッケル、アルミニウム、錫、パラジウム、タングステンなどにより構成されている。 As shown in FIG. 1, the semiconductor package 1 according to the first embodiment includes an upper lead frame 2 that is an example of a first lead frame and a second lead that is disposed so as to face the upper lead frame 2. The lower lead frame 3 which is an example of a frame is provided. The upper and lower lead frames 2 and 3 are made of, for example, gold, silver, copper, nickel, aluminum, tin, palladium, tungsten, or the like.
　上側及び下側リードフレーム２，３間には、半導体素子４が配置されている。半導体素子４は、上側及び下側リードフレーム２，３のそれぞれと接続されている。半導体素子４としては、例えば、シリコン（Ｓｉ）、炭化シリコン（ＳｉＣ）、酸化ガリウム（Ｇａ２Ｏ３）、窒化ガリウム（ＧａＮ）などにより構成されるパワー半導体素子を用いることができる。 A semiconductor element 4 is arranged between the upper and lower lead frames 2 and 3. The semiconductor element 4 is connected to each of the upper and lower lead frames 2 and 3. As the semiconductor element 4, for example, a power semiconductor element made of silicon (Si), silicon carbide (SiC), gallium oxide (Ga2O3), gallium nitride (GaN), or the like can be used.
　上側及び下側リードフレーム２，３は、線状や帯状のリード部材のような補助的な構造部材ではなく、半導体パッケージ１の骨格となるような主要な構造部材として機能するものである。上側及び下側リードフレーム２，３の少なくとも一方は、それらの間に半導体素子４を収容する空間を形成できるように、半導体素子４よりも大きな外形するように形成されている。 The upper and lower lead frames 2 and 3 are not auxiliary structural members such as linear or strip-shaped lead members, but function as main structural members that serve as the skeleton of the semiconductor package 1. At least one of the upper and lower lead frames 2 and 3 is formed to have a larger outer shape than the semiconductor element 4 so that a space for accommodating the semiconductor element 4 can be formed between them.
　上側リードフレーム２は、半導体素子４と接続される部分の近傍の厚さがそれ以外の部分の厚さよりも薄く形成されている。以下、当該部分を薄肉部２ａという。上側リードフレーム２の薄肉部２ａは、それ以外の部分よりも薄いため、塑性変形（弾性変形を含む）し易くなっている。上側リードフレーム２の薄肉部２ａが塑性変形することにより、半導体素子４の発熱時において半導体素子４と上側リードフレーム２との熱膨張係数の違いにより発生する熱応力を緩和することができる。なお、上側リードフレーム２の薄肉部２ａは、半導体素子４の鉛直上方の領域からはみ出すように設けられることが好ましい。すなわち、半導体素子４の鉛直上方の領域に位置する上側リードフレーム２の部分の厚さは、それ以外の部分の厚さよりも薄いことが好ましい。これにより、前記熱応力をより一層緩和することができる。 The upper lead frame 2 is formed so that the thickness in the vicinity of the portion connected to the semiconductor element 4 is thinner than the thickness of the other portions. Hereinafter, the said part is called the thin part 2a. Since the thin portion 2a of the upper lead frame 2 is thinner than the other portions, it is easily plastically deformed (including elastic deformation). When the thin-walled portion 2 a of the upper lead frame 2 is plastically deformed, the thermal stress generated due to the difference in thermal expansion coefficient between the semiconductor element 4 and the upper lead frame 2 when the semiconductor element 4 generates heat can be relieved. Note that the thin portion 2 a of the upper lead frame 2 is preferably provided so as to protrude from the region above the semiconductor element 4 in the vertical direction. That is, it is preferable that the thickness of the upper lead frame 2 located in the vertically upper region of the semiconductor element 4 is thinner than the thickness of the other portions. Thereby, the thermal stress can be further relaxed.
　上側及び下側リードフレーム２，３の厚さは、例えば、１０～１０００μｍであり、電流容量と放熱性の観点から、望ましくは１００～５００μｍである。上側リードフレーム２の薄肉部２ａの厚さは、例えば、１０～２００μｍであり、望ましくは１０～１００μｍである。また、上側リードフレーム２の薄肉部２ａの厚さは、望ましくは、それ以外の部分の厚さの２分の１から１０分の１である。また、上側リードフレーム２の薄肉部２ａの長さ（図１の左右方向の長さ）は、例えば、半導体素子４の長さに１０～１０００μｍを加えた長さであり、望ましくは半導体素子４の長さに１０～２００μｍを加えた長さである。また、薄肉部２ａの形状は、線状であっても、板状であってもよい。なお、薄肉部２ａの形状は、図１に示すように一部が屈曲している方が塑性変形し易く、熱応力の緩和効果が大きいため望ましい。 The thickness of the upper and lower lead frames 2 and 3 is, for example, 10 to 1000 μm, and preferably 100 to 500 μm from the viewpoint of current capacity and heat dissipation. The thickness of the thin portion 2a of the upper lead frame 2 is, for example, 10 to 200 μm, and preferably 10 to 100 μm. Further, the thickness of the thin portion 2a of the upper lead frame 2 is desirably 1/2 to 1/10 of the thickness of other portions. The length of the thin portion 2a of the upper lead frame 2 (the length in the left-right direction in FIG. 1) is, for example, a length obtained by adding 10 to 1000 μm to the length of the semiconductor element 4, and desirably the semiconductor element 4 The length is 10 to 200 μm added to the length. Moreover, the shape of the thin part 2a may be linear or plate-shaped. In addition, as for the shape of the thin part 2a, as shown in FIG. 1, since the one part bent is easy to plastically deform and the relaxation effect of a thermal stress is large, it is desirable.
　また、下側リードフレーム３には、半導体素子４に複数の信号を入出力するための複数の入出力端子（垂直端子）３ａが設けられている。より詳しくは、下側リードフレーム３には、半導体素子４と半導体パッケージ１の外部の部品との間で複数の信号を入出力するための複数の入出力端子３ａが設けられている。複数の入出力端子３ａは、それぞれ、下側リードフレーム３から上側リードフレーム２に向けて突設され、上側リードフレーム２に設けられた穴２ｂに嵌合している。これにより、上側及び下側リードフレーム２，３が互いに電気的に接続されるとともに、上側及び下側リードフレーム２，３の相対位置が保持されている。 The lower lead frame 3 is provided with a plurality of input / output terminals (vertical terminals) 3 a for inputting and outputting a plurality of signals to and from the semiconductor element 4. More specifically, the lower lead frame 3 is provided with a plurality of input / output terminals 3a for inputting / outputting a plurality of signals between the semiconductor element 4 and components outside the semiconductor package 1. Each of the plurality of input / output terminals 3 a protrudes from the lower lead frame 3 toward the upper lead frame 2 and is fitted into a hole 2 b provided in the upper lead frame 2. As a result, the upper and lower lead frames 2 and 3 are electrically connected to each other, and the relative positions of the upper and lower lead frames 2 and 3 are maintained.
　入出力端子３ａの長さ（上側及び下側リードフレーム２，３間の距離）は、例えば、半導体素子４の厚さと、半導体素子４と下側リードフレーム３との接合部の厚さとの合計の厚さに、１０～２００μｍを加えた長さである。また、入出力端子３ａの長さは、望ましくは、前記合計の厚さに１０～１００μｍを加えた長さである。 The length of the input / output terminal 3a (the distance between the upper and lower lead frames 2 and 3) is, for example, the sum of the thickness of the semiconductor element 4 and the thickness of the junction between the semiconductor element 4 and the lower lead frame 3. The thickness is 10 to 200 μm added to the thickness. The length of the input / output terminal 3a is desirably a length obtained by adding 10 to 100 μm to the total thickness.
　また、上側及び下側リードフレーム２，３と半導体素子４とは、樹脂などの封止部材５により互いの隙間が封止されている。 In addition, the gap between the upper and lower lead frames 2 and 3 and the semiconductor element 4 is sealed by a sealing member 5 such as a resin.
　次に、本第１実施形態にかかる半導体パッケージの製造方法について説明する。図２Ａ～図２Ｇは、本第１実施形態にかかる半導体パッケージの製造方法を示す断面図である。 Next, a manufacturing method of the semiconductor package according to the first embodiment will be described. 2A to 2G are cross-sectional views showing a method for manufacturing a semiconductor package according to the first embodiment.
　まず、図２Ａに示す金属板Ａ２をハーフエッチング又はハーフダイシングすることにより、図２Ｂに示すように、薄肉部２ａ及び複数の穴２ｂを備える上側リードフレーム２を製造する。また、図２Ｃに示す金属板Ａ３をハーフエッチング又はハーフダイシングすることにより、図２Ｄに示すように、複数の入出力端子３ａを備える第２リードフレーム３を製造する。なお、上側リードフレーム２と下側リードフレーム３とは、特に製造順序が限定されるものではなく、いずれを先に製造してもよい。 First, by performing half etching or half dicing on the metal plate A2 shown in FIG. 2A, as shown in FIG. 2B, the upper lead frame 2 including the thin portion 2a and the plurality of holes 2b is manufactured. 2C is half-etched or half-diced to produce the second lead frame 3 having a plurality of input / output terminals 3a as shown in FIG. 2D. Note that the manufacturing order of the upper lead frame 2 and the lower lead frame 3 is not particularly limited, and either may be manufactured first.
　なお、「ハーフエッチング」及び「ハーフダイシング」は、いずれも材料の厚み方向に対し、一部を残して加工する方法である。なお、本発明の上側及び下側リードフレーム２，３の製造方法は、これらに限定されるものではなく、他の方法により製造されてもよい。 In addition, both “half etching” and “half dicing” are processing methods that leave a part in the thickness direction of the material. The manufacturing method of the upper and lower lead frames 2 and 3 of the present invention is not limited to these, and may be manufactured by other methods.
　次いで、図２Ｅに示すように、図示しない保持治具を利用して、上側リードフレーム２に設けられた複数の穴２ｂに、下側リードフレーム３に設けられた複数の入出力端子３ａを嵌合させる。すなわち、上側リードフレーム２と下側リードフレーム３とを、かしめにより接合する。 Next, as shown in FIG. 2E, a plurality of input / output terminals 3 a provided in the lower lead frame 3 are fitted into a plurality of holes 2 b provided in the upper lead frame 2 using a holding jig (not shown). Combine. That is, the upper lead frame 2 and the lower lead frame 3 are joined by caulking.
　次いで、図２Ｆに示すように、上側及び下側リードフレーム２，３間に形成された空間に半導体素子４を挿入し、上側リードフレーム２の薄肉部２ａと半導体素子４とを接続するとともに、下側リードフレーム３と半導体素子４とを接続する。図３は、上側及び下側リードフレーム２，３と半導体素子４とを接続した状態を示す平面図である。上側及び下側リードフレーム２，３と半導体素子４とは、例えば、めっき、低融点金属、超音波などで接合することができる。 Next, as shown in FIG. 2F, the semiconductor element 4 is inserted into the space formed between the upper and lower lead frames 2 and 3 to connect the thin portion 2a of the upper lead frame 2 and the semiconductor element 4, and The lower lead frame 3 and the semiconductor element 4 are connected. FIG. 3 is a plan view showing a state in which the upper and lower lead frames 2 and 3 and the semiconductor element 4 are connected. The upper and lower lead frames 2 and 3 and the semiconductor element 4 can be bonded by, for example, plating, a low melting point metal, ultrasonic waves, or the like.
　次いで、図２Ｇに示すように、上側及び下側リードフレーム２，３と半導体素子４との隙間を封止部材５により封止する。なお、この時、研削、ドライエッチングなどにより全体の平坦化を行うことが望ましい。 Next, as shown in FIG. 2G, the gap between the upper and lower lead frames 2, 3 and the semiconductor element 4 is sealed with a sealing member 5. At this time, it is desirable to flatten the entire surface by grinding, dry etching, or the like.
　次いで、図１に示すように、下側リードフレーム３を部分的にエッチングする。これにより、本第１実施形態にかかる半導体パッケージ１が製造される。 Next, as shown in FIG. 1, the lower lead frame 3 is partially etched. Thereby, the semiconductor package 1 according to the first embodiment is manufactured.
　本第１実施形態によれば、上側及び下側リードフレーム２，３の間に半導体素子４を配置することにより、半導体素子４の熱を上側及び下側リードフレーム２，３を通じて放熱することができる。すなわち、放熱方向を二方向にすることができる。これにより、半導体パッケージ１の放熱性能を向上させることができる。 According to the first embodiment, by disposing the semiconductor element 4 between the upper and lower lead frames 2 and 3, the heat of the semiconductor element 4 can be radiated through the upper and lower lead frames 2 and 3. it can. That is, the heat dissipation direction can be two directions. Thereby, the heat dissipation performance of the semiconductor package 1 can be improved.
　また、本第１実施形態によれば、上側リードフレーム２の薄肉部２ａと半導体素子４とを接続するようにしているので、薄肉部２ａが塑性変形することで、熱応力を緩和することができる。 Further, according to the first embodiment, since the thin portion 2a of the upper lead frame 2 and the semiconductor element 4 are connected, the thin portion 2a is plastically deformed so that the thermal stress can be reduced. it can.
　また、本第１態様によれば、下側リードフレーム３が複数の入出力端子３を備え、当該複数の入出力端子３ａが上側リードフレーム２に接続されるようにしているので、配線を従来よりも短縮することができる。 Further, according to the first aspect, the lower lead frame 3 includes the plurality of input / output terminals 3, and the plurality of input / output terminals 3a are connected to the upper lead frame 2, so that the wiring is conventionally provided. Can be shortened.
　また、本第１実施形態によれば、３つ以上の端子を同一面に設けることができる。例えば、半導体素子４が、下面にコレクタ端子、上面にエミッタ端子及びゲート端子を有するトランジスタの機能を備えている場合、下側リードフレーム３の側（図１の下側）から、コレクタ端子Ｃ、エミッタ端子Ｅ、ゲート端子Ｇの全ての端子を取り出すことができる。例えば、図１の右側の下側リードフレーム３をエミッタ端子Ｅ、図１の中央の下側リードフレーム３をコレクタ端子Ｃ、図１の左側の下側リードフレーム３をゲート端子Ｇとすることができる。 Also, according to the first embodiment, three or more terminals can be provided on the same surface. For example, when the semiconductor element 4 has the function of a transistor having a collector terminal on the lower surface and an emitter terminal and a gate terminal on the upper surface, the collector terminal C, from the lower lead frame 3 side (lower side in FIG. 1), All the terminals of the emitter terminal E and the gate terminal G can be taken out. For example, the lower lead frame 3 on the right side of FIG. 1 may be the emitter terminal E, the lower lead frame 3 in the center of FIG. 1 may be the collector terminal C, and the lower lead frame 3 on the left side of FIG. it can.
　なお、本発明は、前記第１実施形態に限定されるものではなく、その他種々の態様で実施できる。例えば、図４に示すように、上側リードフレーム２に接続されている複数の入出力端子３ａの１つ以上を、下側リードフレーム３から切り離すようにしてもよい。この場合、３つ以上の端子を上側及び下側リードフレーム２，３のいずれかから取り出すことができる。例えば、半導体素子４が、下面にコレクタ端子、上面にエミッタ端子及びゲート端子を有するトランジスタの機能を備えている場合、下側リードフレーム３側からエミッタ端子Ｅとゲート端子Ｇとを取り出し、上側リードフレーム２側からコレクタ端子Ｃを取り出すことができる。なお、図示していないが、下側リードフレーム３－１と下側リードフレーム３－２とは、接続されている。 The present invention is not limited to the first embodiment, and can be implemented in various other modes. For example, as shown in FIG. 4, one or more of the plurality of input / output terminals 3 a connected to the upper lead frame 2 may be separated from the lower lead frame 3. In this case, three or more terminals can be taken out from either the upper lead frame 2 or the lower lead frame 3. For example, when the semiconductor element 4 has the function of a transistor having a collector terminal on the lower surface and an emitter terminal and a gate terminal on the upper surface, the emitter terminal E and the gate terminal G are taken out from the lower lead frame 3 side, and the upper lead The collector terminal C can be taken out from the frame 2 side. Although not shown, the lower lead frame 3-1 and the lower lead frame 3-2 are connected.
　また、前記では、上側リードフレーム２にのみ薄肉部２ａを設けたが、本発明はこれに限定されない。上側及び下側リードフレーム２，３の少なくとも一方に、薄肉部を設ければよい。これにより、熱応力を緩和することができる。 In the above description, the thin portion 2a is provided only on the upper lead frame 2, but the present invention is not limited to this. A thin portion may be provided on at least one of the upper and lower lead frames 2 and 3. Thereby, thermal stress can be relieved.
　また、前記では、上側リードフレーム２に複数の穴２ｂを設け、下側リードフレーム３に複数の入出力端子３ａを設けたが、本発明はこれに限定されない。下側リードフレーム３に複数の穴を設け、上側リードフレーム２に複数の入出力端子を設けてもよい。なお、この場合、下側リードフレーム３が第１のリードフレームとなり、上側リードフレーム２が第２のリードフレームとなる。また、複数の入出力端子３ａ及びそれに対応する複数の穴２ｂは、下側リードフレーム３と上側リードフレーム２の両方に設けられてもよい。 In the above description, the upper lead frame 2 is provided with a plurality of holes 2b and the lower lead frame 3 is provided with a plurality of input / output terminals 3a. However, the present invention is not limited to this. A plurality of holes may be provided in the lower lead frame 3, and a plurality of input / output terminals may be provided in the upper lead frame 2. In this case, the lower lead frame 3 becomes the first lead frame, and the upper lead frame 2 becomes the second lead frame. Further, the plurality of input / output terminals 3 a and the plurality of holes 2 b corresponding thereto may be provided in both the lower lead frame 3 and the upper lead frame 2.
　なお、図５に示すように、半導体パッケージ１に絶縁部材６を介してヒートシンク７を取り付けることにより、小型で熱応力に強い半導体モジュールを実現することができる。 As shown in FIG. 5, a small semiconductor module that is resistant to thermal stress can be realized by attaching a heat sink 7 to the semiconductor package 1 via an insulating member 6.
　また、図６に示すように、半導体パッケージ１に制御回路基板８を取り付けることにより、制御回路基板８が一体化された小型の半導体モジュールを実現することができる。なお、半導体パッケージ１と制御回路基板８とは、例えば、半田などの低融点金属、インダクタンス結合などにより接合することができる。 Further, as shown in FIG. 6, by attaching the control circuit board 8 to the semiconductor package 1, a small semiconductor module in which the control circuit board 8 is integrated can be realized. The semiconductor package 1 and the control circuit board 8 can be bonded by, for example, a low melting point metal such as solder, inductance coupling, or the like.
　また、図７に示すように、上側及び下側リードフレーム２，３の少なくとも一方の外面と接触するように金属構造体９を設けることにより、当該金属構造体９を通じて放熱することができる。これにより、放熱性能の高い半導体モジュールを実現することができる。なお、上側及び下側リードフレーム２，３と金属構造体９とは、例えば、半田などの低融点金属、圧接、金バンプなどにより接合することができる。 Further, as shown in FIG. 7, by providing the metal structure 9 so as to be in contact with at least one outer surface of the upper and lower lead frames 2, 3, heat can be radiated through the metal structure 9. Thereby, a semiconductor module with high heat dissipation performance can be realized. The upper and lower lead frames 2 and 3 and the metal structure 9 can be joined by, for example, a low melting point metal such as solder, pressure welding, gold bumps, or the like.
　また、上側及び下側リードフレーム２，３のパターンを工夫し、複数の半導体素子４を備えることにより、半導体パッケージに回路機能を持たせることも可能である。図８Ａ及び図８Ｂは、２つの半導体素子４を備える半導体パッケージの構成例を模式的に示す平面図である。図８Ａは、当該半導体パッケージの下半分を上方から見た平面図であり、図８Ｂは、当該半導体パッケージを上方から見た平面図である。図８Ａ及び図８Ｂにおいては、封止部材５を透過して示している。 Further, the semiconductor package can be provided with a circuit function by devising the patterns of the upper and lower lead frames 2 and 3 and providing a plurality of semiconductor elements 4. 8A and 8B are plan views schematically showing a configuration example of a semiconductor package including two semiconductor elements 4. FIG. 8A is a plan view of the lower half of the semiconductor package as viewed from above, and FIG. 8B is a plan view of the semiconductor package as viewed from above. 8A and 8B show the sealing member 5 in a transparent manner.
　図８Ａ及び図８Ｂの各半導体素子４は、上面にゲート端子とエミッタ端子を備え、下面にコレクタ端子を備えている。図８Ａ及び図８Ｂにおいて、「Ｐ」、「Ｎ」はＤＣ端子、「ＡＣ」はＡＣ端子、「Ｇ」はゲート端子の外部端子を示している。また、「２ａｇ」は半導体素子４のゲート端子に接続される上側リードフレーム２の薄肉部、「２ａｅ」は半導体素子４のエミッタ端子に接続される上側リードフレーム２の薄肉部を示している。このように構成することで、半導体パッケージをハーフブリッジ回路（ダイオードは図示せず）として機能させることができる。 Each semiconductor element 4 in FIGS. 8A and 8B has a gate terminal and an emitter terminal on the upper surface, and a collector terminal on the lower surface. 8A and 8B, “P” and “N” indicate DC terminals, “AC” indicates AC terminals, and “G” indicates external terminals of the gate terminals. “2ag” indicates a thin portion of the upper lead frame 2 connected to the gate terminal of the semiconductor element 4, and “2ae” indicates a thin portion of the upper lead frame 2 connected to the emitter terminal of the semiconductor element 4. With this configuration, the semiconductor package can function as a half-bridge circuit (a diode is not shown).
　また、図９に示すように、２つの半導体パッケージ１を、上面と下面にリードフレームを備える構造体１０を介して接続することで、ハーフブリッジ回路（ダイオードは図示せず）として機能する半導体モジュールを実現することができる。 Further, as shown in FIG. 9, a semiconductor module that functions as a half-bridge circuit (diode not shown) by connecting two semiconductor packages 1 via a structure 10 having a lead frame on the upper and lower surfaces. Can be realized.
　《第２実施形態》
　図１０は、本発明の第２実施形態にかかる半導体パッケージの構造を模式的に示す断面図である。 << Second Embodiment >>
FIG. 10 is a cross-sectional view schematically showing the structure of the semiconductor package according to the second embodiment of the present invention.
　本第２実施形態の半導体パッケージが前記第１実施形態の半導体パッケージと異なる点は、上側リードフレーム２Ａが、材料の異なる２つ金属部材２１，２２で構成されている点である。 The semiconductor package of the second embodiment is different from the semiconductor package of the first embodiment in that the upper lead frame 2A is composed of two metal members 21 and 22 made of different materials.
　本第２実施形態において、半導体素子４と接続される薄肉部２ａを構成する金属部材２２は、金属部材２１よりもヤング率の低い材料で構成されている。例えば、金属部材２２はアルミニウムで構成され、金属部材２１は銅で構成される。アルミニウムのヤング率は約７０ＧＰａであり、銅のヤング率は約１２０ＧＰａである。半導体素子４と接続される金属部材２２を金属部材２１よりもヤング率の低い材料で構成することにより、上側リードフレーム２Ａの熱応力緩和機能を向上させることができる。 In the second embodiment, the metal member 22 constituting the thin portion 2 a connected to the semiconductor element 4 is made of a material having a Young's modulus lower than that of the metal member 21. For example, the metal member 22 is made of aluminum, and the metal member 21 is made of copper. The Young's modulus of aluminum is about 70 GPa and the Young's modulus of copper is about 120 GPa. By configuring the metal member 22 connected to the semiconductor element 4 with a material having a Young's modulus lower than that of the metal member 21, the thermal stress relaxation function of the upper lead frame 2A can be improved.
　上側リードフレーム２Ａは、例えば、図１１Ａに示すように積層した材料の異なる２枚の金属板Ａ２１，Ａ２２を、図１１Ｂに示すように選択エッチングすることにより形成することができる。なお、「選択エッチング」は、材料毎にエッチングをする方法である。但し、上側リードフレーム２Ａの形成方法は、この方法に限定されるものではなく、他の方法でもよい。 The upper lead frame 2A can be formed, for example, by selectively etching two metal plates A21 and A22 having different materials stacked as shown in FIG. 11A as shown in FIG. 11B. “Selective etching” is a method of performing etching for each material. However, the method of forming the upper lead frame 2A is not limited to this method, and other methods may be used.
　なお、上側及び下側リードフレーム２，３の材料としては、例えば、金、銀、銅、ニッケル、アルミニウム、錫、パラジウム、タングステンが挙げられる。上側リードフレーム２の材料と下側リードフレーム３の材料との組合せは、特に限定されるものではないが、熱応力を緩和することができる組合せであることが望ましい。 Note that examples of the material of the upper and lower lead frames 2 and 3 include gold, silver, copper, nickel, aluminum, tin, palladium, and tungsten. The combination of the material of the upper lead frame 2 and the material of the lower lead frame 3 is not particularly limited, but is preferably a combination that can relieve thermal stress.
　《第３実施形態》
　図１２は、本発明の第３実施形態にかかる半導体パッケージの構造を模式的に示す断面図である。 << Third Embodiment >>
FIG. 12 is a cross-sectional view schematically showing the structure of the semiconductor package according to the third embodiment of the present invention.
　本第３実施形態の半導体パッケージが前記第１実施形態の半導体パッケージと異なる点は、半導体素子４の表面に弾性部材１１が設けられるとともに、弾性部材１１に設けられた貫通穴１１ａに導電性部材１２が挿入されている点である。 The semiconductor package of the third embodiment is different from the semiconductor package of the first embodiment in that an elastic member 11 is provided on the surface of the semiconductor element 4 and a conductive member is provided in a through hole 11a provided in the elastic member 11. 12 is inserted.
　弾性部材１１は、半導体素子４を覆う（封止する）ように、半導体素子４の周囲に設けられている。弾性部材１１が弾性変形することにより、熱応力をより一層抑えることができる。弾性部材１１の材料としては、例えばエラストマが挙げられる。なお、弾性部材１１の材料は、特に限定されるものではないが、熱応力を緩和することができる材料であることが望ましい。また、弾性部材１１の材料は、封止部材５の材料と同じであってもよい。 The elastic member 11 is provided around the semiconductor element 4 so as to cover (seal) the semiconductor element 4. When the elastic member 11 is elastically deformed, the thermal stress can be further suppressed. Examples of the material of the elastic member 11 include an elastomer. The material of the elastic member 11 is not particularly limited, but is preferably a material that can relieve thermal stress. Further, the material of the elastic member 11 may be the same as the material of the sealing member 5.
　弾性部材１１には、複数の貫通穴１１ａが設けられている。導電性部材１２は、上側リードフレーム２と半導体素子４、及び上側リードフレーム２と半導体素子４とを接続するように、複数の貫通穴１１ａのそれぞれに挿入されている。貫通穴１１ａの高さは、例えば１０～５００μｍであり、望ましくは１０～２００μｍである。導電性部材１２の材料としては、例えば、金、銀、銅、ニッケル、アルミニウム、錫、パラジウム、タングステンが挙げられる。 The elastic member 11 is provided with a plurality of through holes 11a. The conductive member 12 is inserted into each of the plurality of through holes 11 a so as to connect the upper lead frame 2 and the semiconductor element 4 and the upper lead frame 2 and the semiconductor element 4. The height of the through hole 11a is, for example, 10 to 500 μm, and preferably 10 to 200 μm. Examples of the material of the conductive member 12 include gold, silver, copper, nickel, aluminum, tin, palladium, and tungsten.
　半導体素子４と弾性部材１１と導電性部材１２との構造体は、例えば、以下のようにして製造することができる。 The structure of the semiconductor element 4, the elastic member 11, and the conductive member 12 can be manufactured as follows, for example.
　まず、図１３Ａに示すように、半導体素子４の全体を覆うように弾性部材Ａ１１を形成する。 First, as shown in FIG. 13A, an elastic member A11 is formed so as to cover the entire semiconductor element 4.
　次いで、図１３Ｂに示すように、弾性部材Ａ１１の複数箇所に複数の貫通穴１１ａを形成し、弾性部材１１を形成する。当該複数の貫通穴１１ａは、例えば、レーザを照射することにより形成することができる。 Next, as shown in FIG. 13B, a plurality of through holes 11a are formed at a plurality of locations of the elastic member A11 to form the elastic member 11. The plurality of through holes 11a can be formed by, for example, laser irradiation.
　次いで、図１３Ｃに示すように、弾性部材１１の複数の貫通穴１１ａのそれぞれに導電性部材１２を形成する。当該導電性部材１２は、例えば、めっきや印刷などにより形成することができる。 Next, as shown in FIG. 13C, the conductive member 12 is formed in each of the plurality of through holes 11 a of the elastic member 11. The conductive member 12 can be formed by, for example, plating or printing.
　《第４実施形態》
　図１４は、本発明の第４実施形態にかかる半導体パッケージの構造を模式的に示す断面図である。 << 4th Embodiment >>
FIG. 14 is a cross-sectional view schematically showing the structure of the semiconductor package according to the fourth embodiment of the present invention.
　本第４実施形態の半導体パッケージが前記第３実施形態の半導体パッケージと異なる点は、上側リードフレーム２Ａが、材料の異なる２つ金属部材２１，２２で構成されるとともに、上側及び下側リードフレーム２Ａ，３にめっき１３が施されている点である。めっき１３の厚さは、例えば１～１０μｍである。 The semiconductor package of the fourth embodiment is different from the semiconductor package of the third embodiment in that the upper lead frame 2A is composed of two metal members 21 and 22 made of different materials, and the upper and lower lead frames. 2A and 3 are plated 13. The thickness of the plating 13 is, for example, 1 to 10 μm.
　この構造によれば、例えば、めっき１３を銅で構成することにより、上側及び下側リードフレーム２Ａ，３を、半田などの低融点金属により、半導体素子４（又は導電性部材１２）と接合することができる。すなわち、この構造によれば、半田などの低融点金属による接合など、上側及び下側リードフレーム２Ａ，３と、半導体素子４（又は導電性部材１２）との接合方法の選択肢を増やすことができる。また、この構造によれば、例えば、金属部材２２がアルミニウムで構成されるような場合に、内部破断が生じることを抑えることができる。 According to this structure, for example, the plating 13 is made of copper, so that the upper and lower lead frames 2A and 3 are joined to the semiconductor element 4 (or the conductive member 12) with a low melting point metal such as solder. be able to. That is, according to this structure, it is possible to increase options for a method of joining the upper and lower lead frames 2A, 3 and the semiconductor element 4 (or the conductive member 12) such as joining with a low melting point metal such as solder. . Moreover, according to this structure, when the metal member 22 is comprised with aluminum, it can suppress that an internal fracture arises, for example.
　なお、本第４実施形態では、上側リードフレーム２Ａが、材料の異なる２つ金属部材２１，２２で構成されるものとしたが、本発明はこれに限定されない。例えば、上側リードフレーム２Ａとして、図１に示す上側リードフレーム２が用いられてもよい。例えば、上側リードフレーム２の材料を銅とした場合、めっき１３の材料をニッケル又は金とすることで、上側リードフレーム２の酸化を防ぐことができる。 In the fourth embodiment, the upper lead frame 2A is composed of two metal members 21 and 22 made of different materials, but the present invention is not limited to this. For example, the upper lead frame 2 shown in FIG. 1 may be used as the upper lead frame 2A. For example, when the material of the upper lead frame 2 is copper, oxidation of the upper lead frame 2 can be prevented by using nickel or gold as the material of the plating 13.
　なお、前記第３実施形態にかかる図１２においては、上側リードフレーム２Ａと下側リードフレーム３とをかしめにより接合するものとして図示したが、本発明はこれに限定されない。例えば、めっき１３により、上側リードフレーム２Ａと下側リードフレーム３とを接合するようにしてもよい。 In FIG. 12 according to the third embodiment, the upper lead frame 2A and the lower lead frame 3 are illustrated as being joined by caulking, but the present invention is not limited to this. For example, the upper lead frame 2 </ b> A and the lower lead frame 3 may be joined by plating 13.
　例えば、図１５Ａに示すように、上側リードフレーム２と下側リードフレーム３とを組み合わせた際、穴２ｂと入出力端子３ａとの間に隙間３０が形成されるように、穴２ｂと入出力端子３ａとを形成する。この図１５Ａの状態で、上側及び下側リードフレーム２，３の全体にめっき１３を形成する。これにより、図１５Ｂに示すように、めっき１３が隙間３０に入り込むことで、上側リードフレーム２Ａと下側リードフレーム３とを接合することができる。 For example, as shown in FIG. 15A, when the upper lead frame 2 and the lower lead frame 3 are combined, the hole 2b and the input / output so that a gap 30 is formed between the hole 2b and the input / output terminal 3a. Terminal 3a is formed. In the state of FIG. 15A, the plating 13 is formed on the entire upper and lower lead frames 2 and 3. As a result, as shown in FIG. 15B, the upper lead frame 2 </ b> A and the lower lead frame 3 can be joined by the plating 13 entering the gap 30.
　また、半田などの低融点金属により、上側リードフレーム２Ａと下側リードフレーム３とを接合するようにしてもよい。低融点金属により接合する場合、拡散接合を行い、これにより作製した合金の融点を上昇させることが望ましい。 Alternatively, the upper lead frame 2A and the lower lead frame 3 may be joined with a low melting point metal such as solder. When joining with a low-melting-point metal, it is desirable to perform diffusion bonding and thereby raise the melting point of the produced alloy.
　なお、前記では、上側リードフレーム２の複数の穴２ｂの全てに、下側リードブレーム３の入出力端子３ａが接続されるものとしたが、複数の穴２ｂの一部に入出力端子３ａが接続されるようにしてもよい。このような構造は、例えば、図１６Ａに示すように、上側リードフレーム２に接続しない入出力端子３ａａに対応する穴２ｂａの直径を他の穴２ｂよりも大きくし、その後、図１６Ｂに示すように、上側リードフレーム２にめっき１３を施すことで実現できる。下側リードブレーム３の一部の入出力端子３ａａを上側リードフレーム２に接続しないことで、半導体パッケージとしての端子を、上側及び下側リードフレーム２，３の両方から取り出すことが可能になる。 In the above description, the input / output terminals 3a of the lower lead frame 3 are connected to all of the plurality of holes 2b of the upper lead frame 2. However, the input / output terminals 3a are partially connected to the plurality of holes 2b. You may make it connect. In such a structure, for example, as shown in FIG. 16A, the diameter of the hole 2ba corresponding to the input / output terminal 3aa not connected to the upper lead frame 2 is made larger than that of the other holes 2b, and thereafter, as shown in FIG. 16B. In addition, this can be realized by applying plating 13 to the upper lead frame 2. By not connecting a part of the input / output terminals 3aa of the lower lead frame 3 to the upper lead frame 2, it is possible to take out terminals as a semiconductor package from both the upper and lower lead frames 2 and 3.
　また、以下のような製造方法によっても、上側リードフレーム２と入出力端子３ａの一部とを接続しないようにすることができる。 Also, the upper lead frame 2 and a part of the input / output terminal 3a can be prevented from being connected by the following manufacturing method.
　まず、図１７Ａに示すように、上側リードフレーム２に接続しない入出力端子３ａａに対応する穴２ｂｂ以外の箇所をレジスト膜１４で覆う。 First, as shown in FIG. 17A, a portion other than the hole 2bb corresponding to the input / output terminal 3aa not connected to the upper lead frame 2 is covered with a resist film.
　次いで、図１７Ｂに示すように、上側リードフレーム２の穴２ｂｂの周囲に絶縁領域１５を形成する。例えば、上側リードフレーム２がアルミニウムで構成される場合、上側リードフレーム２の穴２ｂｂの周囲を酸化させることで、当該周囲の部分が酸化アルミニウムとなり、絶縁領域１５が形成される。これにより、上側リードフレーム２の入出力端子３ａａと接続される部分に絶縁性が付与される。 Next, as shown in FIG. 17B, an insulating region 15 is formed around the hole 2bb of the upper lead frame 2. For example, when the upper lead frame 2 is made of aluminum, by oxidizing the periphery of the hole 2bb of the upper lead frame 2, the surrounding portion becomes aluminum oxide and the insulating region 15 is formed. As a result, insulation is imparted to the portion of the upper lead frame 2 connected to the input / output terminal 3aa.
　次いで、図１７Ｃに示すように、上側リードフレーム２の各穴２ｂ，２ｂｂに、下側リードフレーム３の各入出力端子３ａ，３ａａを挿入した後、めっき１３を施す。これにより、上側リードフレーム２と入出力端子３ａの一部とを接続しないようにすることができ、半導体パッケージとしての端子を、上側及び下側リードフレーム２，３の両方から取り出すことが可能になる。 Next, as shown in FIG. 17C, after the input / output terminals 3a and 3aa of the lower lead frame 3 are inserted into the holes 2b and 2bb of the upper lead frame 2, plating 13 is applied. As a result, the upper lead frame 2 and a part of the input / output terminal 3a can be prevented from being connected, and a terminal as a semiconductor package can be taken out from both the upper and lower lead frames 2 and 3. Become.
　なお、前記様々な実施形態のうちの任意の実施形態を適宜組み合わせることにより、それぞれの有する効果を奏するようにすることができる。 It should be noted that, by appropriately combining arbitrary embodiments of the various embodiments described above, the effects possessed by them can be produced.
　本発明は、添付図面を参照しながら好ましい実施の形態に関連して充分に記載されているが、この技術に熟練した人々にとっては種々の変形や修正は明白である。そのような変形や修正は、添付した請求の範囲による本発明の範囲から外れない限りにおいて、その中に含まれると理解されるべきである。 Although the present invention has been fully described in connection with preferred embodiments with reference to the accompanying drawings, various changes and modifications will be apparent to those skilled in the art. Such changes and modifications are to be understood as being included therein, so long as they do not depart from the scope of the present invention according to the appended claims.
　２０１２年４月２０日に出願された日本国特許出願Ｎｏ．２０１２－９６３１０号の明細書、図面、および特許請求の範囲の開示内容は、全体として参照されて本明細書の中に取り入れられるものである。 Japanese patent application No. filed on April 20, 2012. The disclosures of the specification, drawings, and claims of 2012-96310 are hereby incorporated by reference in their entirety.
　本発明にかかる半導体パッケージ及びその製造方法、半導体モジュール、並びに半導体装置は、放熱能力の向上、熱応力の緩和、及び配線の短縮化を実現することができるので、パワー半導体素子の応用だけでなく、ＬＳＩの３次元実装化、ＣＳＰ（Chip Scale Package）などにも応用できる。 Since the semiconductor package and the manufacturing method thereof, the semiconductor module, and the semiconductor device according to the present invention can realize improvement in heat dissipation capability, relaxation of thermal stress, and shortening of wiring, not only the application of power semiconductor elements. It can also be applied to three-dimensional mounting of LSI, CSP (Chip Scale Package), and the like.
　　１　　半導体パッケージ
　　２　　上側リードフレーム
　　２ａ　薄肉部
　　２ｂ　穴
　　３　　下側リードフレーム
　　３ａ　入出力端子
　　４　　半導体素子
　　５　　封止部材
　　６　　絶縁部材
　　７　　ヒートシンク
　　８　　制御回路基板
　　９　　金属構造体
　１０　　構造体
　１１　　弾性部材
　１１ａ　貫通穴
　１２　　導電性部材
　１３　　メッキ
　１４　　レジスト膜
　１５　　絶縁領域
　２１，２２　　金属部材
　３０　　隙間 DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 Upper lead frame 2a Thin part 2b Hole 3 Lower lead frame 3a Input / output terminal 4 Semiconductor element 5 Sealing member 6 Insulating member 7 Heat sink 8 Control circuit board 9 Metal structure 10 Structure 11 Elastic member 11a Through hole 12 Conductive member 13 Plating 14 Resist film 15 Insulating region 21, 22 Metal member 30 Gap

Claims (14)

  1. 　第１のリードフレームと、
    　前記第１のリードフレームと対向するように配置された第２のリードフレームと、
    　前記第１及び第２のリードフレーム間に配置された半導体素子と、
    　前記第１及び第２のリードフレームと前記半導体素子とを封止する封止部材と、
    　を備える半導体パッケージであって、
    　前記第１及び第２のリードフレームの少なくとも一方は、前記半導体素子と接続される部分の近傍の厚さがそれ以外の部分の厚さよりも薄く形成され、
    　前記第２のリードフレームは、前記半導体素子に複数の信号を入出力するための複数の入出力端子を備え、
    　前記複数の入出力端子の少なくとも１つは、前記第２のリードフレームから前記第１のリードフレームに向けて突設され、当該第１のリードフレームに設けられた穴に挿入されることにより、前記第１のリードフレームと電気的に接続されるとともに前記第１及び第２のリードフレームの相対位置を保持する、半導体パッケージ。     A first lead frame;
    A second lead frame arranged to face the first lead frame;
    A semiconductor element disposed between the first and second lead frames;
    A sealing member for sealing the first and second lead frames and the semiconductor element;
    A semiconductor package comprising:
    At least one of the first and second lead frames is formed such that the thickness in the vicinity of the portion connected to the semiconductor element is thinner than the thickness of the other portion.
    The second lead frame includes a plurality of input / output terminals for inputting / outputting a plurality of signals to / from the semiconductor element,
    At least one of the plurality of input / output terminals protrudes from the second lead frame toward the first lead frame, and is inserted into a hole provided in the first lead frame. A semiconductor package electrically connected to the first lead frame and maintaining a relative position between the first and second lead frames.
  2. 　前記第１及び第２のリードフレームの少なくとも一方は、互いに材料が異なる２以上の金属部材で構成されている、請求項１に記載の半導体パッケージ。 2. The semiconductor package according to claim 1, wherein at least one of the first and second lead frames is composed of two or more metal members made of different materials.
  3. 　前記半導体素子と接続される部分の近傍は、他の金属部材よりもヤング率が低い金属部材で構成されている、請求項２に記載の半導体パッケージ。 The semiconductor package according to claim 2, wherein the vicinity of the portion connected to the semiconductor element is made of a metal member having a Young's modulus lower than that of other metal members.
  4. 　前記半導体素子の表面に設けられた弾性部材と、
    　前記弾性部材に設けられた貫通穴に挿入され、前記第１及び第２のリードフレームの少なくとも一方と前記半導体素子とを接続する導電性部材と、
    　をさらに備える、請求項１～３のいずれか１つに記載の半導体パッケージ。     An elastic member provided on a surface of the semiconductor element;
    A conductive member that is inserted into a through hole provided in the elastic member and connects at least one of the first and second lead frames and the semiconductor element;
    The semiconductor package according to any one of claims 1 to 3, further comprising:
  5. 　前記第１のリードフレームの前記入出力端子と接続される部分に絶縁性が付与されている、請求項１～４のいずれか１つに記載の半導体パッケージ。 5. The semiconductor package according to claim 1, wherein a portion connected to the input / output terminal of the first lead frame is provided with an insulating property.
  6. 　前記半導体素子は、パワー半導体素子である、請求項１～５のいずれか１つに記載の半導体パッケージ。 The semiconductor package according to any one of claims 1 to 5, wherein the semiconductor element is a power semiconductor element.
  7. 　請求項１～６のいずれか１つに記載の半導体パッケージを備える半導体モジュール。 A semiconductor module comprising the semiconductor package according to any one of claims 1 to 6.
  8. 　前記半導体パッケージの前記第１及び第２のリードフレームの少なくとも一方の外面と接触する金属構造体を備える、請求項７に記載の半導体モジュール。 The semiconductor module according to claim 7, further comprising a metal structure that contacts at least one outer surface of the first and second lead frames of the semiconductor package.
  9. 　請求項７又は８に記載の半導体モジュールを２つ以上有する半導体装置。 A semiconductor device having two or more semiconductor modules according to claim 7 or 8.
  10. 　第１のリードフレームに設けられた複数の穴に、第２のリードフレームに設けられた複数の入出力端子を挿入して、当該複数の入出力端子の少なくとも１つを前記第１のリードフレームに接続し、
    　前記第１のリードフレームと前記第２のリードフレームとの間に形成された空間に半導体素子を挿入し、
    　前記第１及び第２のリードフレームの少なくとも一方に設けた他の部分よりも厚さが薄い部分と前記半導体素子とを接続し、
    　前記第１及び第２のリードフレームと前記半導体素子との隙間を封止部材により封止し、
    　前記第２のリードフレームを部分的にエッチングする、
    　ことを含む、半導体パッケージの製造方法。     A plurality of input / output terminals provided in the second lead frame are inserted into a plurality of holes provided in the first lead frame, and at least one of the plurality of input / output terminals is connected to the first lead frame. Connected to
    A semiconductor element is inserted into a space formed between the first lead frame and the second lead frame;
    Connecting the semiconductor element with a portion having a smaller thickness than the other portion provided on at least one of the first and second lead frames;
    Sealing a gap between the first and second lead frames and the semiconductor element with a sealing member;
    Partially etching the second lead frame;
    A method for manufacturing a semiconductor package.
  11. 　前記第２のリードフレームは、金属板をハーフエッチング又はハーフダイシングすることにより形成される、請求項１０に記載の半導体パッケージの製造方法。 The method of manufacturing a semiconductor package according to claim 10, wherein the second lead frame is formed by half-etching or half-dicing a metal plate.
  12. 　前記第１のリードフレームは、積層した材料の異なる２枚の金属板を選択エッチングすることにより形成される、請求項１０又は１１に記載の半導体パッケージの製造方法。 12. The method of manufacturing a semiconductor package according to claim 10, wherein the first lead frame is formed by selectively etching two metal plates having different laminated materials.
  13. 　前記第１のリードフレームと第２のリードフレームとは、めっき、低融点金属、又は、かしめにより接合される、請求項１０～１２のいずれか１つに記載の半導体パッケージの製造方法。 The method of manufacturing a semiconductor package according to any one of claims 10 to 12, wherein the first lead frame and the second lead frame are joined by plating, a low melting point metal, or caulking.
  14. 　前記第１及び第２のリードフレームの少なくとも一方と前記半導体素子とは、超音波、低融点金属、又は、めっきにより接合される、請求項１０～１３のいずれか１つに記載の半導体パッケージの製造方法。 The semiconductor package according to any one of claims 10 to 13, wherein at least one of the first and second lead frames and the semiconductor element are joined by ultrasonic waves, a low melting point metal, or plating. Production method.
PCT/JP2013/000155 2012-04-20 2013-01-16 Semiconductor package and method for producing same, semiconductor module, and semiconductor device WO2013157172A1 (en)

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JPWO2022149317A1 (en) * 2021-01-05 2022-07-14
WO2022149317A1 (en) * 2021-01-05 2022-07-14 株式会社村田製作所 Terminal, electronic component package, and method for manufacturing terminal
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