WO2013156990A1

WO2013156990A1 - Memory cell based on electro-statically formed nanowire

Info

Publication number: WO2013156990A1
Application number: PCT/IL2013/050244
Authority: WO
Inventors: Gil Shalev; Yossi Rosenwaks
Original assignee: Ramot At Tel-Aviv University Ltd.
Priority date: 2012-04-19
Filing date: 2013-03-14
Publication date: 2013-10-24

Abstract

A memory cell including at least one electrostatically induced virtual nanowire by which it stores and reads data. In an exemplary embodiment of the invention, the nanowire is created using two lateral gates whose bias determines the nanowire location and thereby the location of a memory storage within said cell.

Description

MEMORY CELL BASED ON ELECTRO-STATICALLY FORMED NANOWIRE

RELATED APPLICATIONS

This application claims the benefit under 35 U.S.C. § 119(e) from U.S. Provisional Patent Application No. 61/635,402 filed on April 19, 2012, the contents of which are incorporated by reference as if fully set forth herein.

This application is related to U.S. Provisional Patent Application No. 61/604,041 filed on February 28, 2012, and to PCT Patent Application PCT/IL2013/050182, filed on February 28, 2013, the contents of which are incorporated by reference as if fully set forth herein.

FIELD AND BACKGROUND OF THE INVENTION

The present invention, in some embodiments thereof, relates to a memory device using virtual nanowires to store and/or access data, optionally more than one nanowire per cell.

Memory devices for non-volatile storage of information are used for various applications. A few examples are read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM.

ROM devices typically suffer from the disadvantage of not being electrically programmable memory devices. ROM programming takes place during manufacturing with masks containing the data to be stored, and hence ROM data is determined before manufacture. EPROM devices remove the need for masks programming but the complexity of the process typically increases significantly, and the die size may be larger due to the addition of programming circuitry. EPROMs are electrically programmed, but for erasing, EPROMs use exposure to ultraviolet (UV) light, and therefore EPROM are constructed with windows transparent to UV. EEPROMs have the advantage of both electrical programming and erasing. Flash EEPROMs are similar to EEPROM with the additional feature that allow the erasing of multiple memory cells at once and the writing of individual cells. FLASH EEPROM typically requires complex and expensive manufacturing. An EEPROM device with oxide-nitride-oxide (ONO) gate dielectric is apparently described by T.Y. Chan, K.K. Young and Chenming Hu, "A true single transistor oxide-nitride-oxide EEPROM device," IEEE Electron Device Letters, Vol. EDL-8, No. 3, p. 93-95 (1987). The memory cell is programmed using hot electron injection where the injected charge is stored in the ONO layer. A model for charge transport and trapping in thin nitride-oxide stacked films is described by K. K. Young, Chenming Hu, and William G. Oldham, "Charge Transport and Trapping Characteristics in Thin Nitride-Oxide Stacked Films," IEEE Electron Device Letters, Vol. 9, No. 11, p. 616-618 (1988).

Alternatively, charge is trapped in another type of material instead of an ONO layer, for example a layer of semiconductor or metallic nanoparticles. Memory devices using charge stored in silicon nanocrystals are described by Tiwari et al, "A silicon nanocrystals based memory," App. Phys. Lett. 68, 1377-1379 (1996), and by Kapetanakis et al, "Charge storage and interface states effects in Si-nanocrystal memory obtained using low-energy Si+ implantation and annealing," Appl. Phys. Lett. 77, 3450- 3452 (2000). Jang-Sik Lee et al, "Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties," Nature Nanotechnology 2, 790-795 (2007) describes a memory device using a multi-layer film consisting of gold nanoparticles alternating with polyelectrolyte insulating layers, the latter comprising poly(allylamine)/poly(styrenesulfonate) deposited on hafnium oxide coated silicon substrates.

Multi-bit transistors use multi-level thresholds to store more than one bit. Multiple threshold FLASH devices typically use an initial erase cycle in order to make sure all memory cells are below a certain threshold. Thereafter, when writing, the threshold is increased until the needed threshold is achieved. As this technique required constant feedback, multi-level programming is generally slow. Some additional problems typically found in such FLASH devices are a decrease in window of operation, reliability issues due to changes over time of the threshold windows, reduced yield, high electric field in the channel, and an increase in programming time in order to support multitude of threshold voltages. The following reviews several publications related to multi-bit semiconductor memory cells. U.S Patent 5,021,999 to Kohda et al. shows a MOS transistor-based non-volatile memory cell. The floating gate is divided into two electrically distinct areas, and in this way obtains three levels of data.

U.S Patent 5,214,303, to Aoki shows a multi-bit transistor which comprises a semiconductor substrate, a gate formed on the substrate, source/drain regions, and an offset step defined in at least one of the source/drain regions that extends downward to the location of the gate electrode.

U.S. Patent 5,414,693 to Ma et al. shows a Flash EEPROM with a spilt gate. The device uses one select gate transistor and two floating gate transistors where each bit is stored in a different transistor.

U.S. Patent 5,434,825 to Harari shows a multi-bit EEPROM with multiple positive and negative threshold voltages. The memory cell comprises a data storage transistor with a series pass transistor.

U.S. Patent 7,405,969 to Eitan shows a two-bit EEPROM device that uses a charge trapping layer (i.e. e.g. ONO). The two-bit mode is formed as electrons can injected into the ONO on either the drain or source ends.

Additional background art includes the following publication which may show non- volatile memory based on vertical silicon nanowires:

1. Y. Sun, H. Y. Yu, N. Singh, K. C. Leong, E. Gnani, G. Baccarani, G. Q. Lo, and D. L. Kwong, "Vertical-Si-Nanowire-Based Nonvolatile Memory Devices With

Improved Performance and Reduced Process Complexity", IEEE transaction on electron devices, vol58, no5, 2011

2. J. Fu, N. Singh, K. D. Buddharaju, S. H. G. Teo, C. Shen, Y. Jiang, C. X. Zhu, M. B. Yu, G. Q. Lo, N. Balasubramanian, D. L. Kwong, E. Gnani, and G. Baccarani, "Si-Nanowire Based Gate-Ail-Around Nonvolatile SONOS Memory

Cell", IEEE Electron device letters, vol.29, no.5, 2008.

SUMMARY OF THE INVENTION

The present invention in some embodiments thereof relates to using one or more virtual nanowires as part of a memory storage element, optionally for storing data in analog form and/or multiple data elements in a single memory cell. There is provided in accordance with an exemplary embodiment of the invention, a memory cell including at least one electrostatically induced virtual nanowire by which the memory cell stores and reads data.

Optionally, said cell is configured to generate said nanowires in any of at least 5 non-overlapping locations.

Optionally, said cell is configured to store at 3 distinguishable charge levels adjacent to said virtual nanowire.

In an embodiment of the invention, the memory cell comprises:

a nanowire defining layer configured to selectively define said at least one nanowire therein; and

a charge retention layer positioned to receive charge via a nanowire created in said nanowire defining layer; and

circuitry for creating said nanowire.

Optionally, said circuitry for creating comprises voltage sources applied to lateral gates for electrostatically creating said nanowire.

Optionally, the memory cell comprises a top gate electrode for creating an electric field between said nanowire and said charge retention layer.

Optionally, the memory cell comprises circuitry for passing charge into said charge retention layer at at least one location, via said nanowire.

Optionally, said circuitry for creating comprises circuitry for selectively creating said nanowire at one of several locations in said nanowire defining layer.

Optionally, the memory cell comprises circuitry for selectively passing charge into said charge retention layer either at one location or simultaneously at a selected number of adjacent locations.

Optionally, said circuitry for creating comprises circuitry for controlling a dimension of said nanowire.

Optionally, the memory cell comprises a source and a drain configured to be connected by said nanowire in at least one location.

Optionally, the memory cell comprises circuitry for extracting charge from said charge retention layer via said nanowire in at least one location.

Optionally, the circuitry for extracting charge comprises circuitry for selectively extracting charge via said nanowire from any one of a plurality of locations. Optionally, said circuitry for extracting charge comprises circuitry for selectively extracting charge via said nanowire at a single location, or simultaneously extracting charge from a selected number of adjacent locations.

Optionally, the memory cell comprises circuitry for sensing a current in said created nanowire.

Optionally, said circuitry for sensing a current can distinguish at least between three different levels of current in the nanowire.

In an embodiment of the invention, the memory cell also comprises:

a source and a drain that the nanowire is configured to connect;

a top gate electrode for creating an electric field between the nanowire and the charge retention layer; and

circuitry for selectively controlling an amount of charge retained in the charge retention layer at at least one location to be one of at least three different levels;

wherein each of the three different levels of current is a level of current that flows in the nanowire for a different one of the three different levels of retained charge, for at least one set of voltages applied to the source, drain, top gate electrode, and lateral gate electrodes.

There is further provided, in accordance with an exemplary embodiment of the invention, an addressable memory array comprising a plurality of memory cells according to an embodiment of the invention.

There is further provided, according to an exemplary embodiment of the invention, a memory cell including a plurality of individually addressable charge locations, each charge location accessible by a nanowire formed adjacent to that location.

There is further provided, according to an exemplary embodiment of the invention, a method of storing or erasing data, comprising:

electrostatically creating a nanowire at a nanowire location; and

changing an amount of charge stored in a charge retention location adjacent to the nanowire, by conveying a charge from the nanowire to the retention layer, or conveying an opposite charge from the retention layer to the nanowire, or both. Optionally, changing the amount of charge stored in the retention layer comprises selectively changing the amount of charge stored in the retention layer at one of a plurality of locations, by creating the nanowire at that location.

Optionally, changing the amount of charge stored in the retention layer comprises selectively changing the amount of charge stored at a single location or simultaneously changing the amount of charge stored at a selected number of adjacent locations, by controlling a width of the nanowire.

There is further provided, in accordance with an exemplary embodiment of the invention, a method of reading data, comprising:

electrostatically creating a nanowire at a nanowire location; and

measuring an effect of a stored charge on conductance of said nanowire.

Optionally, measuring an effect of a stored charge on conductance comprises distinguishing between at least three different levels of stored charge that produce three different levels of conductance in the nanowire.

Unless otherwise defined, all technical and/or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of embodiments of the invention, exemplary methods and/or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting.

Implementation of the method and/or system of embodiments of the invention can involve performing or completing selected tasks manually, automatically, or a combination thereof. Moreover, according to actual instrumentation and equipment of embodiments of the method and/or system of the invention, several selected tasks could be implemented by hardware, by software or by firmware or by a combination thereof using an operating system.

For example, hardware for performing selected tasks according to embodiments of the invention could be implemented as a chip or a circuit. As software, selected tasks according to embodiments of the invention could be implemented as a plurality of software instructions being executed by a computer using any suitable operating system. In an exemplary embodiment of the invention, one or more tasks according to exemplary embodiments of method and/or system as described herein are performed by a data processor, such as a computing platform for executing a plurality of instructions. Optionally, the data processor includes a volatile memory for storing instructions and/or data and/or a non-volatile storage, for example, a magnetic hard-disk and/or removable media, for storing instructions and/or data. Optionally, a network connection is provided as well. A display and/or a user input device such as a keyboard or mouse are optionally provided as well. BRIEF DESCRIPTION OF THE DRAWINGS

Some embodiments of the invention are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the invention. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments of the invention may be practiced.

In the drawings:

FIG. 1 shows a schematic perspective view of an EFN EEPROM, in accordance with an exemplary embodiment of the invention;

FIG. 2 shows a top schematic view of the EFN EEPROM in FIG. 1 ;

FIG. 3 shows a section of the EFN EEPROM in FIG. 1, along a plane parallel to the x-axis and showing the cross-sections of multiple stored nanowires, in accordance with exemplary embodiments of the invention;

FIG. 4 shows a section of the EFN EEPROM in FIG. 1, along a plane parallel to the y-axis and along a middle of a nanowire, in accordance with an exemplary embodiment of the invention;

FIG. 5 shows a flowchart for using an EFN EEPROM when executing a computer program, according to an exemplary embodiment of the invention;

FIG. 6 shows I-V curves of a biosensor based on EFN technology, illustrating an induced nanowire and variation as a function of the lateral gates voltage, in accordance with an exemplary embodiment of the invention; FIG. 7 is a simulation showing variation in charge density profile of an EFN as a function of lateral gate voltage, in accordance with some exemplary embodiments of the invention; and

FIG. 8 is a simulation showing variation in location of an EFN as a function of left and right lateral gate voltage, in accordance with an exemplary embodiment of the invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

The present invention, in some embodiments thereof, relates to a memory cell using one or more dynamically created nanowires to store and/or read data.

An aspect of some embodiments of the invention relates to a memory device in which an active nanowire is not hard coded into the structure but rather electro-statically engineered during operation of the device. In one embodiment, the memory flash device has the form of a field-effect transistor composed of a silicon region surrounded by top gate, bottom gate, and two lateral gates. Also, a charge retention layer is located between the active silicon and the top gate. Correct biasing of the lateral gates produces depletion zones leaving an undepleted silicon region that is available for conduction. This undepleted silicon region is electrostatically shaped into a "virtual nanowire" which may have a width as narrow as several nm, at a location selected according to the voltage on the lateral gates. Different biasing of the lateral gates may create nanowires at different locations in an active region of the silicon. Repeating a biasing at a later time will generally reform the nanowire at a same location.

In an exemplary embodiment of the invention, write, read and/or erase operations are optionally performed with respect to a single nanowire. For example, to write, first the location of the nanowire is selected via the lateral gates and then charge is injected from the nanowire into the retention layer, as is performed in conventional flash devices. The charge is stored in the retention layer (for example, between the nanowire and the top gate) and can be used to modify the conductance properties of the nanowire, for example, to modify the threshold voltage of the nanowire. Reading is optionally done by measuring this threshold. Erasing is optionally done by reversing the bias on the top and bottom gate, so the stored charge is removed through the nanowire (for example, by tunneling). In an exemplary embodiment of the invention, this allows a 'virtual' array of nanowires to be produced in a single memory cell (single device) and allows the formation of a multilevel flash memory cell. In an exemplary embodiment of the invention, an EFN (Electrostatically Formed Nanowire) memory cell can now be realized with a conventional low cost HVM CMOS processing, as no low-dimensional design rules are needed. Rather, in an exemplary embodiment of the invention, high accuracy of nanowire size and/or position and/or shape are provided by voltage control of the lateral, back, and top gates.

Potential benefits of an EFN memory cell over conventional memory devices include one or more of higher cell density, decrease in source, drain and gate contacts and/or cheap fabrication.

An aspect of some embodiments of the invention relates to providing a memory cell with a plurality of nanowire locations, each separately addressable. As noted, in some embodiments, only one nanowire exists at any given time, and is recreated as needed, however, different parts of the memory cell are accessed using nanowires at different locations. In an exemplary embodiment of the invention, the cell is coupled to a controller which controls the cell to selectively create a nanowire at a predefined position. Optionally or alternatively, the nanowire dimensions are also predefined. In an exemplary embodiment of the invention, a cell is used with between 2 and 20 different nanowire settings, for example, 5, 8, 10 or more. For example, an active region width of 20 nm (W in FIG. 2) could theoretically support 2 nanowires each 10 nm in width. An active region width of 100 nm could support 10 nanowires each 10 nm in width, or 4 nanowires each 25 nm in width.

An aspect of some embodiments of the invention relates to a multilevel storage cell supporting multiple storage locations, multiple discernible levels in each of one or more locations and/or multi-resolution reading and/or writing, optionally including analog access.

In an exemplary embodiment of the invention, different locations are accessed using different location nanowires which are created ad-hoc, as needed. Optionally or alternatively, more than two values, for example, between 3 and 10, are stored at a single location and discerned, for example, by sensitive measurement of the effect of a stored charge on nanowire conduction and/or by using different nanowire sizes, shapes and/or locations to read different values stored at a same location.

In an exemplary embodiment of the invention, analog reading is provided by varying the nanowire size, location and/or shape in a continuous manner, so as to be affected in a variable manner by stored charge.

An aspect of some embodiments of the invention relates to selecting erasing of only some of the data stored in an electrically erasable memory cell. In the art, a whole cell or an array of cells is erased together. However, in some exemplary embodiments of the invention erasure is optionally limited to data associated with currently active nanowires. Optionally, this means that data can be selectively erased, rather than only written, using low voltages (e.g., below 10 volts) and short times. Optionally or alternatively, an erase cycle may include creating nanowires in sequence at different locations, erasing the data at one location at a time, and/or creating a nanowire wide enough to cover two or more adjacent locations, or even all the locations, and erasing the data at multiple locations simultaneously.

In an exemplary embodiment of the invention, a memory cell includes a single access gate, and a plurality of stored data items, accessible, for example, using nanowire creating circuits and a sensing or charging circuit. In an exemplary embodiment of the invention, nanowires are selected using lateral gates, for example, on opposite sides of a nanowire formation area.

An aspect of some embodiments of the invention relates to creating a nanowire which is used to pass current for a different function, such as charge storage, without using very fine fabrication techniques. Rather, the wire is created ad hoc, in a suitable bed prepared for such creation and with an accuracy determined, at least in part, by the voltages applied to gates which electrostatically create the nanowire.

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. The invention is capable of other embodiments or of being practiced or carried out in various ways. Configuration of Memory Cell

Referring now to the drawings, FIG. 1 illustrates a nanowire based memory cell 100, specifically an EFN based EEPROM cell, according to an exemplary embodiment of the invention. The memory cell comprises a semiconductor layer built on top of an insulator layer 102, for example a buried oxide (BOX) layer of silicon oxide, optionally on top of a substrate 104, optionally made of the same material as the semiconductor layer, for example silicon. The semiconductor layer over the insulator layer is sometimes referred to herein as an SOI (silicon on insulator) layer, although other semiconductor materials are used instead of silicon in some embodiments of the invention, and materials other than silicon oxide are optionally used for the insulator layer. It should be understood that terms such as "on top of," "above," and "over," as used herein, refer to a direction that is shown as vertical in the drawings, but need not be literally vertical with respect to gravity; generally the device may be oriented in any direction with respect to gravity, without affecting its operation. This vertical direction is shown as the z-axis in FIG. 1.

The semiconductor layer comprises a source region 106 at one end of the SOI layer, and a drain region 108 at the other end, along the y-axis in FIG. 1, both doped with an implant of the same charge, for example an N implant. A right lateral gate region 110 and a left lateral gate region 112 are both doped with an implant of an opposite charge to the implant of the source and drain regions, for example a P implant, and are located at opposite sides of the SOI layer, along the x-axis in FIG. 1. Alternatively, the source and drain regions are doped with a P implant and the gate regions are doped with an N implant. The rest of the semiconductor layer comprises a portion 114 adjacent to the source region, a portion 116 adjacent to the drain region, and an active region 118, mostly hidden in the drawing, optionally narrower than portions 114 and 116, connecting the source region to the drain region. Portions 114 and 116, and active region 118 are optionally doped with an implant of the same sign charge as the implant of the source and drain regions, optionally the same implant, but are less strongly doped than the source and drain region. A source electrode 120 is connected to source region 106, a drain electrode 122 is connected to drain region 108, a right lateral gate electrode 124 is connected to right gate region 110, and a left lateral gate electrode 126 is connected to left gate region 112. The electrodes are optionally metal, for example, or polysilicon. Connectors 128, optionally metal, allow the electrodes to be connected to an external circuit which can control the voltage on each of the electrodes, and can measure the current between the source and drain electrodes.

Optionally, there is a back gate electrode, not shown in FIG. 1, attached to the bottom of substrate 104, or to the bottom of insulator layer 102 if there is no substrate 104 beneath the insulator layer, optionally with its own connector. The presence of insulator layer 102 between the back gate electrode and the other electrodes makes it possible for the back gate electrode to affect the electric field and hence the carrier distribution in the active region, without drawing any current. Alternatively there is no insulator layer, only a semiconductor substrate, but a bottom portion of the substrate is implanted with dopants opposite in sign to the dopants in the source and drain regions, and the back electrode has a voltage that creates a depletion zone at the junction between the bottom portion of the substrate and the source and drain regions, effectively acting like an insulator layer that prevents current from flowing between the back electrode and the source or drain electrodes.

Substrate layer 104, even if it is not needed for the operation of memory cell 100, may be present as a result of the method of manufacture, in some methods of manufacturing memory cell 100.

Active region 118 is covered with a dielectric layer 130, made for example of silicon oxide (Si0₂), topped with a charge retention layer 132, made for example of silicon nitride (S1₃N₄), which is topped with another dielectric layer 134, made for example of silicon oxide. Layers 130, 132, and 134 may be referred to herein as an ONO (oxide-nitride-oxide) layer, although other materials are optionally used for them instead of silicon oxide and silicon nitride. These layers are not drawn to scale, but for clarity are shown much thicker, relative to the other parts of memory cell 100, than they typically are. Optionally layers 130, 132 and 134 extend over the entire length of active region 118, optionally past the ends of active region 118, but in FIG. 1 they are shown slightly shorter than active region 118, so active region 118 can be seen. A top gate electrode, not shown in FIG. 1, made for example of metal or polysilicon, is attached to the top surface of dielectric layer 134, optionally covering its entire length, and optionally has a connector, optionally metal, which can be used to connect it to an external circuit for controlling its voltage. FIG. 2 shows a top view 200 of memory cell 100. FIG. 2 is not drawn at all to scale. Active region 118, whose width W is typically much narrower than its length L, and much narrower than lateral gate regions 110 and 112, is drawn with its width greater than the widths of the lateral gate regions, and comparable to its length L, in order to clearly show multiple nanowire locations arranged across its width. The gray stripes in active region 118, connecting source 106 to drain 108, represent possible preprogrammed locations 202 for an electrostatically formed nanowire 204, connecting source 106 to drain 108. For clarity, only some of the preprogrammed locations are labeled "202" in FIG. 2, but all of the gray vertical stripes represent preprogrammed locations 202. Generally only a single nanowire exists at a given time, with its location and width determined by the voltages Von and Von applied respectively to lateral gate electrodes 124 and 126 on lateral gate regions 110 and 112. Figures 7 and 8, below, give examples of how Von and Von determine the location and width of the nanowire. The black dots shown at the location of nanowire 204, and in locations 206 and 208, represent electric charge stored in charge retention layer 132, above each of those locations. Other locations 202, without black dots, represent locations without stored charge above them in retention layer 132. Each preprogrammed location 202 in active region 118 optionally functions as a bit for the memory cell, which can have a value of 1 or 0, corresponding for example to the location being charged or uncharged. In some embodiments of the invention, each location 202 can store any of more than two discrete amounts of charge, and in that case each location 202 may represent more than one bit in the memory cell.

FIG. 3 shows an axial cross-sectional view 300 of memory cell 100, in the x-z plane, with the nanowire oriented perpendicular to the plane of the drawing. Like view 200 in FIG. 2, view 300 is not drawn at all to scale, with the width of active region 118, which is typically much narrower than lateral regions 110 and 112, shown wider. Similarly, the ONO layers 130, 132 and 134, are shown much thicker than they typically are, relative to their width and the width of active region 118. A top gate electrode 302 is located on the top of layer 134, and a back gate electrode 304 is optionally located at the bottom of substrate 104. Top gate electrode 302 is used for depositing and removing charge from retention layer 132, as will be explained in detail below, and back gate electrode 304 is optionally used for adjusting the vertical position and height of the nanowire, by adjusting a voltage Vc_b applied to the back electrode. Nanowire 204, visible in cross-section, is shown as black, and the other preprogrammed nanowire locations 202 are shown as white. Nanowire 204 has charge 306 stored just above it in retention layer 132, and locations 206 and 208 also have charge 308 and 310 stored just above them in retention layer 132, while the other preprogrammed locations 202 do not have charged stored above them in retention layer 132.

FIG. 4 shows a side cross-sectional view 400 of memory cell 100, in the y-z plane. Nanowire 204 is shown connecting source 106 to drain 108. FIG. 4 is not drawn to scale, and the height of nanowire 204 is shown as much greater, relative to its length, than is typically the case. Charges 306 are shown in retention layer 132, over nanowire 204, distributed optionally along most of the length of nanowire 204.

It should be understood that the memory cell need not have the rectilinear geometry shown in FIGS. 1-4, with the active region oriented along the y-direction, the lateral gate regions surrounding it in the x-direction, and the different layers arranged in the z-direction. Instead, the memory cell may be curved or twisted in any way, for example with the active region C-shaped, or S-shaped, or with the layers having surface curvature, as long as certain features are present, for example a path through the active region connects the source and drain regions, and the lateral gate regions are adjacent to the active region on its sides. However, a rectilinear geometry potentially makes the memory cell easier to manufacture by conventional manufacturing methods for semiconductor devices. The gate electrodes, which generally do not have substantial current running through them in normal operation, need not be in physical contact with the semiconductor layer or insulator layer, but could be separated from them by an air gap, although for reasons of mechanical strength it is potentially advantageous to have any electrodes in direct contact with semiconductor or insulator.

Exemplary method of operation of the memory cell

In an exemplary embodiment of the invention, nanowire 204 is electrostatically formed inside active region 118 by appropriate biasing of the back gate (Vc_b), right lateral gate (VGU) and left lateral gate (Vca) electrodes. Vc_b, VGII ^and Vca are applied in a manner that induces depletion regions at the interfaces of the active region with the insulator layer, the right lateral region, and the left lateral region, respectively. However, not all the active region is depleted. In this manner an undepleted region can be created that functions like a virtual conducting nanowire, connecting the source and drain regions. The biasing of the lateral gates is optionally used to define the lateral size and/or the lateral location of the nanowire. The lateral size and location are optionally controlled independently if the voltages on the right and left lateral gate electrodes are controlled independently, with the location depending mostly on the difference between the right and left lateral gate voltage, and the size depending mostly on the average between the right and left lateral gate voltage. Biasing of the back gate is optionally used to define the vertical size and position of the nanowire. Programming (writing), reading and erasing is optionally performed similarly to conventional flash transistor with the charge retention layer. For example, programming is performed by either Fowler-Nordheim tunneling or via hot electrons injection. In this manner each nanowire location has a unique threshold value of the source to drain voltage that is defined in accordance with the presence or the absence of excess electrons in the retention layer, and the applied voltage at the lateral gates. As can be seen, a single cell can comprise many bits where each bit corresponds, for example, to a different nanowire location.

FIG. 5 shows a flowchart 500 showing how a memory cell is used to write, read and erase data, for example when executing a computer program. Starting at 502, an instruction is followed, at 504, either to write to a preprogrammed nanowire location in a memory cell, to read the location, or to erase the location. Specifically, as used herein, "writing" to a location means to change the corresponding bit from its value when there is no charge in the retention layer, e.g. a zero, to its value when there is charge in the retention layer, e.g. a one. "Erasing" the location means the opposite process, changing the bit from its value when there is charge in the retention layer, e.g. a one, to its value when there is no charge, e.g. a zero. In some embodiments of the invention, each preprogrammed nanowire location stores more than one bit of information, because it can have more than two different discrete amounts of charge that can be stored in the retention layer. For example, there are four different amounts of charge that can be stored at a given location, such as 0, 1, 2 or 3 times some unit of charge, and the location stores two bits, corresponding to these four different amounts of charge (for example, 00, 01, 10, or 11). In this case, "writing" will mean increasing the amount of charge in the retention layer at that location, and "erasing" will mean decreasing the amount of charge. In some embodiments of the invention, either net positive or negative charge can be stored in the retention layer, i.e. holes or electrons, and in that case, "writing" can be defined as making the charge state of the retention layer more positive, while "erasing" can be defined as making the charge state more negative, though the opposite definitions could also be used. In all these cases, "reading" a location means finding out the charge state of the retention layer at that location.

If the instruction is to write to a location, then the desired location is selected at 506, by adjusting the values of the lateral gate voltages at 508, and adjusting the value of the back gate voltage at 510. Figures 7 and 8, described below, give examples of how the location and width of a nanowire is determined by the lateral gate voltages, for a particular configuration. Optionally, the values of the lateral and back gate voltages are selected so that the nanowire is narrow, centered at the desired location, not extending to neighboring locations, and close to the ONO layer. In some embodiments of the invention, multiple adjacent locations may be written to at the same time, and in that case, the lateral and back gate voltages may be selected to make the nanowire wider, extending over all of the locations that are to be written to. If the lateral gate voltages are both set to zero, and the back gate and top gate voltages have appropriate values, then the nanowire may extend across the entire active region, and all preprogrammed nanowire locations may be written to at the same time.

At 512, a relatively high voltage, for example a typical voltage used for writing to a flash EEPROM, is applied to the top gate electrode. This voltage causes charge carriers from the nanowire to tunnel through dielectric layer 130 to retention layer 132, depositing charge there, and/or causes charge carriers of the opposite sign to tunnel from retention layer 132 to the nanowire. The potential of the nanowire optionally remains close to the potential of the source and drain, to which it is in relatively good electrical contact. The high voltage is continued for a period of time, until the charge in the retention layer reaches a desired value, corresponding for example to a desired value of the bit or bits associated with that location. The time required depends on the desired charge, and on the tunneling current, which in turn is sensitive to the tunneling distance between the nanowire and the retention layer, as well as on the carrier density in the nanowire, and on the width and height of the nanowire. At 514, when the desired charge in the retention layer is reached, at the location or multiple locations that the device is writing to, the high voltage applied to the top gate electrode is stopped.

If the instruction is to read the value of a bit or bits associated with a preprogrammed location of the nanowire, then the location is selected at 516. The lateral gate voltages are adjusted at 518, and the back gate voltage is adjusted at 520, to produce a nanowire centered at the desired location, and narrow enough not to extend to neighboring preprogrammed locations. At 522, a voltage is set between the source and drain electrodes, and at 524, a current between the source and drain electrodes is measured, and used to determine a value of the bit or bits associated with that preprogrammed location. Optionally, the source to drain voltage V_SD is set at a value so that it will be below a threshold voltage for current to flow, if there is no charge in the retention layer, but it will be above the threshold voltage if the charge in the retention layer corresponds to a different value of the bit associated with that location. Alternatively, if the charge in the retention layer is such as to decrease the source to drain current, then V_SD is optionally set at such a value that it will be above the threshold for current to flow if there is no charge in the retention layer, and it will be below the threshold for current to flow if there is enough charge in the retention layer to correspond to a different value of the bit. In general, the threshold V_SD for current to flow between the source and drain will also depend on the top gate voltage, as well as on the back gate voltage, and on the width of the nanowire which depends on the lateral gate voltages, and these can be adjusted so V_SD will have a threshold at a convenient value. For example, V_SD is more than 500 mV, or between 500 and 200 mV, or between 200 and 100 mV, or between 100 and 50 mV, or between 50 and 20 mV, or between 20 and 10 mV, or between 10 and 5 mV, or less than 5 mV. Having V_SD much lower in magnitude than the gate voltages, which are typically a few volts, has the potential advantage that the nanowire may be fairly uniform in cross-section along its length in the active region. But using too small a V_SD may result in a current that is so small that it is difficult to measure accurately, even if V_SD is above the threshold, and higher V_SD may be needed especially for nanowires that are relatively long and thin. Optionally, V_SD is kept the same for each measurement of the current, but the top gate voltage, back gate voltage, and/or lateral gate voltages are changed so that the same value of V_SD is above the threshold for some levels of charge in the retention layer, but below the threshold for other levels of charge, and the level of charge can be determined by observing for which measurements current flows between the source and drain and for which measurements it does not.

In embodiments where more than one bit is associated with each location, and the retention layer can have more than two different discrete values of charge, the amount of charge is optionally determined by measuring the source to drain current for a given V_SD and top gate voltage, and a given nanowire width, which can be controlled by the lateral gate voltages even without changing the position of the nanowire. Alternatively, the current is measured more than once, at different values of V_SD and/or the top gate voltage and/or nanowire width, each set of voltages chosen so that V_SD will be above or below the threshold for current to flow, depending on whether the amount of charge in the retention layer has a value associated with one value of the bits or another value of the bits.

If the instruction is to erase a bit or bits associated with one of the preprogrammed locations, then the location is selected at 526. At 528, the lateral gate voltages are adjusted, and at 530 the back gate voltage is optionally adjusted, to produce a nanowire, optionally centered at that location, and narrow enough not to extend to adjacent preprogrammed locations. In some embodiments of the invention, multiple adjacent locations may be erased simultaneously, and if that is being done, then the gate voltages are optionally adjusted to make the nanowire wider, extending over all the locations that are being erased. If the nanowire extends across the entire active region, then all locations may be erased at once. At 532, a relatively high reverse voltage is applied to the top gate electrode, opposite in sign to the voltage that is applied at 512 when writing, optionally of the same magnitude. This top gate voltage causes trapped charge carriers to tunnel from the retention layer to the nanowire, and/or causes charge carriers of the opposite sign to tunnel from the nanowire to the retention layer, discharging the retention layer. The nanowire optionally remains at a potential close to the potential of the source and drain, with which it is in relatively good electrical contact. Optionally, the reverse high voltage on the top gate electrode continues for a period of time until the retention layer is fully discharged, or at least has a low enough charge that it will be read as completely discharged. Alternatively, in embodiments where there are more than two different discrete levels of charge that the retention layer can have at that location, the retention layer is not discharged completely, but only down to a lower level of large. At 534, when the retention layer is discharged, or has reached a desired level of charge, the reverse voltage applied to the top electrode is stopped. In embodiments where the retention layer can store charge of either sign, the reverse voltage may continue to be applied to the top gate electrode, and charge carriers of the opposite sign may continue to tunnel from the nanowire to the retention layer, even after the retention layer is discharged, and charge of the opposite sign starts to accumulate in the retention layer, until it reaches a desired level. In these embodiments, the reverse process may also occur, when writing a bit.

Once the instruction to read, write or erase is completed, at 536, the execution of the program is either ended, at 538, or the next instruction is read at 504. It should be understood that, if flowchart 500 is regarded as a flowchart governing the behavior of one memory cell, then the next instruction may be to wait until instructions are executed at other memory cells, or other hardware of the computer, before executing the next read, write or erase instruction for this memory cell.

Exemplary system configurations

In an exemplary embodiment of the invention, the cell is associated with a control circuit. For example, such a circuit can have preset biasing voltages associated with different nanowire locations, optionally spaced apart, for repeatable access to memory locations in the charge storage area. Optionally or alternatively, such a circuit may control the read, write and/or erase processes and/or provide sensing. Optionally or alternatively, such a circuit is used to calibrate the cell, e.g., to map nanowire addresses to the range attainable by that particular cell. Optionally, low level control software governs how certain tasks are done by the hardware, for example whether data is written to multiple locations in the same memory cell simultaneously using a wider nanowire, or sequentially.

In an exemplary embodiment of the invention, a plurality of cells and optionally control circuitry are arranged to provide a memory array on a single chip, for example, an array of 2^Λ10, 2^Λ15, 2^Λ20, 2^Λ32 or intermediate or greater number of cells may be provided. In an exemplary embodiment of the invention, a separate controller is provided for such chips which may be in charge of higher level processes than individual cell read/write/erase. In an exemplary embodiment of the invention, such a controller or the above circuitry is used to simultaneously erase a particular bit location in a plurality of wired together cells, with the controller or circuitry providing a same bias voltage to the lateral gates to all the cells.

Optionally or alternatively, memory cells are integrated into a different type of integrated circuit, for example, that of a sensor (e.g., with the memory used to store a sensor value), that of a microcontroller or that of a CPU, DSP or GPU (e.g., to serve as permanent or temporary memory).

In an exemplary embodiment of the invention, the memory is configured as a ROM memory, for example, with writing and erasing disabled in the control circuitry.

An potential advantage of EFN memory over conventional EEPROM

In an exemplary embodiment of the invention, while electrostatically-formed nanowires are used to access stored memory, these do not need to be created using fine manufacturing processes, rather, a 0.5 μιη lithography process can be used to achieve nanowires of dimensions of 25 nm or better. For example, a reduction in width of a factor of 5, 7, 10, 20 or intermediate values or more may be achieved between a process width and a nanowire width. In an exemplary embodiment of the invention, a density of storage is provided which exceeds a factor of 10 between the process accuracy and the storage density. For example, an active region width of 20 nm (W in FIG. 2) could support 2 nanowire locations each 10 nm in width. An active region width of 100 nm could support 10 nanowire locations each 10 nm in width, or 4 nanowire locations each 25 nm in width. Exemplary design parameters

Optionally, the active region has a width of 1 μιη, or 400 nm, or 200 nm, or 100 nm, or 50 nm, or a greater, lesser, or intermediate width. Making the width greater has the potential advantage that more nanowire preprogrammed locations can fit within the width of the active region, allowing more bits per memory cell and potentially decreasing the cost per bit. But if the active region is too wide, the lateral gate voltage needed to produce a given width of the nanowire may be great enough to cause breakdown of the PN junction of the lateral gate regions with the active region. The nanowire width is 100 nm, or 50 nm, or 25 nm, or 10 nm, or 5 nm, or a greater, lesser or intermediate value. Making the nanowire narrower has the potential advantage of allowing more nanowire locations to fit within the width of the active region. But if the nanowire is too narrow, it may have only a few charge carriers present in it, on average, and the source to drain current for a given source to drain voltage and a given set of gate voltages may vary a lot due to shot noise, possibly resulting in errors in reading, and the tunneling current through the nanowire to the retention layer, when writing or erasing, may also vary a lot due to shot noise, possibly resulting in errors in writing and erasing. While the number of charge carriers in the nanowire can be increased by increasing the dopant concentration in the active region, this can also lower the breakdown voltage for the PN junction, possibly leading to breakdown.

Layers 130, 132 and 134 are typically several nanometers thick. For example, the ONO layer described in Chan, Young and Hu, cited above, has a lower oxide layer 6 nm thick, a nitride layer 7 nm thick, and an upper oxide layer 10 nm thick. But any of the layers could be up to 1 nm, between 1 and 2 nm, between 2 and 3 nm, between 3 and 4 nm, or more than 4 nm thinner or thicker than these values. The lower layer, in particular, can greatly impede tunneling if it is too thick, but could result in leakage of charge if it is too thin.

A typical charge density that is stored in the retention layer is 10 12 electron charges per cm , described by Young, Hu and Oldham, cited above, and a nanowire that is 10 nm wide and 1 μιη long will have only about 100 electron charges stored above it. Alternatively, the stored charge density is less than 10 ⁰ cm^"2, or between 10¹⁰ and 10¹¹, or between 10¹¹ and 10¹², or between 10¹² and 10¹³, or between 10¹³ and 10¹⁴, or more than 10¹⁴. Using a lower charge density may allow faster reading writing, and erasing, but may lead to more noise and errors in these operations. Using a higher charge density may reduce noise, but may also reduce the lifetime of the stored charge, and may increase the time needed to write or erase, or increase the voltage needed.

Optionally, the effective length of the nanowire, and the length of the retention layer, is less than 1 μιη, or between 1 and 3 μιη, or between 3 and 10 μιη, or between 10 and 30 μιη, or between 30 and 100 μιη, or more than 100 μιη. A shorter length may make the memory cell smaller and allow more memory cells to fit into a given space, but may also increase the relative shot noise in the number of stored charges. A longer length, for the same nanowire width, may result in a longer time required for charging and/or discharging the retention layer, or a higher voltage needed for the same charging time.

The charging time and discharging time for the retention layer may be very sensitive to the thickness of the lower dielectric layer 130, which may affect the tunneling distance. The charging and discharging time also depend on the width and length of the nanowire, and on the density of carriers in the nanowire, as well as on the voltage between the top gate electrode and the source and drain electrodes during charging and discharging. An approximate idea of some typical charging and discharging times, and voltages, may be obtained from the literature on conventional nanowire EEPROM devices, for example Fu et al cited above, or EEPROM devices that do not use nanowires, for example Chan, Young, and Hu, cited above. As indicated by FIG. 6, described below, a change in top gate threshold voltage of about 2 volts is enough to make a large and easily measurable change in the source to drain current, so optionally, the retention layer is charged up enough to change the top gate threshold voltage by 2 volts. Alternatively, the retention layer is charged up enough to change the top gate threshold voltage by an amount less than 1 volt, or between 1 and 2 volts, or between 2 and 3 volts, and between 3 and 5 volts, or between 5 and 10 volts, or more than 10 volts. Making a larger change in threshold voltage may result in more accurate reading of the nanowire location, but it may require a very much longer charging or discharging time, resulting in much slower writing and/or erasing of the memory cell. The voltage applied to the top gate electrode to charge or discharge the retention layer is optionally substantially more than the change in the top gate threshold voltage, so that the stored charge can be read without changing it significantly. For example, it is more than 11 volts, or between 9 and 11 volts, or between 7 and 9 volts, or between 5 and 7 volts, or less than 5 volts. At a given top gate voltage, for example 11 volts, the charging time can vary by several orders of magnitude, depending on the tunneling gap, as well as on the desired change in threshold voltage. The charging or discharging time is, for example, less than 1 μ8, or between 1 and 10 μ8, or between 10 and 100 μ8, or between 100 μ8 and 1 ms, or between 1 and 10 ms, or more than 10 ms. Often the charging and discharging times are very different, because the tunneling characteristics of electrons and holes may be very different, because they may have very different effective masses. For a given geometry, the relation between top gate voltage, charging time, and change in threshold voltage, for evaluating writing and erasing, and the relation between the change in threshold voltage and the change in current for a given set of gate voltages, for evaluating reading, can be calculated numerically, for example using finite element software, and can also be found experimentally. Such studies can point to optimum tradeoffs in the design of the memory cell, and in its operating parameters.

Preliminary data

An exemplary EEPROM EFN device was emulated using an EFN sensor realized for biosensing. The following describes the silicon fabrication. Silicon-On- Insulator (SOI) wafers measuring 6" in diameter were used. The thickness of the SOI layer was 260 nm with boron doping of ~ 1.6x10¹⁴ cm^"3 (resistivity of 13-22 Ωαη). The thickness of the buried oxide (BOX) was 1μ. The fabrication of the device was as follows: MESA-type isolation was used between the devices. A sacrificial layer of Si0₂ was grown at least over the active region, and the active region was implanted with arsenic at a concentration of 1.6 x 10 cm^" . In order to allow the formation of an undepleted nanowire in the active region, the doping concentration in the active region was great enough so that the depletion distance in the active region was less than the 260 nm thickness of the SOI layer, i.e. the active region was only partially depleted. The sacrificial layer was then removed. A Si0₂ gate dielectric of 50 A in thickness was grown with low pressure chemical vapor deposition (LPCVD), followed by deposition of a S1₃N₄ stop etch layer. Subsequent arsenic implants for the source and drain regions took place followed by a boron implant for the lateral regions. The arsenic doping of the source and drain regions were in the range of 5x10 cm^" and the boron doping of the lateral regions was in the range of 5x10 cm^" . The source, drain, and active region implants ensure an n-type accumulation device. To provide contact between the electrodes and gate regions, the implant steps were followed by using plasma enhanced chemical vapor deposition (PECVD) to deposit a 100 nm thick Si0₂ layer as an inter layer dielectric (ILD) between the electrodes and the silicon. Ti/Al/TiN was sputtered and patterned for interconnection of the electrodes, and the top of the device was sealed by a 4,500 A thick passivation layer of PECVD nitride, to keep the silicon away from the conducting liquid sample that the device would be exposed to when it was used as a biosensor. An opening was made in the passivation layer above the active region, exposing the gate dielectric. This was performed with a dry etch followed by a final wet etch. Due to the EFN geometry, two nanowire lengths need to be defined. Full nanowire length (L) is defined as the lithographic length between the source and drain, and the effective length L_eg) is defined as the length of the junction gate. All devices had full nanowire length of 10 μιη and effective length of 7 μιη. The active region width (W) for all devices was 400 nm.

As noted, the above was used to create a biosensor. However, when immersed in a suitable conducting liquid, that liquid, in contact with the gate dielectric covering the active region, served as a top gate electrode, with its potential VREF controlled by a reference electrode also in contact with the conducting liquid. Preliminary results are presented in plot 600 in FIG. 6. Plot 600 shows a series of curves 604 for the source to drain current IDS in micro-amps, plotted on vertical axis 606 on the right side of the plot, for different values of the effective top gate voltage VREF in volts, plotted on horizontal axis 602. For all the curves, the source to drain voltage is kept fixed at 50 mV, and each curve has a different value of the lateral gate voltage Vc_j, the same voltage on both the left and right lateral gate electrodes, with values shown in the key at the upper left part of plot 600. Making the lateral gate electrode more negative reduces the width of the nanowire, as shown below in FIG. 7, reducing the current for a given effective top gate voltage, and increasing the threshold VREF needed to produce significant current. Plot 600 also shows curves for the gain g_m = CIIDS CIVREF, in μ8, plotted on left vertical axis 610, as a function of VREF- Like the current, the gain is smaller for a given VREF when the lateral gate voltage is more negative and the nanowire is narrower, and peak gain is shifted to greater VREF when the nanowire is narrower. When the retention layer above a nanowire location is charged up, the threshold top gate voltage needed to obtain significant source to drain current, for a fixed source to drain voltage of 50 mV for example, changes, and this change in threshold voltage can be used to read the presence or absence of stored charge in the retention layer, by measuring the current for a given top gate voltage. From FIG. 6, it can be seen that a change in top gate threshold voltage of about 2 volts produces a significant change in current for this design, so a change in stored charge corresponding to a 2 volt change in top gate threshold voltage should be easy to read, and this might be a good choice for the level of charge stored in the retention layer.

FIG. 7 shows a plot 700 of the carrier density profile of an EFN in the x- direction for different values of lateral gate voltage Vc_j, based on a simulation, for an EFN device with the same parameters as the EFN biosensor used for FIG. 6. The normalized carrier density is plotted on vertical axis 704, and the x-coordinate in nanometers is plotted on horizontal axis 702. In all cases the left and right lateral gate voltages are equal to each other, so the nanowire is centered at x = 0. Curve 706 is for a lateral gate voltage of 0 volts, curve 708 is for -0.5 volts, curve 710 is for -1.0 volts, curve 712 is for - 1.5 volts, and curve 714 is for -2.0 volts. Making the lateral gate voltage more negative makes the nanowire narrower, and with lateral gate voltage of - 2.0 volts the width of the nanowire is only about 25 nm, even though the narrowest feature produced lithographically is the active region, which is 400 nm wide. Even narrower nanowire widths are possible if the doping concentration in the active region is increased. If the nanowire is made much narrower without increasing the dopant density and hence the carrier density, then on average it will have less than one charge carrier (electron or hole) present in it at a given time, so its conductivity may be dominated by shot noise.

FIG. 8 shows a plot 600, illustrating the results of a simulation of creating a nanowire centered at different locations across the active region by varying the voltage VGII on the right lateral gate electrode, and the voltage VGU on the left lateral gate electrode. In this simulation, the parameters were the same as for the FIG. 7. Curve 602 shows the normalized carrier (electron) density as function of lateral position x in the active region, when VGU = 0 volts and VGU = -5.16 volts. Curve 604 shows the carrier density when VGU = -0.85 volts and VGU = -3.43 volts. Curve 606 shows the carrier density when Vca = -2.0 volts and VGU = -2.0 volts. Curve 608 shows the carrier density when Vca = -3.43 volts and VGU = -0.85 volts. Curve 610 shows the carrier density when VGU = -5.16 volts and VGU = 0 volts. By varying the left and right lateral gate voltages in this way, the position of the conducting channel moves from left to right, over a distance of 200 nm, while the width of the conducting channel remains constant at 100 nm. The active region extends from x = -200 nm to +200 nm. It is expected that during the life of a patent maturing from this application many relevant gate designs and storage technologies will be developed and the scope of the terms gates, bias, nanowires and charge storage are intended to include all such new technologies a priori.

As used herein the term "about" refers to ± 10 %.

The terms "comprises", "comprising", "includes", "including", "having" and their conjugates mean "including but not limited to".

The term "consisting of" means "including and limited to".

The term "consisting essentially of" means that the composition, method or structure may include additional ingredients, steps and/or parts, but only if the additional ingredients, steps and/or parts do not materially alter the basic and novel characteristics of the claimed composition, method or structure.

As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

Throughout this application, various embodiments of this invention may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases "ranging/ranges between" a first indicate number and a second indicate number and "ranging/ranges from" a first indicate number "to" a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween. It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment of the invention. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

Although the invention has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.

All publications, patents and patent applications mentioned in this specification are herein incorporated in their entirety by reference into the specification, to the same extent as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present invention. To the extent that section headings are used, they should not be construed as necessarily limiting.

Claims

WHAT IS CLAIMED IS:

1. A memory cell including at least one electrostatically induced virtual nanowire by which the memory cell stores and reads data.

2. A memory cell according to claim 1, wherein said cell is configured to generate said nanowires in any of at least 5 non-overlapping locations.

3. A memory cell according to claim 1 or claim 2, wherein said cell is configured to store at 3 distinguishable charge levels adjacent to said virtual nanowire.

4. A memory cell according to claim 1, comprising:

circuitry for creating said nanowire.

5. A memory cell according to claim 4, wherein said circuitry for creating comprises voltage sources applied to lateral gates for electrostatically creating said nanowire.

6. A memory cell according to claim 5, comprising a top gate electrode for creating an electric field between said nanowire and said charge retention layer.

7. A memory cell according to claim 6, comprising circuitry for passing charge into said charge retention layer at at least one location, via said nanowire.

8. A memory cell according to claim 5, wherein said circuitry for creating comprises circuitry for selectively creating said nanowire at one of several locations in said nanowire defining layer.

9. A memory cell according to claim 5, comprising circuitry for selectively passing charge into said charge retention layer either at one location or simultaneously at a selected number of adjacent locations.

10. A memory cell according to claim 5, wherein said circuitry for creating comprises circuitry for controlling a dimension of said nanowire.

11. A memory cell according to claim 5, comprising a source and a drain configured to be connected by said nanowire in at least one location.

12. A memory cell according to claim 5, comprising circuitry for extracting charge from said charge retention layer via said nanowire in at least one location.

13. A memory cell according to claim 12, wherein the circuitry for extracting charge comprises circuitry for selectively extracting charge via said nanowire from any one of a plurality of locations.

14. A memory cell according to claim 12, wherein said circuitry for extracting charge comprises circuitry for selectively extracting charge via said nanowire at a single location, or simultaneously extracting charge from a selected number of adjacent locations.

15. A memory cell according to claim 5, comprising circuitry for sensing a current in said created nanowire.

16. A memory cell according to claim 15, wherein said circuitry for sensing a current can distinguish at least between three different levels of current in the nanowire.

17. A memory cell according to claim 16, also comprising:

a source and a drain that the nanowire is configured to connect;

a top gate electrode for creating an electric field between the nanowire and the charge retention layer; and circuitry for selectively controlling an amount of charge retained in the charge retention layer at at least one location to be one of at least three different levels;

18. An addressable memory array comprising a plurality of memory cells according to any of the previous claims.

19. A memory cell including a plurality of individually addressable charge locations, each charge location accessible by a nanowire formed adjacent to that location.

20. A method of storing or erasing data, comprising:

electrostatically creating a nanowire at a nanowire location; and

changing an amount of charge stored in a charge retention location adjacent to the nanowire, by conveying a charge from the nanowire to the retention layer, or conveying an opposite charge from the retention layer to the nanowire, or both.

21. A method according to claim 20, wherein changing the amount of charge stored in the retention layer comprises selectively changing the amount of charge stored in the retention layer at one of a plurality of locations, by creating the nanowire at that location.

22. A method according to claim 20, wherein changing the amount of charge stored in the retention layer comprises selectively changing the amount of charge stored at a single location or simultaneously changing the amount of charge stored at a selected number of adjacent locations, by controlling a width of the nanowire.

23. A method of reading data, comprising:

electrostatically creating a nanowire at a nanowire location; and

measuring an effect of a stored charge on conductance of said nanowire.

24. A method according to claim 23, wherein measuring an effect of a stored charge on conductance comprises distinguishing between at least three different levels of stored charge that produce three different levels of conductance in the nanowire.