WO2013155830A1

WO2013155830A1 - Method for manufacturing array substrate, array substrate, and display device

Info

Publication number: WO2013155830A1
Application number: PCT/CN2012/083889
Authority: WO
Inventors: 金玟秀; 邓立赟; 周纪登
Original assignee: 京东方科技集团股份有限公司; 合肥京东方光电科技有限公司
Priority date: 2012-04-20
Filing date: 2012-10-31
Publication date: 2013-10-24
Also published as: CN102645808A

Abstract

A method for manufacturing an array substrate, the array substrate, and a display device. A display area of the array substrate comprises gate line, a data line (8) and multiple pixel units defined by the gate line and by the data line (8). Each pixel unit comprises a thin-film transistor (TFT), a pixel electrode (12), and a common electrode (16). The pixel electrode (12) is electrically connected to a drain electrode (7) of the TFT. A protective film (13) is arranged between the layer where the common electrode (16) is at and the layer where the pixel electrode (12) is at. An inorganic insulating film (21) and an organic insulating film (10) are provided between the pixel electrode (12) and the data line (8) and between the TFT and the protective film (13), thus reducing signal delays on the data line (8), and preventing the generation of drain current in the TFT at high temperatures.

Description

Array substrate manufacturing method, array substrate and display device

Embodiments of the present invention relate to a method of fabricating an array substrate, an array substrate, and a display device. Background technique

Thin film transistor liquid crystal displays (TFT-LCDs) have a small size, low power consumption, and no radiation, and they dominate the current flat panel display market. The advanced super-dimensional field switching technology (ADS) uses a field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer to form a multi-dimensional electric field, so that the liquid crystal cell is narrow. All the aligned liquid crystal molecules between the electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency. Advanced super-dimensional field switching technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.

ADS mode TFT-LCD uses the fringe field effect between the common electrode and the pixel electrode to drive the liquid crystal. According to its electrode design and interlayer structure, the liquid crystal transmittance and other characteristics have a great change. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing an array substrate of a prior art ADS mode liquid crystal display. As shown in FIG. 1, in the array substrate, a gate electrode 2 is formed on a substrate 1, a gate insulating layer 4 is formed on the gate electrode 2, and a semiconductor layer 5, a source electrode 6 and a drain electrode are formed on the gate insulating layer 4. 7 are formed on the semiconductor layer 5 and spaced apart from each other, the pixel electrode 12 is formed on the gate insulating layer 4 and electrically connected to the drain electrode 7, and the common electrode 16 is formed on the protective film 13, a gate line (not shown) and a data line 8 defines a pixel region, a gate pad 3 is formed on the substrate 1, and a data pad 9 is formed on the gate insulating layer 4. In order to prevent light leakage, a portion of the common electrode 162 is formed over the data line 8.

In the above array substrate, there is a parasitic capacitance between the common electrode 162 and the data line 8

(Cdp_data to Vcom), there is also a parasitic capacitance (Cdp_data to pixel) between the pixel electrode 12 and the data line 8. Structurally, when the distance between the pixel electrode 12 and the data line 8 is small, the parasitic capacitance is relatively large, which affects the charging characteristics of the pixel electrode 12, which in turn affects the quality of the display, resulting in stains on the screen. , afterimage or flickering. For this reason, it is necessary to increase the distance between the pixel electrode 12 and the data line 8 to reduce the parasitic capacitance, but this causes the aperture ratio of the pixel to decrease. In addition, when the parasitic capacitance between the common electrode 162 and the data line 8 is large, the signal on the data line 8 is delayed. The higher the resolution of the liquid crystal display and the larger the area, the more severe the signal delay. In the existing method of improving the signal delay, the parasitic capacitance is mainly reduced by increasing the thickness of the protective film 13 between the data line 8 and the common electrode 162, but this causes a drastic increase in manufacturing time and manufacturing cost. Summary of the invention

Embodiments of the present invention provide a method of fabricating an array substrate, an array substrate, and a display device to reduce signal delay on a data line in an array substrate and prevent generation of leakage current in the TFT at a high temperature.

Embodiments of the present invention provide an array substrate including a display area and a non-display area, the display area including a gate line, a data line, and a plurality of pixel units defined by the gate line and the data line, wherein each The pixel unit includes a thin film transistor, a pixel electrode, and a common electrode, the pixel electrode being electrically connected to a drain electrode of the thin film transistor, wherein an inorganic insulating film is formed on the data line and a source electrode and a drain electrode of the thin film transistor On the semiconductor layer of the channel region, an organic insulating film is formed on the inorganic insulating film, a protective film is formed on the pixel electrode and the organic insulating film, and the common electrode is formed on the protective film such that The protective film is disposed between a layer where the common electrode is located and a layer where the pixel electrode is located, and the inorganic insulating film and the organic insulating film are disposed between the pixel electrode and the data line and The thin film transistor is between the protective film.

Embodiments of the present invention provide a method for fabricating an array substrate, including:

Forming a gate electrode and a gate line on the substrate;

Forming a gate insulating layer on the substrate on which the gate electrode and the gate line are formed;

Forming a semiconductor layer, a source electrode, a drain electrode, and a data line on the substrate on which the gate insulating layer is formed;

Forming an inorganic insulating film on the substrate on which the semiconductor layer, the source electrode, the drain electrode, and the data line are formed;

Forming an organic insulating film on the substrate on which the inorganic insulating film is formed, and patterning the organic insulating film and the inorganic insulating film;

Forming a pixel electrode on the substrate on which the organic insulating film is formed, the pixel electrode being electrically connected to the drain electrode; A protective film is formed on the substrate on which the pixel electrode is formed, and the protective film is patterned; a common electrode is formed on the substrate on which the protective film is formed.

Embodiments of the present invention provide a display device including the above array substrate.

The embodiment of the present invention reduces the parasitic capacitance between the common electrode and the data line by applying a low dielectric constant organic insulating film to the array substrate, thereby reducing signal delay on the data line and improving display quality. The technical solution of the present invention can also reduce the process time and reduce the manufacturing cost as compared with the prior art by reducing the thickness of the protective film to reduce the parasitic capacitance.

In addition, the embodiment of the present invention further forms an inorganic insulating film as a buffer layer between the organic insulating film and the semiconductor layer, and the buffer layer can prevent ionic foreign matter in the organic insulating film from penetrating into the semiconductor layer, thereby preventing TFT at a high temperature. The generation of medium leakage current. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1 is a cross-sectional view of an array substrate of a prior art ADS mode liquid crystal display; FIG. 2 to FIG. 15 are cross-sectional views of an array substrate in a method of fabricating an array substrate according to an embodiment of the present invention;

Figure 16 is a cross-sectional view of an array substrate in accordance with an embodiment of the present invention. detailed description

The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

Unless otherwise defined, technical terms or scientific terms used herein shall be of ordinary meaning as understood by those of ordinary skill in the art to which the invention pertains. The words "first", "second" and similar terms used in the specification and claims of the invention are not intended to indicate any order, quantity or importance, but are merely used to distinguish different components. Similarly, "one" or "one" The like words do not denote a quantitative limitation, but rather indicate that there is at least one. "Connected" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "Bottom", "Left", "Right", etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship is also changed accordingly.

Embodiments of the present invention provide an array substrate including a display area including a gate line, a data line, and a plurality of pixel units between the gate line and the data line, wherein the non-display area includes a gate a pad and a data pad, wherein the pixel unit includes a thin film transistor (TFT), a pixel electrode, and a common electrode, wherein the pixel electrode is connected to a drain electrode of the thin film transistor, wherein the common electrode includes a pixel a first common electrode above the electrode and a second common electrode above the data line; a protective film is disposed between the layer where the common electrode is located and the layer where the pixel electrode is located; the pixel electrode and the data line And an inorganic insulating film and an organic insulating film interposed between the thin film transistor and the protective film, the inorganic insulating film being formed on a source electrode, a drain electrode, and a channel region of the data line and the thin film transistor On the semiconductor layer, the organic insulating film is on the inorganic insulating film.

The technical solution of the present invention reduces the parasitic capacitance between the common electrode and the data line by applying a low dielectric constant organic insulating film to the array substrate, thereby reducing signal delay on the data line and improving display quality. Compared with the prior art, by increasing the thickness of the protective film to reduce the parasitic capacitance, the technical solution of the present invention can also reduce the process time and reduce the manufacturing cost.

In addition, the technical solution of the present invention further forms an inorganic insulating film as a buffer layer between the organic insulating film and the semiconductor layer, and the buffer layer can prevent ionic foreign matter in the organic insulating film from penetrating into the semiconductor layer, thereby preventing high temperature The generation of leakage current in the TFT.

In the embodiment of the present invention, in addition to the above structure, the substrate structure of the array substrate may be set according to actual conditions, for example, the thin film transistor may be a top gate structure or a bottom gate structure; a connection manner of the pixel electrode and the drain electrode It may be a lap joint, a through-hole connection, or the like, which is not limited herein. The following describes an exemplary embodiment of the present invention by taking an array substrate as an example.

Figure 16 is a cross-sectional view of an array substrate in accordance with an embodiment of the present invention. Referring to FIG. 16, the array substrate may include: a substrate 1; a gate electrode 2, a gate line (not shown), and a gate pad 3 formed on the substrate 1; a gate insulating layer 4 formed on the gate electrode 2 and the gate line Upper; semiconductor layer 5, data line 8 and data Pads 9 are formed on the gate insulating layer 4; source electrodes 6 and drain electrodes 7 are formed on the semiconductor layer 5; and an inorganic insulating film 21 is formed on the source electrode 6, the drain electrode 7, the data line 8, and the semiconductor layer 5. The organic insulating film 10 is formed on the inorganic insulating film 21, and the first contact hole 11 is formed in the inorganic insulating film 21 and the organic insulating film 10; the pixel electrode 12 is formed on the organic insulating film 10, and the pixel electrode 12 passes through the first The contact hole 11 is electrically connected to the drain electrode 7; the protective film 13 is formed on the pixel electrode 12 and the organic insulating film 10; the common electrode 16 is formed on the protective film 13, and the common electrode 16 includes the first common electrode located above the pixel electrode 12. An electrode 161 and a second common electrode 162 located above the data line 8; a gate pad electrode 17 formed on the protective film 13 at a position corresponding to the gate pad 3, the gate pad electrode 17 passing through the second contact hole 14 is electrically connected to the gate pad 3, the second contact hole 14 passes through the protective film 13, the organic insulating film 10, and the inorganic insulating film 21; the data pad electrode 18 is formed on the protective film 13 and corresponds to the data pad 9 Position of the data pad electrode 18 through the third contact 9 and 15 is electrically connected to the data pad, the third contact hole 15 through the protective film 13, the organic insulating film 10 and the inorganic insulating film 21.

According to the embodiment of the present invention, the data line 8 can be reduced by applying the low dielectric constant (2.0 to 4.0) of the organic insulating film 10 to the array substrate to reduce the parasitic capacitance between the common electrode 162 and the data line 8. Signal delay on the board to improve display quality. The embodiment of the present invention can also reduce the process time and reduce the manufacturing cost as compared with the prior art by reducing the thickness of the protective film 13 to reduce the parasitic capacitance.

According to the embodiment of the present invention, since the organic insulating film 10 having a low dielectric constant is used, it is also possible to reduce the horizontal direction (i.e., the direction parallel to the substrate 1) between the pixel electrode 12 and the data line 8 The distance is increased to increase the aperture ratio of the pixel, wherein the distance between the pixel electrode 12 and the data line 8 in the direction parallel to the substrate 1 can be reduced to 0 to 1 μm.

In addition, if the organic insulating film 10 is in contact with the semiconductor layer 5, ionic foreign matter in the organic insulating film 10 penetrates into the semiconductor layer 5 in a high temperature environment, resulting in an increase in leakage current in the TFT. According to an embodiment of the present invention, an inorganic insulating film 21 is formed as a buffer layer between the organic insulating film 10 and the semiconductor layer 5, and the buffer layer can prevent ionic foreign matter in the organic insulating film 10 from penetrating into the semiconductor layer 5, thereby preventing The generation of leakage current in the TFT at high temperatures.

In one embodiment, the material of the organic insulating film 10 may be made of polyacrylic acid, and the thickness of the organic insulating film 10 may be 10,000 to 40,000 Å. The protective film 13 can be made of an inorganic insulating material and has a thickness of 2000 to 4000 Å. The inorganic insulating film 21 may be an oxide (for example, SiOx) or a nitride (for example) For materials such as SiNx), the thickness is 1000~2000A.

In the embodiment of the present invention, the semiconductor layer may be left under the data line (as shown in FIG. 13), or the semiconductor layer may not be retained (as shown in FIG. 14); the source electrode and/or the drain electrode may be completely located above the semiconductor layer ( As shown in Figure 13, it can also extend to areas outside the semiconductor layer (as shown in Figure 14). When the source electrode and/or the drain electrode extend to a region other than the semiconductor layer, it is possible to have a better contact effect.

In the embodiment of the present invention, the semiconductor layer 5 may be a common silicon semiconductor (intrinsic semiconductor or doped semiconductor), an organic semiconductor, or an oxide semiconductor.

In the embodiment of the present invention, the common electrode 16 may be in the shape of a slit, and the pixel electrode 12 may be in the form of a plate or a slit.

The embodiment of the invention further provides a display device, which may include any of the above array substrates. The display device can be any product or component having a display function, such as a liquid crystal panel, an electronic paper, a cell phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

The method of manufacturing the above array substrate is given below.

Method embodiment 1

Step S11, providing a substrate, forming a gate line, a gate electrode and a gate pad on the substrate; specifically, first, sputtering, thermal evaporation or other film forming method may be used on the glass substrate or other type of transparent substrate Forming a gate metal layer, the gate metal layer may be made of chromium (Cr), molybdenum (Mo), aluminum (A1), copper (Cu), tungsten (W), niobium (Nd) or alloys thereof, and the gate metal layer may One or more layers; then, forming a photoresist on the gate metal layer; then, exposing and developing the photoresist with a patterned mask to form a photoresist mask; A photoresist mask etches the gate metal layer to form a pattern of gate lines, gate electrodes, and gate pads; finally, the remaining photoresist is stripped. It should be noted that, in this step, the common electrode lines may be formed while forming the patterns of the gate lines, the gate electrodes, and the gate pads.

Step S12, forming a gate insulating layer on the substrate completing step S11;

Specifically, as shown in Fig. 2, a gate insulating layer 4 having a thickness of 2000 8000 A may be deposited on the substrate 1 on which step S11 is completed by plasma enhanced chemical vapor deposition (PECVD) or the like. The gate insulating layer 4 may be selected from an oxide (e.g., SiOx) or a nitride (e.g., SiNx).

Step S13, forming a semiconductor layer on the substrate on which step S12 is completed; Specifically, as shown in FIG. 3, first, a semiconductor material layer having a thickness of 1000 4000 A may be formed on the substrate 1 on which step S12 is completed by a method such as PECVD; then, a photoresist is formed on the semiconductor material layer; Etching and developing the photoresist with a patterned mask to form a photoresist mask; next, etching the semiconductor material layer with a photoresist mask to form a pattern of the semiconductor layer 5; , peel off the remaining photoresist.

Step S14, forming a source electrode, a drain electrode, a data line and a data pad on the substrate completing step S13;

Specifically, as shown in FIG. 4, first, a source/drain metal layer having a thickness of 1000 to 6000 A may be formed on the substrate 1 on which the step S13 is completed by using sputtering, thermal evaporation or other film forming methods, and the source/drain metal layer may be used. Using chromium (Cr), molybdenum (Mo), aluminum (A1), copper (Cu), tungsten (W), niobium (Nd) or alloys thereof, and the source and drain metal layers may be one or more layers; Forming a photoresist on the source/drain metal layer; then, exposing and developing the photoresist with a patterned mask to form a photoresist mask; next, using a photoresist mask to the source The drain metal layer is etched to form a pattern of the source electrode 6, the drain electrode 7, the data line 8 and the data pad 9; finally, a portion of the semiconductor layer 5 between the source electrode 6 and the drain electrode 7 is etched away, and The remaining photoresist is stripped to complete the channel of the thin film transistor. When the semiconductor layer 5 is a silicon semiconductor structure composed of an intrinsic semiconductor and a doped semiconductor (ohmic contact layer), "etching away a portion of the semiconductor layer 5 between the source electrode 6 and the drain electrode 7" mainly means etching The ohmic contact layer between the source electrode 6 and the drain electrode 7 is dropped; and when the semiconductor layer 5 is an organic semiconductor or an oxide semiconductor, "etching away a portion of the semiconductor layer 5" is mainly due to etching of the source and drain metal layer Due to the etching, it is not necessary to etch away a part of the semiconductor layer 5, and it is only necessary to ensure that the source and drain metal layers of the channel region are completely etched away.

Step S15, forming an inorganic insulating film on the substrate on which step S14 is completed;

Specifically, as shown in Fig. 5, an inorganic insulating film 21 having a thickness of 1000 2000 A may be deposited on the substrate 1 on which step S14 is completed by a method such as PECVD. The inorganic insulating film 21 may be selected from an oxide (e.g., SiOx) or a nitride (e.g., SiNx).

Step S16, forming an organic insulating film on the substrate on which step S15 is completed, and patterning the organic insulating film;

Specifically, as shown in FIG. 6, first, an organic insulating film 10 having a thickness of 10000-40000 A is formed on the substrate 1 on which the step S15 is completed, and the organic insulating film 10 can be made of an organic photosensitive material such as polyacrylic acid; An organic insulating film is exposed and developed by a patterned mask. The inorganic insulating film 21 at a position corresponding to the drain electrode 7, the data pad 9, and the gate pad 3 is exposed; finally, the organic insulating film 10 is subjected to a curing process.

In this step, if the thickness of the organic insulating film 10 is too small, the effect of reducing the parasitic capacitance between the subsequent common electrode and the data line (relative to the inorganic insulating film) is not significant; if the thickness of the organic insulating film 10 is too high , the slope of the step between the layers will increase, which may cause defects such as disconnection of the pixel electrode.

In this step, the curing temperature may be 230 to 260 ° C and the time may be 30 to 60 minutes. If the curing temperature is lower than 230 ° C, the micro-cure of the protective film may cause contamination and film lift, etc.; if the curing temperature is higher than 260 ° C, the organic insulating film 10 may be denatured, thereby This makes the transmission rate low.

Step S17, etching away the exposed inorganic insulating film;

Specifically, as shown in FIG. 7, the exposed inorganic insulating film 21 is etched using the organic insulating film 10 as a mask to form a first contact hole 11 and expose the gate insulating layer 4 and data at the gate pad 3. Pad 9.

Step S18, forming a pixel electrode on the substrate of step S17, wherein the pixel electrode is electrically connected to the drain electrode through the first contact hole;

Specifically, as shown in FIG. 8, first, a transparent conductive layer having a thickness of 100 lOOOA may be formed on the substrate 1 on which the step S17 is completed by using magnetron sputtering, thermal evaporation or other film forming methods, and the transparent conductive layer may be釆 using indium tin oxide (ITO), indium oxide (IZO) or alumina, etc.; then, forming a photoresist on the transparent conductive layer; then, using a patterned mask to expose the photoresist And developing, forming a photoresist mask; next, etching the transparent conductive layer with a photoresist mask to form a pattern of the pixel electrode 12, the pixel electrode 12 passing through the first contact hole 11 and leakage The pole 7 is electrically connected; thereafter, the exposed gate insulating layer 4 is etched away with a photoresist mask to expose the gate pad 3; finally, the remaining photoresist is stripped.

In this step, if the thickness of the pixel electrode 12 is too small, the resistance thereof is too high; if the thickness of the pixel electrode 12 is too large, the transmittance is lowered.

The left half of Fig. 9 is a cross-sectional view of the array substrate after completion of the pixel electrode according to the prior art, and the right half is a cross-sectional view of the array substrate after completion of the pixel electrode according to an embodiment of the present invention. As shown in FIG. 9, in the prior art, in order to avoid the influence of the parasitic capacitance between the pixel electrode 12 and the data line 8 on the charging characteristics of the pixel electrode 12, between the pixel electrode 12 and the data line 8 The distance dl needs to be made larger, generally about 2 μm, which results in a decrease in the aperture ratio of the pixel. In the embodiment of the present invention, since the organic insulating mold 10 is used, even between the pixel electrode 12 and the data line 8 The distance d2 in the horizontal direction is made smaller, and the parasitic capacitance between the pixel electrode and the data line is not too large. Therefore, the distance d2 can be reduced to 0 to 1 μm to increase the aperture ratio of the pixel.

Step S19, forming a protective film on the substrate on which step S18 is completed, and patterning the protective film; specifically, as shown in FIG. 10, first, a thickness of the substrate 1 on which the step S18 is completed may be formed by a method such as PECVD. 2000 4000 Α protective film 13, the protective mold 13 can be made of SiNx or SiOx; then, a photoresist is formed on the protective film 13; then, the photoresist is exposed and developed by using a patterned mask Forming a photoresist mask; next, etching the protective film 13 with a photoresist mask to form a second contact hole 14 and a third contact hole 15 to expose the gate pad 3 and the data pad, respectively 9; Finally, strip the remaining photoresist.

In this step, if the thickness of the protective film 13 is less than 2000 A, the storage capacitor (Cst) rises, causing an increase in signal delay; if the thickness of the protective film 13 is larger than 4000 A, the process time and manufacturing cost are too high.

Step S20, forming a common electrode, a gate pad electrode, and a data pad electrode on the substrate on which step S19 is completed.

Specifically, as shown in FIG. 16, first, a transparent conductive layer having a thickness of 100 to 1000 A may be formed on the substrate 1 on which the step S19 is completed by using magnetron sputtering, thermal evaporation, or other film forming methods, and the transparent conductive layer may be Using a material such as indium tin oxide (ITO), indium oxide (IZO) or alumina; then, forming a photoresist on the transparent conductive layer; and then, exposing the photoresist with a patterned mask And developing, forming a photoresist mask; next, etching the transparent conductive layer with a photoresist mask to form a pattern of the common electrode 16, the gate pad electrode 17, and the data pad electrode 18; finally, stripping Remaining photoresist

The common electrode 16 may include a first common electrode 161 located above the pixel electrode 12 and a second common electrode 162 located above the data line 8. The common electrode 16 may have a slit shape. The gate pad electrode 17 is electrically connected to the gate pad 3 through the second contact hole 14, and the data pad electrode 18 is electrically connected to the data pad 9 through the third contact hole 15.

In this step, if the thickness of the common electrode 16 is too small, the resistance thereof is too high; if the thickness of the common electrode 16 is too large, the transmittance is lowered.

In this embodiment, the second common electrode 162 is located above the data line 8 and is capable of shielding pixels. The electromagnetic field between the electrode 12 and the data line 8 can thereby reduce the width of the black matrix on the color filter, thereby increasing the aperture ratio of the pixel.

Method embodiment 2

Step S21, providing a substrate, forming a gate line, a gate electrode and a gate pad on the substrate; specifically, first, sputtering, thermal evaporation or other film forming method may be used on the glass substrate or other type of transparent substrate Forming a gate metal layer, the gate metal layer may be made of chromium (Cr), molybdenum (Mo), aluminum (A1), copper (Cu), tungsten (W), niobium (Nd) and alloys thereof, and the gate metal layer may be One or more layers; then, a photoresist is formed on the gate metal layer; then, the photoresist is exposed and developed by using a patterned mask to form a photoresist mask; The gate mask etches the gate metal layer to form a pattern of gate lines, gate electrodes and gate pads; finally, the remaining photoresist is stripped. It should be noted that, in this step, a common electrode line may be formed while forming a pattern of a gate line, a gate electrode, and a gate pad.

Step S22, forming a gate insulating layer on the substrate on which step S21 is completed;

Specifically, as shown in Fig. 2, a gate insulating layer 4 having a thickness of 2000 8000 A may be deposited on the substrate 1 on which step S21 is completed by plasma enhanced chemical vapor deposition (PECVD) or the like. The gate insulating layer 4 may be selected from an oxide (e.g., SiOx) or a nitride (e.g., SiNx).

Step S23, forming a semiconductor material layer on the substrate completing step S22;

Specifically, as shown in Fig. 11, a semiconductor material layer 20 having a thickness of 1000 4000 A can be formed on the substrate 1 on which step S22 is completed by a method such as PECVD.

Step S24, forming a source/drain metal layer on the substrate of step S23;

Specifically, a source/drain metal layer having a thickness of 1000 6000 A may be formed on the substrate 1 completing the step S23 by sputtering, thermal evaporation or other film forming method, and the source/drain metal layer may be made of chromium (Cr) or molybdenum. (Mo), aluminum (A1), copper (Cu), tungsten (W), niobium (Nd) or an alloy thereof, and the source/drain metal layer may be one or more layers.

Step S25, forming a photoresist mask on the substrate completing step S24;

Specifically, as shown in FIG. 12, first, a photoresist layer 19 is formed on the source/drain metal layer; then, the photoresist layer 19 is exposed and developed by using a gray tone or halftone mask patterned with a pattern, A photoresist mask including a photoresist completely reserved region, a photoresist portion remaining region, and a photoresist unretained region is formed.

Step S26, forming a pattern of the data line and the data pad; Specifically, as shown in FIG. 13, the source/drain metal layer of the unretained region of the photoresist is etched by a photoresist mask to form a pattern of the data line 8 and the data pad 9.

Step S27, etching a semiconductor material layer in the unreserved region of the photoresist, and performing an ashing process; specifically, as shown in FIG. 14, first, using a photoresist mask to the semiconductor material in the region where the photoresist is not reserved The layer 20 is etched to form a pattern of the semiconductor layer 5; then, the photoresist in the remaining portion of the photoresist is removed by an ashing process, and the photoresist in the completely remaining region of the photoresist is thinned to form a new photoresist. Mask.

Step S28, forming a pattern of the source electrode and the drain electrode;

Specifically, as shown in FIG. 15, first, the exposed source/drain metal layer is etched by a photoresist mask to form a pattern of the source electrode 6 and the drain electrode 7; then, the source electrode 6 and the drain electrode 7 are etched away. A portion of the semiconductor layer 5 is interposed and the remaining photoresist is stripped to form a channel of the thin film transistor. When the semiconductor layer 5 is a silicon semiconductor structure composed of an intrinsic semiconductor and a doped semiconductor (ohmic contact layer), "etching away a portion of the semiconductor layer 5 between the source electrode 6 and the drain electrode 7" mainly means etching The ohmic contact layer between the source electrode 6 and the drain electrode 7 is dropped; and when the semiconductor layer 5 is an organic semiconductor or an oxide semiconductor, "etching away a portion of the semiconductor layer 5" is mainly due to etching of the source and drain metal layer Due to the etching, it is not necessary to etch away a part of the semiconductor layer 5, and it is only necessary to ensure that the source and drain metal layers of the channel region are completely etched away.

In the following steps, although not shown in the drawings, it is understood that the unetched semiconductor material remains under the data lines 8 and the data pads 9.

Step S29, forming an inorganic insulating film on the substrate completing step S28;

Specifically, as shown in Fig. 5, an inorganic insulating film 21 having a thickness of 1000 2000 A may be deposited on the substrate 1 on which step S28 is completed by a method such as PECVD. The inorganic insulating film 21 may be selected from an oxide (e.g., SiOx) or a nitride (e.g., SiNx).

Step S30, forming an organic insulating film on the substrate on which step S29 is completed, and patterning the organic insulating film;

Specifically, as shown in FIG. 6, first, an organic insulating film 10 having a thickness of 10000-40000 A is formed on the substrate 1 on which the step S29 is completed, and the organic insulating film 10 can be made of an organic photosensitive material such as polyacrylic acid; The patterned insulating mask exposes and develops the organic insulating film to expose the drain electrode, the data pad 9 and the inorganic insulating film 21 at the gate pad 3; finally, the organic insulating film 10 is subjected to a curing (Cure) process. In this step, if the thickness of the organic insulating film 10 is too small, the effect of reducing the parasitic capacitance between the subsequent common electrode and the data line (relative to the inorganic insulating film) is not significant; if the organic insulating film

If the thickness of 10 is too large, the slope of the step between the layers may increase, which may cause the pixel electrode to be broken or the like.

In this step, the curing temperature may be 230 to 260 ° C, and the treatment time may be 30 to 60 minutes. If the curing temperature is lower than 230 ° C, the micro-cure of the protective film may cause contamination and film lift, etc.; if the curing temperature is higher than 260 ° C, the organic insulating film 10 may be denatured, thereby This makes the transmission rate low.

Step S31, etching away the exposed inorganic insulating film;

Specifically, as shown in FIG. 7, the exposed inorganic insulating film is formed using the organic insulating film 10 as a mask.

The etching is performed to form the first contact hole 11 and expose the gate insulating layer 4 and the data pad 9 at the gate pad 3.

Step S32, forming a pixel electrode on the substrate of the step S31, wherein the pixel electrode is electrically connected to the drain electrode through the first contact hole;

Specifically, as shown in FIG. 8, first, a transparent conductive layer having a thickness of 100 lOOOA may be formed on the substrate 1 on which the step S31 is completed by using magnetron sputtering, thermal evaporation, or other film forming methods, and the transparent conductive layer may be釆 using indium tin oxide (ITO), indium oxide (IZO) or alumina, etc.; then, forming a photoresist on the transparent conductive layer; then, using a patterned mask to expose the photoresist And developing, forming a photoresist mask; next, etching the transparent conductive layer with a photoresist mask to form a pattern of the pixel electrode 12, the pixel electrode 12 passing through the first contact hole 11 and leakage The pole 7 is electrically connected; thereafter, the exposed gate insulating layer 4 is etched away with a photoresist mask to expose the gate pad 3; finally, the remaining photoresist is stripped. In each of the pixel units, the pixel electrode may be in the form of a plate or a slit.

The left half of Fig. 9 is a cross-sectional view of the array substrate after completion of the pixel electrode according to the prior art, and the right half is a cross-sectional view of the array substrate after completion of the pixel electrode according to an embodiment of the present invention. As shown in FIG. 9, in the prior art, in order to avoid the influence of the parasitic capacitance between the pixel electrode 12 and the data line 8 on the charging characteristics of the pixel electrode 12, the distance between the pixel electrode 12 and the data line 8 is dl. Need to be done, generally about 2μπι, which leads to a decrease in the aperture ratio of the pixel; In the embodiment, since the organic insulating mold 10 is used, even if the distance d2 between the pixel electrode 12 and the data line 8 is made small, the parasitic capacitance between the pixel electrode and the data line is not too large, so The distance d2 can be reduced to 0 ~ Ιμπι to increase the aperture ratio of the pixel.

Step S33, forming a protective film on the substrate on which step S32 is completed, and patterning the protective film; specifically, as shown in FIG. 10, first, a method such as PECVD may be used to complete the steps.

A protective film 13 having a thickness of 2000 4000 Å is formed on the substrate 1 of S32, and a material such as SiNx or SiOx can be used for the protective mold 13; then, a photoresist is formed on the protective film 13; and then, a mask pair patterned with a pattern is used. The photoresist is exposed and developed to form a photoresist mask. Next, the protective film 13 is etched by using a photoresist mask to form a second contact hole 14 and a third contact hole 15 to respectively expose the gate. Pad 3 and data pad 9; Finally, the remaining photoresist is stripped.

In this step, if the thickness of the protective film 13 is less than 2000 A, the storage capacitor (Cst) rises, causing an increase in signal delay; if the thickness of the protective film 13 is larger than 4000 A, the process time and the manufacturing cost are too high.

Step S34, forming a common electrode, a gate pad electrode, and a data pad electrode on the substrate on which step S33 is completed.

Specifically, as shown in FIG. 16, first, a transparent conductive layer having a thickness of 100 lOOOA may be formed on the substrate 1 on which step S33 is completed by magnetron sputtering, thermal evaporation or other film forming method, and the transparent conductive layer may be 釆Using a material such as indium tin oxide (ITO), indium oxide (IZO) or alumina; then, forming a photoresist on the transparent conductive layer; then, exposing the photoresist with a patterned mask Developing, forming a photoresist mask; next, etching the transparent conductive layer with a photoresist mask to form a pattern of the common electrode 16, the gate pad electrode 17, and the data pad electrode 18; finally, peeling off the remaining Photoresist.

The common electrode 16 may include a first common electrode 161 located above the pixel electrode 12 and a second common electrode 162 located above the data line 8. The gate pad electrode 17 may be electrically connected to the gate pad 3 through the second contact hole 14, and the data pad electrode 18 may be electrically connected to the data pad 9 through the third contact hole 15.

In this embodiment, the second common electrode 162 is located above the data line 8, and can shield the electromagnetic field between the pixel electrode 12 and the data line 8, thereby reducing the width of the black matrix on the color filter. Thereby, the aperture ratio of the pixel can be increased. Further, in forming the semiconductor layer 5, the source electrode 6, and the drain electrode 7, since the ashing process is used, the number of masks can be reduced, thereby reducing the manufacturing cost.

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

Claim

An array substrate comprising a display region including a gate line, a data line, and a plurality of pixel units defined by the gate line and the data line, wherein each of the pixel units a thin film transistor, a pixel electrode, and a common electrode, wherein the pixel electrode is electrically connected to a drain electrode of the thin film transistor,

Wherein an inorganic insulating film is formed on the data line and the semiconductor layer of the source electrode, the drain electrode and the channel region of the thin film transistor, an organic insulating film is formed on the inorganic insulating film, and a protective film is formed on the pixel electrode And the organic insulating film, the common electrode is formed on the protective film such that the protective film is disposed between a layer where the common electrode is located and a layer where the pixel electrode is located, and the inorganic insulating A film and the organic insulating film are disposed between the pixel electrode and the data line and between the thin film transistor and the protective film.

2. The array substrate of claim 1, wherein:

a gate electrode of the thin film transistor and the gate line are formed on a substrate;

a gate insulating layer is formed on the gate electrode and the gate line;

a semiconductor layer and the data line are formed on the gate insulating layer;

The source electrode and the drain electrode are formed on the semiconductor layer;

a first contact hole formed in the inorganic insulating film and the organic insulating film;

The pixel electrode is formed on an organic insulating film, and the pixel electrode is electrically connected to the drain electrode through the first contact hole;

The common electrode includes a first common electrode above the pixel electrode and a second common electrode above the data line.

The array substrate according to any one of claims 1 to 2, wherein a semiconductor layer material remains under the data line, or the data line is in direct contact with the underlying gate insulating layer.

The array substrate according to any one of claims 1 to 3, further comprising:

a gate pad in the non-display area and in the same layer as the gate line;

a data pad in the non-display area and in the same layer as the data line;

a gate pad electrode formed on the protective film and at a position corresponding to the gate pad, the gate pad electrode being electrically connected to the gate pad through a second contact hole, the second contact hole being worn Passing through the protective film, the organic insulating film, and the inorganic insulating film; a data pad electrode formed on the protective film and at a position corresponding to the data pad, the data pad electrode being electrically connected to the data pad through a third contact hole, the third contact hole being worn The protective film, the organic insulating film, and the inorganic insulating film are passed through.

The array substrate according to any one of claims 1 to 4, wherein:

The distance between the pixel electrode and the data line in the horizontal direction is 0 ~ 1μπι.

The array substrate according to any one of claims 1 to 5, wherein:

The inorganic insulating film has a thickness of 1000 to 2000 Å.

The array substrate according to any one of claims 1 to 6, wherein:

The material of the organic insulating film is polyacrylic acid.

The array substrate according to any one of claims 1 to 7, wherein:

The organic insulating film has a thickness of 10,000 to 40,000 Å.

The array substrate according to any one of claims 1 to 8, wherein:

The protective film is made of an inorganic insulating material and has a thickness of 2000 to 4000 Å.

10. A method of fabricating an array substrate, comprising:

Forming a gate electrode and a gate line on the substrate;

Forming a pixel electrode on the substrate on which the organic insulating film is formed, the pixel electrode being electrically connected to the drain electrode;

A protective film is formed on the substrate on which the pixel electrode is formed, and the protective film is patterned; a common electrode is formed on the substrate on which the protective film is formed.

11. The manufacturing method according to claim 10, wherein:

a gate pad is formed on the substrate, and a data pad is formed on the gate insulating layer;

Forming the organic insulating film and the inorganic insulating film to form a first contact hole through the organic insulating film and the inorganic insulating film and exposing a gate insulating layer at the gate pad and the a data pad, the pixel electrode being electrically connected to the drain electrode through the first contact hole; the patterning the protective film to form a second contact hole and a third contact hole, the second contact hole passing through The protective film, the organic insulating film, the inorganic insulating film, and the gate insulating layer, the third contact hole passes through the protective film, the organic insulating film, and the inorganic insulating film;

a gate pad electrode and a data pad electrode are formed on the protective film, the gate pad electrode is electrically connected to the gate pad through the second contact hole, and the data pad electrode passes through the third a contact hole electrically connected to the data pad;

The manufacturing method according to any one of claims 10 to 11, wherein after the organic insulating film is patterned, the method further comprises:

The organic insulating film is subjected to a curing treatment at a temperature of 230 to 260 ° C for a period of 30 to 60 minutes.

The manufacturing method according to any one of claims 10 to 12, wherein:

a distance between the pixel electrode and the data line in a direction parallel to the substrate is

0 ~ 1μπι.

The manufacturing method according to any one of claims 10 to 13, wherein:

The inorganic insulating film has a thickness of 1000 to 2000 Å.

The manufacturing method according to any one of claims 10 to 14, wherein:

The material of the organic insulating film is polyacrylic acid.

The manufacturing method according to any one of claims 10 to 15, wherein:

The organic insulating film has a thickness of 10,000 to 40,000 Å.

The manufacturing method according to any one of claims 10 to 16, wherein:

The protective film is made of an infinitely insulating material and has a thickness of 2000 to 4000 Å.

The manufacturing method according to any one of claims 10 to 17, wherein the semiconductor layer, the source electrode, the drain electrode, and the thin film are formed on a substrate on which the gate insulating layer is formed The data line and the data pad include:

Forming a semiconductor material layer on the substrate on which the gate insulating layer is formed;

Patterning the layer of semiconductor material to form a semiconductor layer;

Forming a metal layer on the substrate on which the semiconductor layer is formed; The metal layer is patterned to form a source electrode, a drain electrode, a data line, and a data pad, and a semiconductor layer between the source electrode and the drain electrode forms a channel.

The manufacturing method according to any one of claims 10 to 18, wherein the semiconductor layer, the source electrode, the drain electrode, and the thin film are formed on a substrate on which the gate insulating layer is formed The data line and the data pad include:

Forming a semiconductor material layer and a metal layer on the substrate on which the gate insulating layer is formed; forming a photoresist layer on the metal layer;

Exposing and developing the photoresist layer with a halftone or gray tone mask to form a photoresist completely reserved region, a photoresist portion remaining region, and a photoresist unretained region;

Etching off the metal layer and the semiconductor material layer of the unretained region of the photoresist;

Removing the photoresist of the remaining portion of the photoresist by an ashing process;

A metal layer of the photoresist portion remaining region and a portion of the semiconductor material layer are etched away.

A display device comprising the array substrate according to any one of claims 1 to 9.