WO2013022192A2

WO2013022192A2 - Phase-locked loop and clock-generating system comprising same

Info

Publication number: WO2013022192A2
Application number: PCT/KR2012/005527
Authority: WO
Inventors: 황인준
Original assignee: 주식회사 아이덴코아
Priority date: 2011-08-05
Filing date: 2012-07-12
Publication date: 2013-02-14
Also published as: KR20130015924A; WO2013022192A3

Abstract

A phase-locked loop according to one embodiment of the present invention comprises: a phase sensor for generating a phase sensor signal by sensing the phase difference between a reference clock signal and an output clock signal; a charge pump for providing a pumping current on the basis of the phase sensor signal; a loop filter for providing filtered pumping voltage corresponding to the pumping current; a voltage controlled crystal oscillator, comprising a crystal vibrator, for generating a crystal oscillator signal on the basis of the filtered pumping voltage; and a supplementary phase-locked loop for locking the phase of the output clock signal on the basis of the crystal oscillator signal and then providing same.

Description

Phase Locked Loops and Clock Generation Systems Including the Same

The present invention relates to a phase locked loop, and more particularly, to a low noise phase locked loop and a clock generation system including the same to minimize noise of an oscillation signal generated in the phase locked loop.

The phase locked loop may include a reference clock generator, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider. .

The phase detector can generate a phase sensing signal by comparing the phase of the divided oscillator signal of the divider based on the oscillation signal of the voltage controlled oscillator with the reference clock signal, and the charge pump pumps the charge according to the phase sensing signal to pump the current. The loop filter generates a voltage according to the pumped current and provides the voltage to the voltage controlled oscillator. The voltage controlled oscillator may provide an oscillation signal based on the signal provided by the phase comparator.

However, jitter caused by jitter and external factors of the reference clock signal provided to the phase locked loop affects the oscillation signal of the voltage controlled oscillator.

To eliminate this jitter, a method of generating a clock signal based on the output of the jitter-free VCXO including a voltage controlled crystal oscillator (VCXO) has been proposed, but the VCXO has a very narrow oscillation range. This can limit the frequency of the output clock to a constant value.

An object of the present invention is to provide a phase locked loop capable of setting various oscillation frequencies while minimizing jitter occurring in the phase locked loop.

Another object of the present invention is to provide a low noise phase locked loop in which no jitter occurs even when a plurality of phase locked loops are cascaded.

A phase locked loop according to an embodiment of the present invention, a phase detector for detecting a phase difference between a reference clock signal and an output clock signal to generate a phase detection signal, and generating a voltage corresponding to the phase detection signal and filtering the pumped voltage. A voltage controlled crystal oscillator including a charge pump and a loop filter, a crystal oscillator, and generating a crystal oscillation signal based on the filtered pumping voltage, and fixing a phase of the output clock signal based on the crystal oscillation signal. And an auxiliary phase locked loop.

According to an embodiment of the present invention, a phase lock loop divides a reference clock signal into a preset third division value and provides a main divider by dividing a third divider and an output clock signal into a preset fourth divider value. A fourth detector configured to provide a divided output clock signal, a phase detector configured to detect a phase difference between the main clock signal and the divided output clock signal to generate a phase detection signal, and provide a pumping current based on the phase detection signal A charge pump, a loop filter providing a filtered pumping voltage corresponding to the pumping current, a voltage controlled crystal oscillator comprising a crystal oscillator and generating a crystal oscillation signal based on the filtered pumping voltage, and based on the crystal oscillation signal And an auxiliary phase locked loop for fixing and providing a phase of the output clock signal.

In a clock generation system according to an embodiment of the present invention, with respect to a clock generation system in which a plurality of phase locked loops are cascaded, each of the plurality of phase locked loops includes a crystal oscillator, and includes a crystal oscillator. A voltage controlled crystal oscillator for generating a crystal oscillation signal on the basis of and an auxiliary phase locked loop for fixing and providing a phase of the output clock signal based on the crystal oscillation signal.

A phase locked loop according to an embodiment of the present invention includes a clock signal that minimizes jitter by including an auxiliary phase locked loop operating based on a jitter free oscillation signal generated as an output of the VCXO in the phase locked loop. Can be generated.

Also, in general, when providing output clocks having various frequencies, a plurality of VCXOs are required. However, a phase locked loop according to an embodiment of the present invention can provide output clocks having various frequencies even though only one VCXO is included. It is suitable for miniaturization.

The phase locked loop according to another embodiment of the present invention does not accumulate jitter even if the plurality of phase locked loops are cascaded, and can operate by adaptively changing a frequency in response to various frequencies. It is possible to improve the design convenience for the containing system.

1 is a block diagram illustrating a phase locked loop according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the auxiliary phase locked loop of FIG. 1.

3 is a block diagram illustrating a phase locked loop according to an embodiment of the present invention.

4 is a block diagram illustrating a clock generation system in which a phase locked loop is cascaded according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

Referring to FIG. 1, the phase locked loop 10a may include a phase detector 100, a charge pump 200, a loop filter 300, a VCXO 400, and an auxiliary phase locked loop 500.

The phase detector 100 receives the reference clock signal RCLK and the output clock signal TXCLK and detects a phase difference between the two signals to generate a phase detection signal PD.

The charge pump 200 receives a phase detection signal PD to charge or discharge a predetermined charge. When the pumping current PC is provided through the charge pump 200, the loop filter 300 provides the filtered pumping voltage FPC based on the pumping current PC. For example, the loop filter 300 may include a low pass filter, and may include a capacitor to store or discharge the pumping current PC. It also filters out sudden noise, i.e., jitter, to provide a pumping voltage (FPC) filtered to within a certain value for the VCXO 400. Accordingly, the charge pump 200 and the loop filter 300 may be implemented as pulse-voltage converters that provide a filtered pumping voltage FPC having a preset value to the VCXO 400 based on the phase detection signal PD. have.

The VCXO 400 is a crystal oscillator, which generates a crystal oscillation signal SRCLK based on the filtered pumping voltage FPC. The VCXO 400 operates using a crystal piezoelectric effect and a reverse piezoelectric effect, including a crystal oscillator. Since the Q is higher than other crystals, stable vibration is obtained, so that jitter can be minimized. The VCXO 400 has an advantage of generating a jitter-free crystal oscillation signal SRCLK, but has a disadvantage in that the frequency range of the crystal oscillation signal SRCLK is narrow, so that the frequency of the clock signal is variously set in one system. Cannot work properly. Accordingly, the phase locked loop 10a according to an embodiment of the present invention provides a crystal oscillation signal SRCLK without jitter to the auxiliary phase locked loop 500 to extend the frequency setting range of the output clock signal TXCLK. You can.

The auxiliary phase locked loop 500 may generate an output clock signal TXCLK by detecting a phase difference between the reference clock and the output clock signal TXCLK using the jitter-free crystal oscillation signal SRCLK as a reference clock. According to an exemplary embodiment, the auxiliary phase locked loop 500 may include substantially the same components as the general phase locked loop, and a detailed configuration of the auxiliary phase locked loop 500 will be described later with reference to FIG. 2.

From the perspective of the auxiliary phase locked loop 500, the crystal oscillation signal SRCLK provided as a reference clock to the auxiliary phase locked loop 500 has no jitter, and as a result, the output output from the auxiliary phase locked loop 500. Jitter of the clock signal TXCLK may be minimized. In addition, the auxiliary phase locked loop 500 according to an embodiment of the present invention does not include a VCXO, but includes a general voltage controlled oscillator (VC0) so that the output clock signal TXCLK may have more various frequencies. do.

When the auxiliary phase locked loop 500 is not included, there is a problem that accurate phase detection between the reference signal and the fed back output clock signal cannot be performed by using the clock signal including jitter as a reference signal, and also the reference clock signal. When VCXO is used to eliminate jitter of jitter or jitter that may be included in an input pumping voltage to finally provide an output clock signal, there may be a problem that the output clock signal is generated only within a limited frequency range.

The phase locked loop 10a according to an embodiment of the present invention uses the crystal oscillation signal SRCLK provided from the VCXO 400 with little jitter as a reference clock to generate an output phase clock signal TXCLK. Including 500, frequency accuracy may be improved by minimizing jitter in the output clock signal TXCLK. At the same time, the VCXO removes the limitation of the frequency range of the output clock signal that can occur when the output clock signal is generated, and thus is highly adaptable to a system requiring a clock signal having various frequencies.

Referring to FIG. 2, the auxiliary phase locked loop 500 includes a first divider 510, an auxiliary phase detector 520, an auxiliary charge pump 530, an auxiliary loop filter 540, a VCO 550, and a second divider. Period 560 may be included.

The first divider 510 may divide the crystal oscillation signal SRCLK according to a preset first division value to generate a divided crystal oscillation signal DRCLK. In addition, the second divider 560 may divide the output clock signal TXCLK according to a preset second division value to generate a divided auxiliary output clock signal DCLK.

The auxiliary phase detector 520 may generate the auxiliary phase detection signal SPD by detecting a phase change between the divided crystal oscillation signal DRCLK and the divided auxiliary output clock signal DCLK. Compared with the phase detector 100 of FIG. 1, the auxiliary phase detector 520 of FIG. 2 may perform substantially the same operation as the received signal is different.

The auxiliary charge pump 530 may provide a different auxiliary pumping current SPC according to the auxiliary phase sensing signal SPD. Likewise, the auxiliary charge pump 530 of FIG. 2 may perform substantially the same function as the charge pump 200 of FIG. 1.

The auxiliary loop filter 540 may generate the filtered auxiliary pumping voltage SFPC by converting the auxiliary pumping current SPC into a voltage. The auxiliary loop filter 540 may perform substantially the same function as the loop filter 300 of FIG. 1.

The VCO 550 receives the filtered auxiliary pumping voltage SFPC to generate an output clock signal TXCLK. The auxiliary phase locked loop 500 according to an embodiment of the present invention may include a VCO other than a VCXO to reduce the size and extend a range of frequencies in which the output clock signal TXCLK may be generated. For example, the VCO 550 may include a ring oscillator. According to an exemplary embodiment, the loop band of the auxiliary phase locked loop 500 may be set wide to reduce jitter generated in the VCO 550 itself.

The frequency of the output clock signal TXCLK output from the auxiliary phase locked loop 500 may be expressed by Equation 1 below.

[Equation 1]

In Equation 1, f _SRCLK is the frequency of the crystal oscillation signal SRCLK, f _TXCLK is the frequency of the output clock signal TXCLK, M is the first divided frequency value of the first divider 510, N is the second minute. The second divided frequency value of the period 560 is shown.

Therefore, the crystal oscillation signal SRCLK in the auxiliary phase locked loop 500 may not be an integer multiple of the output clock signal TXCLK. That is, even if the frequency of the crystal oscillation signal SRCLK generated from the VCXO 400 is limited to a certain range, the output clock signal (according to the combination of the division values of the first divider 510 and the second divider 560) The frequency of TXCLK) can be freely controlled without being limited to the frequency range of the crystal oscillation signal SRCLK.

For example, in the case of a general phase locked loop not including the auxiliary phase locked loop 500, the operation was possible only when the oscillation signal output from the VCXO 400 corresponds to an integer multiple of the reference clock. The phase locked loop 10a according to the embodiment may include an auxiliary phase locked loop 500 capable of setting a divided value, thereby overcoming the frequency range limitation according to the VCXO 400.

In the conventional phase locked loop, which does not include the auxiliary phase locked loop 500 that can set the division value, it is designed to further include a separate VCXO to match the frequency of the signal output from the VCXO and the frequency of the reference clock by an integer multiple. In some cases, the phase locked loop 10a according to an embodiment of the present invention includes an auxiliary phase locked loop 500 having a divider instead of a large separate VCXO to limit the frequency value according to the VCXO. It is possible to provide an output clock signal TXCLK having various frequencies without receiving.

In conclusion, the phase locked loop 10a according to the embodiment of the present invention includes a VCXO 400 to provide a jitter-free crystal oscillation signal SRCLK to be used as a reference clock of the auxiliary phase locked loop 500. The jitter of the output clock signal TXCLK may be reduced, and the output clock signal TXCLK may be provided without being limited to the frequency range of the crystal oscillation signal SRCLK provided by the VCXO 400.

Compared with the phase locked loop 10a of FIG. 1, the phase locked loop 10b of FIG. 3 may further include a third divider 600 and a fourth divider 700.

In FIG. 3, the same reference numerals as used in FIG. 1 denote the same components, and thus detailed description thereof will be omitted since the same components and operations are substantially performed.

Referring to FIG. 3, the third divider 600 divides the reference clock signal RCLK into a preset third division value to generate a main clock signal MCLK. The fourth divider 700 divides the output clock signal TXCLK into a preset fourth division value to generate a divided output clock signal DTXCLK.

The phase detector 100 detects a phase difference between the main clock signal MCLK and the divided output clock signal DTXCLK to generate a phase detection signal PD, and the charge pump 200 generates the phase detection signal PD. Based on the pumped current PC, and the loop filter 300 generates the filtered pumping voltage FPC based on the pumped current PC.

The VCXO 400 generates a jitter free crystal oscillation signal SRCLK based on the filtered pumping voltage FPC and provides it to the auxiliary phase locked loop 500 as a reference clock, and the auxiliary phase locked loop 500 corrects. Based on the oscillation signal SRCLK, the output clock signal TXCLK of a constant frequency is provided through a phase fixing process with the output clock signal TXCLK.

In the phase locked loop 10b of FIG. 3, the third divider 600 and the fourth divider 700 are further included, so that the frequency of the reference clock signal RCLK and the output clock signal TXCLK is different. Operation is possible even without a separate frequency synthesizer.

Specifically, if the preset third division value of the third divider 600 is P and the preset fourth division value of the fourth divider 700 is Q, this indicates the frequency of the reference clock signal RCLK. f _RCLK, f represents the frequency of f _SRCLK, and the output clock signal (TXCLK) indicating the frequency of the crystal oscillating signal (SRCLK) _TXCLK has the relationship such as expression (2) below.

[Equation 2]

Therefore, the frequency of the output clock signal TXCLK output from the phase locked loop 10b according to an embodiment of the present invention does not need to be an integer multiple of the frequency of the crystal oscillation signal SRCLK and the frequency of the reference clock signal RCLK. The output clock signal TXCLK having various frequencies may be provided based on a combination of the divided values of the first to

third dividers

510, 560, 600, and 700.

That is, the phase locked loop 10b according to an embodiment of the present invention may have various frequencies without including jitter and not limited to integer multiples or divided by integers of frequencies of the respective reference clock signals.

Referring to FIG. 4, the clock generation system 20 may include a plurality of phase locked loops 10_1, 10_2, 10_3,..., 10_n.

Each of the plurality of phase locked loops 10_1, 10_2, 10_3,..., 10_n shown in FIG. 4 may include the configuration shown in FIGS. 1 and 3, and the phase locked loops 10_1, 10_2, The auxiliary phase locked loop included in 10_3,..., 10_n) may include a configuration as shown in FIG. 2.

The first phase locked loop 10_1 receives the reference clock signal RCLK to generate the first output clock signal TXCLK1, and the second phase locked loop 10_2 receives the first output clock signal TXCLK1. The second output clock signal TXCLK2 is generated using the first output clock signal TXCLK1 as a reference clock. Similarly, the third phase locked loop 10_3 generates the third output clock signal TXCLK3 using the second output clock signal TXCLK2 as a reference clock.

In the clock generation system 20, the plurality of phase locked loops 10_1, 10_2, 10_3,..., 10_n finally receive outputs as input signals, thereby finally generating the nth output clock signal TXCLKn, or The output clock signal TXCLK having various frequencies may be provided by connecting an output to each of the first through nth output clock signals TXCLK1, TXCLK2, TXCLK3,..., TXCLKn-1, TXCLKn.

As described above, each of the plurality of phase locked loops 10_1, 10_2, 10_3,..., 10_n according to an embodiment of the present invention includes an auxiliary phase locked loop 500 as shown in FIG. 2. It is possible to generate an output clock signal TXCLK having various frequencies without generating jitter.

For example, when each of the phase locked loops 10_1, 10_2, 10_3,..., 10_n does not include the auxiliary phase locked loop 500 and is cascaded with each other as shown in FIG. 4. Since the jitter generated in the first phase locked loop 10_1 affects the second phase locked loop 10_2, the second output clock signal TXCLK may generate the jitter and the second phase generated in the first phase locked loop 10_1. The jitter generated in the fixed loop 10_2 may be added to generate larger jitter. As a result, the n-th output clock signal TXCLKn output from the n-th phase locked loop 10_n may cause all the jitter generated in the plurality of phase locked loops. Can accumulate and contain very large jitter.

However, the phase locked loops 10_1, 10_2, 10_3,..., 10_n according to an embodiment of the present invention are output from the VCXO to receive the jitter-free crystal oscillation signal SRCLK as a reference clock and output an output clock signal ( Since the jitter-free output clock signal TXCLK is provided by including an auxiliary phase-locked loop that generates TXCLK, the generation of jitter can be minimized even when a plurality of cascaded circuits are connected as shown in FIG. 4.

In addition, the phase locked loops 10_1, 10_2, 10_3,..., 10_n may further include first to fourth dividers, so that the output clock signal TXCLK is limited to an integer multiple of the frequency of the reference clock. It is possible to generate the output clock signal TXCLK having various frequencies according to the combination of the divided values of the dividers without generating only).

In addition, when the plurality of phase locked loops 10_1, 10_2, 10_3,..., 10_n are cascaded as shown in FIG. 4, each of the phase locked loops 10_1, 10_2, 10_3,. The output clock signal TXCLK of more various values may be provided according to a combination of included dividers.

Therefore, a phase locked loop and a clock generation system including the same according to an embodiment of the present invention may include an output clock signal TXCLK including an auxiliary phase locked loop that uses the output signal of the VCXO that generates little jitter as a reference clock. This minimizes jitter generation.

In addition, a phase locked loop and a clock generation system including the same according to an embodiment of the present invention include a VCO having a wide range of oscillation frequency in an auxiliary phase locked loop for generating an output clock signal TXCLK. The output clock signal TXCLK having various frequencies can be generated without generating.

Furthermore, a phase locked loop and a clock generation system including the same according to an embodiment of the present invention may generate an output clock signal TXCLK that includes at least one frequency divider and is not tied to an integer multiple of the frequency of the reference clock. have.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope without departing from the technical spirit of the present invention. It will be apparent to those who have the knowledge of.

The phase locked loop and the system including the same according to an embodiment of the present invention can be usefully used in a small device because it can provide an output clock having various frequencies while minimizing jitter while including only one VCXO.

In addition, the phase locked loop and the system including the same according to an embodiment of the present invention can minimize the consideration of jitter in the design because the jitter does not accumulate even when a plurality of phase locked loops are connected in a cascade, thereby simplifying design. It can be applied to various devices.

Claims

A phase detector for detecting a phase difference between the reference clock signal and the output clock signal to generate a phase detection signal;

A charge pump providing a pumping current based on the phase sense signal;

A loop filter providing a filtered pumping voltage corresponding to the pumping current;

A voltage controlled crystal oscillator including a crystal oscillator, the crystal oscillator generating a crystal oscillation signal based on the filtered pumping voltage; And

And an auxiliary phase locked loop for fixing and providing a phase of the output clock signal based on the crystal oscillation signal.
The method according to claim 1,

The auxiliary phase locked loop,

A first divider which divides the crystal oscillation signal into a preset first division value and provides it as a divided crystal oscillation signal;

An auxiliary phase detector for detecting a phase difference between the divided crystal oscillation signal and the divided auxiliary output clock signal to generate an auxiliary phase detection signal;

An auxiliary charge pump providing an auxiliary pumping current corresponding to the auxiliary phase sensing signal;

An auxiliary loop filter for generating a filtered auxiliary pumping voltage corresponding to the auxiliary pumping current;

A voltage controlled oscillator for generating an output clock signal based on the auxiliary pumping voltage; And

And a second divider for dividing the output clock signal into a preset second divided value to generate the divided auxiliary output clock signal.
The method according to claim 2,

The voltage controlled oscillator comprises a ring oscillator or an LC oscillator.
A third divider dividing the reference clock signal into a preset third divided value to provide the main clock signal;

A fourth divider which divides the output clock signal into a preset fourth divided value and provides the divided output clock signal as a divided output clock signal;

A phase detector configured to detect a phase difference between the main clock signal and the divided output clock signal to generate a phase detection signal;

A charge pump providing a pumping current based on the phase sense signal;

A loop filter providing a filtered pumping voltage corresponding to the pumping current;

A voltage controlled crystal oscillator comprising a crystal oscillator and generating a crystal oscillation signal based on the filtered pumping voltage; And

And an auxiliary phase locked loop for fixing and providing a phase of the output clock signal based on a crystal oscillation signal.
The method according to claim 4,

The frequency of the output clock signal is a phase locked loop, characterized in that corresponding to the ratio of the third divided value and the fourth divided value.
In a clock generation system in which a plurality of phase locked loops are cascaded,

Each of the plurality of phase locked loops,

A voltage controlled crystal oscillator comprising a crystal oscillator, the voltage controlled crystal oscillator generating a crystal oscillation signal based on a reference clock and an output clock signal; And

And an auxiliary phase locked loop configured to fix a phase of the output clock signal based on the crystal oscillation signal.
The method according to claim 6,

The auxiliary phase locked loop,

A first divider which divides the crystal oscillation signal into a first divided frequency value; And

A second divider for dividing the output clock signal into a preset second divider value;

And the crystal oscillation signal and the output clock signal have different frequencies according to a ratio of the first division value and the second division value.
The method according to claim 6,

Each of the plurality of phase locked loops,

A third divider for dividing the reference clock signal into a preset third divided value to provide a main clock signal;

A fourth divider for dividing the output clock signal into a preset fourth divided value to provide a divided output clock signal;

A phase detector configured to detect a phase difference between the main clock signal and the divided output clock signal to generate a phase detection signal;

A charge pump providing a pumping current based on the phase sense signal; And

And a loop filter for providing a filtered pumping voltage corresponding to the pumping current.
The method according to claim 8,

And the reference clock signal and the output clock signal have different frequencies according to a ratio of the third division value and the fourth division value.