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WO2013071840A1 - Tft阵列基板及显示设备 - Google Patents

Tft阵列基板及显示设备 Download PDF

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Publication number
WO2013071840A1
WO2013071840A1 PCT/CN2012/084335 CN2012084335W WO2013071840A1 WO 2013071840 A1 WO2013071840 A1 WO 2013071840A1 CN 2012084335 W CN2012084335 W CN 2012084335W WO 2013071840 A1 WO2013071840 A1 WO 2013071840A1
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WIPO (PCT)
Prior art keywords
pixel electrode
electrode layer
pixel
array substrate
strip
Prior art date
Application number
PCT/CN2012/084335
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English (en)
French (fr)
Inventor
孙荣阁
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US13/704,684 priority Critical patent/US9557620B2/en
Publication of WO2013071840A1 publication Critical patent/WO2013071840A1/zh
Priority to US15/397,196 priority patent/US10088720B2/en

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • Embodiments of the present invention relate to a thin film transistor (TFT) array substrate and a display device.
  • TFT thin film transistor
  • TN, IPS, VA, and ADS are several modes of liquid crystal display.
  • ADS is the abbreviation of ADSDS (ADvanced Super Dimension Switch), which is an advanced super-dimensional field conversion technology.
  • the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer form a multi-dimensional electric field. All of the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field switching technology can improve the picture quality of TFT products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura.
  • the first layer is a transparent pixel electrode layer (usually indium tin oxide (ITO)), which is the above-mentioned plate electrode, and then a gate metal layer is sequentially formed.
  • ITO indium tin oxide
  • a source/drain metal electrode layer and a second layer of pixel electrode layers (usually also ITO), and the second pixel electrode layer is the slit electrode described above.
  • a plurality of strip structures having a certain width and a pitch in the second layer of pixel electrode layers are referred to as strip-shaped pixel electrodes. The openings between the strip structures and the strip structures form slit electrodes.
  • the TFT pixel structure of the ADS mode has been evolving.
  • the early structure is a single domain structure, as shown in Figure 1.
  • the single-domain pixel structure includes: a gate line 102, a data line 103, a second pixel electrode layer 101, and a strip-shaped pixel electrode 101a on the second pixel electrode layer 101 and an opening 101b of the second pixel electrode layer.
  • the gate line 102 and the data line 103 cross each other to define a sub-pixel unit.
  • the data line 103 is connected to the drain 103a of the TFT, and the source 103b of the TFT is connected to the second pixel electrode layer 101.
  • the strip-shaped pixel electrodes in the same sub-pixel have the same direction.
  • the sub-pixels in the two-domain structure can be divided into two parts, the strip-shaped pixel electrodes of the two parts are bilaterally symmetrical, and the chromatic aberration can be further reduced. However, there are vertical strips of black lines at the intersection of the two domains in the center of the sub-pixel.
  • a pixel structure design is proposed in US Patent Application Publication No. US 2002/0041354, for example.
  • Figure 2 shows.
  • the pixel unit also has a two-domain structure, which is divided into upper and lower parts.
  • the strip-shaped pixel electrodes of the two parts are vertically symmetrical, which has the effect of low chromatic aberration and reduces the black-grain area at the boundary of the domain, thereby improving the penetration characteristics.
  • Embodiments of the present invention can overcome the disadvantage of excessive edge black areas of the pixel unit, thereby increasing aperture ratio and transmittance.
  • An aspect of the invention provides a TFT array substrate comprising: a gate line and a data line formed on a substrate; and a sub-pixel unit defined by the intersection of the gate line and the data line.
  • the sub-pixel unit includes a thin film transistor device, a common electrode, a first pixel electrode layer, and a second pixel electrode layer.
  • One of the first pixel electrode layer and the second pixel electrode layer is connected to the common electrode, and the other pixel electrode layer is connected to the source or the drain of the thin film transistor, and the first pixel electrode layer and the second pixel electrode layer pass The insulating layer is separated; the second pixel electrode layer is located above the first pixel electrode layer, and the pattern of the strip pixel electrode of the second pixel electrode layer overlaps with the pattern of the first pixel electrode layer, the strip pixel electrode and the liquid crystal
  • the initial orientation has a range of 3° to 15. The tilt angle is such that the gate line or data line is parallel to the strip pixel electrode near itself.
  • the inclination angle is 3 to 15. .
  • the inclination angle is 7° to 12°.
  • a plurality of strip-shaped pixel electrodes of the second pixel electrode layer are parallel to each other.
  • the gate line is parallel to the strip pixel electrode of the second pixel electrode layer, and the data line is perpendicular to the initial orientation of the liquid crystal.
  • the data line is parallel to the strip pixel electrode of the second pixel electrode layer, and the gate line is perpendicular to the initial orientation of the liquid crystal.
  • the gate line is parallel to a group of strip-shaped pixel electrodes in the second pixel electrode layer that are close to itself, and the data lines are perpendicular to the initial orientation of the liquid crystal.
  • the first portion of the data line is parallel to a group of strip-shaped pixel electrodes in the second pixel electrode layer, and the second portion of the data line is adjacent to another strip-shaped pixel electrode in the second pixel electrode layer.
  • the gate line is perpendicular to the initial orientation of the liquid crystal.
  • the TFT array substrate may, for example, include a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixel units defined by the intersection of the plurality of gate lines and the plurality of data lines, along a direction in which the liquid crystal is initially oriented,
  • the strip-shaped pixel electrodes in the adjacent sub-pixel units are symmetrical with each other with respect to the gate line or the data line therebetween, and adjacent strip pixels in the two adjacent sub-pixel units in the vertical direction of the initial orientation of the liquid crystal
  • the electrodes are parallel to each other.
  • the first pixel electrode layer includes a plate electrode.
  • Another aspect of the present invention provides a display device, wherein the array substrate in the display device is the TFT array substrate.
  • Embodiments of the present invention make the direction of the disturbing electric field of the gate line or the data line coincide with the direction of the fringe field inside the pixel unit by making the direction of the gate line or the data line parallel to the pixel electrode in the vicinity; at the same time, the vicinity of the gate line or the data line
  • the edge of the pixel electrode is parallel to the direction of the strip electrode of the inner pixel, so that the direction of the electric field at the edge of the pixel unit is consistent with the direction of the fringe field inside the pixel unit, thereby reducing the disordered liquid crystal orientation at the edge of the pixel unit, and improving the aperture ratio of the pixel unit and Penetration characteristics.
  • the embodiment of the present invention does not increase the process steps, can achieve higher aperture ratio and transmittance, improve optical utilization, reduce backlight cost and energy consumption, and achieve more green and Environmentally friendly effect.
  • FIG. 1 is a schematic view showing a structure of a TFT array substrate of the prior art
  • FIG. 2 is a schematic structural view of another TFT array substrate in the prior art
  • FIG. 3 is a schematic diagram of a sub-pixel structure in a TFT array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of an array substrate including nine sub-pixel structures shown in FIG. 5 is a schematic diagram of a sub-pixel structure in another TFT array substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of an array substrate including nine sub-pixel structures shown in FIG. 5;
  • FIG. 7 is a schematic diagram of a sub-pixel structure in another TFT array substrate according to an embodiment of the present invention
  • FIG. 8 is a schematic diagram of an array substrate including nine sub-pixel structures shown in FIG. 7;
  • FIG. 9 is a schematic diagram of a sub-pixel structure in another TFT array substrate according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of an array substrate including nine sub-pixel structures shown in FIG. detailed description
  • the array substrate of the embodiment of the present invention may include a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining sub-pixel units arranged in an array, each of the sub-pixel units including a thin film transistor as a switching element And a pixel electrode and a common electrode for controlling the arrangement of the liquid crystals.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • the following description is mainly for single or multiple sub-pixel units, but other sub-pixel units can Formed identically.
  • FIG. 3 is a schematic diagram showing a single sub-pixel structure in a TFT array substrate structure according to the present invention.
  • the array substrate includes: a plurality of gate lines 102 and a plurality of data lines 103 formed on a base substrate (not shown); the gate lines 102 and the data lines 103 cross each other to define a plurality of sub-pixel units, each of the sub-pixels
  • the unit includes a thin film transistor device as a switching element and includes a common electrode, a first pixel electrode layer 110, and a second pixel electrode layer 101.
  • the first pixel electrode layer 110 is shown by a broken line in Fig. 3, and includes, for example, a plate electrode.
  • the second pixel electrode layer 101 has a stripe pixel electrode 101a and an opening 101b of the second pixel electrode layer 101.
  • One of the first pixel electrode layer 110 and the second pixel electrode layer 101 is connected to the common electrode, and the other pixel electrode layer is connected to the source or the drain of the thin film transistor, and the first pixel electrode layer 110 and the second pixel electrode layer 101 Separated by an insulating layer.
  • the second pixel electrode layer 101 is positioned above the first pixel electrode layer 110, and the pattern of the stripe pixel electrode 101a of the second pixel electrode layer 101 overlaps the pattern of the first pixel electrode layer 110.
  • the alignment layer located above the array substrate is rubbed, for example, in the horizontal direction as shown in Fig. 3, so that the liquid crystal is initially oriented horizontally.
  • the plurality of strip-shaped pixel electrodes 101a are all parallel to each other, the gate line 102 is parallel to the strip-shaped pixel electrode 101a, the direction of the data line 103 is perpendicular to the initial orientation of the liquid crystal, and the entire second pixel electrode layer 101 has a parallelogram.
  • the strip pixel electrode 101a has a liquid crystal initial orientation of 3. ⁇ 15.
  • the angle of inclination is preferably 7. ⁇ 12. , such as 9. , 10. .
  • Such a design causes the direction of the disturbing electric field generated by the gate line 102 to coincide with the direction of the fringe field of the liquid crystal driving in the pixel unit, while the edge of the pixel electrode near the gate line 102 is parallel to the inner strip pixel electrode 101a.
  • This causes a liquid crystal alignment disorder to occur at the edge of the pixel unit without the influence of a disordered electric field, and no black streaks are generated in the vicinity of the gate line 102.
  • the width of the black matrix at the corresponding position of the color filter substrate can be reduced, and the aperture ratio and the transmittance are improved.
  • the strip-shaped pixel electrodes in the two adjacent sub-pixel structures are symmetrical with each other with respect to the data line therebetween; in the vertical direction along the initial orientation of the liquid crystal (ie, In the vertical direction in the figure, the strip-shaped pixel electrodes in two adjacent sub-pixel structures are parallel to each other.
  • the alignment layer on the array substrate is as shown in FIG. 5. Shown in the vertical direction, for example, being rubbed so that the liquid crystal is initially oriented in the vertical direction, the data line
  • the entire second pixel electrode layer 101 is in the form of a parallelogram.
  • Such a design causes the direction of the disturbing electric field generated by the data line 103 to coincide with the direction of the edge field of the liquid crystal driving in the pixel, while the edge of the pixel electrode near the data line 103 is parallel to the inner strip pixel electrode 101a.
  • This causes a liquid crystal alignment disorder to occur at the edge of the pixel unit without the influence of a disordered electric field, and no black streaks are generated in the vicinity of the data line 103.
  • the width of the black matrix at the corresponding position of the color filter substrate can be reduced, and the aperture ratio and the transmittance are improved.
  • the strip-shaped pixel electrodes in the two adjacent sub-pixel structures are symmetrical with respect to each other with respect to the grid line therebetween; in the vertical direction along the initial orientation of the liquid crystal (ie, In the horizontal direction in the figure, the strip-shaped pixel electrodes in two adjacent sub-pixel structures are parallel to each other.
  • a plurality of strip-shaped pixel electrodes 101a on the second pixel electrode layer 101 are divided into symmetrical with respect to, for example, a horizontal center line of the sub-pixel unit.
  • the two sets, the respective strip pixel electrodes 101a in each group are parallel to each other.
  • the two gate lines 102 sandwiching the sub-pixel unit are respectively parallel to a group of strip-shaped pixel electrodes 101a close to themselves in the second pixel electrode layer, so that the entire second pixel electrode layer 101 of the sub-pixel unit has a trapezoidal shape.
  • the alignment layer on the array substrate is rubbed, for example, in the horizontal direction as shown in Fig. 7, so that the liquid crystal is initially oriented horizontally.
  • Such a design causes the direction of the disturbing electric field generated by the gate line 102 to coincide with the direction of the edge field of the liquid crystal driving in the pixel, while the edge of the pixel electrode near the gate line 102 is parallel to the inner strip-shaped pixel electrode 101a.
  • This causes a liquid crystal alignment disorder to occur at the edge of the pixel unit without the influence of a disordered electric field, and no black streaks are generated in the vicinity of the gate line 102. Therefore, the width of the black matrix at the corresponding position of the color filter substrate can be reduced, and the aperture ratio and the transmittance are improved.
  • the strip-shaped pixel electrodes 101a are divided into two groups as compared with the first and second embodiments, and have a lower chromatic aberration advantage with respect to the set of strip-shaped pixel electrodes 101a.
  • the strip-shaped pixel electrodes in the two adjacent sub-pixel structures are mutually opposite to each other Symmetrical; along the vertical direction of the initial orientation of the liquid crystal (i.e., in the vertical direction in the drawing), the strip-shaped pixel electrodes in the two adjacent sub-pixel structures are parallel to each other.
  • the alignment layer located above the array substrate is rubbed, for example, in the vertical direction, so that the liquid crystal is initially oriented in the vertical direction.
  • the data line 103 is parallel to the strip pixel electrode 101a, and the direction of the gate line 102 is perpendicular to the initial orientation of the liquid crystal. Since the two strip-shaped pixel electrodes 101a are symmetrically distributed with respect to the center line in the vertical direction of the sub-pixel unit, the portions of the two data lines 103 sandwiching the sub-pixel unit corresponding to the sub-pixel unit are bent into 2 The segment is such that the entire second pixel electrode layer 101 of the sub-pixel unit has a hexagonal shape.
  • Such a design causes the direction of the disturbing electric field generated by the data line 103 to coincide with the direction of the edge field of the liquid crystal driving in the pixel, while the edge of the pixel electrode near the data line 103 is parallel to the inner strip pixel electrode 101a.
  • This causes a liquid crystal alignment disorder to occur at the edge of the pixel unit without the influence of a disordered electric field, and no black streaks are generated in the vicinity of the data line 103. Therefore, the width of the black matrix at the corresponding position of the color filter substrate can be reduced, and the aperture ratio and the transmittance are improved.
  • the strip-shaped pixel electrodes in the two adjacent sub-pixel structures are symmetrical with respect to each other with respect to the grid line therebetween; in the vertical direction along the initial orientation of the liquid crystal (ie, In the horizontal direction in the figure, the strip-shaped pixel electrodes in two adjacent sub-pixel structures are parallel to each other.
  • the present invention also provides a display device, such as a liquid crystal panel, a liquid crystal television, a mobile phone, a liquid crystal display, a digital photo frame, etc., which further includes an opposite substrate.
  • a display device such as a liquid crystal panel, a liquid crystal television, a mobile phone, a liquid crystal display, a digital photo frame, etc.
  • the opposite substrate is a color film substrate, and the color film substrate corresponds to
  • the sub-pixel unit on the array substrate is formed with a color filter sub-pixel unit for displaying pixel points of color (for example, red, green, and blue).
  • some display devices such as an electronic paper display device, do not require a color filter substrate other than the array substrate, and the opposite substrate is, for example, a transparent glass or a plastic substrate.
  • the array substrate of these display devices is any of the TFT array substrates of the above-described Embodiments 1 to 4.
  • Various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention, and therefore all equivalent technical solutions are also within the scope of the invention. It should be defined by the claims.

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Abstract

一种薄膜晶体管（TFT）阵列基板，包括子像素单元，该子像素单元包括薄膜晶体管器件、公共电极、第一像素电极层（110）和第二像素电极层（101）；第一像素电极层（110）或第二像素电极层（101）之一与公共电极连接，另一与薄膜晶体管的源极或漏极连接，第一像素电极层（110）和第二像素电极层（101）通过绝缘层隔开，第二像素电极层（101）位于第一像素电极层（110）上方；第二像素电极层（101）的条状像素电极（101a）与液晶初始取向具有倾斜角度，栅线（102）或数据线（103）与靠近自身的条状像素电极（101a）平行。在像素单元的边缘不会因为杂乱电场的影响而产生液晶取向紊乱现象。

Description

TFT阵列基板及显示设备 技术领域
本发明的实施例涉及一种薄膜晶体管 （TFT ) 阵列基板及显示设备。 背景技术
TN、 IPS, VA、 ADS是液晶显示的几种模式。 ADS是 ADSDS ( ADvanced Super Dimension Switch ) 的简称， 即高级超维场转换技术， 通过同一平面内 狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成 多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向液晶分子都能够产 生旋转， 从而提高了液晶工作效率并增大了透光效率。 高级超维场开关技术 可以提高 TFT产品的画面品质，具有高分辨率、 高透过率、低功耗、 宽视角、 高开口率、 低色差、 无挤压水波紋（push Mura )等优点。
ADS模式的 TFT液晶显示器的阵列基板制作过程中， 第一层为透明像 素电极层（通常为铟锡氧化物 （ITO ) ) , 即为上述的板状电极， 其后依次 形成有栅金属层、 源漏金属电极层、 第二层像素电极层（通常也为 ITO ) ， 该第二像素电极层即为上述的狭缝状电极。 为了说明方便， 将第二层像素电 极层中多条具有一定宽幅和间距的条状结构称为条状像素电极。 这些条状结 构和条状结构之间的开口形成了狭缝状电极。
ADS模式的 TFT像素结构一直在发生演变。 早期结构为单畴结构， 如 图 1所示。 该单畴像素结构包括： 栅线 102, 数据线 103、 第二像素电极层 101及位于第二像素电极层 101上的条状像素电极 101a和第二像素电极层的 开口 101b。栅线 102和数据线 103彼此交叉以定义了子像素单元。数据线 103 连接 TFT的漏极 103a, TFT的源极 103b与第二像素电极层 101连接。 图中 同一个子像素内条状像素电极方向一致。
后来一种两畴结构被提出。 该两畴结构中子像素可分为左右两部分， 两 部分的条状像素电极左右对称， 色差可以进一步降低。 但是， 子像素中央两 畴交界处有竖长条黑紋产生。
后来美国专利申请公开 US 2002/0041354提出了一种像素结构设计， 如 图 2所示。 该像素单元同样具有两畴结构， 分为上下两部分， 两部分的条状 像素电极上下对称， 具备低色差效果的同时减少了畴交界处的黑紋区域， 提 升了穿透特性。
但上述现有技术都未能解决像素单元边缘处的黑紋。 在 ADS模式下于 像素单元的边缘处， 由于栅线或数据线产生的扰动电场， 并且由于像素电极 边缘本身的影响，该处的电场方向与像素内部驱动液晶的边缘场方向不一致， 使得像素单元的边缘处出现液晶取向紊乱。 图 1和图 2中的 A, B分别为数 据线和栅线附近的液晶取向紊乱区域。 出现黑紋将影响显示面板的透过率和 响应速度。 为改善显示效果， 一般在对向彩膜基板上制作较宽的黑矩阵来遮 挡取向紊乱区域， 这就造成了开口率的降低， 因此降低了穿透率。 发明内容
本发明的实施例可以克服像素单元的边缘黑紋区域过多的缺点， 从而提 高开口率和穿透率。
本发明的一个方面提供了一种 TFT阵列基板， 包括： 形成在基板上的栅 线和数据线； 栅线和数据线交叉定义的子像素单元。 所述子像素单元包括薄 膜晶体管器件、 公共电极、 第一像素电极层和第二像素电极层。 所述第一像 素电极层和所述第二像素电极层之一与公共电极连接， 另一像素电极层与薄 膜晶体管的源极或漏极连接， 第一像素电极层和第二像素电极层通过绝缘层 隔开； 第二像素电极层位于第一像素电极层的上方， 第二像素电极层的条状 像素电极的图形与第一像素电极层的图形上下重叠， 所述条状像素电极与液 晶初始取向具有 3° ~15。 的倾斜角度，所述栅线或数据线与靠近自身的所述 条状像素电极平行。
对于该 TFT阵列基板， 例如， 所述倾斜角度为 3° ~15。 。
对于该 TFT阵列基板， 例如， 所述倾斜角度为 7° ~12° 。
对于该 TFT阵列基板， 例如， 所述第二像素电极层的若干条状像素电极 相互平行。 例如， 所述栅线与第二像素电极层的条状像素电极平行， 所述数 据线与所述液晶初始取向垂直。 或者， 例如， 所述数据线与第二像素电极层 的条状像素电极平行， 所述栅线与所述液晶初始取向垂直。
对于该 TFT阵列基板， 例如， 所述第二像素电极层的若干条状像素电极 分为相互对称的两组。 例如， 所述栅线与第二像素电极层中靠近自身的一组 条状像素电极平行， 所述数据线与所述液晶初始取向垂直。 或者， 例如， 数 据线的第一部分与第二像素电极层中靠近自身的一组条状像素电极平行， 数 据线的第二部分与第二像素电极层中靠近自身的另一组条状像素电极平行， 所述栅线与所述液晶初始取向垂直。
该 TFT阵列基板， 例如， 可以包括多条栅线、 多条数据线和有所述多条 栅线和多条数据线交叉定义的多个子像素单元， 沿所述液晶初始取向的方向 上， 两个邻接的子像素单元中的条状像素电极相对于之间的栅线或数据线相 互对称， 沿所述液晶初始取向的垂直方向上， 两个邻接的子像素单元中的邻 接的条状像素电极相互平行。
对于该 TFT阵列基板， 例如， 所述第一像素电极层包括板状电极。
本发明的另一方面还提供了一种显示设备， 所述显示设备中的阵列基板 为上述 TFT阵列基板。
本发明的实施例通过使栅线或数据线的方向与附近的像素电极平行， 使 得栅线或数据线的扰动电场方向与像素单元内部的边缘场的方向一致； 同时 栅线或者数据线附近的像素电极边缘与内部像素条状电极方向平行， 使得像 素单元边缘处的电场方向与像素单元内部的边缘场方向一致， 这样减少了像 素单元边缘的液晶取向紊乱区域， 提升了像素单元的开口率和穿透特性。 本 发明的实施例相对于现有技术， 并不增加工艺步骤， 既可实现更高的开口率 和穿透率， 提升了光学利用率， 降低背光源的成本及能耗， 达到更为绿色和 环保的效果。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术的 TFT阵列基板结构的示意图；
图 2为现有技术的另一种 TFT阵列基板结构示意图；
图 3为本发明实施例的一种 TFT阵列基板中子像素结构的示意图； 图 4为含有 9个图 3所示的子像素结构的阵列基板示意图； 图 5为本发明实施例的另一种 TFT阵列基板中子像素结构的示意图; 图 6为含有 9个图 5所示的子像素结构的阵列基板示意图；
图 7为本发明实施例的另一种 TFT阵列基板中子像素结构的示意图; 图 8为含有 9个图 7所示的子像素结构的阵列基板示意图；
图 9为本发明实施例的另一种 TFT阵列基板中子像素结构的示意图; 图 10为含有 9个图 9所示的子像素结构的阵列基板示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
本发明实施例的阵列基板可包括多条栅线和多条数据线， 这些栅线和数 据线彼此交叉由此限定了排列为阵列的子像素单元， 每个子像素单元包括作 为开关元件的薄膜晶体管和用于控制液晶的排列的像素电极和公共电极。 例 如， 每个像素的薄膜晶体管的栅极与相应的栅线电连接或一体形成， 源极与 相应的数据线电连接或一体形成，漏极与相应的像素电极电连接或一体形成。 下面的描述主要针对单个或多个子像素单元进行， 但是其他子像素单元可以 相同地形成。
实施例 1
如图 3所示，为本发明的一种 TFT阵列基板结构中单个子像素结构示意 图。 该阵列基板包括： 形成在基底基板（图中未示出）上的多条栅线 102和 多条数据线 103; 这些栅线 102和数据线 103彼此交叉定义了多个子像素单 元，每个子像素单元包括作为开关元件的薄膜晶体管器件以及包括公共电极、 第一像素电极层 110和第二像素电极层 101。 第一像素电极层 110如图 3中 虚线所示， 例如包括板状电极。 第二像素电极层 101上有条状像素电极 101a 和第二像素电极层 101的开口 101b。第一像素电极层 110和第二像素电极层 101 其中之一与公共电极连接， 另一像素电极层与薄膜晶体管的源极或漏极 连接， 第一像素电极层 110和第二像素电极层 101通过绝缘层隔开。 第二像 素电极层 101位于第一像素电极层 110的上方， 第二像素电极层 101的条状 像素电极 101a的图形与第一像素电极层 110的图形上下重叠。
本实施例中， 位于阵列基板之上的取向层如图 3所示在水平方向上例如 被摩擦，从而使得液晶初始取向为水平。若干条状像素电极 101a均相互平行， 栅线 102与条状像素电极 101a平行,数据线 103的方向与液晶初始取向垂直， 整个第二像素电极层 101呈平行四边形。条状像素电极 101a与液晶初始取向 具有 3。 ~15。 的倾斜角度， 优选为 7。 ~12。 ， 如 9。 、 10。 。
这样的设计使得栅线 102产生的扰动电场方向与像素单元内驱动液晶的 边缘场方向一致， 同时靠近栅线 102处的像素电极边缘与内部的条状像素电 极 101a平行。这在像素单元边缘不会杂乱电场的影响而产生液晶取向紊乱现 象， 且使得栅线 102附近没有黑紋产生。 由此， 彩膜基板对应位置处的黑矩 阵宽幅可以减少， 提升了开口率和穿透率。
如图 4所示， 为利用图 3中的 TFT像素结构制成的 TFT阵列基板， 图 中示出了 9个图 3所示的子像素结构。 沿液晶初始取向的方向上（即图中的 水平方向上） ， 两个邻接的子像素结构中的条状像素电极相对于之间的数据 线相互对称； 沿液晶初始取向的垂直方向上（即图中的垂直方向上） ， 两个 邻接的子像素结构中的条状像素电极相互平行。
实施例 2
如图 5所示， 与实施例 1不同的是， 位于阵列基板之上的取向层如图 5 所示在垂直方向上例如被摩擦， 从而使得液晶初始取向为竖直方向， 数据线
103与条状像素电极 101a平行， 栅线 102的方向与液晶初始取向垂直， 整个 第二像素电极层 101呈平行四边形。
这样的设计使得数据线 103产生的扰动电场方向与像素内驱动液晶的边 缘场方向一致， 同时靠近数据线 103处的像素电极边缘与内部的条状像素电 极 101a平行。这在像素单元边缘不会杂乱电场的影响而产生液晶取向紊乱现 象， 且使得数据线 103附近没有黑紋产生。 由此， 彩膜基板对应位置处的黑 矩阵宽幅可以减少， 提升了开口率和穿透率。
如图 6所示， 为利用图 5中的 TFT像素结构制成的阵列基板， 图中示出 了 9个图 5所示的子像素结构。 沿液晶初始取向的方向上（即图中的垂直方 向上） ， 两个邻接的子像素结构中的条状像素电极相对于之间的栅线相互对 称； 沿液晶初始取向的垂直方向上（即图中的水平方向上） ， 两个邻接的子 像素结构中的条状像素电极相互平行。
实施例 3
如图 7所示， 与实施例 1不同的是， 每个子像素单元之中， 第二像素电 极层 101上的若干条状像素电极 101a被分为相对于例如该子像素单元的水平 中心线对称的两组，每一组中各自的条状像素电极 101a彼此平行。夹住该子 像素单元的两条栅线 102分别与第二像素电极层中靠近自身的一组条状像素 电极 101a平行， 从而该子像素单元的整个第二像素电极层 101呈梯形。
本实施例中， 位于阵列基板之上的取向层如图 7所示在水平方向上例如 被摩擦， 从而使得液晶初始取向为水平。
这样的设计使得栅线 102产生的扰动电场方向与像素内驱动液晶的边缘 场方向一致， 同时靠近栅线 102 处的像素电极边缘与内部的条状像素电极 101a平行。 这在像素单元边缘不会杂乱电场的影响而产生液晶取向紊乱现 象， 且使得栅线 102附近没有黑紋产生。 因此， 彩膜基板对应位置处的黑矩 阵宽幅可以减少， 提升了开口率和穿透率。 与实施例 1和 2相比， 将条状像 素电极 101a分为两组，相对于一组条状像素电极 101a具有更低色差的优势。
如图 8所示， 为利用图 7中的 TFT像素结构制成的阵列基板， 图中示出 了 9个图 7所示的子像素结构。 沿液晶初始取向的方向上（即图中的水平方 向上） ， 两个邻接的子像素结构中的条状像素电极相对于之间的数据线相互 对称； 沿液晶初始取向的垂直方向上（即图中的垂直方向上） ， 两个邻接的 子像素结构中的条状像素电极相互平行。
实施例 4
如图 9所示， 与实施例 3不同的是， 位于阵列基板之上的取向层在垂直 方向上例如被摩擦， 从而使得液晶初始取向为竖直方向。 数据线 103与条状 像素电极 101a平行，栅线 102的方向与液晶初始取向垂直。 由于两组条状像 素电极 101a相对于子像素单元的垂直方向上的中心线对称分布，所以夹住该 子像素单元的两条数据线 103对应于该子像素单元的部分被弯折成了 2段， 使得该子像素单元的整个第二像素电极层 101呈六边形。
这样的设计使得数据线 103产生的扰动电场方向与像素内驱动液晶的边 缘场方向一致， 同时靠近数据线 103处的像素电极边缘与内部的条状像素电 极 101a平行。这在像素单元边缘不会杂乱电场的影响而产生液晶取向紊乱现 象， 且使得数据线 103附近没有黑紋产生。 因此， 彩膜基板对应位置处的黑 矩阵宽幅可以减少， 提升了开口率和穿透率。
如图 10所示， 为利用图 9中的 TFT像素结构制成的阵列基板， 图中示 出了 9个图 9所示的子像素结构。 沿液晶初始取向的方向上（即图中的垂直 方向上） ， 两个邻接的子像素结构中的条状像素电极相对于之间的栅线相互 对称； 沿液晶初始取向的垂直方向上（即图中的水平方向上） ， 两个邻接的 子像素结构中的条状像素电极相互平行。
实施例 5
本发明还提供了一种显示设备， 比如液晶面板、 液晶电视、 手机、 液晶 显示器、 数码相框等， 其还包括对置基板， 该对置基板的一个示例为彩膜基 板， 彩膜基板上对应于阵列基板上的子像素单元形成有滤色器子像素单元， 用于显示彩色 （例如红、 绿和蓝色） 的像素点。 但是， 有一些显示设备， 比 如电子纸显示装置除阵列基板之外并不需要彩膜基板， 对置基板例如为透明 玻璃或塑料基板。
这些显示设备的阵列基板为上述实施例 1~4的 TFT阵列基板中任一种。 有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下， 还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴， 本发明的专利保护范围应由权利要求限定。

Claims

权利要求书
1、 一种薄膜晶体管 （TFT ) 阵列基板， 包括：
形成在基板上的栅线和数据线， 栅线和数据线交叉定义的子像素单元， 其中，
所述子像素单元包括薄膜晶体管器件、 公共电极、 第一像素电极层和第 二像素电极层； 其中，
所述第一像素电极层和所述第二像素电极层之一与公共电极连接， 另一 像素电极层与薄膜晶体管的源极或漏极连接， 第一像素电极层和第二像素电 极层通过绝缘层隔开；
第二像素电极层位于第一像素电极层的上方， 第二像素电极层的条状像 素电极的图形与第一像素电极层的图形上下重叠；
所述条状像素电极与液晶初始取向具有倾斜角度， 所述栅线或数据线与 靠近自身的所述条状像素电极平行。
2、 根据权利要求 1所述的 TFT阵列基板， 其中， 所述倾斜角度为 3。
~15。 。
3、 根据权利要求 2所述的 TFT阵列基板， 其中， 所述倾斜角度为 7。
~12。 。
4、 根据权利要求 1所述的 TFT阵列基板， 其中， 所述第二像素电极层 的若干条状像素电极相互平行。
5、 根据权利要求 4所述的 TFT阵列基板， 其中， 所述栅线与第二像素 电极层的条状像素电极平行， 所述数据线与所述液晶初始取向垂直。
6、 根据权利要求 4所述的 TFT阵列基板， 其中， 所述数据线与第二像 素电极层的条状像素电极平行， 所述栅线与所述液晶初始取向垂直。
7、 根据权利要求 1所述的 TFT阵列基板， 其中， 所述第二像素电极层 的若干条状像素电极分为相互对称的两组。
8、 根据权利要求 7所述的 TFT阵列基板， 其中， 所述栅线与第二像素 电极层中靠近自己的一组条状像素电极平行， 所述数据线与所述液晶取向垂 直。
9、 根据权利要求 7所述的 TFT阵列基板， 其中， 数据线的第一部分与 第二像素电极层中靠近自身的一组条状像素电极平行， 数据线的第二部分与 第二像素电极层中靠近自身的另一组条状像素电极平行， 所述栅线与所述液 晶取向垂直。
10、 根据权利要求 1所述的 TFT阵列基板， 包括多条栅线、 多条数据线 和有所述多条栅线和多条数据线交叉定义的多个子像素单元， 其中， 沿所述 液晶初始取向的方向上， 两个邻接的子像素单元中的条状像素电极相对于之 间的栅线或数据线相互对称， 沿所述液晶初始取向的垂直方向上， 两个邻接 的子像素单元中的邻接的条状像素电极相互平行。
11、 根据权利要求 1所述的 TFT阵列基板， 其中， 所述第一像素电极层 包括板状电极。
12、 一种显示设备， 包括权利要求 1所述的 TFT阵列基板。
PCT/CN2012/084335 2011-11-15 2012-11-08 Tft阵列基板及显示设备 WO2013071840A1 (zh)

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