WO2013057857A1

WO2013057857A1 - Boost rectifier circuit system

Info

Publication number: WO2013057857A1
Application number: PCT/JP2012/004585
Authority: WO
Inventors: 修二玉岡
Original assignee: パナソニック株式会社
Priority date: 2011-10-19
Filing date: 2012-07-18
Publication date: 2013-04-25
Also published as: JP2015006012A

Abstract

A boost rectifier circuit (50) is provided with: a first circuit (50a) which includes switching elements (51, 52, 53, 54, 55, 56, 65) and is connected to the output end of an alternating-current power source (1); a reactor (61) which is connected to the output end of the first circuit (50a); a second circuit (50b) which includes switching elements (57, 58, 59) and is connected to the reactor (61); and a third circuit (50c) which is connected to the second circuit (50b). A rectification control circuit (200) switches the current path of the second circuit (50b) when the boost rectifier circuit (50) operates by using a single-rectification method and when the boost rectifier circuit operates by using a double-rectification method, causes switching elements (51, 52) in the first circuit (50a) to perform switching operations when the boost rectifier circuit (50) performs a step-down operation, and causes switching elements (57, 58) in the second circuit (50b) to perform switching operations when the boost rectifier circuit performs a step-up operation.

Description

Buck-boost rectifier circuit system

The present invention relates to a step-up / step-down rectifier circuit system, and more particularly to a technique for widely varying an output voltage.

Conventionally, a rectifier circuit has been proposed in which the output voltage is variable by combining the operation by the single rectification method, the operation by the double rectification method, and the boosting operation (see Patent Document 1).

接続 By connecting this rectifier circuit to an inverter, the inverter can be driven by a PAM (Pulse Amplitude Modulation) method.

For an inverter used to drive a three-phase motor, the current to be supplied to the motor is higher when the motor speed is in the low speed range than when the motor speed is in the high speed range.・ The voltage may be small. Here, if the inverter is driven by the PAM method, the input voltage to the inverter can be reduced as the output current / voltage of the inverter is reduced according to the rotational speed of the motor. The switching loss can be reduced.

An example of a motor drive system using an inverter driven by the PAM method is shown in FIG.

As shown in FIG. 18, the motor drive system includes an inverter 1003 for driving the motor 1004 and a boost rectifier circuit 1050 that supplies a DC voltage to the inverter 1003. Here, the boost rectifier circuit 1050 has a reactor L1 having one end connected to the output end of the AC power supply 1001, and a rectifier circuit 1051 connected between the other end of the reactor L1 and the output end of the AC power supply 1001. And a bidirectional switch circuit 1002 connected between the input terminals of the rectifier circuit 1051. Here, the rectifier circuit 1051 includes a diode bridge composed of diodes D1 to D4, a capacitor C3 connected between the output ends of the diode bridge, and a series circuit composed of capacitors C1 and C2 connected in parallel to the capacitor C3; A switch SW1 connected between the connection point of the capacitors C1 and C2 and the input terminal of the diode bridge is provided. The bidirectional switch circuit 1002 includes a diode bridge composed of diodes D5 to D8 and a switching element Q1. The step-up rectifier circuit 1050 performs a step-up operation when the switching element Q1 of the bidirectional switch 1002 performs a switching operation.

Next, the operation of the step-up rectifier circuit 1050 will be described in relation to the rotation speed of the motor 1004.

FIG. 19 shows the relationship between the rotation speed of the motor 1004 and the output voltage (input voltage to the inverter 1003) Vi of the step-up rectifier circuit 1050. In FIG. 19, the rectification operation of the step-up rectifier circuit is switched between a low rotation area where the rotation speed of the motor 1004 is around 60 rps and a high rotation area where the rotation speed is around 120 rps.

When the rotation speed of the motor 1004 is in the high rotation region, the boost rectifier circuit 1050 performs a boost operation in a state where the switch SW1 is closed (a state in which the double rectification operation is performed), and the voltage Vi is between 220V and 280V. It changes in accordance with the number of revolutions 1004 (see the portion surrounded by the one-dot chain line B1 in FIG. 19).

On the other hand, when the rotation speed of the motor 1004 is in the low rotation range, the boost rectifier circuit 1050 performs a boost operation with the switch SW1 open (a state in which normal rectification operation is performed), and the voltage Vi is between 105V and 140V. Thus, it changes in accordance with the number of revolutions of the motor 1004 (see the portion surrounded by the one-dot chain line B2 in FIG. 19).

As described above, the boost rectifier circuit 1050 reduces the switching loss in the switching element of the inverter 1003 by the PAM-type inverter control in which the input voltage to the inverter 1003 is set to the minimum necessary level according to the rotational speed of the motor 1004. This can reduce power consumption in the motor drive system.

JP 2001-95262 A

By the way, when the motor 1004 starts to move from a stopped state, the motor 1004 may be driven in a rotation region lower than the low rotation region (see the region surrounded by the one-dot chain line B2 in FIG. 19).

However, since the step-up rectifier circuit 1050 having the configuration shown in FIG. 18 can only perform a step-up operation, the input voltage to the inverter 1003 (the output voltage of the step-up rectifier circuit 1050) in the rotation range lower than the low rotation range of the motor 1004. Cannot be set to the minimum necessary voltage according to the rotation speed of the motor 1004. Therefore, in this rotational range, the input voltage to the inverter 1003 must be set to a value larger than necessary, and the switching loss in the switching element of the inverter 1003 cannot be reduced. That is, the variable range of the input voltage to the inverter 1003 (the output voltage of the step-up rectifier circuit 1050) is smaller than the input voltage range corresponding to the entire rotation range of the motor 1004. Therefore, depending on the rotation range of the motor 1004, In some cases, the input voltage to the inverter 1003 cannot be set to the minimum necessary voltage according to the number of revolutions of the motor 1004, and the switching loss in the switching element of the inverter 1003 cannot be sufficiently reduced.

The present invention has been made in view of the above reasons, and is to provide a step-up / step-down rectifier circuit in which the variable range of the output voltage is expanded.

In order to achieve the above object, a buck-boost rectifier circuit system according to the present invention is a buck-boost rectifier circuit system comprising a buck-boost rectifier circuit and a rectification control circuit for controlling the buck-boost rectifier circuit. The pressure type rectifier circuit includes a plurality of dual gate type switching elements, a first circuit connected to the output end of the AC power supply, a reactor connected to the output end of the first circuit, and at least two single gate type A second circuit including a switching element and at least one dual-gate switching element and connected to the reactor, and a third circuit including at least two capacitors and connected to the second circuit, and rectifying control The circuit is different between the first circuit and the second circuit when the step-up / step-down rectifier circuit operates in the single rectification method and the double rectification method. When the step-down operation is performed by switching the flow path and the buck-boost rectifier circuit storing the energy in the reactor and releasing the energy stored in the reactor, the two switching elements included in the first circuit are alternately turned on and off. When the step-up operation is performed by storing the energy in the reactor and releasing the energy stored in the reactor, the two single-gate switching elements included in the second circuit are alternately switched. A control signal is input to the gates of the switching elements included in the first circuit and the second circuit so that the switching operation is repeated in a manner of repeatedly turning on and off.

According to this configuration, the step-up / step-down rectifier circuit is operated by the single rectification method and the double rectification method, and the boost operation is performed when the single rectification method and the double rectification method are operated. Since the step-down operation can be performed, the variable range of the output voltage of the step-up / step-down rectifier circuit can be expanded. Further, if the step-up / step-down rectifier circuit is connected to the inverter, the input voltage from the step-up / step-down rectifier circuit to the inverter can be changed in a wide voltage range, so that the inverter is driven while being driven by the PAM method. The variable range of voltage can be expanded.

In the step-up / step-down rectifier circuit system according to the present invention, the step-up / step-down rectifier circuit further includes at least two capacitors and is connected to the second circuit to smooth the output from the second circuit. A bridge circuit including dual gate type first, second, third, and fourth switching elements, and a first output terminal and an input terminal of the bridge circuit. Connection between a dual gate type fifth switching element and a sixth switching element connected in series between the first output terminal of the bridge circuit and a series circuit including the fifth switching element and the sixth switching element on one end side A dual gate type seventh switching element connected to the point, and the second circuit is between the other end side of the seventh switching element and the second output end of the bridge circuit. A single-gate eighth switching element and a ninth switching element connected in series; a dual-gate tenth switching element having one end connected to a connection point between the eighth switching element and the ninth switching element; A first capacitor connected between both ends of the series circuit including the eighth switching element and the ninth switching element, one end side of the first capacitor, and the other end of the tenth switching element. A second capacitor connected between the first capacitor and a third capacitor connected between the other end side of the first capacitor and the other end side of the tenth switching element. It is connected to the connection point between the fifth switching element and the sixth switching element, and the other end side is connected to the eighth switching element and the ninth switching element. Or it may be formed by connecting the point.

In the step-up / step-down rectifier circuit system according to the present invention, the fifth and sixth switching elements are single-gate FETs, and the first to fourth and seventh to tenth switching elements are two single gates. It may be a dual gate FET formed by connecting the drains of a type FET.

According to this configuration, since the bridge circuit is configured by the dual gate FET, power loss in the bridge circuit can be reduced as compared with the case where the bridge circuit is configured by only the diode.

In the step-up / step-down rectifier circuit system according to the present invention, the single gate FET is provided with a semiconductor layer stack made of a nitride semiconductor formed on a semiconductor substrate and a semiconductor layer stack spaced apart from each other. The heterojunction field effect transistor may include a drain terminal and a source terminal, and a gate terminal provided between the drain terminal and the source terminal.

According to this configuration, since there is no minority carrier accumulation effect and there is little recovery current and tail current at turn-off, switching loss during switching operation can be reduced, and power consumption can be reduced. Further, according to this configuration, since the on-resistance is small and the conduction loss can be reduced, the power consumption can be reduced.

In the step-up / step-down rectifier circuit system according to the present invention, the dual gate FET is provided with a semiconductor layer stack made of a nitride semiconductor formed on a semiconductor substrate and a semiconductor layer stack spaced apart from each other. And a first output terminal and a second output terminal, and a first gate terminal and a second gate terminal which are provided separately between the first output terminal and the second output terminal. .

According to this configuration, there is no minority carrier accumulation effect, and there is no recovery current or tail current at turn-off, so that switching loss during switching operation can be reduced, and power consumption can be reduced. In addition, since the on-resistance is small and conduction loss can be reduced, power consumption can be reduced. Furthermore, the size can be reduced as compared with a configuration in which the drains of two single gate FETs are connected to each other.

In the step-up / step-down rectifier circuit system according to the present invention, the control signal may be a signal having a pulse train-like time waveform.

According to this configuration, the step-up / step-down rate can be continuously changed by continuously changing the pulse width of the control signal. Therefore, if the step-up / step-down rectifier circuit is connected to the inverter, The input voltage can be continuously changed. Therefore, it is possible to continuously change the output voltage of the inverter connected to the step-up / step-down rectifier circuit while performing PAM control.

The present invention also includes a first circuit including a plurality of dual gate type switching elements and connected to an output terminal of an AC power source, a reactor connected to the first circuit, and at least one single gate type switching element. A step-up / step-down rectifier circuit including a second circuit connected to the reactor, and a third circuit including at least two capacitors and connected to the second circuit. Also good.

According to this configuration, the current path can be switched between the single rectification method and the double rectification method, but the step-up rate is continuously increased by switching the at least one switching element included in the second circuit. The step-up operation can be performed by changing the step-down rate, and the step-down operation can be performed by continuously changing the step-down rate by switching the at least one switching element included in the first circuit. Therefore, by connecting to the inverter, the input voltage to the inverter can be continuously changed over a wide voltage range. Therefore, it is possible to continuously change the output voltage in a wide voltage range while performing PAM control for the inverter to which the buck-boost rectifier circuit is connected.

According to the present invention, the first circuit includes a bridge circuit including dual gate type first, second, third, and fourth switching elements, and a first output terminal and an input terminal of the bridge circuit. And a connection point between a fifth switching element and a sixth switching element of a dual gate type connected in series with each other, and a series circuit having one end side of the first output terminal of the bridge circuit and the fifth switching element and the sixth switching element A single gate connected in series between the other end side of the seventh switching element and the second output end of the bridge circuit. Type eighth switching element and ninth switching element, and a dual gate having one end connected to a connection point between the eighth switching element and the ninth switching element. A first capacitor connected between both ends of a series circuit composed of an eighth switching element and a ninth switching element, and one end side of the first capacitor. And a second capacitor connected between the other end side of the tenth switching element and a third capacitor connected between the other end side of the first capacitor and the other end side of the tenth switching element. The reactor has one end connected to a connection point between the fifth switching element and the sixth switching element, and the other end connected to a connection point between the eighth switching element and the ninth switching element. A step-up / step-down rectifier circuit may be used.

1 is a circuit block diagram of a motor drive system according to Embodiment 1. FIG. FIG. 4 is an IV characteristic diagram of the single gate type switching element according to the first embodiment. FIG. 5 is an operation explanatory diagram of the single gate type switching element according to the first embodiment. 1 is a cross-sectional view of a single gate type switching element according to a first embodiment. FIG. 6 is an operation explanatory diagram of the dual gate type switching element according to the first embodiment. 1 is a cross-sectional view of a dual gate type switching element according to a first embodiment. 3 is a time chart illustrating an operation of a switching element constituting the step-up / step-down rectifier circuit according to the first embodiment. FIG. 4 is an operation explanatory diagram of the step-up / step-down rectifier circuit according to the first embodiment. 3 is a time chart illustrating an operation of a switching element constituting the step-up / step-down rectifier circuit according to the first embodiment. FIG. 4 is an operation explanatory diagram of the step-up / step-down rectifier circuit according to the first embodiment. 3 is a time chart illustrating an operation of a switching element constituting the step-up / step-down rectifier circuit according to the first embodiment. FIG. 4 is an operation explanatory diagram of the step-up / step-down rectifier circuit according to the first embodiment. It is a figure which shows the relationship between the rotation speed of the motor in the buck-boost type rectifier circuit which concerns on Embodiment 1, and the input voltage to an inverter. 6 is a time chart showing an operation of a switching element constituting the step-up / step-down rectifier circuit according to Embodiment 2. FIG. 10 is an operation explanatory diagram of the step-up / step-down rectifier circuit according to the second embodiment. It is a figure which shows the relationship between the rotation speed of the motor in the buck-boost type rectifier circuit which concerns on Embodiment 2, and the input voltage to an inverter. It is a figure which shows the relationship between the rotation speed of the motor in the buck-boost type rectifier circuit which concerns on a modification, and the input voltage to an inverter. It is a circuit block diagram of the motor drive system which concerns on a prior art example. It is a figure which shows the relationship between the rotation speed of the motor in the motor drive system which concerns on a prior art example, and the input voltage to an inverter.

<Embodiment 1>
<1> Configuration FIG. 1 is a circuit block diagram showing a motor drive system according to the present embodiment.

As shown in FIG. 1, the motor drive system is a system that receives power supply from an AC power supply 1 and drives a three-phase motor 4.

This motor drive system includes a step-up / step-down rectifier circuit 50 that rectifies the alternating current supplied from the AC power supply 1 by a single rectification operation or a double rectification operation, a rectification control circuit 200 that controls the step-up / step-down rectifier circuit 50, and a step-up / step-down type. An inverter circuit 3 that converts a DC voltage input from the rectifier circuit 50 into a three-phase pulse train voltage and inputs the voltage to the motor 4, an inverter control circuit 41 that controls the operation of the inverter circuit 3, a rectifier control circuit 200, And a control instruction circuit 40 for instructing the inverter control circuit 41 of control contents. Here, the AC power source 1 is, for example, a power source that outputs AC with a frequency of 60 Hz.

<1-1> Inverter Circuit The inverter circuit 3 is a three-phase output inverter and includes six switching

elements

31, 32, 33, 34, 35, and 36. The inverter circuit 3 changes the magnitudes of the output current and the output voltage according to the rotation speed of the motor 4.

Here, between the magnitude Io and the magnitude Vo of the output voltage of the inverter circuit 3 and the magnitude of the input voltage Vi (denoted as Vdc in FIG. 1) to the inverter circuit 3, the formula (1) And the relationship of Formula (2) is materialized.

Here, Io is the magnitude of the output current of the inverter circuit 3, Vo is the magnitude of the output voltage of the inverter circuit 3, Vi is the magnitude of the input voltage to the inverter circuit 3, and Duty is the switching element 31. , 32, 33, 34, 35, and 36, the modulation rate (duty ratio) of the signal PWM having a pulse train-like time waveform input to the gate. The on-duty ratio of the signal PWM input to the gates of the switching

elements

31, 32, 33, 34, 35, and 36 is the same.

The inverter circuit 3 of the present embodiment is driven by a PAM (Pulse Amplitude Modulation) method. This will be described using equations (1) and (2). In the expressions (1) and (2), Io and Vo are AC waveforms. This AC waveform is generated by changing the duty of PWM drive in accordance with the AC cycle. In PAM driving, PWM is driven so that the maximum value of the duty is fixed to 100%, and the amplitude Vo of the AC output voltage of the inverter circuit 3 is changed by changing the magnitude Vi of the input voltage to the inverter circuit 3. The amplitude Io of the AC output current is changed.

<1-2> Inverter Control Circuit The inverter control circuit 41 is based on the motor rotation speed designation signal Nrm input from the control instruction circuit 40, and the

switching elements

31, 32, 33, 34, and 35 that constitute the inverter circuit 3. , 36, the frequency is adjusted while fixing the maximum duty ratio of the PWM signal inputted to the gates to 100%. Specifically, when the motor rotation speed designation signal Nrm increases, the frequency of the PWM signal is increased and the input voltage Vi is increased so that the amplitude of the AC output voltage Vo or the AC output current Io is increased. When the motor rotation speed designation signal Nrm decreases, the frequency of the PWM signal is decreased and the input voltage Vi is decreased so that the amplitude of the AC output voltage Vo or the AC output current Io is decreased. As a result, when the frequency of the PWM signal increases, the rotational speed of the motor 4 increases, and when the frequency of the PWM signal decreases, the rotational speed of the motor 4 decreases.

<1-3> Control Instruction Circuit The control instruction circuit 40 inputs the motor rotation speed designation signal Nrm to the inverter control circuit 41, and also inputs the direct current input from the step-up / step-down rectifier circuit 50 to the inverter circuit 3 to the rectification control circuit 200. A voltage instruction signal VdcIN that indicates the magnitude of the voltage is input. This voltage instruction signal VdcIN indicates the magnitude of the voltage input from the step-up / step-down rectifier circuit 50 to the inverter circuit 3, and it is several% to several% of the target value of the output voltage of the step-up / step-down rectifier circuit 50. The size is 10%. Note that the target value of the output voltage of the step-up / step-down rectifier circuit 50 is an optimum value when the motor 4 rotates at the rotation speed designated by the motor rotation speed designation signal Nrm when the inverter circuit 3 is driven by the PAM method. Equivalent to.

Further, the control instruction circuit 40 inputs a rectification method switching signal Rectsw for switching the rectification method between the single rectification method and the double rectification method to the rectification control circuit 200. This rectification method switching signal Rectsw instructs whether the step-up / step-down rectifier circuit 50 is operated by the single rectification method or the double rectification method.

<1-4> Step-up / step-down rectifier circuit The step-up / step-down rectifier circuit 50 performs a one-fold rectification operation or a double rectification operation as well as a step-up / step-down operation under the control of the rectification control circuit 200. The magnitude of the DC voltage input to the inverter 3 changes according to the rotation speed of the motor 4. Thereby, the inverter 3 can be driven by the PAM method.

As shown in FIG. 1, the step-up / step-down rectifier circuit 50 includes a first circuit 50a connected to the AC power supply 1, a reactor 61 connected to the first circuit 50a, and a second circuit 50b connected to the reactor 61. And a third circuit 50c connected to the second circuit 50b.

The first circuit 50a includes a bridge circuit composed of four dual gate

type switching elements

51, 52, 53, 54, a first output terminal (the upper output terminal in FIG. 1) and an input terminal of the bridge circuit. Two

dual-gate switching elements

55 and 56 connected between each other, and a dual-gate switching element 65 whose one end is connected to a connection point between the first output terminal of the bridge circuit and the switching element 56, Have

The second circuit 50b includes two single-gate switching elements 57, which are connected in series between the other end side of the switching element 65 and the second output end (lower output end in FIG. 1) of the bridge circuit. 58 and a dual gate type switching element 59 having one end connected to a connection point between the two switching

elements

57 and 58.

The third circuit 50 c is a smoothing circuit, and is connected between both ends of a series circuit composed of two switching

elements

57 and 58, and between one end side of the capacitor 64 and the other end side of the switching element 59. And a capacitor 63 connected between the other end side of the capacitor 64 and the other end side of the switching element 59.

Reactor 61 has one end connected to a connection point between two switching

elements

55 and 56 and the other end connected to a connection point between two switching

elements

57 and 58.

Further, a current sensor 60 for detecting the magnitude of a current flowing through the reactor 61 (hereinafter referred to as “reactor current”) is interposed between the reactor 61 and the switching element 55. As will be described later, the current sensor 60 is for the rectification control circuit 200 to control the step-up / step-down rectifier circuit 50 by PFC (Power Factor Correction).

<1-4-1> Single Gate Type Switching Element The single gate type switching element 57 is composed of an FET, and has the current-voltage characteristics (IV characteristics) shown in FIGS. 2 (a) to 2 (c). have. Here, the drain voltage based on the source voltage is VDS, and the current flowing from the drain to the source at this time is IDS. Note that the single gate type switching element 58 is the same as the switching element 57, and thus the description thereof is omitted.

When the gate-source voltage Vgs is higher than a predetermined threshold voltage Vth, as shown in FIGS. 2A and 2B, the IV characteristics of the switching element 57 include a so-called triode region and saturation region. Appears. Here, the triode region is a region where the IV characteristic is linear, that is, a region where the current IDS and the voltage VDS are in a substantially direct relationship (in FIGS. 2A and 2B). A region surrounded by an alternate long and short dash line A1). Since the characteristic in the triode region is linear similar to the IV characteristic, it can be regarded as resistance as long as the switching element 57 operates in the triode region. The slope of the straight line representing the IV characteristic corresponds to the resistance value Ron. Hereinafter, the IV characteristics of the switching element 57 in a state where the drain voltage is higher than the source voltage and current flows from the drain to the source as shown in FIG. The IV characteristic of the switching element 57 in a state where the drain voltage is lower than the source voltage and the current flows from the source to the drain as shown in b) is referred to as an inverse FET characteristic.

On the other hand, the saturation region is a region where the current IDS hardly changes even when the voltage VDS changes.

When the gate-source voltage Vgs is lower than the threshold voltage Vth, as shown in FIG. 2C, the IV characteristic of the switching element 57 indicates that the source voltage is higher than the drain voltage (Vth−Vgs). A region where the current from the source to the drain is interrupted until it becomes high appears. Here, in the switching element 57, even when the gate-source voltage Vgs is lower than the predetermined threshold voltage Vth, the gate voltage is higher than the drain voltage, and the voltage (Vgs−VDS) is a predetermined voltage. If it is higher than the threshold voltage Vth, the current IDS flows from the source to the drain. Thereafter, as shown in FIG. 2C, when the source voltage becomes higher than the drain voltage (Vth−Vgs) by more than the voltage (Vth−Vgs), the IV characteristic of the switching element 57 in which a current flows from the source to the drain is reversed conduction characteristic. Called. Here, regarding the switching element 57, when the gate-source voltage Vgs is 0V, that is, when the gate and the source are short-circuited, the source side is the anode, the drain side is the cathode, and the forward voltage is the threshold voltage Vth. This is the same as the IV characteristic of the diode (see the region surrounded by the one-dot chain line A2 in FIG. 2C).

Here, as shown in FIG. 3 (a-1), the state where the ON signal “High” is inputted to the gate of the switching element 57 is as shown in FIG. 3 (a-2). This corresponds to a state in which the voltage Vgs is larger than the threshold voltage Vth, and can be regarded as equivalent to the resistor Ron. Hereinafter, the state shown in FIG. 3A-1 is referred to as a “conduction mode”.

As shown in FIG. 3 (b-1), the state in which the OFF signal “Low” is input to the gate of the switching element 57 is the voltage Vgs between the gate and the source as shown in FIG. 3 (b-2). Can be regarded as equivalent to a diode having a source as an anode and a drain as a cathode. Hereinafter, the state shown in FIG. 3B-1 is referred to as “reverse conduction mode”.

Next, the structure of the switching element 57 will be described.

The switching element 57 is a normally-off type heterojunction FET. As shown in FIG. 4, the switching element 57 is a silicon substrate 301, a buffer layer 302 stacked on the silicon substrate 301, and a nitride semiconductor formed on the buffer layer 302. A semiconductor layer stack 303 including layers, electrodes 306a and 306b provided in the semiconductor layer stack 303, wirings 310 electrically connected to the electrodes 306a and 306b, and electrodes 306a and 306a in the semiconductor stack 303, respectively. A control layer 309 for controlling the characteristics of the switching element 57, a gate electrode 308 formed on the control layer 309, and a protective film 307 are provided between 306b.

Here, the buffer layer 302 is formed by alternately laminating aluminum nitride and gallium nitride.

The semiconductor layer stack 303 is composed of an undoped gallium nitride layer 304 and an n-type aluminum gallium nitride layer 305 stacked on the gallium nitride layer 304, and between the gallium nitride layer 304 and the aluminum gallium nitride layer 305. A heterointerface is formed. In the vicinity of this hetero interface, a region having a high carrier concentration called a two-dimensional electron gas is formed and becomes a channel region of the single gate type switching element 57.

The electrodes 306a and 306b are formed in a portion of the semiconductor layer stack 303 where the gallium nitride layer 304 is exposed, and are in ohmic contact with the gallium nitride layer 304. The electrodes 306a and 306b function as a source terminal and a drain terminal of the single gate type switching element 57.

The control layer 309 is made of a p-type semiconductor layer and is formed on the aluminum gallium nitride layer 305.

The gate electrode 308 is in ohmic contact with the control layer 309.

As shown in FIG. 4, in the switching element 57, the distance from the electrode 306b functioning as the drain terminal to the gate electrode 308 is longer than the distance from the electrode 306a functioning as the source terminal to the gate electrode 308. This is because the breakdown voltage required between the drain and the gate is larger than the breakdown voltage required between the source and the gate.

The switching element 57 formed using a nitride semiconductor described above is called a so-called GaN transistor, and can be driven with a high current with a high breakdown voltage like an IGBT, for example. The switching element 57 has no offset voltage unlike the IGBT, has FET characteristics and reverse FET characteristics as shown in FIGS. 2A and 2B, and is a chip that constitutes the switching element 57. The on-resistance value Ron with respect to the area is very small.

<1-4-2> Dual Gate Type Switching Element The dual gate type switching element 51 is formed by connecting the drains of two FETs. The dual gate

type switching elements

52, 53, 54, 55, 56, 59, and 65 are the same as the switching element 51, and thus description thereof is omitted.

Here, as shown in FIG. 5 (a-1), the state where the ON signal “High” is inputted to the gates “A” and “B” of the switching element 51 is shown in FIG. 5 (a-2). As described above, this corresponds to a state in which the gate-source voltage Vgs of both two FETs is larger than the threshold voltage Vth, and can be regarded as equivalent to a circuit formed by connecting two resistors Ron in series. Hereinafter, the state shown in FIG. 5A-1 is referred to as a “conduction mode”. In this case, the switching element 51 can flow current in both directions.

As shown in FIG. 5 (b-1), the state where the ON signal “High” is input to the gate “A” of the switching element 57 and the OFF signal “Low” is input to the gate “B” is shown in FIG. As shown in (b-2), the gate-source voltage Vgs of the FET on the gate “A” side is larger than the threshold voltage, and the gate-source voltage Vgs of the gate “B” -side FET is 0V. It corresponds to a certain state and can be regarded as equivalent to a circuit comprising a diode and a resistor Ron connected to the cathode of the diode. Hereinafter, the state shown in FIG. 5B-1 is referred to as “reverse conduction mode 1”. In this case, the switching element 51 can flow a current (current flowing upward in FIG. 5) from the off-state FET to the on-state FET side, but cannot flow a current in the reverse direction.

As shown in FIG. 5C-1, the state where the off signal “Low” is inputted to the gate “A” of the switching element 57 and the on signal “High” is inputted to the gate “B” is shown in FIG. As shown in (c-2), the gate-source voltage Vgs of the FET on the gate “A” side is 0 V, and the gate-source voltage Vgs of the gate “B” -side FET is greater than the threshold voltage Vth. Can be regarded as being equivalent to a circuit comprising a diode and a resistor Ron connected to the cathode of the diode. Hereinafter, the state shown in FIG. 5C-1 is referred to as “reverse conduction mode 2”. In this case, the switching element 51 can flow a current (current flowing downward in FIG. 5) from the off-state FET to the on-state FET side, but cannot flow a current in the reverse direction.

As shown in FIG. 5D-1, the state where the OFF signal “Low” is input to the gate “A” of the switching element 57 and the OFF signal “Low” is input to the gate “B” is as shown in FIG. As shown in (d-2), this corresponds to a state where the gate-source voltage Vgs of both two FETs is 0 V, and is regarded as equivalent to a circuit formed by connecting the cathodes of two diodes. Can do. Hereinafter, the state shown in FIG. 5B-1 is referred to as a “cut-off mode”. In this case, no current can flow through the switching element 51.

Next, the structure of the switching element 51 will be described.

The switching element 51 is formed by connecting drains of normally-off type heterojunction FETs. As shown in FIG. 6, the switching element 51 includes a silicon substrate 311, a buffer layer 312 stacked on the silicon substrate 311, and a buffer layer. A semiconductor layer stack 313 composed of a nitride semiconductor layer formed on 312;

electrodes

316a and 316b provided on the semiconductor layer stack 313; and a wiring 320 electrically connected to each of the

electrodes

316a and 316b; The first control layer 319a and the second control layer 319b provided between the

electrodes

316a and 316b in the semiconductor stacked body 313 for controlling the characteristics of the switching element 51, and the gate formed on the first control layer 319a A gate formed on the electrode 318a and the second control layer 319b. Comprising an electrode 318b, and a protective film 317.

Here, the buffer layer 312 is formed by alternately laminating aluminum nitride and gallium nitride.

The semiconductor layer stack 313 is composed of an undoped gallium nitride layer 314 and an n-type aluminum gallium nitride layer 315 stacked on the gallium nitride layer 314, and between the gallium nitride layer 314 and the aluminum gallium nitride layer 315. A heterointerface is formed. In the vicinity of this hetero interface, a region having a high carrier concentration called a two-dimensional electron gas is formed and becomes a channel region of the switching element 51. In the switching element 51, the drains of the two FETs constituting the switching element 51 are provided in common on the channel region.

The

electrodes

316a and 316b are formed in a portion of the semiconductor layer stack 313 where the gallium nitride layer 314 is exposed, and are in ohmic contact with the gallium nitride layer 314. The

electrodes

316a and 316b function as source terminals of two FETs constituting the switching element 51.

The first control layer 319a and the second control layer 319b are made of a p-type semiconductor layer, and are formed on the aluminum gallium nitride layer 315.

The

gate electrodes

318a and 319b are in ohmic contact with the

control layers

319a and 319b. Here, the current flowing through the FET having the gate electrode 318a is controlled by a control signal input to the gate electrode 318a. Similarly, the current flowing through the FET having the gate electrode 318b is controlled by a control signal input to the gate electrode 318b.
Here, the distance between the two

gate electrodes

318a and 318b is longer than the distance from the gate electrode 318a to the electrode 316a and the distance from the gate electrode 318b to the electrode 316b. This is because the region between the two

gate electrodes

318a and 318b is a drain region shared by the two FETs when the two FETs are connected in series. Yes. However, as shown in FIG. 6, this switching element 51 has a configuration in which two FETs sharing a drain region are connected in series, and therefore, for example, compared to a configuration in which two single-gate switching elements are connected in series. Thus, the circuit scale can be reduced.

As described above, the dual gate type switching element 51 composed of two so-called GaN transistors has a high withstand voltage and can be driven with a large current similarly to the switching element composed of the GaN transistors described above. The on-resistance value Ron with respect to the area of the chip constituting the element 51 is very small.

Furthermore, the switching element 51 has a low forward voltage in the

reverse conduction modes

1 and 2, and power loss due to a voltage drop at the switching element is reduced.

In addition, since the so-called GaN transistor described above has almost no accumulation effect due to minority carriers, there is almost no influence of the tail current effect at the time of turn-off like IGBT and other silicon-based semiconductor elements. As a result, the switching loss during the switching operation is extremely small as compared with a switching element formed of a silicon-based semiconductor. Therefore, an increase in power consumption due to switching loss can be suppressed even when used at a high switching frequency. If the switching frequency can be increased, the size of the inductor required for the reactor 61 can be reduced, so that the reactor 61 can be reduced in size.

<1-5> Rectification Control Circuit The rectification control circuit 200 controls a signal voltage input to the gate of each switching element included in the step-up / step-down rectifier circuit 50.

Further, the rectification control circuit 200 further includes a step-up / step-down rectifier circuit 50 so that the current waveform of the reactor current detected by the current sensor 60 and the voltage waveform of the output voltage of the AC power supply 1 are similar to each other. A so-called PFC control is also performed to control a signal input to the gate of each switching element included. Specifically, the rectification control circuit 200 attempts to improve the power factor of the step-up / step-down rectifier circuit 50 by controlling the reactor current and the output voltage and output current of the AC power supply 1 so that the phases are substantially the same. Thereby, the harmonic noise generated in the step-up / step-down rectifier circuit 50 can be reduced.

As shown in FIG. 1, the rectification control circuit 200 includes

voltage dividing resistors

120 and 121 connected between the output terminal on the high potential side of the step-up / step-down rectifier circuit 50 and a ground terminal, and an inverting input terminal having a resistor 120. , 121 and a first error amplifier 101 having a non-inverting input terminal connected to a reference voltage output terminal of the control instruction circuit 40 and a first absolute value connected to the current sensor 60 of the buck-boost rectifier circuit 50. The circuit 103, the differential amplifier 116 connected to the AC power source 1, the second absolute value circuit 117 connected to the output terminal of the differential amplifier 116, and the second absolute value circuit 117 connected to the inverting input terminal. A first comparator 107 having an output terminal on the high potential side of the buck-boost rectifier circuit 50 connected to the inverting input terminal, an output terminal of the differential amplifier 116 connected to the non-inverting input terminal, and an inverting input terminal connected to the ground terminal. The second comparator 118, the multiplication circuit 102 connected to the output terminal of the first error amplifier 101 and the second absolute value circuit 117 at the input terminal, and the first absolute value circuit 103 connected to the inverting input terminal. A second error amplifier 104 having a multiplier circuit 102 connected to a terminal; a PWM comparator 106 having a non-inverting input terminal connected to an output terminal of the second error amplifier 104 and an inverting input terminal connected to a triangular wave generating circuit 105; And an output terminal of a first comparator 107, an output terminal of a second comparator 118, a drive logic circuit 108 to which a first absolute value circuit 103 and a PWM comparator 106 are connected. The drive logic circuit 108 also receives the rectification method switching signal Rectsw from the control instruction circuit 40.

The first error amplifier 101 receives a voltage generated at the connection point of the

resistors

120 and 121, that is, a voltage obtained by dividing the output voltage Vdc of the step-up / step-down control circuit 50 by the

resistors

120 and 121 and the control instruction circuit 40. A differential voltage VE1 from the voltage instruction signal VdcIN is output. This is for the rectification control circuit 200 to perform a constant value control so that the output voltage Vdc of the step-up / step-down control circuit 50 is maintained at a voltage indicated by the voltage instruction signal VdcIN.

The multiplication circuit 102 outputs a voltage VE2 obtained by analog multiplication of the voltage VE1 output from the first error amplifier 101 and the voltage output from the second absolute value circuit 117.

The second error amplifier 104 outputs a differential voltage VE3 between the output voltage VIR of the first absolute value circuit 103 and the output voltage VE2 of the multiplication circuit 102.

The triangular wave generation circuit 105 is configured by combining, for example, a Schmitt circuit constituted by an operational amplifier and an integration circuit, and outputs a voltage Vsaw having a triangular waveform (sawtooth shape) time waveform.

The PWM comparator 106 outputs a rectangular pulse train signal PWM based on the output voltage VE3 of the second error amplifier 104 and the voltage Vsaw output from the triangular wave generation circuit 105.

The drive logic circuit 108 is configured by appropriately combining a combination circuit and a flip-flop circuit, for example. When the rectification method switching signal Rectsw input from the control instruction circuit 40 is a signal indicating a single rectification method, the drive logic circuit 108 performs each switching so that the step-up / step-down rectifier circuit 50 performs a single rectification operation. A control signal is input to the gate of the element. Specifically, for each of the

dual gate transistors

55, 59, 65, the control signals input to the two gates are both maintained at "Low", and the

dual gate transistors

55, 59, 65 are maintained in the cutoff mode. At the same time, the control signals input to the two gates of the dual gate transistor 56 are both maintained at “High”, and the dual gate transistor 56 is maintained in the conduction mode. On the other hand, when the rectification method switching signal Rectsw is a signal indicating the double rectification method, the drive logic circuit 108 controls the gate of each switching element so that the buck-boost rectifier circuit 50 performs the double rectification operation. Enter. Specifically, for each of the

dual gate transistors

55 and 65, the control signals input to the two gates are both maintained at “High”, the

dual gate transistors

55 and 65 are maintained in the conduction mode, and the dual gate transistors For the type transistor 56, the control signals input to the two gates are both maintained at "Low", and the dual gate type transistor 56 is maintained in the cutoff mode. The time waveform of the signal input to the gate of each switching element will be described in detail in <2>.

Further, when the rectification method switching signal Rectsw is a signal indicating the single rectification method, the drive logic circuit 108 performs a boost operation on the step-up / step-down rectifier circuit 50 based on the binary output signal DR input from the first comparator 107. Alternatively, a step-down operation is performed. Specifically, when the output voltage of the step-up / step-down rectifier circuit 50 is equal to or higher than the output voltage of the AC power supply 1 (when the binary output signal DR is “High”), the drive logic circuit 108 performs step-up / step-down rectification. The circuit 50 is caused to perform a boosting operation. On the other hand, when the output voltage of the step-up / step-down rectifier circuit 50 is smaller than the output voltage of the AC power supply 1 (when the binary output signal DR is “Low”), the drive logic circuit 108 performs a step-down operation on the step-up / step-down rectifier circuit 50. Let it be done.

Eventually, in this rectification control circuit 200, the first error amplifier 101 detects a differential voltage between the voltage instruction signal VdcIN and the voltage obtained by dividing the output voltage Vdc by the

resistors

120 and 121, and this error output is detected by the multiplication circuit 102. The phase difference between the signal on which the AC output power supply voltage is superimposed and the current detected by the current sensor 60 is detected, and the PWM comparator 106 is based on the phase difference and the differential voltage detected by the two

error amplifiers

104 and 101. The duty ratio of the PWM signal to be output is changed. Thereby, the rectification control circuit 200 can feed back the fluctuation of the output voltage of the step-up / step-down rectifier circuit 50 to the duty ratio of the signal PWM input to the step-up / step-down rectifier circuit 50, and the step-up / step-down rectifier circuit 50 can be fed into the PFC (Power Power factor of the step-up / step-down control circuit 50 can be improved by controlling the factor control. In the rectification control circuit 200, the drive logic circuit 108 causes the step-up / step-down rectifier circuit 50 to perform a boost operation when the rectification method switching signal Rectsw is a signal indicating the double rectification method.

<2> Operation Next, the operation of the step-up / step-down rectifier circuit system according to the present embodiment will be described. Here, the case where the step-up / step-down rectifier circuit 50 operates by the single rectification method and the case of the double rectification method will be described separately. Hereinafter, of the output terminals of the AC power supply 1, the side connected to the connection point of the

transistors

51 and 53 is referred to as a first output terminal, and the side connected to the connection point of the

transistors

52 and 54 is the second output terminal. Will be described.

<2-1> Operation by Single Rectification Method A case where the step-up / step-down rectifier circuit 50 performs a single rectification operation will be described. First, when the drive logic circuit 108 included in the rectification control circuit 200 receives the rectification method switching signal Rrectsw indicating the single rectification method from the control instruction circuit 40, the drive logic circuit 108 Input a control signal to operate in the single rectification method. Here, the case where the step-up / step-down rectifier circuit 50 performs the step-down operation is described separately from the case where the step-up operation is performed. Here, in the rectification control circuit 200, the step-up / step-down rectifier circuit 50 is stepped down based on the magnitude relationship between a signal obtained by full-wave rectification of the output voltage of the AC power supply 1 and the output voltage Vdc of the step-up / step-down rectifier circuit 50. Decide whether to operate or boost.

<2-1-1> Step-Down Operation When performing step-down operation, the time waveform of the control signal input to each gate of the dual gate type switching elements 51 to 56, 59, 65 constituting the step-up / step-down rectifier circuit 50 FIG. 7 shows time waveforms of control signals input to the gates of the single gate

type switching elements

57 and 58.

As shown in FIG. 7, the drive logic circuit 108 inputs an off signal “Low” to the two gates of the switching

elements

55, 59 and 65. In other words, the gates and the sources of the two gates of the switching

elements

55, 59 and 65 are short-circuited. Thereby, the switching

elements

55, 59, 65 are maintained in the cutoff mode. Further, the rectification control circuit 200 inputs an ON signal “High” to the two gates of the switching element 56. In other words, the gate-source voltage Vgs is maintained at the threshold voltage Vth or higher for the two gates of the switching element 56. As a result, the switching element 56 is maintained in the conduction mode. Thereby, the series circuit formed by connecting the smoothing

capacitors

62 and 63 in series and the smoothing capacitor 64 are in a parallel connection relationship, and a single rectification system operation is realized.

Further, as shown in FIG. 7, when the polarity of the output voltage of the AC power supply 1 is positive, the drive logic circuit 108 inputs the off signal “Low” to the two gates of the switching element 53, and The switching element 53 is set to the cut-off mode by short-circuiting the gate and the source for one gate. On the other hand, when the polarity is negative, an ON signal “High” is input to the two gates of the switching element 53, and the gate-source voltage Vgs is set to be equal to or higher than the threshold voltage Vth for the two gates of the switching element 53. Is set to the conduction mode. Here, the polarity of the output voltage of the AC power supply 1 being positive means that the first output terminal of the AC power supply 1 in FIG. 8 is on the high potential side and the second output terminal is on the low potential side. On the other hand, the polarity of the output voltage of the AC power supply 1 being negative means that the first output terminal of the AC power supply 1 in FIG. 8 is on the low potential side and the second output terminal is on the high potential side. means. Here, the drive logic circuit 108 detects the polarity of the output voltage of the AC power supply 1 based on the signal PN output from the second comparator 118 and the signal DR output from the first comparator 107.

As shown in FIG. 7, when the polarity of the output voltage of the AC power supply 1 is positive, the drive logic circuit 108 inputs an ON signal “High” to the two gates of the switching element 54, and For one gate, the gate-source voltage Vgs is set to be equal to or higher than the threshold voltage Vth, and the switching element 54 is set in the conduction mode. On the other hand, when the polarity is negative, an OFF signal “Low” is input to the two gates of the switching element 54, and the switching element 54 is set in the cutoff mode with the two gates of the switching element 54 short-circuited between the gate and the source. . That is, the switching

elements

53 and 54 repeat the cutoff mode and the conduction mode every half cycle of the output voltage of the AC power supply 1, and the

switching elements

53 and 54 are shifted in the cutoff mode and the conduction mode by a half cycle. ing.

As shown in FIG. 7, when the polarity of the output voltage of the AC power supply 1 is positive, the drive logic circuit 108 inputs the signal PWM to the gate “A” of the switching element 51 and turns on the gate “B”. Enter “High”. On the other hand, when the polarity is negative, the ON signal “High” is input to the gate “A” of the switching element 51 and the signal PWMX whose phase is inverted from that of the signal PWM signal is input to the gate “B”. Here, the signal PWM is a so-called PWM control signal in the form of a rectangular pulse train, and the signal PWMX is a rectangle whose phase is shifted by a half cycle from the signal PWM so as to complement the signal PWM in synchronization with the signal PWM. It is a pulse train signal. This signal PWM is the signal PWM itself output from the PWM comparator 106, and the signal PWMX is a signal obtained by inverting the phase of the signal PWM. Further, when the polarity of the output voltage of the AC power supply 1 is positive, the rectification control circuit 200 inputs the ON signal “High” to the gate “A” of the switching element 52 and the signal PWMX to the gate “B”. On the other hand, when the polarity is negative, the signal PWM is input to the gate “A” of the switching element 52 and the ON signal “High” is input to the gate “B”. As a result, the switching element 51 and the switching element 53 perform a switching operation such that they are alternately turned on and off.

Next, the flow of current in the buck-boost rectifier circuit 50 during the step-down operation will be described with reference to FIGS.

FIG. 8A shows the flow of current in the buck-boost rectifier circuit 50 when the polarity of the output voltage of the AC power supply 1 is positive, and FIG. 8B shows the polarity of the output voltage of the AC power supply 1 being negative. The flow of current in the buck-boost rectifier circuit 50 in the case of FIG.

8A, a broken line (H) indicates a current flow when the signal PWM is “High” and the signal PWMX is “Low”. As indicated by the broken line (H), the current flows from the first output terminal of the AC power supply 1 to the switching element 51, the switching element 56, the reactor 61, the switching element 57, the smoothing

capacitors

62, 63, 64, and the switching element 54 in this order. Via, it flows into the second output terminal of the AC power supply 1. In this case, the AC power source 1 accumulates magnetic energy in the reactor 61 while charging the smoothing

capacitors

62, 63 and 64.

8A, a broken line (L) indicates a current flow when the signal PWM is “Low” and the signal PWMX is “High”. As indicated by the broken line (L), the current returns to the reactor 61 via the reactor 61, the switching element 57, the smoothing

capacitors

62, 63, 64, the switching element 54, the switching element 52, and the switching element 56 in this order, and the AC Do not go through power supply 1. In this case, since the AC power source 1 cannot flow current through the reactor 61, magnetic energy cannot be accumulated in the reactor 61. Here, the magnetic energy accumulated in the reactor 61 is released through a current path indicated by a broken line (L).

In FIG. 8A, the drain side (side connected to the reactor 61) in the switching element 58 is at a higher potential than the source side, and no current flows from the source side to the drain side. . This is because the source side is always maintained at substantially the same potential as the low potential side of the AC power supply or at the same potential as the low potential side of the reactor 61.

8B, a broken line (H) indicates a current flow when the signal PWM is “High” and the signal PWMX is “Low”. As indicated by the broken line (H), the current passes from the second output terminal of the AC power supply 1 through the switching element 52, the switching element 56, the reactor 61, the switching element 57, the smoothing

capacitors

62, 63, 64, and the switching element 53. Then, it flows into the first output terminal of the AC power supply 1. In this case, the AC power supply 1 stores magnetic energy in the reactor 61 while charging the smoothing

capacitors

62, 63 and 64.

8B, a broken line (L) indicates a current flow when the signal PWM is “Low” and the signal PWMX is “High”. As indicated by a broken line (L), the current returns to the reactor 61 through the reactor 61, the switching element 57, the smoothing

capacitors

62, 63, 64, the switching element 53, the switching element 51, and the switching element 56 in this order, and the AC power supply Do not go through 1. In this case, since the AC power source 1 cannot flow current through the reactor 61, magnetic energy cannot be accumulated in the reactor 61. Here, the magnetic energy accumulated in the reactor 61 is released through a current path indicated by a broken line (L).

In FIG. 8B, the drain side (the side connected to the reactor 61) of the switching element 58 is at a higher potential than the source side, and no current flows from the source side to the drain side. . The reason is the same as described above.

Here, the rectification control circuit 200 includes the magnetic energy accumulated in the reactor 61 by the current path indicated by the broken line (H) from the AC power supply 1 and the magnetic energy released by the current path indicated by the broken line (L). So that the energy is equal. Thereby, even if the output voltage of the AC power supply 1 is higher than the output voltage Vdc of the step-up / step-down rectifier circuit 50, the voltage Vdc is controlled to a voltage lower than the AC amplitude voltage value of the AC power supply 1 determined by the voltage instruction signal Vdcin. The

By the way, when the time during which the signal PWMX is maintained in the “High” state is longer than the time until the release of the magnetic energy accumulated in the reactor 61 is completed, the current flowing through the reactor 61 is indicated by a broken line ( It flows in the direction opposite to the direction indicated by L). At this time, the charges accumulated in the smoothing

capacitors

62, 63, 64 are discharged, which may lead to a decrease in the output voltage of the buck-boost rectifier circuit 50 and an increase in pulsation components. Therefore, in the present embodiment, in the rectification control circuit 200, the current flowing through the reactor 61 is detected by the current sensor 60, and the detected current is converted into the voltage VIR by the absolute value circuit 117 and input to the drive logic circuit 108. It is configured. Then, when the voltage VIR is substantially 0 V, the drive logic circuit 108 switches the signal PWMX input to the switching element 51 or the switching element 52 from “High” to “Low”. That is, when the current flowing through the reactor 61 becomes approximately 0 A, the signal PWMX is switched from “High” to “Low”. Thus, since the switching element 52 is switched from the conduction mode to the reverse conduction mode 1 by switching the signal PWMX to “Low”, the current flows in the direction opposite to the direction indicated by the broken line (L). It is possible to prevent the smoothing

capacitors

62, 63, 64 from being discharged.

As described above, in the step-up / step-down rectifier circuit 50 according to the present embodiment, when operating by the single rectification method, the current supplied from the AC power supply 1 to the reactor 61 is cut off at the cycle of the signal PWM (signal PWMX). This realizes step-down operation. The step-down operation is realized by using the characteristics of the dual gate

type switching elements

51 and 52 as shown in FIGS. As described above, by using the dual gate

type switching elements

51 and 52 having circuit symmetry, the possibility of further developing the configuration of the step-up / step-down rectifier circuit 50 according to the present embodiment is expanded.

<2-1-2> Boosting Operation In the case of performing the boosting operation, the time waveform of the control signal input to each gate of the dual gate type switching elements 51 to 56, 59, 65 constituting the step-up / step-down rectifier circuit 50; FIG. 9 shows time waveforms of control signals input to the gates of the single gate

type switching elements

57 and 58.

As shown in FIG. 9, the drive logic circuit 108 inputs the off signal “Low” to the two gates of the switching

elements

55, 59, 65 in the same manner as in the step-down operation, thereby switching the switching

elements

55, 59, 65 is maintained in the shut-off mode. Further, the rectification control circuit 200 inputs the ON signal “High” to the two gates of the switching element 56, whereby the switching element 56 is maintained in the conduction mode. Thereby, the series circuit formed by connecting the smoothing

capacitors

62 and 63 in series and the smoothing capacitor 64 are in a parallel connection relationship, thereby realizing a single rectification operation.

As shown in FIG. 9, when the polarity of the output voltage of the AC power supply 1 is positive, the drive logic circuit 108 inputs an off signal “Low” to each of the two gates of the switching

elements

52 and 53. The two

gates

52 and 53 are short-circuited between the gate and the source, and the

switching elements

52 and 53 are both set to the cutoff mode. On the other hand, when the polarity is negative, an ON signal “High” is input to the two gates of the switching

elements

52 and 53, and the gate-source voltage Vgs is set to be equal to or higher than the threshold voltage Vth for the two gates of the switching

elements

52 and 53. Thus, both the

switching elements

52 and 53 are set to the conduction mode. Here, the polarity of the output voltage of the AC power source 1 means that the first output terminal of the AC power source 1 in FIG. 10 is on the high potential side and the second output terminal is on the low potential side. On the other hand, the negative polarity of the output voltage of the AC power supply 1 means that the first output terminal of the AC power supply 1 in FIG. 10 is on the low potential side and the second output terminal is on the high potential side. means.

As shown in FIG. 9, when the polarity of the output voltage of the AC power supply 1 is positive, the drive logic circuit 108 inputs an ON signal “High” to each of the two gates of the switching

elements

51 and 54. For the two

gates

51 and 54, the gate-source voltage Vgs is set to be equal to or higher than the threshold voltage Vth, and the

switching elements

51 and 54 are set in the conduction mode. On the other hand, when the polarity is negative, an OFF signal “Low” is input to the two gates of the switching

elements

51 and 54, and the two gates of the switching

elements

51 and 54 are short-circuited between the gate and the source. 54 is set to the cutoff mode. That is, the switching

elements

52 and 53 and the

switching elements

51 and 54 repeat the cutoff mode and the conduction mode every half cycle of the output voltage of the AC power supply 1, and the

switching elements

52 and 53 and the

switching elements

51 and 54 The timing for entering the cutoff mode and the conduction mode is shifted by a half cycle.

Also, as shown in FIG. 9, the drive logic circuit 108 continues to input the signal PWMX to the gate of the switching element 57 and continues to input the signal PWM signal to the gate of the switching element 58. As a result, the switching element 57 and the switching element 58 are switched on and off alternately.

Next, the flow of current in the buck-boost rectifier circuit 50 during the boosting operation will be described with reference to FIGS.

FIG. 10A shows the flow of current in the buck-boost rectifier circuit 50 when the polarity of the output voltage of the AC power supply 1 is positive, and FIG. 10B shows the polarity of the output voltage of the AC power supply 1 being negative. The flow of current in the buck-boost rectifier circuit 50 in the case of FIG.

10A, the broken line (H) indicates the flow of current when the signal PWM is “High” and the signal PWMX is “Low”. As indicated by the broken line (H), the current flows from the first output terminal of the AC power source 1 through the switching element 51, the switching element 56, the reactor 61, the switching element 58, and the switching element 54 in this order. It flows into the second output terminal. In this case, AC power supply 1 accumulates magnetic energy in reactor 61.

10A, a broken line (L) indicates a current flow when the signal PWM is “Low” and the signal PWMX is “High”. As indicated by a broken line (L), the current passes from the first output terminal of the AC power supply 1 through the switching element 51, the switching element 56, the reactor 61, the switching element 57, the smoothing

capacitors

62, 63, 64, and the switching element 54. Then, it flows into the second output terminal of the AC power source 1. In this case, magnetic energy is released from the reactor 61, and the smoothing

capacitors

62, 63, and 64 are charged. As a result, the output voltage Vdc of the step-up / step-down rectifier circuit 50 is boosted to a voltage larger than the voltage amplitude of the AC power supply 1.

10B, a broken line (H) indicates a current flow in a state where the signal PWM is “High” and the signal PWMX is “Low”. As indicated by the broken line (H), the current flows from the second output terminal of the AC power supply 1 through the switching element 52, the switching element 56, the reactor 61, the switching element 58, and the switching element 53, and the current of the AC power supply 1 is changed. 1 flows into the output terminal. In this case, the AC power supply 1 stores magnetic energy in the reactor 61.

10B, a broken line (L) indicates a current flow in a state where the signal PWM is “Low” and the signal PWMX is “High”. As indicated by the broken line (L), the current passes from the second output terminal of the AC power supply 1 through the switching element 52, the switching element 56, the reactor 61, the switching element 57, the smoothing

capacitors

62, 63, 64, and the switching element 53. Then, it flows into the first output terminal of the AC power supply 1. In this case, magnetic energy is released from the reactor 61, and the smoothing

capacitors

62, 63, 64 from being discharged.

<2-2> Operation by Double Rectification Method A case where the buck-boost rectifier circuit 50 performs a double rectification operation will be described. First, when the drive logic circuit 108 included in the rectification control circuit 200 receives the rectification method switching signal Rrectsw indicating the single rectification method from the control instruction circuit 40, the drive logic circuit 108 A control signal for operating the double rectification method is output. Thereafter, the case where the step-up / step-down rectifier circuit 50 performs the step-down operation will be described separately from the case where the step-up operation is performed. In the first embodiment, the rectification control circuit 200 causes the step-up / step-down rectifier circuit 50 to perform only the boosting operation, and does not switch the operation between the step-down operation and the step-up operation.

When the step-up operation is performed by the double rectification method, the time waveform of the control signal input to each gate of the dual gate type switching elements 51 to 56, 59, 65 constituting the step-up / step-down type rectifier circuit 50, and the single gate type FIG. 11 shows time waveforms of control signals input to the gates of the switching

elements

57 and 58 of FIG.

As shown in FIG. 11, the rectification control circuit 200 inputs an off signal “Low” to the two gates of the switching

elements

52, 54, and 56. In other words, the gates and the sources of the two gates of the switching

elements

52, 54, and 56 are short-circuited. Thereby, the switching

elements

52, 54, and 56 are maintained in the cutoff mode. Further, the rectification control circuit 200 inputs an ON signal “High” to the two gates of the switching

elements

55 and 65. In other words, the gate-source voltage Vgs is maintained at the threshold voltage Vth or higher for the two gates of the switching

elements

55 and 65. Thereby, the switching

elements

55 and 65 are maintained in the conduction mode. Thus, the smoothing

capacitors

62 and 63 are charged only when the polarity of the AC power source 1 is positive, and charged only when the polarity of the AC power source 1 is negative. And the operation | movement of a double rectification system is implement | achieved by setting it as the structure which outputs the voltage which added the voltage between the both ends of two smoothing

capacitors

62 and 63 together. Here, the smoothing capacitor 64 plays a role of removing ripples included in the voltage between both ends of the smoothing

capacitors

62 and 63.

Further, as shown in FIG. 11, when the polarity of the output voltage of the AC power supply 1 is positive, the rectification control circuit 200 inputs the off signal “Low” to the two gates of the switching element 53, and The switching element 53 is set to the cut-off mode by short-circuiting the gate and the source for one gate. On the other hand, when the polarity is negative, an ON signal “High” is input to the two gates of the switching element 53, and the gate-source voltage Vgs is set to be equal to or higher than the threshold voltage Vth for the two gates of the switching element 53. Is set to the conduction mode. Here, the polarity of the output voltage of the AC power supply 1 being positive means that the first output terminal of the AC power supply 1 in FIG. 12 is on the high potential side and the second output terminal is on the low potential side. On the other hand, the polarity of the output voltage of the AC power supply 1 being negative means that the first output terminal of the AC power supply 1 in FIG. 12 is on the low potential side and the second output terminal is on the high potential side. means. Here, the drive logic circuit 108 of the rectification control circuit 200 sets the polarity of the output voltage of the AC power supply 1 based on the signal PN output from the second comparator 118 and the signal DR output from the first comparator 107. Detect.

Further, as shown in FIG. 11, when the polarity of the output voltage of the AC power supply 1 is positive, the rectification control circuit 200 inputs an ON signal “High” to the two gates of the switching element 51, and For one gate, the gate-source voltage Vgs is set to be equal to or higher than the threshold voltage Vth, and the switching element 51 is set in the conduction mode. On the other hand, when the polarity is negative, an OFF signal “Low” is input to the two gates of the switching element 51, and the switching element 51 is placed in the cutoff mode with the two gates of the switching element 51 short-circuited between the gate and the source. . That is, the switching element 53 and the switching element 51 repeat the cutoff mode and the conduction mode every half cycle of the output voltage of the AC power supply 1, and the switching element 53 and the switching element 51 are in the cutoff mode and the conduction mode. Is shifted by a half cycle.

As shown in FIG. 11, the rectification control circuit 200 inputs the signal PWM to the gate of the switching element 57 when the polarity of the output voltage of the AC power supply 1 is positive. On the other hand, when the polarity is negative, an OFF signal “Low” is input to the gate of the switching element 57. Further, the rectification control circuit 200 inputs an off signal “Low” to the gate of the switching element 58 when the polarity of the output voltage of the AC power supply 1 is positive. On the other hand, when the polarity is negative, the signal PWM is input to the gate of the switching element 58. Further, when the polarity of the output voltage of the AC power supply 1 is positive, the rectification control circuit 200 inputs the ON signal “High” to the gate “A” of the switching element 59 and the signal PWMX to the gate “B”. On the other hand, when the polarity is negative, the signal PWMX is input to the gate “A” of the switching element 59 and the ON signal “High” is input to the gate “B”. As a result, when the polarity of the output voltage of the AC power supply 1 is positive, the switching element 57 and the switching element 59 perform switching operations so as to be alternately turned on and off, and when the polarity of the output voltage of the AC power supply 1 is negative, The switching element 58 and the switching element 59 perform a switching operation such that they are alternately turned on and off.

Next, the flow of current in the buck-boost rectifier circuit 50 during the double rectification operation will be described with reference to FIGS.

FIG. 12A shows the flow of current in the step-up / step-down rectifier circuit 50 when the polarity of the output voltage of the AC power supply 1 is positive, and FIG. 12B shows the polarity of the output voltage of the AC power supply 1 being negative. The flow of current in the buck-boost rectifier circuit 50 in the case of FIG.

12A, a broken line (H) indicates a current flow in a state where the signal PWM is “High” and the signal PWMX is “Low”. As indicated by the broken line (H), the current flows from the positive output terminal of the AC power supply 1 through the switching element 51, the switching element 65, the switching element 57, the reactor 61, and the switching element 55 in this order, and the current of the AC power supply 1 is changed. 2 into the output terminal. In this case, the AC power supply 1 stores magnetic energy in the reactor 61.

12A, a broken line (L) indicates a current flow in a state where the signal PWM is “Low” and the signal PWMX is “High”. As indicated by the broken line (L), the current flows from the first output terminal of the AC power supply 1 through the switching element 51, the switching element 65, the smoothing capacitor 62, the switching element 59, the reactor 61, and the switching element 55 in this order. It flows into the second output terminal of the AC power supply 1. In this case, magnetic energy is released from the reactor 61 and the smoothing capacitor 62 is charged. As a result, the voltage across the smoothing capacitor 62 is boosted to a voltage larger than the voltage amplitude of the AC power supply 1.

In FIG. 12B, a broken line (H) indicates a current flow when the signal PWM is “High” and the signal PWMX is “Low”. As indicated by the broken line (H), the current flows from the second output terminal of the AC power supply 1 through the switching element 55, the reactor 61, the switching element 58, and the switching element 53 in this order, and the first output of the AC power supply 1 is output. Flow into the terminal. In this case, AC power supply 1 accumulates magnetic energy in reactor 61.

12B, a broken line (L) indicates a current flow in a state where the signal PWM is “Low” and the signal PWMX is “High”. As indicated by the broken line (L), the current flows from the second output terminal of the AC power source 1 through the switching element 55, the reactor 61, the switching element 59, the smoothing capacitor 63, and the switching element 53 in this order. 1 to the output terminal. In this case, magnetic energy is released from the reactor 61, and the smoothing capacitor 63 is charged. As a result, the voltage across the smoothing capacitor 63 is boosted to a voltage larger than the voltage amplitude of the AC power supply 1.

Here, the output voltage Vdc of the step-up / step-down rectifier circuit 50 is the sum of the voltages across the two smoothing

capacitors

62 and 63, and the voltage across the smoothing

capacitors

62 and 63 is an alternating current as described above. It is larger than the voltage amplitude of the power source 1. Therefore, the output voltage Vdc of the step-up / step-down rectifier circuit 50 has a value larger than twice the voltage amplitude of the output voltage of the AC power supply 1.

Here, the rectification control circuit 200 includes the magnetic energy accumulated in the reactor 61 by the current path indicated by the broken line (H) from the AC power supply 1 and the magnetic energy released by the current path indicated by the broken line (L). So that the energy is equal. As a result, the output voltage of the step-up / step-down rectifier circuit 50 is controlled at a constant value with the voltage determined by the voltage instruction signal Vdcin.

After all, the step-up / step-down rectifier circuit 50 according to the present embodiment has a voltage from around 0V to a voltage V2 that is about twice the voltage amplitude V1 of the AC power supply 1 by the single rectification system operation, as shown in FIG. In the range, the output voltage Vi can be controlled to increase. Then, by the operation of the double rectification method, it is possible to control the output voltage Vi to be increased in a voltage range equal to or higher than the voltage V2 that is twice the voltage amplitude of the AC power supply 1. As a result, the step-up / step-down rectifier circuit 50 has a wider variable range of output voltage than the step-up rectifier circuit 1050 configured as shown in FIG. Further, if this step-up / step-down rectifier circuit 50 is connected to the inverter 3, the input voltage to the inverter 3 can be changed in a wide voltage range, so that the variable range of the output voltage can be increased while the inverter 3 is driven by the PAM method. Can be enlarged.

Thus, the inverter 3 can be driven by the PAM method using the input voltage to the inverter 3 as a voltage corresponding to the rotation range of the motor 4 in almost all rotation ranges from the lower limit to the upper limit of the rotation range of the motor 4. Therefore, since the input voltage (output voltage Vi) of the inverter 3 can be set to the minimum necessary level, the switching

element

31, 32, 33, 34, 35, 36 constituting the inverter 3 is connected between the source and drain. Since the applied voltage can be lowered, the switching loss in each of the switching

elements

31, 32, 33, 34, 35, and 36 can be reduced.

In the step-up / step-down rectifier circuit 50, the smaller the output voltage Vi, the smaller the magnitude of the pulsating flow component included in the output voltage Vi. The pulsating component included in the output voltage (input voltage to the inverter 3) Vi is also included in the output current of the inverter 3 (driving current of the motor 4) as a pulsating component. Therefore, by reducing the output voltage Vi as much as possible as in the present embodiment, the pulsating flow component included in the drive current of the motor 4 can be reduced correspondingly, so the iron loss generated in the motor 4 is reduced. There is also an advantage that it can be done.

In addition, by combining the operation by the single rectification method, the operation by the double rectification method, the step-up operation and the step-down operation to change the output voltage in a wide voltage range, the step-up rate required for the step-up operation is relatively narrow. Since it can limit to a range, the design of the reactor 61 can be made easy.

<Embodiment 2>
Since the configuration of the motor drive system according to the present embodiment is the same as that of the first embodiment, the description thereof is omitted. The motor drive system according to the present embodiment is implemented in that the rectification control circuit 200 does not cause the step-up / step-down rectifier circuit 50 to perform the step-down operation using the double rectification method and not perform the step-up operation using the single rectification method. This is different from Form 1.

Here, only the step-down operation in the double rectification method, which is a difference from the first embodiment, will be described. The configuration of the motor drive system according to the present embodiment, the step-down operation using the single rectification method, and the step-up operation using the double rectification method are the same as those in the first embodiment, and thus description thereof is omitted here.

First, when the drive logic circuit 108 included in the rectification control circuit 200 receives the rectification method switching signal Rectsw indicating the double rectification method from the control instruction circuit 40, the drive logic circuit 108 A control signal for operating the double rectification method is output. Here, in the rectification control circuit 200, the step-up / step-down rectifier circuit 50 is stepped down based on the magnitude relationship between a signal obtained by full-wave rectification of the output voltage of the AC power supply 1 and the output voltage Vdc of the step-up / step-down rectifier circuit 50. Decide whether to operate or boost. When the rectification control circuit 200 receives the rectification method switching signal Rrectsw indicating the single rectification method from the control instruction circuit 40, the rectification control circuit 200 causes the step-up / step-down rectifier circuit 50 to perform only the step-down operation, and between the step-down operation and the step-up operation. Do not switch the operation.

When the step-down operation is performed by the double rectification method, the time waveform of the control signal input to each gate of the dual gate type switching elements 51 to 56, 59, 65 constituting the step-up / step-down type rectifier circuit 50, and the single gate type FIG. 14 shows time waveforms of control signals input to the gates of the switching

elements

57 and 58.

As shown in FIG. 14, the rectification control circuit 200 continues to input the off signal “Low” to the two gates of the switching element 56. In other words, the two gates of the switching element 56 are kept short-circuited between the gate and the source. Thereby, the switching element 56 is maintained in the cutoff mode. In addition, the rectification control circuit 200 continues to input the ON signal “High” to the two gates of the switching

elements

55, 59, and 65. In other words, the gate-source voltage Vgs is maintained at the threshold voltage Vth or higher for the two gates of the switching

elements

55, 59, 65. Thereby, the switching

elements

55, 59, 65 are maintained in the conduction mode. Thus, the smoothing

capacitors

62 and 63.

Further, as shown in FIG. 14, when the polarity of the output voltage of the AC power supply 1 is positive, the rectification control circuit 200 inputs the signal PWM to the gate “A” of the switching element 51 and turns on the gate “B”. “High” is input, the ON signal “High” is input to the gate “A” of the switching element 52, and the signal PWMX is input to the gate “B”. On the other hand, when the polarity is negative, an OFF signal “Low” is input to the two gates of the switching

elements

51 and 52, and the

switching elements

51 and 52 are short-circuited with the sources. Set to shut-off mode. Here, the drive logic circuit 108 of the rectification control circuit 200 sets the polarity of the output voltage of the AC power supply 1 based on the signal PN output from the second comparator 118 and the signal DR output from the first comparator 107. Detect.

As shown in FIG. 14, when the polarity of the output voltage of the AC power supply 1 is positive, the rectification control circuit 200 inputs an off signal “Low” to each of the two gates of the switching

elements

53 and 54, The switching

elements

53 and 54 are set to the cutoff mode with the two

gates

53 and 54 short-circuited to the source. On the other hand, when the polarity is negative, the signal PWM is input to the gate “A” of the switching element 53, the ON signal “High” is input to the gate “B”, and the ON signal “High” is input to the gate “A” of the switching element 54. “High” is input, and the signal PWMX is input to the gate “B”. That is, the switching

elements

51 and 52 and the

switching elements

53 and 54 repeat the cutoff mode every half cycle of the output voltage of the AC power supply 1, and the

switching elements

51 and 52 and the

switching elements

53 and 54 enter the cutoff mode. The timing is shifted by half a cycle. As a result, when the polarity of the output voltage of the AC power supply 1 is positive, the switching element 51 and the switching element 52 perform the switching operation so as to be alternately turned on and off, and when the polarity of the output voltage of the AC power supply 1 is negative, The switching element 53 and the switching element 54 perform a switching operation so as to be alternately turned on and off.

Further, as shown in FIG. 14, the rectification control circuit 200 continues to input the off signal “Low” to the gates of the switching

elements

57 and 58. In other words, the gates and sources of the switching

elements

57 and 58 are kept short-circuited. Thereby, the switching

elements

57 and 58 are maintained in the cutoff mode.

FIG. 15A shows the flow of current in the buck-boost rectifier circuit 50 when the polarity of the output voltage of the AC power supply 1 is positive, and FIG. 15B shows the polarity of the output voltage of the AC power supply 1 being negative. The flow of current in the buck-boost rectifier circuit 50 in the case of FIG.

15A, a broken line (H) indicates a current flow when the signal PWM is “High” and the signal PWMX is “Low”. As indicated by the broken line (H), the current flows from the first output terminal of the AC power supply 1 through the switching element 51, the switching element 65, the smoothing capacitor 62, the switching element 59, the reactor 61, and the switching element 55 in this order. It flows into the second output terminal of the AC power supply 1. In this case, the AC power supply 1 accumulates magnetic energy in the reactor 61 while charging the smoothing capacitor 62.

15A, a broken line (L) indicates a current flow in a state where the signal PWM is “Low” and the signal PWMX is “High”. As indicated by the broken line (L), the current returns from the reactor 61 to the reactor 61 through the switching element 55, the switching element 52, the switching element 65, the smoothing capacitor 62, and the switching element 59 in this order, and then passes through the AC power source 1. do not do. In this case, since the AC power source 1 cannot flow current through the reactor 61, magnetic energy cannot be accumulated in the reactor 61. Here, the magnetic energy accumulated in the reactor 61 is released through a current path indicated by a broken line (L).

15B, a broken line (H) indicates a current flow in a state where the signal PWM is “High” and the signal PWMX is “Low”. As indicated by a broken line (H), the current flows from the second output terminal of the AC power source 1 through the switching element 55, the reactor 61, the switching element 59, the smoothing capacitor 63, and the switching element 53 in this order. Flow into the first output terminal. In this case, the AC power supply 1 accumulates magnetic energy in the reactor 61 while charging the smoothing capacitor 62.

15B, the broken line (L) indicates the flow of current when the signal PWM is “Low” and the signal PWMX is “High”. As indicated by a broken line (L), the current returns from the reactor 61 to the reactor 61 through the switching element 59, the smoothing capacitor 63, the switching element 54, and the switching element 55 in this order, and then passes through the AC power source 1. do not do. In this case, since the AC power source 1 cannot flow current through the reactor 61, magnetic energy cannot be accumulated in the reactor 61. Here, the magnetic energy accumulated in the reactor 61 is released through a current path indicated by a broken line (L).

Here, the output voltage Vdc of the step-up / step-down rectifier circuit 50 is a sum of voltages between both ends of the two smoothing

capacitors

62 and 63. The voltage across the smoothing

capacitors

62 and 63 is smaller than the voltage amplitude of the AC power supply 1. Therefore, the output voltage Vdc of the step-up / step-down rectifier circuit 50 has a value smaller than twice the voltage amplitude of the output voltage of the AC power supply 1.

Eventually, the step-up / step-down rectifier circuit 50 according to the present embodiment generates the output voltage Vi in the voltage range from around 0 V to the voltage amplitude V1 of the AC power supply 1 by the single rectification operation as shown in FIG. It can be controlled to increase. Then, by the operation of the double rectification method, the output voltage Vi is set in the voltage range from the voltage amplitude V1 of the AC power supply 1 to more than twice the voltage amplitude centering on the voltage V2 that is twice the voltage amplitude of the AC power supply 1. It can be controlled to increase. If the step-up / step-down rectifier circuit 50 is connected to the inverter 3, the input voltage to the inverter 3 can be changed in a wide voltage range. Therefore, the inverter 3 to which the step-up / step-down rectifier circuit 50 is connected is driven by the PAM method. However, the output voltage can be changed over a wide voltage range.

Thus, as in the first embodiment, in almost all the rotation ranges from the lower limit to the upper limit of the rotation range of the motor 4, the input voltage to the inverter 3 is set to a voltage corresponding to the rotation range of the motor 4, and the inverter 3 is set to PAM. The inverter 3 can be driven and the input voltage (output voltage Vi) of the inverter 3 can be set to the minimum necessary level, so that the switching loss in the switching elements 31 to 36 of the inverter 3 can be reduced.

<Modification>
(1) In the first and second embodiments, the voltage range from the voltage amplitude V1 of the output voltage of the AC power supply 1 to the voltage V2 that is twice the voltage amplitude of the input voltage to the inverter 3 is boosted by a single rectification method. Alternatively, the example of the step-up / step-down rectifier circuit 50 that outputs by the double rectification step-down operation has been described, but the present invention is not limited to this. For example, as shown in FIG. 17, a specified voltage V3 that is larger than the voltage V1 and smaller than the voltage V2 is set, and the voltage range between the voltage V1 and the voltage V3 is output by the boosting operation of the single rectification method. The voltage range between the voltage V3 and the voltage V2 may be output by the double rectification step-down operation.

(2) In the first and second embodiments, examples in which single-gate FETs are used as the switching

elements

57 and 58 have been described. However, the present invention is not limited to this, and dual-gate FETs may be used.

The present invention relates to a rectifier circuit that converts alternating current into direct current, and in particular, when the output voltage of the rectifier circuit is desired to be variable in a voltage range from near 0 V to a voltage value that is twice or more the voltage amplitude of the alternating current power supply. Useful for. The step-up / step-down rectifier circuit system according to the present invention is useful as a power supply source to an inverter for driving a motor.

DESCRIPTION OF SYMBOLS 1 AC power supply 3 Inverter 4 Motor 40 Control circuit 41 Inverter control circuit 50 Buck-boost

type rectifier circuit

51,52,53,54,55,56,59,65 Dual gate

type switching element

57,58 Single gate type switching element 60 Current sensor 61

Reactor

62, 63, 64 Smoothing capacitor 101 First error amplifier 102 Multiplying circuit 103 First absolute value circuit 104 Second error amplifier 105 Triangular wave generation circuit 106 PWM comparator 107 First comparator 108 Drive logic circuit 116 Differential amplifier 117 Second absolute value circuit 118

Second comparator

120, 121 Resistance 200 Rectification control circuit

Claims

A buck-boost rectifier circuit system comprising a buck-boost rectifier circuit and a rectification control circuit for controlling the buck-boost rectifier circuit,
The step-up / step-down rectifier circuit is:
A first circuit including a plurality of dual gate type switching elements and connected to an AC power supply;
A reactor connected to the output end of the first circuit;
A second circuit including at least two single-gate switching elements and at least one dual-gate switching element and connected to the reactor;
The rectification control circuit includes:
The step-up / step-down rectifier circuit switches the current path between the first circuit and the second circuit depending on whether the step-up / step-down rectifier circuit operates by a single rectification method or a double rectification method. When the step-down operation is performed by storing energy in and discharging the energy stored in the reactor, the two switching elements included in the first circuit are alternately switched on and off, and the switching operation is performed. When boosting operation is performed by accumulating energy in the reactor and releasing energy accumulated in the reactor, switching is performed by alternately turning on and off the two single-gate switching elements included in the second circuit. Each switching element included in the first circuit and the second circuit so as to operate Buck-boost rectifier circuit system, wherein the control signal is input to the gate.
The step-up / step-down rectifier circuit further includes a third circuit including at least two capacitors and connected to the second circuit for smoothing an output from the second circuit,
The first circuit includes:
A bridge circuit composed of dual gate type first, second, third and fourth switching elements;
A dual-gate fifth switching element and a sixth switching element connected in series between a first output terminal and an input terminal of the bridge circuit;
A dual-gate seventh switching element having one end connected to a connection point between the first output terminal of the bridge circuit and a series circuit including the fifth switching element and the sixth switching element;
The second circuit includes:
A single gate type eighth switching element and a ninth switching element connected in series between the other end side of the seventh switching element and the second output end of the bridge circuit;
A dual gate type tenth switching element having one end side connected to a connection point between the eighth switching element and the ninth switching element;
The third circuit includes:
A first capacitor connected between both ends of a series circuit composed of the eighth switching element and the ninth switching element;
A second capacitor connected between one end side of the first capacitor and the other end side of the tenth switching element;
A third capacitor connected between the other end side of the first capacitor and the other end side of the tenth switching element;
The reactor has one end connected to a connection point between the fifth switching element and the sixth switching element, and the other end connected to a connection point between the eighth switching element and the ninth switching element. The step-up / step-down rectifier circuit system according to claim 1.
The eighth and ninth switching elements are single gate FETs,
The step-up / step-down rectifier circuit system according to claim 2, wherein the first to seventh and tenth switching elements are dual gate type FETs in which drains of two FETs are connected to each other.
Single gate type FET
A semiconductor layer stack made of a nitride semiconductor formed on a semiconductor substrate;
A drain terminal and a source terminal provided apart from each other on the semiconductor layer stack;
The step-up / step-down rectifier circuit system according to claim 3, further comprising: a gate terminal provided between the drain terminal and the source terminal.
The dual gate FET is
A semiconductor layer stack made of a nitride semiconductor formed on a semiconductor substrate;
A first output terminal and a second output terminal provided on the semiconductor layer stack so as to be spaced apart from each other;
The step-up / step-down type according to claim 3, further comprising: a first gate terminal and a second gate terminal which are provided apart from each other between the first output terminal and the second output terminal. Rectifier circuit system.
The step-up / step-down rectifier circuit system according to any one of claims 1 to 5, wherein the control signal is a signal having a pulse train waveform.
A first circuit including a plurality of dual gate type switching elements and connected to an AC power source;
A reactor connected to the first circuit;
A second circuit including at least one single gate type switching element and at least one dual gate type switching element and connected to the reactor;
A step-up / step-down rectifier circuit comprising: a third circuit including at least two capacitors and connected to the second circuit.
The first circuit includes:
A bridge circuit composed of dual gate type first, second, third and fourth switching elements;
A dual-gate fifth switching element and a sixth switching element connected in series between a first output terminal and an input terminal of the bridge circuit;
A dual-gate seventh switching element having one end connected to a connection point between the first output terminal of the bridge circuit and a series circuit including the fifth switching element and the sixth switching element;
The second circuit includes:
A single gate type eighth switching element and a ninth switching element connected in series between the other end side of the seventh switching element and the second output end of the bridge circuit;
A dual gate type tenth switching element having one end side connected to a connection point between the eighth switching element and the ninth switching element;
The third circuit includes:
A first capacitor connected between both ends of a series circuit composed of the eighth switching element and the ninth switching element;
A second capacitor connected between one end side of the first capacitor and the other end side of the tenth switching element;
A third capacitor connected between the other end side of the first capacitor and the other end side of the tenth switching element;
The reactor has one end connected to a connection point between the fifth switching element and the sixth switching element, and the other end connected to a connection point between the eighth switching element and the ninth switching element. The step-up / step-down rectifier circuit according to claim 7.