WO2012106954A1

WO2012106954A1 - Method and device for flashing basic input output system memory of multi-processor

Info

Publication number: WO2012106954A1
Application number: PCT/CN2011/079196
Authority: WO
Inventors: 侯国良
Original assignee: 华为技术有限公司
Priority date: 2011-08-31
Filing date: 2011-08-31
Publication date: 2012-08-16
Also published as: CN102725731A; CN102725731B

Abstract

A method for flashing the Basic Input Output System (BIOS) memory of a multi-processor system includes: receiving a flash command, and reading specified BIOS files required to be flashed in the flash command into the memory; and awakening the slave thread of each processor specified in the flash command, sending to the awakened slave threads the target addresses for the flashed BIOS files in the BIOS memories corresponding thereto, and flashing the BIOS files in parallel at the target addresses of the respectively corresponding BIOS memories according to the respectively received target addresses by the awakened slave threads of the processors. A processor includes a flash command receiving unit, a BIOS file read-in unit and an awakening unit.

Description

Multi-processor basic input/output system memory writing method and device

The present invention relates to the field of computer technologies, and in particular, to a multi-processor basic input/output system memory writing method and apparatus.

Background technique

With the continuous improvement of computer performance requirements in scientific computing and transaction processing, SMP (Symmetric Multi-Processing) systems are becoming more widely used and larger in scale. However, in the traditional SMP system, all processors (CPUs) share the system bus. When the number of processors increases, the system bus conflicts will increase, so the processor in the current SMP system The number can't be too much, generally only a few dozen, which greatly limits the scalability of the system.

In order to solve the above problem, a NUMA (Non-Uniform Memory Access) technology is proposed in the prior art. In an architecture system adopting the technology, each CPU has a corresponding basic input/output system. (BIOS) memory, during the development and maintenance of the product, when it is found that the BIOS needs to be updated, the main thread running the operating system calls the program that flashes the BIOS memory, and serially writes the storage for each processor. BIOS memory. When the number of processors is large, the amount of memory that needs to be written to store the BIOS is large, which results in a time-consuming extension.

Summary of the invention

Embodiments of the present invention provide a memory flash writing method and a processor for a multi-processor basic input/output system, which can reduce the time consumed by the memory of the basic input/output system of the multi-processor.

An aspect of the present invention provides a method for flashing a BIOS of a basic input/output system of a multiprocessor system, including:

Receiving a flash write command, and reading a BIOS file specified in the flash write command to be flushed into the memory;

Awakening the slave threads of the respective processors specified in the flash write command, and sending the target addresses of the flashed BIOS files in the corresponding BIOS memory to the awakened slave threads, according to the slave threads of the awakened processor according to the respective The received target addresses are flashed in parallel with the BIOS file at the destination address of the corresponding BIOS memory. Another aspect of the present invention provides a processor, including:

a flashing command receiving unit, configured to receive a flash write command;

a BIOS file reading unit, configured to read a BIOS file specified in the flash write command to be written into the memory;

a wake-up unit, configured to wake up a slave thread of each processor specified in the flash write command, and send a wake-up slave thread a target address for flashing a BIOS file in its corresponding BIOS memory, by the awakened processor The slave threads flush the BIOS files in parallel at the target addresses of the respective corresponding BIOS memories according to the respective received target addresses.

It can be seen that the flash memory writing method of the BIOS of the multiprocessor system provided by the embodiment of the present invention no longer serially flashes the BIOS memory of each processor by the main thread of the operating system, but triggers the slave processes of the respective processors. Each of the BIOS memories is flushed in parallel by the slave processes of the respective processors, so that the time consumed for flash writing can be greatly shortened. DRAWINGS

1 is a schematic diagram of a flash memory write method of a BIOS memory of a multiprocessor system according to an embodiment of the present invention;

2 is a schematic diagram of a specific embodiment of a flash memory writing method of a BIOS memory of a multiprocessor system provided by the present invention;

3 is a schematic diagram of another specific embodiment of a flash memory writing method of a BIOS memory of a multiprocessor system provided by the present invention;

FIG. 4 is a schematic diagram of a processor according to an embodiment of the present invention.

detailed description

The embodiment of the invention provides a memory flash writing method of a multi-processor BIOS, which wakes up a thread of each processor through a main thread of the operating system, and flashes the BIOS of the corresponding processor in parallel by the awakened thread. Therefore, the time spent on flash writing is greatly reduced.

When the multi-processor system is powered on, one of the many threads in each processor selects one of the processor's main threads (PBSP) for local processor initialization, and other processes can be called slave processes; The main thread of all processors participates in the main thread of the operating system (SBSP), which is booted by the main thread of the operating system to boot the system into the operating system. As shown in FIG. 1 , a method for writing a BIOS memory of a multiprocessor system according to an embodiment of the present invention includes the following steps:

Step S101: receiving a flash write command;

Step S102: Read the BIOS file that needs to be flashed specified in the flash write command into the memory; Step S103: Wake up the slave thread of each processor specified in the flash write command, and send the corresponding slave thread to the waked up The BIOS memory stores the target address of the BIOS file, and the slave thread of the awakened processor writes the BIOS file in parallel according to the target address received by each other at the target address of the corresponding BIOS memory.

It can be seen that the flash memory writing method of the BIOS of the multiprocessor system provided by the embodiment of the present invention no longer serially flashes the BIOS memory of each processor by the main thread of the operating system, but triggers the slave processes of the respective processors. Each of the BIOS memories is flushed in parallel by the slave processes of the respective processors, so that the time consumed for flash writing can be greatly shortened. Embodiment 1

2 is a schematic diagram of a specific embodiment of a method for writing a BIOS memory of a multiprocessor system according to the present invention. As shown in FIG. 2, the method includes:

Step S201: The user inputs a flash write command, such as fvupdateipf, and an identifier of a BIOS file that needs to be written, such as a file name of the file.

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The following command format can be used:

Fvupdateipf -UE0 -UE1 elilo.efi

Wherein - UE0 represents one processor UEO, - UE1 represents another processor UE1, and elilo.efi represents the file name of the BIOS binary file to be flashed.

Step S202: The main thread of the operating system checks the integrity of the BIOS file that needs to be written, and checks whether the BIOS file matches the platform of the current processor. If any of the above two inspection results is unsatisfactory, step S209 is performed: the flow is exited.

Step S203: If the result of the check in step S202 is all qualified, the BIOS file to be flashed is read into the memory.

Step S204: The main thread of the operating system will need to flash the middle of each processor of the BIOS memory. The value of the interrupt request register (IRR) in the controller is set to a value indicating that the interrupt is requested; Step S205: When the corresponding slave thread polling of each processor detects that the value of the interrupt request register of the processor in which it is located indicates that the request is interrupted The value is awakened and the value in the interrupt request register is cleared.

The interrupt request register here can preferably use S APIC ( Streamlined Advanced

Interrupt request register for Programmable Interrupt Controller, ). The slave threads in each processor can disable other interrupts and can only poll the values in the SAPIC interrupt request register.

The slave thread can clear the value of the interrupt request register by sending an EOI (End of Interrupt) signal.

In practice, the slave threads of each processor can disable other interrupts, only continuously polling

Step S206: The main thread in the operating system sends the target address of the BIOS file in the BIOS memory to the slave thread in the processor that is woken up in step S205;

Step S207: The slave threads of the awake processors separately write the BIOS files in parallel at the target addresses of the corresponding BIOS memories according to the respective received target addresses, and after all the BIOS memories of the multi-processing system are overwritten, Notifying the main thread of the operating system;

Step S208: After the main thread of the operating system finds that all the waking slave threads have finished writing the corresponding BIOS memory, it starts to check whether the current file in each BIOS memory is consistent with the BIOS file that needs to be written. If yes, step S209 is performed. .

It should be noted that the step S208 is performed to perform verification after the completion of the brush writing, and the reliability of the brush writing result is enhanced, so that step S208 can also be omitted in practice.

In this embodiment, the main thread wakes up the slave threads for flashing the BIOS memory by interrupting, and the slave threads that wake up in parallel flash the BIOS memory of the corresponding processor in parallel, which greatly shortens the time consumed. , improve the efficiency of product research and development. Embodiment 2

FIG. 3 is a schematic diagram of another specific embodiment of a method for writing a BIOS memory of a multiprocessor system according to the present invention. As shown in FIG. 3, the method includes:

Step S301:

The user enters a flash write command, such as fvupdateipf, and the identifier of the BIOS file that needs to be written, For example, the file name of the file.

The following command format can be used:

Fvupdateipf -UE0 -UE1 elilo.efi

Step S302: The main thread of the operating system checks the integrity of the BIOS file that needs to be written, and checks whether the BIOS file matches the platform of the current processor. If any of the above two inspection results is unsatisfactory, step S209 is performed: the flow is exited.

Step S303: If the result of the check in step S202 is all qualified, the BIOS file to be flashed is read into the memory.

Step S304: The main thread of the operating system sets the value of the wake-up memory variable to the identifier of the slave process of each processor that needs to wake up;

Step S305: All slave threads of each processor poll and detect the value of the wake-up memory variable, wake up from the slave process identified by the value of the wake-up memory variable, and clear the value of the wake-up memory variable.

Step S306: The main thread in the operating system sends the target address of the BIOS file in the BIOS memory to the slave thread in the processor that is woken up in step S205;

Step S307: The slave threads of each processor that are awake are in parallel to write the BIOS file at the target address of the corresponding BIOS memory according to the respective received target addresses, and after all the BIOS memories of the multi-processing system are overwritten, Notifying the main thread of the operating system;

Step S308: The main thread of the operating system finds that all the waking slave threads have finished writing the corresponding

After the BIOS memory, it is checked whether the current BIOS file in each of the flashed BIOS memories is consistent with the BIOS file to be erased. If they are consistent, step S309 is performed.

In practice, the slave thread that completes the flashing of the BIOS memory can actively send a notification to the main operating system thread that the brush is written.

It should be noted that the step S308 is performed to perform verification after the completion of the brush writing, and the reliability of the brushing result is enhanced, so that step S308 can also be omitted in practice.

In this embodiment, the main thread wakes up the slave threads of each processor by setting the value of the wake-up memory variable, and the slave ROMs flash the corresponding BIOS memory of the corresponding processor in parallel, thereby greatly shortening the time consumed and improving. Product development efficiency. In addition, the embodiment of the present invention further provides a processor. As shown in FIG. 4, the processor 40 includes: a flash write command receiving unit 401, a BIOS file read-in unit 402, and a wake-up unit 403.

The flash write command receiving unit 401 is configured to receive a flash write command;

The BIOS file reading unit 402 is configured to read the BIOS file specified in the flash write command to be written into the memory;

The waking unit 403 is configured to wake up the slave threads of the respective processors specified in the flush command, and send the waking slave thread a target address for flashing the BIOS file in its corresponding BIOS memory, from the slave of the awakened processor. The threads flush the BIOS files in parallel at the target addresses of the respective BIOS memories according to the respective received target addresses.

A wake-up unit of a specific implementation manner specifically includes an interrupt request register setting unit for setting a value of an interrupt request register in an interrupt controller of each processor that needs to flash the BIOS memory to indicate a request The value of the interrupt is such that the corresponding slave thread wakes up when the poll detects that the value of the terminal request register of its processor indicates the value of the requesting terminal, and clears the value in the interrupt request register.

The wake-up unit of another specific implementation specifically includes a wake-up memory variable setting unit, where the wake-up memory variable setting unit is configured to set the value of the wake-up memory variable to the identifier of the slave process of each processor that needs to wake up, to wake up the memory variable. The value identifies the slave process and clears the value of the wake-up memory variable.

In addition, the above processor may further include a first checking unit for checking whether the BIOS file to be flashed is complete and whether it matches the platform of the current processor.

In addition, the processor may further include a brush completion notification receiving unit and a second inspection unit. The flashing completion notification receiving unit is configured to receive a notification that the slave processor of the wake-up processor sends a flash to write the BIOS memory; and the second checking unit is configured to check whether the current BIOS file of the flashed BIOS memory is required or not. The flashed BIOS file is consistent.

The above disclosure is only a few specific embodiments of the present invention, but the present invention is not limited thereto, and any changes that can be made by those skilled in the art should fall within the protection scope of the present invention.

Claims

Rights request

1. A basic input/output system for a multiprocessor system. A flash memory writing method for a BIOS memory, comprising:

Wake up the slave thread of the processor specified in the flush command and send the target address of the flashed BIOS file in its corresponding BIOS memory to the awakened slave thread, according to the slave thread of the awakened processor The target address is written in parallel with the BIOS file at the target address of the corresponding BIOS memory.

2. The method according to claim 1, wherein the awakening the slave thread of the processor specified in the flash write command comprises:

Setting a value of an interrupt request register in an interrupt controller of each processor that needs to flash the BIOS memory to a value indicating that the interrupt is requested, so that the corresponding slave thread detects the value of the requesting terminal when polling The slave thread is woken up and clears the value in the interrupt request register.

3. The method according to claim 1, wherein the awakening the slave thread of the processor specified in the flash write command comprises:

Set the value of the wake-up memory variable to the identity of the slave process of the processor that needs to wake up to wake up the slave process identified by the value of the wake-up memory variable and clear the value of the wake-up memory variable.

The method according to any one of claims 1 to 3, characterized in that the method further comprises:

Before reading the BIOS file specified in the flash command to be flushed into the memory, check whether the BIOS file to be flashed is complete and whether it matches the platform of the current processor.

The method according to any one of claims 1 to 4, further comprising:

Receiving a notification sent by the slave process of the wake-up processor to write the BIOS memory; checking whether the current BIOS file of the flashed BIOS memory is consistent with the BIOS file that needs to be flashed.

6. A processor, comprising:

a flashing command receiving unit, configured to receive a flash write command;

The processor according to claim 6, wherein the waking unit comprises: an interrupt request register setting unit, and an interrupt request register in an interrupt controller of each processor that needs to flash the BIOS memory The value is set to a value indicating the request interrupt, so that the corresponding slave thread wakes up when the poll detects that the value of the terminal request register of its processor indicates the value of the requesting terminal, and clears the interrupt request register. value.

The processor according to claim 6, wherein the waking unit comprises: a wake-up memory variable setting unit, configured to set a value of the wake-up memory variable to be an identifier of a slave process of each processor that needs to wake up, The slave process identified by waking up the value of the wakeup memory variable and clearing the value of the wakeup memory variable.

The processor according to any one of claims 6 to 8, wherein the processor further comprises:

The first checking unit is configured to check whether the BIOS file that needs to be written is complete and whether it matches the platform of the current processor.

The flashing completion notification receiving unit is configured to receive a notification sent by the slave process of the awake each processor to write the BIOS memory;

a second checking unit, configured to check whether a current BIOS file of the flashed BIOS memory is Need to flash the BIOS file