WO2012176209A1

WO2012176209A1 - Serially fed flash type analog to digital converter

Info

Publication number: WO2012176209A1
Application number: PCT/IN2011/000415
Authority: WO
Inventors: Chandra Kumar NAVEEN; M Venkatarajesh; M Akshaya; Bharadwaj P. BHEEMA; Kumar K GANESH; Kumar ASHWIN; Mendonca PRASHANTH; K Yashavantha; M Jayaprakash; Dilraj Veigas SANTHOSH; Bhat MURALIDHARA
Original assignee: Naveen Chandra Kumar; M Venkatarajesh; M Akshaya
Priority date: 2011-06-21
Filing date: 2011-06-21
Publication date: 2012-12-27

Abstract

The disclosure is about a type of flash ADC, called 'Serially Fed Flash Analog to Digital Converter', where the analog input voltage signal is fed to a single node of a Resistor Ladder consisting of L+1 voltage taps, where L = 2ⁿ. In the Embodimentl of this ADC, the voltages tapped from the Resistor Ladder are fed to an XOR Device Array (XDA), which contains L+1 XOR2 devices. The output of the XDA is a One-Out-Of-One-Code which can be easily encoded to Binary Code. This single node analog input architecture leads to reduced input capacitance which is a major cause of concern in a Conventional Flash ADC. In the Embodiment2, the voltages tapped from the Resistor Ladder are fed to an Analog Comparator Array, producing Thermometer Code which can be encoded to Binary Code via One-Out-Of- N-Code. Out of the two Embodiments, Embodimentl is an 'All Digital ADC' making it highly attractive for very effective system integration and low power applications. Apart from being at the central working of this ADC, the main Achilles' Heels of this ADC is the Resistor Ladder with exponentially decaying resistance ratios which need to be precisely fabricated for good conversion precision.

Description

Serially Fed Flash Type Analog to Digital Converter

Technical Field

This invention relates to the field of Analog to Digital Converter (ADC), an electronic circuit, more specifically, the Flash ADC. In the Conventional Flash ADC, analog input voltage is fed to all the comparators in the Comparator Array simultaneously, which leads to large input capacitance. Whereas, in the 'Serially Fed Flash ADC, the analog input voltage signal is fed to a single node of a 'Resistor ladder' reducing the input capacitance, apart from many more other advantages. Background Art

Analog to Digital Converter is an important interface block in most of the modern electronic circuits. There are many ADC architectures proposed for different purposes. Among them, the "Flash ADC" architecture is the fastest, because of its parallel nature. In a Conventional Flash ADC, analog to digital conversion starts with comparing simultaneously the analog input voltage Vj_n with a L number of fixed voltage levels through L comparators, (L = 2") simultaneously, which gives what is known as 'Thermometer-Code', combination of series- of-zeros and series-of-ones, e.g., 000...001 1..1 1 1. Thermometer Code is then converted into One-Out-Of-N-Code and then to Binary Code. Since the analog input voltage signal is fed to all the comparators simultaneously, it leads to large input capacitance which is a major drawback of a Conventional Flash ADC along with the large silicon area. The high input capacitance, in turn, demands for pre power amplifiers to boost analog input signal power before being fed to the Comparators Array. Further, the Conventional Flash ADC contains 'analog comparators' made out of operational amplifiers. To maintain a healthy Signal to Noise Ratio(SNR), the size of operational amplifiers and in turn the MOSFETs should be made as large as possible, demanding large silicon area, which is an opposite trend to the constantly improving VLSI technologies. Thus, all the advantages of the best available VLSI technology at a time cannot be used for fabrication of analog components. In addition, system integration is a major challenge when analog components have to be integrated into a single silicon chip along with digital components. Also, the accuracy of the Conventional Flash ADC is very much dependent on the precision of the reference DC voltage, which has to be carefully designed. In addition, in a Conventional Flash ADC, there are three conversion stages, the one, Analog to Thermometer Code, the second, Thermometer Code to One-Out- of-N-Code, and the third, One-Out-of-N-Code to Binary Code. Out of these, in the first stage, Thermometer Code is prone to be affected by bubbles due to the meta-stability errors in the comparators demanding for costly bubble error and sparkle error corrector schemes.

In this disclosure, we propose a radically different kind of Flash ADC which alleviates most of the problems of the Conventional Flash ADC. This new topology is theoretically simple, sound and instead of working around the problems of the Conventional Flash ADC, a paradigm shift in the design approach has been taken. It can be tested for preliminary functioning using simulation software like Multisim 2001 textbook version from Interactive Image Technologies Ltd.

Disclosure of the Invention This disclosure is about a type of flash ADC, called 'Serially Fed Flash ADC, where the analog input voltage signal Vj_n is fed to a single node of a 'Resistor Ladder' consisting of L (= 2ⁿ ) voltage taps. Two possible Embodiments of this invention are disclosed here.

Embodiment 1

In the Embodiment 1, voltages tapped in the Resistor Ladder are fed to an XOR Device Array (XDA), which contains L + 1 XOR2 devices (L = 2"). The output of the XDA is a One-Out- Of-N-Code which can be easily encoded to Binary Code.

The central working principle of the Embodiment 1 of this ADC is in the 'Thresh-hold behavior' of an XOR2 device, with a 'Thresh-hold voltage', V_th and all the XOR2 devices in the XDA are of the same V_th. If V_a and V_b are two analog inputs to an XOR2 device, then, for (i). V_a > V_th and V_b < V_th , Similarly, for (ii). V_a < V_th and V_b > ν_Λ, the outputs of the XOR2 is HIGH(or 1), This is called as 'Thresh-hold behavior'. The Resistor Ladder, containing L + 1 resistors, is designed such that, for a step change in V_ln by ± ? , the voltage level equal to Thresh-hold voltage V^ of the XOR2 device climbs up or down inside the Resistor Ladder by one resistor step.

Moreover, the connection of the XOR2 devices in the XDA is also such that, at a time, only one XOR2 device shall have the voltage level equal to Thresh-hold voltage, V_th lying in between two of its inputs. For any other XOR2 device in the XDA, either both inputs are greater than V_th or both inputs are lesser than V_th. Thus, only one XOR2 device is at output state 1 (or HIGH) out of L + 1 XOR2 devices in the XDA.

This generates One-Out-Of-N-Code directly from the analog input without resorting to Thermometer Code in between, leading to faster conversion to Binary Code than in the Conventional Flash ADC. In addition, the Resistor Ladder, XDA, and One-Out-Of-N-Code to Binary Code Converter are all digital circuits making this ADC, totally an 'All Digital ADC, which is a huge advantage for system integration into a single silicon chip, along with the digital components.

To improve the input reception and rejection capacity of the XOR2 devices in the XDA, an additional 'Buffer Array' can be inserted between the Resistor Ladder and XDA. A Buffer is nothing but two inverters cascaded together with sharper transfer characteristics and the ones used here are of Thresh-hold voltages same as the XOR2 devices in the XDA. Depending on the requirement, inside the Buffer Array, many stages of buffers can be used in cascade, forming a 'Buffer Stack'. Since, Buffer Array has the capacity to condition the voltages tapped from the Resistor Ladder into 'logically better acceptable levels' to the XOR2 devices, effectively, Buffer Array produces Thermometer Code.

Similarly, to generate Thermometer Code from the voltages tapped from the Resistor Ladder, 'AND gate Array' can also be used in the place of Buffer Array. Main attraction of this ADC is that all the Buffers and XOR2 devices are identical in every respect, thus, increasing the 'Regularity' of the VLSI silicon chip design. There is also no demand as to what should be the Thresh-hold voltage V_tll by this topology, rather, whatever Vth the best available VLSI technology at the time produces is taken. This, Thresh-hold voltage V_th is taken into consideration during the Resistor Ladder design.

Embodiment2

In the Embodiment2, The Resistor Ladder is same as in the Embodimentl, but, the voltages tapped in the Resistor Ladder are fed to a Comparator Array (CA), which contains L ( where, L - 2ⁿ ) Comparators. The output of the CA is a Thermometer-Code which can be encoded to One-Out-Of-N-Code and then to Binary Code.

The central working principle of the Embodiment2 of this ADC is the Comparator Array with all the comparators connected to a single 'Thresh-hold voltage' (or 'Reference voltage'), V_th. As in the case of the Embodimentl, the Resistor Ladder, containing L + 1 resistors, is designed such that, for a step change in Vj_n by ±? , the voltage level equal to Thresh-hold voltage V_th of the Comparator Array climbs up or down inside the resistor ladder by one resistor step.

The connection of the Comparator Array to the Resistor Ladder is also such that, as the voltage levels in successive tapping points in the ladder, V₀, Vi, . . . , V_(L-i), raise, Thermometer Code is generated at the output of the Comparator Array. This Thermometer Code is converted into One-Out-Of-N-Code and, then to Binary Code through proper or suitable logic circuits already known to the 'skilled persons' in the 'Art'.

Resistor Ladder Design

In both the Embodiments, specification for an ADC is provided as follows, FIG 2B,

(a), n , the Resolution of the ADC in positive integers (b). Vin_(max), in Volts, maximum analog input voltage signal (c). V_th, in Volts, the Thresh-hold voltage of the XOR2 devices in the XDA (for

Embodiment 1) or the Comparator Array (for Embodiment2).

Then, Δ= "^¹"³*^ a step change in the input voltage signal Vj_n 200 is calculated, where L

Ju

= 2". Thus, the input voltage signal, V;_n 200 is restricted to be in the range of values, [ 0 <= Vjn <= Vi_n(raaX) ]. Given, R = [ Ro + R_\ + R₂ + + R< L - I > + ovf ], the total resistance of the ladder, the resistors, R₀, R_{l 5} R₂, , R(L-I>, and Rovf, FIG 2 A, the successive resistors in the ladder are calculated using the following routine, FIG 2B :

(i) . Select a suitable value for R.

(ii) . For k = 0, 1, 2, 3, , (L-l), calculate, iteratively, R_k = [ Z_k - Z_(k-1)]

Where, Z_k = ^(k+1)AR , with Z__v = 0

' ^K (k+l)A+V_th ' ¹

Brief Description of the Drawing

FIG 1 , is about an n-bit Conventional Flash ADC, Prior Art FIG 2, The Resistor Ladder in FIG 2A and the Resistor Ladder Design Calculation routine in FIG 2B

FIG 3, is about an n-bit version of Embodiment 1 of the Serially Fed Flash ADC FIG 4, is about the 3-bit version of Embodimentl of the Serially Fed Flash ADC FIG 5, is about an n- bit version of Embodiment2 of the Serially Fed Flash ADC FIG 6, is about the 3-bit version of Embodiment2 of the Serially Fed Flash ADC FIG 7, is about an n-bit version of Embodiment 1 of the Serially Fed Flash ADC with additional 'Buffer Array' (BA) to improve the input reception of the 'XOR Device Array' (XDA), FIG 8, is about the 3-bit version of FIG 7

FIG 9, is about an n-bit version of Embodiment 1 of the Serially Fed Flash ADC, where Full XOR2 devices of the XDA is replaced by Half XOR2 devices, FIG 10, is about the 3-bit version of FIG 9.

FIG 1 1, Shows the "Thresh-hold behavior' of the XOR2 device. FIG 11a, when V_a < V_th and V is varied from 0V to a final HIGH value and FIG 1 lb when V_a > V_th and V_b is varied from 0V to a final HIGH value. FIG 12, is about an n-bit version of Embodiment 1 of the Serially Fed Flash ADC with additional 'AND gate Array' to improve the input reception of the 'XOR Device Array' (XDA), FIG 13, is about the 3-bit version of FIG 12

FIG 14, is about tables containing voltage tapped in the Resistor Ladder. FIG 14 A,

Best mode to perform the Invention

Embodiment 1

The best mode to perform the Emobodimentl of this ADC is explained with a 3-bit case as the example, FIG 4. FIG 3 shows the n-bit version of the Embodiment 1.

Consider (i). n = 3, the resolution of the ADC (ii). V;_{n (max}) = 10V, maximum analog input voltage signal, Vj_n 400 (iii). Δ = ^Vin<-^max^ =— = 1.25V, a step change in the input voltage

L 8

signal, V_in 400 (iv). V_th= 2.5V, the Thresh-hold voltage of the XOR2 devices 430-0 to 430-8 in the XDA 430, selected for illustration. These specifications work for the XOR2 gates of IC 7486 in Multisim. Thus, the input voltage signal, Vj_n 400 is restricted to be in the range of values, [ 0 <= Vj_n <= Vj_n(_max) ]. It should be understood that this restriction is only for the explanation and as such invention is applicable to any n greater than 1 and any Vi_n(maX) greater than OV and V_th greater than OV. ν_Λ 420, the DC voltage kept in series with V_in 400 in the FIG 4, is equal to the Thresh-hold voltage of the XOR2 devices 430-0 to 430-8 in the XDA 430, always.

For this specification, the values of the resistors in the Resistor Ladder 410 calculated using the routine in FIG 2B, are as follows: R₀ = 0.3333R, Ri = 0.1667R, R₂ = 0.1000R, R₃ = 0.0667R, R4 = 0.0476R, R₅ = 0.0357R, R6 - 0.0278R, R₇ = 0.0222R, R_ovf = 0.2000R, where R is the total sum of all the resistors in the ladder. When Vi_n 400 takes the values in integral multiples of ? , the voltages at different taps in the Resistor Ladder 410, V₀, Vj, . . . . , V₇, and V_0Vf are given in the FIG 14A. The FIG 14B shows the voltage information V₀, Vi, . . . . , V₇, and V_ovf , where every voltage is compared with V_th 420. FIG 14C shows the levels of voltage tappings in the Resistor Ladder 410 with reference to V_th 420 when Vj_n 400 lies in the interval [k? < V_in < = (k+1)? ], for k = 0, 1, 2, , 8 and for V_in > 9? .

(1) . When V_in = 0V, V₀ = V,_h 420 and all the other voltages, Vi through V₇, are less than ν_Λ 420 But, when 0 < V_in < = ? , V₀ > V_th 420 and all the other voltages, Vi through V₇, are less than V_th 420. Thus, for the XOR2 device 430-0, the V_th lies between its two inputs, V₀ and V). For all other XOR2 devices, 430-1 through 430-7 both inputs are less than V_ft 420. Therefore, Y0 = 1 , Yl = 0, Y2 = 0, Y3 = 0, Y4 = 0, Y5 = 0, Y6 = 0 and Y7 = 0, i.e, Y - [ 1 0 0 0 0 0 0 0 ] 440 and [ B₀ = 0, B, = 0, B₂ = 0 ] 480.

(2) . When V_in = ? = 1.25V, V₀ > V_ft 420, V_{ = V_th 420, and all the other voltages, V₂ through V₇, are less than V_th 420. But, when ? < V_in < = 2? , both V₀ and V! are greater than ν_Λ 420, and all the other voltages, V₂ through V₇, are less than V_tll 420. Thus, for the XOR2 device 430-0 both the inputs are greater than V_th 420, for the XOR2 device 430-1 the ν_Λ 420 lies between two of its inputs, Vi and V₂. For all other XOR2 devices, 430-2 through 430-7 both inputs are less than V_th 420. Therefore, Y0 = 0 , Yl = 1 , Y2 = 0, Y3 = 0, Y4 = 0, Y5 = 0, Y6 = 0 and Y7 = 0, i.e, Y = [ 0 1 0 0 0 0 0 0 ] 440 and [ B₀ = 0, Bi = 0, B₂ = 1 ] 480.

(3) . When V_in = 2? = 2.5V, both V₀ and Vi are greater V,_h, V₂ = V_th 420, and all the other voltages, V₃ through V₇, are less than V_th 420. But, when 2? < V_in < = 3? , all the voltages V₀ through V₂ are greater than V_th 420, and all the other voltages, V₃ through V₇, are less than ν_Λ 420. Thus, for the XOR devices 430-0 and 430-1, both the inputs are greater than V_th420, for the XOR2 device 430-2 the V_th420 lies between two of its inputs, V₂ and V₃. For all other XOR2 devices, 430-3 through 430-7 both inputs are less than V_th 420. Therefore, Y0 = 0, Yl = 0, Y2 = 1, Y3 = 0, Y4 = 0, Y5 = 0, Y6 = 0 and Y7 = 0, i.e, Y = [ 0 0 1 0 0 0 0 0 ] 440 and [ B₀ = 0, B, = 1, B₂ = 0 ] 480.

(4) . When V_in = 3? = 3.75V, all the voltages V₀ through V₂ are greater V_th, V₃ = V_th 420, and all the other voltages, V₄ through V₇, are less than V^ 420. But, when 3? < V_in < = 4? , all the voltages V₀ through V₃ are greater than V^ 420, and all the other voltages, V₄ through V₇, are less than V_th 420. Thus, for the XOR2 devices 430-0 through 430-2, both the inputs are greater than V_th 420, for the XOR2 device 430-3 the ν_Λ 420 lies between two of its inputs, V₃ and V₄. For all other XOR2 devices, 430-4 through 430-7 both inputs are less than V_th 420. Therefore, Y0 = 0, Yl = 0, Y2 = 0, Y3 = 1, Y4= 0, Y5 - 0, Y6 = 0 and Y7 = 0, i.e, Y = [ 0 0 0 1 0 0 0 0 ] 440 and [ Bo = 0, Bi = 1, B₂ = 1 ] 480.

(5) . When V_in = 4? = 5 V, all the voltages V₀ through V₃ are greater V_th 420, V₄ = V^ 420, and all the other voltages, V₅ through V₇, are less than V_th 420. But, when 4? < V_jn < = 5? , all the voltages V₀ through V₄ are greater than V^ 420, and all the other voltages, V₅ through V₇, are less than V_th 420. Thus, for the XOR2 devices 430-0 through 430-3, both the inputs are greater than V_th 420, for the XOR2 device 430-4 the V_th 420 lies between two of its inputs, V₄ and V₅. For all other XOR2 devices, 430-5 through 430-7 both inputs are less than V_ft 420. Therefore, Y0 = 0, Yl = 0, Y2 = 0, Y3 = 0, Y4 = 1, Y5 = 0, Y6 = 0 and Y7 = 0, i.e, Y = [ 0 0 0 0 1 0 0 0 ] 440 and [ Bo = 1, B, = 0, B₂ = 0 ] 480.

(6) . When V_in = 5? = 6.25V, all the voltages V₀ through V₄ are greater V_ft420, V₅ = V_th 420, and both V₆ and V₇ are less than V_ft 420. But, when 5? < V_in < = 6? , all the voltages V₀ through V₅ are greater than V^ 420, and all the other voltages, V₆ through V₇, are less than V_th 420. Thus, for the XOR2 devices 430-0 through 430-4, both the inputs are greater than ν_Λ 420, for the XOR2 device 430-5 the V_th 420 lies between two of its inputs, V₅ and V₆. For all other XOR2 devices, 430-6 through 430-7 both the inputs are less than V_th 420. Therefore, Y0 = 0, Yl = 0, Y2 = 0, Y3 = 0, Y4= 0, Y5 = 1, Y6 = 0 and Y7 = 0, i.e, Y = [ 0 0 0 0 0 1 0 0 ] 440 and [ Bo = 1, Bi = 0, B₂ = 1 ] 480. (7) . When V_in = 6? = 7.5V, all the voltages V₀ through V₅ are greater V_th 420, V₆ = V* 420, and V₇ is less than V_th 420. But, when 6? < V_in < = 7? , all the voltages V₀ through V₆ are greater than V_th 420, and V₇ is less than ν_Λ 420. Thus, for the XOR2 devices 430-0 through 430-5, both the inputs are greater than V_th 420, for the XOR2 device 430-6 the ν_Λ 420 lies between two of its inputs, V₆ and V₇. For the XOR2 device 430-7 both inputs are less than V_A 420. Therefore, Y0 = 0, Yl = 0, Y2 = 0, Y3 = 0, Y4 = 0, Y5 = 0, Y6 = 1 and Y7 = 0, i.e, Y = [ 0 0 0 0 0 0 1 0 ] 440 and [ B₀ = 1, B, = 1, B₂ = 0 ] 480.

(8) . When V_in = 7? = 8.75V, all the voltages V₀ through V₆ are greater V_ft 420, V₇ = V_th 420. But, when 7? < V_in < = 8? , all the voltages V₀ through V₇ are greater than V,_h 420. Thus, for the XOR2 devices 430-0 through 430-6, both the inputs are greater than V_th 420, for the XOR2 device 430-7 the V_th420 lies between two of its inputs, V₇ and 0V (GND). Therefore, Y0 = 0, Yl = 0, Y2 = 0, Y3 = 0, Y4= 0, Y5 = 0, Y6 = 0 and Y7 = 1, i.e, Y = [ 0 0 0 0 0 0 0 1 ] 440 and [ B₀ = 1, Bi = 1, B₂ = 1 ] 480.

(9) . when V_in > 8? = V_in(max) = 10V, V₀ through V₇ are greater than V_th 420 and V_0Vf > ν_Λ 420. Now for XOR2 device 430-8, V_th 420 lies between V_ovf and 0V (GND). Therefore, B_ovf

= 1 , which indicate the overflow of the analog input voltage. Also, for the XOR2 device 430- 7, V_th 420 lies between two of its inputs V₇ and OV(GND), therefore, Y7 - 1, producing the maximum possible One-Out-Of-N-Code, i.e, Y = [ 0 0 0 0 0 0 0 1 ] and [ B₀ = l, B, = l, B₂ = 1 ]· (10). In general, when V_in 400 is lesser than 8? = V_in(max) = 10V, both the inputs of XOR2 device 430-8 are less than V¾ 420, therefore, B_ovf = 0, indicating that Vj_n 400 is within the maximum allowed level.

The output of the XDA 430, i.e, Y 440, which is a One-Out-Of-N-Code, can be encoded to Binary Code using many possible methods already known to skilled persons in the art, one of them being, Binary ROM Encoder 450.

The internal architecture of the ROM Encoder 450 is such that to the line corresponding to Y0, memory cells producing the Binary Code [ B₀ = 0, Bi = 0, B₂ = 0 ] is kept, the line corresponding to Yl, memory cells producing the Binary Code [ B₀ = 0, Bi = 0, B₂ = 1 ] is kept , to the line corresponding to Y2, memory cells producing the Binary Code [ B₀ = 0, B_t = 1 , B₂ = 0 ] is kept, to the line corresponding to Y3, memory cells producing the Binary Code [ B₀ = 0, B} = 1, B₂ = 1 ] is kept, to the line corresponding to Y4, memory cells producing the Binary Code [ B₀ = 1, Bi = 0, B₂ = 0 ] is kept, to the line corresponding to Y5, memory cells producing the Binary Code [ B₀ = 1, Bi = 0, B₂ = 1 ] is kept, to the line corresponding to Y6, memory cells producing the Binary Code [ B₀ = 1, B_\ = 1, B₂ = 0 ] is kept and to the line corresponding to Y7, memory cells producing the Binary Code [ B₀ = 1, Bi = 1, B₂ = 1 ] is kept.

Very importantly, the XDA 430 need not contain full XOR2 devices, implementing Y = ab + ab, instead, Half XOR2 devices of the same V_th are sufficient, i.e, to implement, Y = ab, as shown in the FIG 9 and FIG 10, with the working same as in FIG 3 and FIG 4 circuits. Half XOR2 devices in the place of Full XOR2 devices is sufficient for this circuit since (0,0), (1,0) and (1,1) are the only three input combinations appearing and (0,1) is never an input combination from the Resistor Ladder. Embodiment2

In the Embodiment 1, XDA can be replaced by a Comparator Array (CA) which is used in the conventional flash ADC. With this and other minor modifications, we explain the working of the best way to implement Embodiment2, with a specific example of 3-bit ADC, FIG 6. FIG 5 shows the n-bit version of the Embodiment2. Consider (i). n = 3, the resolution of the ADC (ii). Vj_n (_maX) = 10V, maximum analog input voltage signal (iii). ? = Vj_n(max) / L = 10 / 8 = 1.25V, a step change in the input voltage signal, Vin (iv). V_th = 2.5V, the reference voltage for the Comparator Array (selected). Thus, the input voltage signal, Vi„ is restricted to be in the range of values, [ 0 <= V;_n <= Vi_n(max) ]. It should be understood that this restriction is only for the explanation and as such invention is applicable to any n greater than 1 and any Vj_n(max₎ greater than 0V and V_th greater than 0V.

For this specification, the resistors calculated in the Resistor Ladder 610 will be exactly same as those in the Resistor Ladder 410. It should be understood that different specifications will lead to different resistor values, but for the uniformity of this document same specification is maintained for both the Embodiments. With this, FIGs 14A, 14B and 14C show the values of the voltage tappings as in the case of Embodiment 1.

(1) . When Vj„ = 0, all the voltages V₀ through V₇, are less than V_th. Therefore, all the Comparators 140-0 through 140-7 produce output 0. Thus, [ TO = 1, Tl = 0, T2 = 0, T3 = 0, T4 = 0, T5 = 0, T6 = 0, T7 = 0] , [ O0 = 1, 01 = 0, 02 = 0, 03 = 0, 04 = 0, 05 = 0, 06 = 0, 07 = 0 ] and [B₀ = 0, Bi = 0, B₂ = 0]. This remains the Binary output as long as the Vj„ is less than or equal to ? , i.e, 0 < V_in < =? .

(2) . When Vi_n = ? = Vt_h, V₀ = V_th, and all the other voltages, Vi through V₇, are less than Vt_h. But, when ? < V;_n < = 2? , V₀ > V_tll, and all the other voltages, V_\ through V₇, are less than V_th. Therefore, Comparator 140-0 produces output 1 and all the Comparators 140-1 through 140-7 produce output 0. Thus, [ TO = 1, Tl = 1, T2 = 0, T3 = 0, T4 = 0, T5 = 0, T6 = 0, T7 = 0] , [ O0 = 0, Ol = 1, 02 = 0, 03 = 0, 04 = 0, 05 = 0, 06 = 0, 07 = 0 ] and [B₀ = 0, B, = 0, B₂ = l].

(3) . When V;_n = 2? , V₀ is greater than V_th, Vi = ν_Λ, and all the other voltages, V₂ through V₇, are less than V_th. But, when 2? < V;_n < = 3? , V| > V_th, and all the other voltages, V₂ through

V₇, are less than V_ti,. Therefore, Comparators 140-0 and 140-1 produce output 1 and all the Comparators 140-2 through 140-7 produce output 0. Thus, [ TO = 1, Tl = 1, T2 = 1, T3 = 0, T4 = 0, T5 = 0, T6 = 0, T7 = 0] , [ O0 = 0, Ol = 0, 02 = 1, 03 = 0, 04 = 0, 05 = 0, 06 = 0, 07 = 0 ] and [Bo = 0, Bi = 1, B₂ = 0]. (4). When V_in = 3? , V₀ and Vi are greater than V_th, V₂ = V_th, and all the other voltages, V₃ through V₇, are less than V_th. But, when 3? < Vj_n < = 4? , V₂ > V_th, and all the other voltages, V₃ through V₇, are less than V_th. Therefore, Comparators 140-0 through 140-2 produce output 1 and all the Comparators 140-3 through 140-7 produce output 0. Thus, [ TO = 1, Tl = 1, T2 = 1, T3 = 1, T4 = 0, T5 = 0, T6 = 0, T7 = 0] , [ O0 = 0, Ol = 0, 02 = 0, 03 = 1, 04 = 0, 05 = 0, 06 = 0, 07 = 0 ] and [B₀ = 0, Bi = 1, B₂ = 1].

(5). When Vj_n = 4? , V₀ through V₂ are greater than V_ft, V₃ = V_th, and all the other voltages, V₄ through V₇, are less than V,_h. But, when 4? < V_in < = 5? , V₃ > V_th, and all the other voltages, V₄ through V₇, are less than V_th. Therefore, Comparators 140-0 through 140-3 produce output 1 and all the Comparators 140-4 through 140-7 produce output 0. Thus, [ TO = 1, Tl = 1, T2 = 1, T3 = 1, T4 = 1, T5 = 0, T6 = 0, T7 = 0] , [ 00 = 0, Ol = 0,02 = 0, 03 =

0, 04 = 1, 05 = 0, 06 = 0, 07 = 0 ] and [B₀ = 1, B, = 0, B₂ = 0].

(6). When Vj_n = 5? , V₀ through V₃ are greater than V_th, V₄ = and all the other voltages V₅ through V₇, are less than V_th. But, when 5? < Vj_n < = 6? , V₄ > V_tll, and all the other voltages, V₅ through V₇, are less than ν_Λ. Therefore, Comparators 140-0 through 140-4 produce output 1 and all the Comparators 140-5 through 140-7 produce output 0. Thus, [ TO = 1, Tl = 1, T2 = 1, T3 = 1, T4 = 1, T5 = 1, T6 = 0, T7 = 0] , [ O0 = 0, Ol = 0, 02 = 0, 03 = 0, 04 = 0, 05 =

1, 06 = 0, 07 = 0 ] and [B₀ = 1, Bi = 0, B₂ = 1]. (7). When V;_n = 6? , V₀ through V₄ are greater than V_th, V = V_th, V₆ and V are less than V_th. But, when 6? < Vj_n < = 7? , V₅ > Vth, and V₆ and V₇ are less than V_th. Therefore, Comparators 140-0 through 140-5 produce output 1 and the Comparators 140-6 and 140-7 produce the output 0. Thus, [ TO = 1, Tl = 1, T2 = 1, T3 = 1, T4 = 1, T5 = 1, T6 = 1, T7 = 0] , [ O0 = 0, Ol = 0, 02 = 0, 03 = 0, 04 = 0, 05 = 0, 06 = 1, 07 = 0 ] and [B₀ = 1, Bi = 1, B₂ = 0].

(8) . When V_in = 7? , V₀ through V₅ are greater than V_th, V₆ = V_th, V₇ is less than V_A. But, when 7? < Vj_n < = 8? , V₆> Va,. Therefore, Comparators 140-0 through 140-6 produce output 1 and comparator 140-7 produces 0. Thus, [ TO - 1, Tl = 1, T2 = 1, T3 = 1, T4 = 1, T5 = 1, T6 = 1, T7 = 1] , [ O0 = 0, Ol = 0, 02 = 0, 03 = 0, 04 = 0, 05 = 0, 06 = 0, 07 = 1] and [B₀ = l,Bi = 1,B₂= 1].

(9) . When Vin > 8? , Comparators 140-0 through 140-6 produce output 1. Thus, [ TO = 1, Tl = 1, T2 = 1, T3 = 1, T4 = 1, T5 = 1, T6 = 1, T7 = 1] , [ O0 = 0, Ol = 0, 02 = 0, 03 = 0, 04 = 0, 05 = 0, 06 = 0, 07 = 1] and [B₀ = 1, Bi = 1, B₂ = 1]. In addition, V_ovf > V_th, therefore, comparator 140-7 produces output 1, thus B_ovf = 1, indicating the overflow of the Vj_n above the allowable maximum input voltage.

(10) . In general, when Vj_n < = 8? , V_ovf < = V_th, therefore, B_ovf= 0, indicating that Vj_n is within the allowable maximum range.

Claims

Claims We claim,

1. A Resistor Ladder, which is connected to a varying input voltage Signal Vi„ in series with a DC voltage V_tll, Completing an 'Electrical Loop' containing (i) Vth, (ii) Vj_n and (iii) The Resistor Ladder in that sequence,

With L+l series resistors (for L > 1 ) R₀, Ri , ,R(L-_I), Rovf , with consecutive L+l voltage tappings V₀, Vi , , V(L-I), V_ovf, with 'V₀ at the junction of Vj_n and the resistor Ro', with every, 'V_k at the junction of resistors R₍k-i) and R_k for k = 1, 2, 3, . . . . , (L-l)' and with, 'V_0Vf at the junction of R₍L_ i ₎ and Ro_Vf ' ,

The values of the resistors R₀, Ri, ,R(L-i), Rovf, calculated such that for a selected resistor

R = Ro + Ri + R₂ + + R(L- i ) + Rovf , the k^th resistor R_k = [ Z_k - Z_(k-i)], where

Z_k = ₍-_k+1-_)A+v— _> with Z__! = 0, for k = 0, 1, 2, 3 , (L-l), and the input step size

Δ = ^v'^{n( ax)} , where Vj_n(max) is the maximum value of Vj_n and Ro_Vf = [ R - Z_(L-i₎ ],

Wherein, the resistors R₀, Ri, ,R(L-I >, Rovf calculated are such that for a change in Vj_n by ±? , the voltage level equal to V_th climbs up or down inside the Resistor Ladder by one resistor step,

And, V_th can be an algebraic sum of many DC voltages, i.e kept or connected in series, and Vj_n can be an algebraic sum of many varying input voltage signals, i.e kept or connected in series.

2. An n-bit ( n > 0 ) Analog to Digital Converter comprising of a Resistor Ladder and the Electrical Loop of Claim 1, with L replaced by 2ⁿ, and An Array of L+l XOR2 devices (XDA), the inputs of k"¹ XOR2 device connected to voltage tappings V_k and V_(k+i₎ , for k = 0, 1, . . . . , (L-2) and the inputs of (L-l)* XOR2 device are connected to the voltage tapping V(L-i) and GND(OV), the inputs of L^th XOR2 device are connected to the voltage tapping V_ovf and GND, where the output of the XDA is an One-Out-Of-N-Code which can be encoded to Binary Code, the output of the L XOR2 device giving B_0Vf, the overflow indication of Vj_n

3. An Analog to Digital Converter of Claim2, where a 'Buffer Array' with L+l 'Buffer stacks' is included between Resistor Ladder and the XDA, the input of every k^th Buffer Stack connected to voltage tapping V_k for k = 0, 1, 2 (L-l) and the input of L* Buffer Stack connected to V_ovf, and the outputs of every k^th and (k+l)^th Buffer Stacks connected to the inputs of k^th XOR2 device in the XDA, for k = 0, 1, 2, , (L-2) and the inputs of (L-l)*

XOR2 device connected to the output of (L-l)¹¹¹ Buffer Stack and GND, the inputs of L* XOR2 device connected to the output of L^th Buffer Stack and GND.

4. An Analog to Digital Converter of Claim2, where an 'AND Gate Array' with L+l two- input AND gates (AND2) is included between the Resistor Ladder and the XDA, the two inputs of every k^th AND2 is connected to the voltage tapping pairs [ Vu , V_(k+1) ], for k = 0, 1, 2, . . . . , (L-2), the two inputs of the (L -l)^th AND2 is connected to the voltage tapping V_{( L-}i ) and logic 1 ( or HIGH ), the two inputs of the L^th AND2 is connected to the voltage tapping V_ovf and logic 1 ( or HIGH ), The XOR devices in the XDA are connected to the outputs of the AND Gate Array as, with, the two inputs of the 0^th XOR2 is connected to the logic 1 ( or HIGH ) and the output of 0^th AND2, the two inputs of every k* XOR2 connected to the outputs of the (k-l)^th and k^th AND2 gates for k = 1, 2,3, , L, The output of the L^th

XOR2 giving the output B_ovf , indicating the overflow of Vj_n over Vj_n(max).

5. Analog to Digital Converter of Claim2 or Claim3 or Claim4, where in XOR2 device in XDA is replaced by the 'Half XOR2 Devices' implementing only the one min-term corresponding to the input combination ( 1, 0 ) out of four input possibilities ( 0 , 0 ), ( 0 , 1), ( 1 , 0 ) and ( 1 , 1 ), i.e, Y = ab

6. An n-bit ( n > 0 ) Analog to Digital Converter comprising of a Resistor Ladder and the Electrical Loop of Claiml, with L replaced by 2ⁿ, and a Comparator Array (CA) - An Array of L number of Analog Comparators, which are generally two input devices with an inverting and a non-inverting input, with inverting inputs of all the Comparators in the Array are connected to a single DC reference or Thresh-hold voltage V_th, and non-inverting inputs of every k Comparator connected to the (k+1) voltage tappings V_(k+i>, for k = 0, 1, 2, . . . . , (L-2), and the non-inverting input of (L-l)^th Comparator connected to the voltage tapping V_ovf, as a whole the output of the array is taken, The output of the CA producing what are known in most of the scientific and Engineering literatures as 'Thermometer Code', which can be further converted into Binary Code through proper electronic circuits and the output of the (L-l)^th Comparator giving the overflow indication of Vj_n over Vi_n(_max).