WO2012143944A2

WO2012143944A2 - Multi-host nand flash controller

Info

Publication number: WO2012143944A2
Application number: PCT/IN2012/000274
Authority: WO
Inventors: Balaji Kanigicherla; Siva Raghuram VOLETI; Krishna Mohan Tandaboina
Original assignee: Ineda Systems Pvt. Ltd
Priority date: 2011-04-18
Filing date: 2012-04-17
Publication date: 2012-10-26
Also published as: WO2012143944A3

Abstract

Described herein is a multi-host computing system (200) having multiple host processors running different operating systems. The described multi-host computing system (200) comprises a multi-host NAND flash controller (202) to allow sharing of a NAND flash device (108) among the multiple host processors. The described multi-host NAND flash controller (202) may include host interaction components, host command switching logic (310), and NAND command logic (316) to enable sharing of the NAND flash device (108).

Description

MULTI-HOST NAND FLASH CONTROLLER

FIELD OF INVENTION

[0001] The present subject matter, in general, relates to a NAND flash controller and in particular to a NAND flash controller for multi-host computing systems running multiple operating systems.

BACKGROUND

[0002] Computing systems, such as laptops, netbooks, workstations, and desktop computers typically include a central processing unit (CPU), also known as a host processor, running an operating system for carrying out various functionalities of the computing system. The host processor generally includes softwares, known as system drivers, for interacting with and controlling various peripheral devices connected to the computing systems for providing various functionalities of the computing systems. The peripheral devices include, for instance, mass storage devices and media devices such as audio players. For example, the mass storage devices may be NAND flash devices, such as USB based flash drives and SD based memory cards.

[0003] Further, the system drivers generally interact with the peripheral devices through hardware interfaces, known as device controllers provided in the computing systems for controlling the peripheral devices. For example, the computing systems include NAND flash controllers for controlling the NAND flash devices connected to the computing systems.

[0004] Further, with advancement in computing technologies a single computing system may include two host processors having two separate operating systems. In order to reduce system costs and power consumption both the host^' processors are configured to share the same peripheral devices and device controllers. Sharing the same peripheral devices and device controllers, however, may not be possible in cases when both the host processors need to access the same peripheral device at the same time. A second host processor, which was not initially using a particular peripheral device, may thus need to wait for a first host processor, presently using the peripheral device, to release the peripheral device, thus effecting experience of a user using the second host processor.

SUMMARY

[0005] This summary is provided to introduce concepts related to a NAND flash controller to allow sharing of NAND flash devices by more than one host in multi-host computing systems running multiple operating systems which are further described below in the detailed description. This summary is not intended to identify essential features of the present subject matter nor is it intended for use in determining or limiting the scope of the present subject matter. These and other features, aspects, and advantages of the present subject matter will be better understood with reference to the following description.

[0006] In one implementation, the NAND flash controller allows host processors of multi-host computing system to share a single NAND flash device. The NAND flash controller receives operational commands from all the host processors simultaneously and executes the operational command one by one based on arbitration logic.

BRIEF DESCRIPTION OF DRAWINGS

[0007] . The above and other features, aspects and advantages of the subject matter will be better understood with regard to the following description and accompanying drawings, where:

[0008] Figure 1 illustrates system architecture for implementing a NAND flash controller in a conventional single host computing system.

[0009] Figure 2 illustrates system architecture for implementing a multi-host

NAND flash controller in a multi-host computing system, according to an embodiment of the present subject matter.

[00010] Figure 3 illustrates a block diagram representing components of the multi- host NAND flash controller for the multi-host computing system, according to an embodiment of the present subject matter. [00011] Figure 4 illustrates an exemplary method for sharing a NAND flash device through a NAND flash controller in a multi-host computing system, according to an embodiment of the present subject matter.

DETAILED DESCRIPTION [00012] The present subject matter relates to a flash controller for multi-host computing systems running multiple operating systems. In one implementation, the flash controller is a NAND flash controller configured to allow sharing of NAND flash devices between multiple host processors.

[00013] Computing systems, such as laptops, netbooks, workstations, and desktop computers have nowadays become an essential part of a user's life. A user may use the computing systems for various purposes, such as to prepare and edit various documents, play music files, and watch videos. The documents, the music files, and the videos are generally stored on mass storage devices, such as hard disks and flash based memory devices connected to the computing systems. The flash based memory devices may be, for example, NAND flash devices, such as USB based flash drives and SD based memory cards. The NAND flash devices are non volatile devices which can be electronically erased and programmed and generally used for data storage and data transfer purposes between computing systems and various media devices. The NAND flash devices are based on NAND flash memory which stores data in group of memory cells generally made from floating gate transistors.

[00014] Further, the NAND flash devices are accessed as block devices similar to hard disk. A NAND flash device typically consists up to 8K blocks and each block consists of pages for storing data. Each time some data needs to be stored in the NAND flash device an erase cycle needs to be performed on the NAND flash device. Thus, if a word needs to be replaced in a given page, the entire block where the word exists needs to be erased first and then the corresponding word is written in the page. Further, latest NAND flash devices are organized in the form of multiple Logic Units (LUNs) such that operations are performed concurrently on each LUN thus improving overall performance of the NAND flash devices.

[00015] Conventional computing systems typically include a NAND flash controller for interfacing the NAND flash devices with the computing systems. The NAND flash controller is typically connected to a central processing unit, also known as host processor, of the computing system. The host processor may be understood as the component of a computing system provided for carrying out the computing system's functions. The host processor generally includes an operating system and softwares, known as system drivers, such as flash drivers for interacting with and controlling the NAND flash controller and in turn the NAND flash devices. The NAND flash driver interacts with the NAND flash controller to provide operational commands, such as write command and read command to the NAND flash controller for either writing data in or reading data from the NAND flash devices.

[00016] Typically, the NAND flash controller works with a single host processor and operates on predefined protocols. Figure 1 illustrates a conventional computing system 100 implementing a NAND flash controller 102. The computing system 100 ■ includes an operating system (OS) 104 that interacts with the NAND flash controller 102 through a flash driver 106 for reading data from or writing data in NAND flash device(s)

108. Further, the OS 104 includes file system drivers 110 that allow host applications 112 running on the OS 104 to interact with the storage device, such as the NAND flash devices

108.

[00017] However, since the NAND flash devices 108 are block devices, thus the file system drivers 110 of common file systems such as NTFS, FAT32 or EXT3 are not able to interact directly with the NAND flash devices 108. The file system drivers 110 typically consider the NAND flash devices 108 as hard disk drives and thus use logical block addressing (LB A) format to access the NAND flash devices 108. Therefore, when the host application 112 running on the OS 104 wants to access some data stored on the NAND flash devices 108, the file system drivers 110 provide a read command and address of the data, in LB A format, to the flash driver 106.

[00018] The flash driver 106, based on the read command and the address in the LB A format, accesses the NAND flash devices 108 through a NAND I/O bus 114 and reads the required data. For the purpose, the flash driver 106 typically includes a flash translation layer (FTL) 116 and a memory technology driver (MTD) 118. The FTL 116 is configured to translate address from the LBA format to a physical address format used by the NAND flash devices 108 to store data. Address translation by the FTL 1 16 generally includes mapping algorithms and tables, wear leveling, and bad block management etc. [00019] The MTD 118 implements various interfacing functionalities to manage interfacing between the computing system 100 and the NAND flash devices 108. For instance, the MTD 118 controls NAND device I/O bus width, error correcting code (ECC) configuration, DMA engine configuration, interrupt service routines, and sequencing the operational commands for various operations such as read and write. The flash driver 106 provides the operational command and the DMA engine configuration commands to the NAND flash controller 102 thorough a command control bus.

[00020] The NAND flash controller 102 includes NAND device registers 120, a data FIFO 122, ECC logic 124, NAND protocol logic 126, DMA engines 128 and other various registers such as PCI registers (not shown in the figure). The NAND device registers 120 include configuration data such as data related to the host processor and the NAND flash devices 108. The data FIFO 122 is configured to transfer data between the NAND flash devices 108 and the OS 104. Typically, the data FIFO 122 receives data to be written on the NAND flash devices 108 from the OS 104 through the DMA engines 128. The data FIFO 122 receives the data from the DMA engines 128 and stores the data till the entire data for a page of the NAND flash device 108 is collected. Once the entire data for the page is collected, the NAND protocol logic 126 erases the entire block which contains the page in which the data is to be written. The NAND flash controller 102 may then write the data on the NAND flash device 108 through the NAND I/O bus 114. Further, the ECC logic 124 is configured to correct errors that may occur in data written on the NAND flash device 108. For example, when the NAND flash controller 102 accesses some data stored in the NAND flash device 108, the ECC logic 124 checks the data to determine if the data contains any error. Any error in the data is then corrected by the ECC logic 124 before being sent to the OS 104. The NAND flash controller 102 thus assists the OS 104 in accessing the NAND flash devices 108.

[00021] Further, with advent of multi-host computing systems, multiple host processors running different operating systems can be included in the same computing system. Multi-host systems are generally configured to share the same peripheral devices and resources in order to reduce the system costs and power consumption. Thus, in present multi-host computing systems native NAND flash controller 102 configured to interact with one host are shared between multiple hosts. However, sharing the same NAND flash devices 108 and the NAND flash controller 102 may require software and hardware overhead. Further, sharing the NAND flash devices 108 and the NAND flash controller 102 may affect the experience of a user of the multi-host computing system. For instance, a user may not be able to access data stored in the NAND flash devices 108 using multiple host processors simultaneously as the NAND flash controller 102 may be controlled by a single host processor.

[00022] To this end, various embodiments of system architecture implementing a single NAND flash controller for a multi-host computing system having multiple host processors running multiple operating systems are described. Further, the system architecture can be implemented in a variety of computing systems. The multi-host computing system may include, but are not limited to, desktop computers, hand-held devices, laptops or other portable computers, mobile phones, personal digital assistants (PDA's), tablet personal computers, netbooks, workstations, and the like which utilize multiple processors on the same hardware platform. In one implementation, the system architecture can also be implemented for systems running any operating system such as Linux, Unix, Microsoft® Windows®, Mac OS X®, Android, and the like. Although the description herein is with reference to certain multi-host computing systems running particular operating systems, the systems and methods may be implemented in other operating systems and computing systems, albeit with a few variations, as will be understood by a person skilled in the art. [00023] Multiple operating systems are typically used to perform different functions on the same hardware platform. Each operating system may provide a particular advantage over the other operating systems. For example, in a multi-host computing system which may run two different operating systems, OS1 and OS2, the OS 1 may provide better performance or support more applications than OS2 however, the OS2 may consume less resources such as memory, processing power, battery power when compared to OS1. In such a scenario, the computing system may implement OS1 for application processing and computational purposes and OS2 during the idle state.

[00024] According to an embodiment of the present subject matter, the multi-host computing system includes a multi-host NAND flash controller configured to allow sharing of NAND flash devices between multiple host processors. The multi-host NAND flash controller is connected to two host processors, hostl running a first operating system hostl OS and a host2 running a second operating system host2 OS. Each of the hostl and the host2 further connect to flash drivers, hostl flash driver and host2 flash driver, respectively, for controlling the multi-host NAND flash controller for accessing the NAND flash devices connected to the multi-host computing system. Further, the multi- host NAND flash controller is connected to system memories, hostl system memory and host2 system memory, of the hostl and the host2, respectively. The multi-host NAND flash controller is connected to the system memories for storing in or fetching, data, read from or to be written in the NAND flash devices. [00025] In one implementation, the multi-host NAND flash device connected to the multi-host computing system, hereinafter referred to as the system, is divided into multiple partitions. Each host processor, i.e., hostl and host2 is assigned one partition from the multiple partitions such that one host processor has access to a particular partition only and does not have access to other partitions. When a host processor, say, the hostl wants to write some data to the NAND flash device, the OS1 may direct the hostl flash driver to access the NAND flash device. The hostl flash driver in turn interacts with the NAND flash controller. The multi-host NAND flash controller then accesses the partition specified for the hostl and writes the data in the said partition. Further, when both the host processors want to access the NAND flash device at the same time, the NAND flash controller may select command from one of the host processor, say, the host2 based on an arbitration logic. On execution of the command from the host2, the multi-host NAND flash controller will then execute the command from the hostl. Thus, both the host processors can access the NAND flash devices simultaneously.

[00026] The present subject matter thus provides embodiments for a multi-host computing system having a single NAND flash controller to allow sharing of NAND flash devices between two or more different host processors running their own operating systems. [00027] Although the present subject matter has been described in relation to two host processors, it will be understood that the system architecture may be implemented for two or more host processors.

[00028] Figure 2 illustrates system architecture for implementing a multi-host NAND flash controller in a multi-host computing system 200, according to an embodiment of the present subject matter. Examples of the multi-host computing system 200 include, but are not limited to, computing device, such as mainframe computers, workstations, personal computers, desktop computers, minicomputers, servers, multiprocessor systems, netbooks, and laptops; cellular communicating devices, such as a personal digital assistant, a smart phone, and a mobile phone; and the like. The multi-host computing system 200, hereinafter referred to as the system 200, is connected to various memory devices, such as the NAND flash device(s) 108 for storing data. The system 200 further includes a Multi-host NAND flash controller 202 configured to allow one or more host processors implemented in the system 200 to access the NAND flash devices 108. [00029] In one implementation, the system 200 includes two host processors, hostl (not show in the figure) running a hostl operating system (OS) 204-1 and host2 (not show in the figure) running a host2 OS 204-2. Each of the host operating systems, the hostl OS 204-1 and the host2 OS 204-2, interact with the Multi-host NAND flash controller 202 for reading data from or writing data to the NAND flash devices 108. The hostl OS 204-1 and the host2 OS 204-2 interact with the Multi-host NAND flash controller 202 through a hostl flash driver 206-1 and a host2 flash driver 206-2, respectively. Further, each of the host operating systems, the hostl OS 204-1 and the host2 OS 204-2, includes file system drivers, hostl file system drivers 208-1 and host2 file system drivers 208-2, respectively. Each of the file system drivers, i.e., the hostl file system drivers 208-1 and the host2 file system drivers 208-2, are configured similar to the file system drivers 110 and allow host applications, hostl applications 210-1 and host2 applications 210-2, running on the hostl OS 204-1 and the host2 OS 204-2, respectively, to interact with storage device, such as the NAND flash devices 108, through a NAND flash controller, such as the multi-host NAND flash controller 202.

[00030] As described previously, the file system drivers 208-1 and 208-2 consider the NAND flash devices 108 as hard disk drives and use logical block addressing (LB A) format to access the NAND flash devices 108. Therefore, when the host applications 210- 1 and 210-2 want to access data stored on the NAND flash devices 108, the file system drivers 208-1 and 208-2 provide a read command and address of the data, in LB A format, to the flash drivers 206-1 and 206-2, respectively.

[00031] The flash drivers 206-1 and 206-2, based on the read command and the address in the LB A format, access the NAND flash devices 108 through the multi-host NAND flash controller 202 and a NAND I/O bus 212 to read the required data. Further, each of the flash drivers 206-1 and 206-2 typically includes a flash translation layer, a hostl FTL 214-1 and a host2 FTL 214-2, respectively, and a memory technology driver, a hostl MTD 216-1 and a host2 MTD 216-2, respectively. The hostl FTL 214-1 and the host2 FTL 214-2 are configured similar to the FTL 1 16 and thus translate address from the LBA format to a physical address format used by the NAND flash devices 108 to store data. Further, the hostl MTD 216-1 and the host2 MTD 216-2 are configured similar to the MTD 118 and implement various interfacing functionalities to manage interfacing between the system 200 and the NAND flash devices 108. Thus each of the host processors, the hostl and the host2, access the NAND flash devices 108 through the flash drivers 206-1 and 206-2, respectively, and the Multi-host NAND flash controller 202.

[00032] In one implementation, the NAND flash device 108 is partitioned into multiple partitions by the system 200 and each host processor is assigned one partition from the multiple partitions such that one host processor has access to a particular partition only and does not have access to other partitions. For example, if a NAND flash device of four Gigabytes (GB) is connected to system 200 and the system 200 has two host processors, the hostl and the host2, then the system will divide the NAND flash device into two partitions of two GB each. The hostl will then be given access to one partition of two GB, whereas the host2 will be given access to the other partition of two GB. For the purpose, the system 200 includes a platform controller (not shown in the figures) configured to partition the NAND flash devices 108 into multiple partitions such that each host processor has access to at least one partition.

[00033] In operation, when the system 200 is switched ON and the NAND flash device 108 is connected to the system 200, the platform controller partitions the NAND flash devices 108 into two partitions, say a first partition and a second partition. The host processors, the hostl and the host2, then perform Peripheral Component Interconnect (PCI) enumeration. By performing the enumeration, the hostl and the host2 are enabled to communicate with the Multi-host NAND flash controller 202 to access NAND flash device 108. The hostl and the host2 are then assigned one partition each. For instance, the hostl and the host2 are assigned the first partition and the second partition, respectively. When an application running on a host processor, say, the hostl application running on the hostl wants to read some data stored in the NAND flash device 108, the hostl OS 204-1 directs the hostl flash driver 206-1 to access the NAND flash device 108. For instance, the hostl file system drivers 208-1 provides a read command and address of the data in the NAND flash device 108, in LBA format, to the flash driver 106. The hostl FTL 214-1 then translates address from the LBA format to a physical address format used by the NAND flash devices 108. The Multi-host NAND flash controller 202 then accesses the first partition specified for the hostl through the NAND I/O bus 212 and reads the data.

[00034] Further, when both the host applications, the hostl applications 210-1 and the host2 applications 210-2, want to access the NAND flash device 108 at the same time, the Multi-host NAND flash controller 202 will select a command from one of the host applications based on priority configuration. For instance, based on the priority configuration, the Multi-host NAND flash controller 202 may select a command from the host2. On execution of the command from the host2, the Multi-host NAND flash controller 202 will then execute the command from the hostl . Thus, the Multi-host NAND flash controller 202 effectively allows both the host processors to access the NAND flash devices 108 simultaneously. [00035] Although the present subject matter has been described in relation to two host processors, it will be understood that the system architecture may be implemented for two or more host processors.

[00036] Figure 3 illustrates a block diagram representing components of the Multi- host NAND flash controller 202 for the multi-host computing system 200, according to an embodiment of the present subject matter.

[00037] As described previously, the Multi-host NAND flash controller 202 is configured to allow sharing of the NAND flash devices 108 between multiple host processors, say, the hostl and the host2. In one implementation, the Multi-host NAND flash controller 202 includes a set of host interaction components, i.e., DMA engines, data FIFO, command FIFO, and NAND device registers for each of the host processors running on the system 200. For instance, when the system 200 has only two host processors, the hostl and the host2, the Multi-host NAND flash controller 202 includes two sets of the host interaction components. The Multi-host NAND flash controller 202 will thus have a hostl DMA engine 302-1 and a host2 DMA engine 302-2, a hostl data FIFO 304-1 and a host2 data FIFO 304-2, a hostl command FIFO 306-1 and a host2 command FIFO 306-2, and hostl registers 308-1 and host2 registers 308-2. It may be noted that since the Multi-host NAND flash controller 202 is configured to appear as a typical NAND flash controller to each of the host processors, the configuration and working of the host interaction components in the Multi-host NAND flash controller 202 is similar to that in a typical single host NAND flash controller.

[00038] Thus, when a host processor, say, the hostl wants to access the NAND flash devices 108, the host interaction components dedicated for the hostl manage the interaction between the hostl and the NAND flash devices 108. Similarly, when both the host processors want to access the NAND flash devices 108, the host interaction components dedicated for both the host processors independently manage the interaction between the host processors and the NAND flash devices 108. For instance, when the hostl applications 210-1 and the host2 applications 210-2 want to access the NAND flash devices 108 simultaneously the hostl MTD 216-1 and the host2 MTD 216-2, respectively, issue an operational command, say, a write command to the Multi-host NAND flash controller 202. The operational command from the hostl MTD 216-1 and the host2 MTD 216-2 is received by the hostl registers 308-1 and the host2 registers 308-2, respectively. The hostl registers 308-1 and the host2 registers 308-2 then store the operational command in the hostl data FIFO 304-1 and the host2 data FIFO 304-2, respectively.

[00039] A host command switching logic 310 of the Multi-host NAND flash controller 202 is then notified about the presence of operational commands in the hostl data FIFO 304-1 and the host2 data FIFO 304-2. The host command switching logic 310 is configured to select, based on arbitration logic, one operational command from the operational commands stored in the hostl data FIFO 304-1 and the host2 data FIFO 304-2 for execution. On execution of the selected operational command, the other operational command may be processed for execution. In one implementation, the arbitration logic may include selecting the operational command based on a priority configuration. In another implementation, the arbitration logic may include selecting the operational command based on a selection algorithm, for example, a round robin method. In yet another implementation, the arbitration logic may include selecting the operational command based on a priority configuration and in case of equal priority using the round robin method.

[00040] On selection of one operational command, say, the operational command from the hostl MTD 216-1, the host command switching logic 310 provides the selected operational command to a NAND command issue logic 312. The NAND command issue logic 312 is configured to determine the type of the operational command, i.e., whether the operational command is a read command or a write command. Based on the determination, the NAND command issue logic 312 enables the hostl DMA engine 302-1. For instance in case of a write command, the NAND command issue logic 312 enables the hostl DMA engine 302-1 to get data from a hostl memory and provide the data to the hostl data FIFO 304-1. The hostl data FIFO 304-1 stores the data till entire data for a page of the NAND flash device 108 is collected. Once the entire data for the page is collected, ECC logic 314, similar to the ECC logic 124, generates ECC parity bytes. NAND protocol logic 316, similar the NAND protocol logic 126, then writes the page in the NAND flash device 108 which contains the page in which the data is to be written. The Multi-host NAND flash controller 202 may then write the data on the NAND flash device 108 through the NAND I/O bus 212.

[00041] On writing the data on the NAND flash device 108, the Multi-host NAND flash controller 202 may then execute the operational command from the host2. The Multi-host NAND flash controller 202 thus allows both the host processors to share the NAND flash devices 108. [00042] Figure 4 illustrates an exemplary method 400 for sharing a NAND flash controller in a multi-host computing system, such as the multi-host computing system 200, according to an embodiment of the present subject matter. The exemplary method 400 may be described in the general context of computer executable instructions embodied on a computer-readable medium. Generally, computer executable instructions can include routines, programs, objects, components, data structures, procedures, modules, functions, etc., that perform particular functions or implement particular abstract data types. The method 400 may also be practiced in a distributed computing environment where functions are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, computer executable instructions may be located in both local and remote computer storage media, including memory storage devices.

[00043] The order in which the method 400 is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined ,in any order to implement the method 400, or an alternative method.

Additionally, individual blocks may be deleted from the method 400 without departing from the spirit and scope of the method, systems and devices described herein.

Furthermore, the method 400 can be implemented in any suitable hardware, software, firmware, or combination thereof.

[00044] Additionally, the method 400 has been described in the context of the multi-host computing system 200 and the Multi-host NAND flash controller 202, however, other embodiments may also be possible as will be understood by a person skilled in the art. [00045] At block 402, an operational command is received from each of one or more host processors. For example, an operational command may be received by a flash controller, say, the Multi-host NAND flash controller 202 from the hostl and the host2 of the system 200. The operational command may be one of a read command or a write command. For instance, when the hostl applications 210-1 and the host2 applications 210- 2 want to access the NAND flash devices 108 simultaneously the hostl MTD 216-1 and the host2 MTD 216-2, respectively, issue an operational command, say, to the Multi-host NAND flash controller 202. [00046] At block 404, an operational command from a host processor selected from among the one or more host processors is selected. For example, an operational command from the hostl may be selected by the Multi-host NAND flash controller 202. In one implementation, the operational command may be selected using an arbitration logic. The arbitration logic may be based on, for example, a priority configuration and a selection algorithm, such as a round robin method. For instance, the host command switching logic 310 of the Multi-host NAND flash controller 202 may select based on the arbitration logic, one operational command from the operational commands.

[00047] At block 406, a type of the operational command is determined, for example, by the Multi-host NAND flash controller 202. In one implementation, it is determined whether the operational command is a read command or a write command. For instance, the NAND command issue logic 312 determines the type of the operational command, i.e., whether the operational command is a read command or a write command. If the operational command is determined to be a read command, which is the 'No' path from the block 406, the Multi-host NAND flash controller 202 fetches data form a NAND flash device, for example, the NAND flash device 108 at block 408. For instance, the data is read from the NAND flash device 108 and stored in the data FIFO, for example, the hostl data FIFO 304-1.

[00048] At block 410, it is determined if all the data is received from the NAND flash device, for example, the NAND flash device 108. For example, it is determined if all the data has been received by the hostl data FIFO 304-1. If it is determined that some data has not been read, which is the 'No' path from the block 406, the method at the block 408 is repeated.

[00049] In case it is determined that all the data has been received, which is the 'Yes' path from the block 410, the data is moved to a system memory corresponding to the host processor, i.e., the hostl at the block 412. From the block 412, the method proceeds to block 414. [00050] In case it is determined that the operational command is a write command, which is the 'Yes' path from the block 406, a DMA engine corresponding to the host processor is enabled to fetch data from a host system memory corresponding to the host processor at the block 416. For example, the hostl DMA engine 302-1 is enabled to fetch data from the host system memory corresponding to the hostl. The hostl DMA engine 302-1 fetches and stores the data in the data FIFO, for example, the hostl data FIFO 304- 1.

[00051] At block 418 it is determined if all the data is received in the data FIFO, for example, the hostl data FIFO 304-1. For instance, it is determined if all the data has been fetched by the hostl DMA engine 302-1 from the host system memory corresponding to the hostl. If it is determined that some data has not been fetched, which is the 'No' path from the block 418, the method at the block 416 is repeated.

[00052] In case it is determined that all the data has been fetched, which is the 'Yes' path from the block 418, the data is written in a NAND flash device at the block 420., From the block 412, the method proceeds to the block 414.

[00053] At the block 414, a command from other host processors from the one or more host processors is executed. For example, the Multi-host NAND flash controller 202 determines if any other operational commands are remaining. Based on the determination, the Multi-host NAND flash controller 202 executes the operational command from the other host processors, i.e., the host2.

[00054] The method 400 thus describes an embodiment for sharing a NAND flash device between two host processors using a single NAND flash controller.

[00055] Although implementations of a NAND flash controller for multi-host computing systems have been described in language specific to structural features and/or methods, it is to be understood that the present subject matter is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as exemplary implementations of the NAND flash controller.

Claims

I/We claim:

1. A multi-host computing system (200) for sharing of a NAND flash device (108) among a plurality of host processors of the multi-host computing system (200), wherein the multi-host computing system (200) comprising: a plurality of host flash drivers (206), each corresponding to a host processor from amongst the plurality of host processors, configured to receive simultaneous commands from the plurality of host processors to access the NAND flash device (108), wherein an address of data associated with each of the simultaneous commands is received in logical block addressing (LBA) format by each of the plurality of host flash drivers (206), and wherein each of the plurality of host flash drivers (206) comprises a host flash translation layer (FTL) (214) configured to translate the address of data received in LBA format to a physical address format utilized by the NAND flash device (108) to store data; and a multi-host NAND flash controller (202) coupled to the plurality of host flash drivers (206), configured to: arbitrate among the plurality of commands received from the plurality of host flash drivers to select a command from amongst a plurality of simultaneous commands for propagation to the NAND flash device (108); and obtain data for an entire page of the NAND flash device (108) associated with the selected command, based on the address of data received in LBA format to provide the data to the NAND flash device (108) shared among the plurality of host processors.

2. The multi-host computing system (200) as claimed in claim 1, wherein each of the plurality of host flash drivers (206) comprises a memory technology driver (216) configured to manage interfacing between the multi-host computing system (200) and the NAND flash device (108), wherein the managing comprises one or more controlling NAND device (108) bus width, configuring error correcting code (ECC), configuring direct memory access (DMA) engine, handling interrupt service routines, and sequencing operational commands for read and write operations.

3. The multi-host computing system (200) as claimed in claim 1, wherein the FTL (214) is configured to translate the address of data based on one or more of address mapping based on mapping algorithms and tables, wear leveling, and bad block management.

4. The multi-host computing system (200) as claimed in claim 1, wherein the multi- host NAND flash controller (202) comprises a platform controller configured to logically partition the NAND flash device (108) into a plurality of partitions, each partition corresponding to a host processor from amongst the plurality of host processors of the multi-host computing system (200).

5. The multi-host computing system (200) as claimed in claim 1, wherein the multi- host NAND flash controller (202) comprises a plurality of host interaction components, each corresponding to a host processor from amongst a plurality of host processors, comprising one or more host registers (308), host DMA engine (302), host data FIFO (304), and host command FIFO (306); configured to manage communication between the host processor and the NAND flash device (108) shared among the plurality of host processors.

6. A multi-host NAND flash controller (202) comprising: a plurality of host interaction components, each corresponding to a host processor from amongst a plurality of host processors; wherein each host interaction component comprises: host registers (308) configured to define configuration data for the NAND flash device (108) corresponding to a host processor coupled to the host interaction component, wherein the host processor sends a command for the NAND flash device (108) through the host interaction component; a command FIFO (306) configured to store the command received from the host processor; and a host DMA engine (302) configured to obtain data for an entire page Of the NAND flash device (108) associated with the command from a memory of the host processor to store in a data FIFO 304; and a host command switching logic (322) coupled to the command FIFO (306) of each of the plurality of host interaction components, configured to arbitrate among command FIFOs (306) of each of the plurality of host interaction components to select a command corresponding to the host processor for propagation to the NAND flash device (108).

7. The multi-host NAND flash controller (202) as claimed in claim 6, further comprising a NAND command issue logic (312), wherein the NAND command issue logic (312) is configured to: determine a type of the selected command, wherein the type is indicative of the operation associated with the command comprising on of read and write operation; and obtain data for an entire page of the NAND flash device (108) associated with the selected command from the host data FIFO (304).

8. The multi-host NAND flash controller (202) as claimed in claim 7, wherein the NAND command issue logic (312) is further configured to provide the obtained data to an ECC logic (314), wherein the ECC logic (314) is configured to generate ECC parity bits for the data to be provided to the NAND flash device (108).

9. The multi-host NAND flash controller (202) as claimed in claim 7, further comprising a AND protocol logic (316) configured to erase a block containing the entire page to write the data on the NAND flash device (108).