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WO2012141365A1 - Semiconductor element and production method therefor - Google Patents

Semiconductor element and production method therefor Download PDF

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Publication number
WO2012141365A1
WO2012141365A1 PCT/KR2011/003142 KR2011003142W WO2012141365A1 WO 2012141365 A1 WO2012141365 A1 WO 2012141365A1 KR 2011003142 W KR2011003142 W KR 2011003142W WO 2012141365 A1 WO2012141365 A1 WO 2012141365A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor layer
layer
semiconductor
forming
semiconductor device
Prior art date
Application number
PCT/KR2011/003142
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French (fr)
Korean (ko)
Inventor
유명철
오세종
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(주)버티클
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Publication of WO2012141365A1 publication Critical patent/WO2012141365A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction

Definitions

  • the present invention relates to a semiconductor device capable of emitting light when a current is injected and a method for manufacturing the same, and more particularly to a semiconductor device capable of improving light extraction efficiency and luminous efficiency and a method of manufacturing the same.
  • a semiconductor device having a PN junction and emitting light when a current is injected in a forward direction is called a light emitting diode (LED).
  • a light emitting diode can easily obtain light of a specific frequency desired, and has the advantages of being small, strong in vibration, and low in power consumption compared to a bulb using a filament, and having a long life.
  • GaN gallium-nitrogen compound
  • a light emitting diode is generally formed by growing a GaN based semiconductor device layer on a substrate, and a process of obtaining a separate light emitting diode device by separating the semiconductor device layer and the substrate is required.
  • GaN-based light emitting diodes are formed on a flat sapphire substrate.
  • the sapphire substrate has a large lattice mismatch, low thermal conductivity, high dicing cost, but similar crystal structure with hexagonal structure like GaN.
  • sapphire has a high melting point, which is suitable as a substrate for high temperature evaporation thin film such as GaN, and is inexpensive, while the total reflection phenomenon causes the GaN layer to form an optical cavity, resulting in a low light extraction efficiency, thereby producing a high efficiency LED. There is a limit.
  • GaN-based light emitting diodes were manufactured by using a sapphire processed substrate (PSS: Patterned Sapphire Substrate).
  • PSS reduces the dislocation density of GaN and greatly improves the light extraction efficiency of LEDs. That is, in the case of a flat sapphire substrate, the light extraction efficiency of the LED is lowered because the GaN layer forms an optical cavity due to total reflection, but in the case of PSS, the light trapping effect is lowered due to the uneven structure of the GaN and sapphire interface. The efficiency is improved.
  • the present invention is derived to solve the problems of the prior art as described above, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can improve the light extraction efficiency.
  • an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can improve the luminous efficiency by improving the surface area of the active layer.
  • an object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can improve the light extraction efficiency and the light emission efficiency while reducing the manufacturing cost.
  • a semiconductor device is a first type of semiconductor layer; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, wherein one surface of the first semiconductor layer in contact with one surface of the active layer is formed in an uneven shape.
  • the other surface of the active layer may be formed in an uneven form corresponding to the shape of the uneven surface of the first semiconductor layer, and one surface of the second semiconductor layer spaced apart from the other surface of the active layer may be formed in the form of unevenness. Can be.
  • the semiconductor device may further include a support layer, wherein the support layer may be formed on the second semiconductor layer.
  • the semiconductor device may be formed in a polygonal or circular columnar shape.
  • a semiconductor device may include a first semiconductor layer of a first type; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer includes a plurality of scattering means for scattering light.
  • the scattering means may be composed of at least one material of SiO 2, Si 3 N 4, TiO 2, ZnO, MgZnO, Al 2 O 3, AlN, In 2 O 3.
  • the scattering means may be located on one surface of the second semiconductor layer in contact with the active layer, on the other surface of the second semiconductor layer or in the second semiconductor layer.
  • a method of manufacturing a semiconductor device includes forming a first semiconductor layer of a first type on a substrate; Treating the first semiconductor layer according to a preset mask pattern to form one surface of the first semiconductor layer in an uneven form; Forming an active layer on one surface of the first semiconductor layer formed in the uneven form; And forming a second semiconductor layer of a second type on the active layer.
  • the active layer may be formed such that one surface of the active layer in contact with the second semiconductor layer has a concave-convex shape corresponding to the concave-convex shape of one surface of the first semiconductor layer.
  • the second semiconductor layer may be formed such that one surface of the second semiconductor layer spaced apart from the active layer has an uneven shape.
  • a support layer for supporting the semiconductor device on the second semiconductor layer Separating the substrate from the first semiconductor layer; And forming an electrode layer on one surface of the first semiconductor layer from which the substrate is separated.
  • a method of manufacturing a semiconductor device includes forming a first semiconductor layer of a first type on a substrate; Forming an active layer on the first semiconductor layer; And forming a second type of semiconductor layer comprising a plurality of scattering means for scattering light on the active layer.
  • the forming of the second semiconductor layer may include forming the plurality of scattering means on the active layer to expose a portion of the active layer; And forming the second semiconductor layer on the active layer in which the plurality of scattering means is formed.
  • the plurality of scattering means may be formed on the second semiconductor layer so that a part of the second semiconductor layer is exposed.
  • the forming of the second semiconductor layer may include forming the second semiconductor layer having a first height; Forming the plurality of scattering means on the second semiconductor layer of the first height and the second semiconductor layer of the second height on the second semiconductor layer of the first height on which the plurality of scattering means is formed It may include forming a.
  • the semiconductor device of the present invention and a method of manufacturing the same, in the semiconductor device for manufacturing a semiconductor device, for example, GaN-based light-emitting diode on the substrate, for example, sapphire substrate, SiC substrate, and then separating the substrate, the active layer and
  • the semiconductor layer By forming the semiconductor layer in the form of unevenness, the light confinement effect is reduced to improve the light extraction efficiency, and the surface area of the active layer is increased by the uneven shape of the active layer, thereby improving the light emitting efficiency per unit area to improve the light emitting efficiency of the semiconductor device.
  • the substrate for example, sapphire substrate, SiC substrate
  • the active layer By forming the semiconductor layer in the form of unevenness, the light confinement effect is reduced to improve the light extraction efficiency, and the surface area of the active layer is increased by the uneven shape of the active layer, thereby improving the light emitting efficiency per unit area to improve the light emitting efficiency of the semiconductor device.
  • the present invention can improve the light extraction efficiency by lowering the light trapping effect by forming a plurality of scattering means for scattering light in the second semiconductor layer formed on the active layer.
  • the manufacturing cost can be reduced compared to the semiconductor device using the PSS. Through this, the price competitiveness of semiconductor devices can be improved.
  • the present invention not only lowers the light confinement effect on the light propagation path, but also has the effect of improving the luminous efficiency by increasing the surface area of the interface between the active layer and the neighboring GaN semiconductor layer.
  • Such a semiconductor device manufacturing method of the present invention is not limited to the vertical semiconductor device manufacturing method, it is also applicable to a horizontal semiconductor device.
  • FIG. 1 is a diagram illustrating a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
  • FIG. 3 is a plan view of an example of one surface of a first semiconductor layer adjacent to the active layer illustrated in FIG. 1.
  • FIG. 4 is a plan view illustrating another example of one surface of a first semiconductor layer adjacent to the active layer illustrated in FIG. 1.
  • 5 to 7 illustrate cross-sectional views of one embodiment for describing a process of the method of manufacturing the semiconductor device illustrated in FIG. 2.
  • FIG. 8 is a diagram illustrating a semiconductor device according to another embodiment of the present invention.
  • FIG. 9 is a sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 10 is a sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 11 is a sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 12 to 14 illustrate cross-sectional views of one embodiment for describing a process of the method of manufacturing the semiconductor device illustrated in FIG. 9.
  • a semiconductor device is a first type of semiconductor layer; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, wherein one surface of the first semiconductor layer in contact with one surface of the active layer is formed in an uneven shape.
  • the other surface of the active layer may be formed in an uneven form corresponding to the shape of the uneven surface of the first semiconductor layer, and one surface of the second semiconductor layer spaced apart from the other surface of the active layer may be formed in the form of unevenness. Can be.
  • the semiconductor device may further include a support layer, wherein the support layer may be formed on the second semiconductor layer.
  • the semiconductor device may be formed in a polygonal or circular columnar shape.
  • a semiconductor device may include a first semiconductor layer of a first type; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer includes a plurality of scattering means for scattering light.
  • the scattering means may be composed of at least one material of SiO 2, Si 3 N 4, TiO 2, ZnO, MgZnO, Al 2 O 3, AlN, In 2 O 3.
  • the scattering means may be located on one surface of the second semiconductor layer in contact with the active layer, on the other surface of the second semiconductor layer or in the second semiconductor layer.
  • a method of manufacturing a semiconductor device includes forming a first semiconductor layer of a first type on a substrate; Treating the first semiconductor layer according to a preset mask pattern to form one surface of the first semiconductor layer in an uneven form; Forming an active layer on one surface of the first semiconductor layer formed in the uneven form; And forming a second semiconductor layer of a second type on the active layer.
  • the active layer may be formed such that one surface of the active layer in contact with the second semiconductor layer has a concave-convex shape corresponding to the concave-convex shape of one surface of the first semiconductor layer.
  • the second semiconductor layer may be formed such that one surface of the second semiconductor layer spaced apart from the active layer has an uneven shape.
  • a support layer for supporting the semiconductor device on the second semiconductor layer Separating the substrate from the first semiconductor layer; And forming an electrode layer on one surface of the first semiconductor layer from which the substrate is separated.
  • a method of manufacturing a semiconductor device includes forming a first semiconductor layer of a first type on a substrate; Forming an active layer on the first semiconductor layer; And forming a second type of semiconductor layer comprising a plurality of scattering means for scattering light on the active layer.
  • the forming of the second semiconductor layer may include forming the plurality of scattering means on the active layer to expose a portion of the active layer; And forming the second semiconductor layer on the active layer in which the plurality of scattering means is formed.
  • the plurality of scattering means may be formed on the second semiconductor layer so that a part of the second semiconductor layer is exposed.
  • the forming of the second semiconductor layer may include forming the second semiconductor layer having a first height; Forming the plurality of scattering means on the second semiconductor layer of the first height and the second semiconductor layer of the second height on the second semiconductor layer of the first height on which the plurality of scattering means is formed It may include forming a.
  • the first semiconductor layer, the active layer, and the second semiconductor layer described in the present invention may be implemented with one or more materials including at least one of GaN, AlGaN, AlGaAs, AlGaInP, GaAsP, GaP, or InGaN.
  • the semiconductor device 100 includes a support layer 110, a reflective layer 120, a third semiconductor layer 130, and a second semiconductor layer 140. , An active layer 150, a first semiconductor layer 160, and an electrode layer 170, and have a regular hexagonal pillar shape.
  • the layers constituting the semiconductor device 100 will be described with reference to FIG. 2, and the semiconductor device of the present invention is not limited to a regular hexagonal column shape but may have a polygonal shape.
  • the semiconductor device 200 includes a support layer 210, a reflective layer 220, a third semiconductor layer 230, and a second semiconductor layer 240. , An active layer 250, a first semiconductor layer 260, and an electrode layer 270.
  • the first semiconductor layer 260 is a first type of semiconductor layer, and one surface adjacent to the active layer 250 is formed in an uneven form.
  • the first semiconductor layer 260 may be an N type semiconductor layer, for example, an N type GaN layer.
  • the first semiconductor layer 260 may form a mask pattern having a predetermined shape on one surface of the first semiconductor layer formed by epitaxial growth and then etch the first semiconductor layer 260 having an uneven shape. Can be formed.
  • the first semiconductor layer 260 may be formed of a first semiconductor layer having a predetermined thickness by using epitaxial growth, and then may be formed using a physical mask pattern spaced apart from a surface of the first semiconductor layer by a predetermined distance. By epitaxially growing on the semiconductor layer again, the first semiconductor layer 260 having an uneven shape may be formed.
  • the first semiconductor layer is etched using the mask pattern, and thus, the first semiconductor layer is formed in the form of irregularities.
  • the first semiconductor layer 260 may have a rounded or quadrangular shape with a protruding portion having a concave-convex shape.
  • the shape of the concave-convex shape of the first semiconductor layer 260 is not limited to a circle or a rectangle, and may have various forms such as a semicircle, a cylinder, and a polygonal column.
  • the active layer 250 is formed in contact with one surface of the first semiconductor layer 260 formed in the uneven shape, and between the first semiconductor layer 260 and the second semiconductor layer 240 in order to increase the luminous efficiency of the LED semiconductor device. Is formed.
  • the active layer 250 may also be referred to as a quantum well bonding layer (MQW).
  • MQW quantum well bonding layer
  • the active layer 250 in order to improve the luminous efficiency per unit area, has one surface in contact with the second semiconductor layer 240 in a concave-convex shape, and the concave-convex shape of the active layer 250 is formed in the first semiconductor layer 260. Corresponds to the uneven form. That is, since the surface area of the active layer 250 is larger than that of the flat state, the luminous efficiency per unit area is improved.
  • one surface of the active layer 250 in an uneven form.
  • the active layer 250 when the active layer 250 is deposited or epitaxially grown on one surface of the first semiconductor layer 260 having an uneven shape, one surface of the active layer 250 corresponds to the uneven shape of the first semiconductor layer 260. It can be formed while having.
  • the active layer 250 may be formed by etching using a mask pattern after forming the active layer.
  • the active layer 250 is formed on one surface of the first semiconductor layer 260 having the uneven shape to simplify the process and reduce the process cost. The following process will be mainly described based on the embodiment in which the active layer is naturally formed to have an uneven shape.
  • the second semiconductor layer 240 is a second type of semiconductor layer, which is formed on one surface of the active layer 250 formed in the uneven form, and also one surface of the second semiconductor layer 240 adjacent to the third semiconductor layer 230. It is formed in the form of unevenness.
  • the second semiconductor layer 240 may be a P-type semiconductor layer, for example, may be a P-type GaN layer.
  • the third semiconductor layer 230 may be formed on one surface of the second semiconductor layer 240, and one surface of the third semiconductor layer 230 may also be formed in an uneven shape corresponding to the uneven shape of the second semiconductor layer 240. have.
  • the third semiconductor layer 230 is a semiconductor layer capable of contacting the P electrode on the second semiconductor layer 240, and may be an In 1-x Ga x N layer.
  • the reflective layer 220 is formed on one surface of the third semiconductor layer 230 and serves to reflect the light generated in the active layer 250 and traveling backward.
  • one surface of the reflective layer 220 may be formed in a flat shape.
  • the support layer 210 is a layer providing mechanical support of the semiconductor device, and is formed on one surface of the reflective layer 220 and may be a metal support layer.
  • the support layer 210 may be formed of a metal having high electrical conductivity and thermal conductivity and having a relatively high mechanical strength, for example, copper or a copper compound.
  • the support layer 210 may be formed through an electroplating method, and according to the embodiment, a flexible copper layer (not shown) having a low density and alleviating stress, and a high density and strength, It may also consist of two layers of a hard copper layer (not shown) that provides mechanical support.
  • the flexible copper layer may be formed by a plating method having a slower plating rate than the hard copper layer, and may provide a means for relieving stress due to the thickness of the support layer 210.
  • Examples of the plating method of the flexible copper layer include a sulfate-based plating method, and the possible plating speed is 3 to 5 um / hour.
  • An example of the plating method of the hard copper layer is a metal alloy-based plating method including tin (Sn) and iron (Fe), and the possible plating speed is 20 um / hour.
  • the electrode layer 270 is formed on the other surface of the first semiconductor layer 260 having an uneven shape and is a layer for applying power to the semiconductor device.
  • the electrode layer 270 may be formed using a metal and a metal compound.
  • the semiconductor device is formed such that the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer have an uneven shape, thereby lowering the light confinement effect and improving light extraction efficiency.
  • the surface area of the active layer may be increased to improve luminous efficiency per unit area.
  • FIG. 2 illustrates that the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer all have a concave-convex shape
  • the present invention is not limited thereto. Only the first semiconductor layer is formed in the concave-convex shape.
  • the second semiconductor layer and the third semiconductor layer may be formed of a flat layer. That is, in the present invention, only the first semiconductor layer, for example, an N type GaN layer may be formed in an uneven form, and if necessary, the active layer and the second semiconductor layer, for example, a P type GaN layer and a second semiconductor layer may be used.
  • the third semiconductor layer formed on the upper portion may also be formed in an uneven form.
  • first semiconductor layer and the active layer may be formed in an uneven form, and the second semiconductor layer and the third semiconductor layer may be formed as flat layers.
  • the active layer may be formed in an uneven form according to the uneven form of the first semiconductor layer, but may be formed flat when grown to a predetermined thickness or more.
  • 5 to 7 illustrate cross-sectional views of one embodiment for describing a process of the method of manufacturing the semiconductor device illustrated in FIG. 2.
  • a first type semiconductor layer 520 having a predetermined thickness for example, an N type, is formed on the substrate 510, for example, an sapphire substrate or an SiC substrate by epitaxial growth.
  • the first semiconductor layer 520 formed on the substrate 510 is etched using a preset mask pattern to form an upper portion of the first semiconductor layer 520 to have an uneven shape.
  • the shape and the extraction interval of the uneven shape of the first semiconductor layer 520 may be determined in consideration of light extraction efficiency and luminous efficiency.
  • the active layer 530, the second semiconductor layer 540, the third semiconductor layer 550, the reflective layer 560, and the support layer 570 are sequentially formed on the first semiconductor layer 520 having an uneven shape.
  • the active layer 530, the second semiconductor layer 540, and the third semiconductor layer 550 may be formed in an uneven shape corresponding to the uneven shape of the first semiconductor layer 520, and the unevenness is formed in each layer.
  • the size of the shapes may be the same or different.
  • the active layer 530 formed on the first semiconductor layer 520 may be formed to have a concave-convex shape different from the concave-convex shape of the first semiconductor layer 520 in consideration of luminous efficiency. That is, the active layer 530 is formed on the first semiconductor layer 520 to have a predetermined thickness, and then the active layer 530 is etched using a separate mask pattern, so that the unevenness of the first semiconductor layer 520 is different from that of the uneven shape of the first semiconductor layer 520. It may have a form.
  • a semiconductor is formed on the other surface of the first semiconductor layer 520 formed in the uneven shape, that is, the flat surface of the first semiconductor layer.
  • An electrode layer 580 for supplying power to the device is formed.
  • An example method of separating the substrate 510 and the first semiconductor layer 520 is a laser lift off (LLO) method, which irradiates the substrate with a laser of a specific frequency band that may pass through the substrate 510.
  • LLO laser lift off
  • CLO chemical lift off
  • the semiconductor device of the present invention may improve the light extraction efficiency like the semiconductor device formed on the PSS even when the substrate is separated, the active layer is irregular shape
  • the light emitting efficiency of the semiconductor device can be improved by forming a larger surface area. That is, since manufacturing is possible using a flat substrate instead of PSS, it is possible to manufacture a light emitting diode with high efficiency while reducing manufacturing cost.
  • the semiconductor device 800 may include the support layer 810, the reflective layer 820, the third semiconductor layer 830, the second semiconductor layer 840, the active layer 850, the first semiconductor layer 860, and the electrode layer 870. Include.
  • the semiconductor device 100 shown in FIG. 1 and the semiconductor device 800 shown in FIG. 8 differ only in that the formed shapes are regular hexagons and circles, respectively, and the overall structure is very similar. Therefore, description of each component is omitted.
  • FIG. 9 is a sectional view of a semiconductor device according to another embodiment of the present invention.
  • the semiconductor device 900 includes a support layer 910, a reflective layer 920, a third semiconductor layer 930, a second semiconductor layer 940, an active layer 960, and a first semiconductor layer 970. And an electrode layer 980.
  • the first semiconductor layer 970 is a first type semiconductor layer.
  • the first semiconductor layer 970 may be an N type GaN layer, and is formed by epitaxial growth.
  • the first semiconductor layer 970 is formed on a substrate (not shown).
  • a cross-sectional view of the first semiconductor layer 970 is separated from the substrate.
  • the active layer 960 is formed on the first semiconductor layer 970, and is formed between the first semiconductor layer 970 and the second semiconductor layer 940 to increase the light emitting efficiency of the light emitting diode semiconductor device.
  • the active layer 960 may also be referred to as a quantum well bonding layer (MQW).
  • MQW quantum well bonding layer
  • the second semiconductor layer 940 is a second type of semiconductor layer formed on the active layer 960 and includes a plurality of scattering means 950 for scattering light therein.
  • the second semiconductor layer 940 may be a P-type GaN layer, and may be formed by epitaxial growth as in the method of forming the first semiconductor layer 970.
  • the plurality of scattering means 950 serves to scatter the light to improve the light extraction efficiency of the semiconductor device.
  • the plurality of scattering means 950 formed in the second semiconductor layer 940 may be formed by at least one of SiO 2, Si 3 N 4, TiO 2, ZnO, MgZnO, Al 2 O 3, AlN, and In 2 O 3.
  • the second semiconductor layer 940 including the plurality of scattering means 950 forms a second semiconductor layer by a predetermined thickness, and then forms a plurality of scattering means 950 thereon, and then a second semiconductor on the top thereof. By forming a layer, it can be formed.
  • the third semiconductor layer 930 is formed on the second semiconductor layer 940 and may be an In 1-x Ga x N layer on the second semiconductor layer 940 that may contact the P electrode. .
  • the reflective layer 920 is formed on the third semiconductor layer 930 and reflects light generated in the active layer 960 and traveling backward.
  • the support layer 910 is a layer providing mechanical support of the semiconductor device.
  • the support layer 910 is formed on the reflective layer 920 and may be a metal support layer.
  • the support layer 910 may be formed of a metal having high electrical conductivity and thermal conductivity and having a relatively high mechanical strength, for example, copper or a copper compound.
  • the support layer 910 may be formed through an electroplating method, and in some embodiments, a flexible copper layer (not shown) having a low density and relieving stress, and having a high density and strength, It may also consist of two layers of a hard copper layer (not shown) providing support.
  • the electrode layer 980 is formed on one surface of the first semiconductor layer 970 which is not adjacent to the active layer 960 and is a layer for applying power to the semiconductor device.
  • the electrode layer 980 may be formed using a metal and a metal compound.
  • the semiconductor device 1000 may include a support layer 1010, a reflective layer 1020, a third semiconductor layer 1030, a second semiconductor layer 1040, an active layer 1060, a first semiconductor layer 1070, and an electrode layer 1080. Include.
  • the semiconductor device 1000 shown in FIG. 10 and the semiconductor device 900 shown in FIG. 9 differ only in positions where a plurality of scattering means 950 and 1050 are formed, and the overall structure is very similar. That is, a plurality of scattering means 1050 in FIG. 10 is formed between the active layer 1060 and the second semiconductor layer 1040.
  • the thickness of the second semiconductor layer 1040 is the thickness of the second semiconductor layer 940 shown in FIG. It may differ from the thickness.
  • the semiconductor device 1100 may include a support layer 1110, a reflective layer 1120, a third semiconductor layer 1130, a second semiconductor layer 1140, an active layer 1160, a first semiconductor layer 1170, and an electrode layer 1180. Include.
  • the semiconductor device 1100 illustrated in FIG. 11 and the semiconductor devices 900 and 1000 illustrated in FIGS. 9 and 10 differ only in positions where a plurality of scattering means 950, 1050, and 1150 are formed, and the overall structure is very similar. Do. That is, a plurality of scattering means 1150 in FIG. 11 is formed between the second semiconductor layer 1140 and the third semiconductor layer 1130.
  • the semiconductor device of the present invention can improve the light extraction efficiency by the second semiconductor layer including a plurality of scattering means, for example, a substrate for improving the light extraction efficiency is expensive. It is not necessary to use a PSS substrate. Therefore, the light extraction efficiency can be improved by using a low-cost sapphire substrate or the like, whereby a high-efficiency LED can be manufactured at low cost.
  • FIG. 12 to 14 illustrate cross-sectional views of one embodiment for describing a process of the method of manufacturing the semiconductor device illustrated in FIG. 9.
  • a first type semiconductor layer 1220 having a predetermined thickness is formed on the substrate 1210 such as a sapphire substrate or a SiC substrate by epitaxial growth.
  • An active layer 1230 is formed on the first semiconductor layer 1220, and a second semiconductor layer 1241 having a predetermined thickness is formed on the formed active layer 1230.
  • a plurality of scattering means 1250 is formed on the second semiconductor layer 1241 having a predetermined thickness. It may be formed by the above materials.
  • the plurality of scattering means 1250 is formed by forming a scattering layer (not shown) on the second semiconductor layer 1241 and then etching a portion of the upper portion of the second semiconductor layer 1241 by using a mask pattern.
  • the scattering layer may be formed by various methods such as CVD method such as MOCVD, PECVD, sputtering.
  • a plurality of scattering means 1250 may be formed on the second semiconductor layer 1241 by laminating the film with the plurality of scattering means 1250 on the second semiconductor layer 1241.
  • the plurality of scattering means 1250 is a lift off for first forming a patterned photoresist PR on the second semiconductor layer 1241 and depositing a scattering layer thereon to remove the photoresist. It can also be formed by a method.
  • the method of forming the plurality of scattering means 1250 is not limited to the above-described method, and all methods capable of forming the plurality of scattering means 1250 may be applied to the present invention. It is obvious to those skilled in the art.
  • the second semiconductor layer 1242 is formed on the second semiconductor layer 1241 on which the plurality of scattering means 1250 is formed.
  • the third semiconductor layer 1260, the reflective layer 1270, and the support layer 1280 are formed on the second semiconductor layer 1240. Form sequentially.
  • the method of separating the substrate 1210 and the first semiconductor layer 1220 may be performed by an LLO process, a CLO process, or the like.
  • the first semiconductor layer is described as being directly formed on the substrate, but the present invention is not limited thereto. That is, at least one other layer may be formed between the substrate and the first semiconductor layer, which may vary depending on the semiconductor device to be manufactured.
  • the method of manufacturing a semiconductor device according to an embodiment of the present invention may be implemented in the form of program instructions that may be executed by various computer means, and may be recorded in a computer readable medium.
  • the method may be provided in the form of software / firmware that is pre-programmed in a memory of a controller that generates a control signal of a semiconductor device manufacturing equipment, and may be sequentially performed in the programmed order.
  • the computer readable medium may include program instructions, data files, data structures, etc. alone or in combination.
  • Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those skilled in the art of computer software.
  • Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks.
  • Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like.
  • the hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.
  • a semiconductor device includes a first semiconductor layer of a first type; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, and one surface of the first semiconductor layer in contact with one surface of the active layer may be formed in an uneven shape.
  • a semiconductor device may include a first semiconductor layer of a first type; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer includes a plurality of scattering means for scattering light, thereby improving light extraction efficiency and luminous efficiency.

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Abstract

Disclosed are a semiconductor element and a production method therefor. A semiconductor element according to one embodiment of the present invention comprises: a first semiconductor layer of a first type; a second semiconductor layer of a second type; and an active layer positioned between the first semiconductor layer and the second semiconductor layer; wherein one surface of the first semiconductor layer, which makes contact with one surface of the active layer, is given an uneven form. Also, a semiconductor element according to another embodiment of the present invention comprises: a first semiconductor layer of a first type; a second semiconductor layer of a second type; and an active layer positioned between the first semiconductor layer and the second semiconductor layer; wherein the second semiconductor layer comprises a plurality of scattering means for scattering light, thereby making it possible to improve the light-extraction efficiency and the light-emission efficiency.

Description

반도체 소자 및 그 제조 방법 Semiconductor device and manufacturing method thereof
본 발명은 전류를 주입하는 경우 발광이 가능한 반도체 소자 및 그 제조 방법에 관한 것이며, 특히 광 도출 효율과 발광 효율을 향상시킬 수 있는 반도체 소자 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of emitting light when a current is injected and a method for manufacturing the same, and more particularly to a semiconductor device capable of improving light extraction efficiency and luminous efficiency and a method of manufacturing the same.
일반적으로 PN접합을 가지며 순방향으로 전류를 주입했을 때 발광하는 반도체 소자를 발광 다이오드(LED: light emitting diode)라고 한다. 발광 다이오드는 원하는 특정 주파수의 빛을 간단히 얻을 수 있으며, 필라멘트를 사용하는 전구에 비하여 소형이며 진동에 강하고 전력 소비가 적어 긴 수명을 가지고 있다는 장점이 있다. In general, a semiconductor device having a PN junction and emitting light when a current is injected in a forward direction is called a light emitting diode (LED). A light emitting diode can easily obtain light of a specific frequency desired, and has the advantages of being small, strong in vibration, and low in power consumption compared to a bulb using a filament, and having a long life.
갈륨-질소 화합물(GaN) 기반의 발광 다이오드가 개발되어 청색광을 쉽게 얻을 수 있게 됨으로써 발광 다이오드를 이용하여 다양한 색상의 빛을 구현할 수 있게 되었으며 이로 인하여 발광 다이오드의 응용 범위는 더욱 확대되고 있다. The development of a gallium-nitrogen compound (GaN) based light emitting diode makes it easy to obtain blue light, thereby enabling light of various colors using the light emitting diode, thereby expanding the application range of the light emitting diode.
발광 다이오드는 일반적으로 기판 위에 GaN 기반의 반도체 소자층을 성장하여 형성하며, 반도체 소자층 및 기판을 분리하여 개별 발광 다이오드 소자를 얻는 공정이 필요하다.A light emitting diode is generally formed by growing a GaN based semiconductor device layer on a substrate, and a process of obtaining a separate light emitting diode device by separating the semiconductor device layer and the substrate is required.
GaN 기반의 발광 다이오드는 평탄한 사파이어 기판 상에 형성되는데, 사파이어 기판은 격자 부정합이 크고, 열전도율이 낮으며 다이싱(dicing) 비용이 높으나 GaN과 같이 육방정 구조로 결정학적 구조가 비슷하다. 또한 사파이어는 융점이 높아 GaN과 같이 고온증착 박막의 기판으로 적합하고, 가격이 저렴한 반면, 전반사 현상으로 GaN층이 광학 공동(optical cavity)을 형성하기 때문에 광 도출 효율이 낮아져 고효율의 LED를 제조하는데 한계가 있다.GaN-based light emitting diodes are formed on a flat sapphire substrate. The sapphire substrate has a large lattice mismatch, low thermal conductivity, high dicing cost, but similar crystal structure with hexagonal structure like GaN. In addition, sapphire has a high melting point, which is suitable as a substrate for high temperature evaporation thin film such as GaN, and is inexpensive, while the total reflection phenomenon causes the GaN layer to form an optical cavity, resulting in a low light extraction efficiency, thereby producing a high efficiency LED. There is a limit.
종래 평탄한 사파이어 기판의 장점을 살리고 단점을 보완하기 위하여 표면에 요철을 가공한 사파이어 가공기판(PSS: Patterned Sapphire Substrate)을 이용하여 GaN 기반의 발광 다이오드를 제조하였다.In order to make use of the advantages of the conventional flat sapphire substrate and to compensate for the disadvantages, GaN-based light emitting diodes were manufactured by using a sapphire processed substrate (PSS: Patterned Sapphire Substrate).
PSS는 GaN의 전위밀도를 감소시키며, LED의 광 도출 효율을 크게 향상 시킨다. 즉, 평탄한 사파이어 기판의 경우 전반사 현상으로 GaN층이 광학 공동을 형성하기 때문에 LED의 광 도출 효율이 낮아지지만, PSS를 사용한 경우 GaN과 사파이어 계면의 요철 구조에 의하여 광 가둠 효과가 낮아져서 LED의 광 도출 효율이 향상된다.PSS reduces the dislocation density of GaN and greatly improves the light extraction efficiency of LEDs. That is, in the case of a flat sapphire substrate, the light extraction efficiency of the LED is lowered because the GaN layer forms an optical cavity due to total reflection, but in the case of PSS, the light trapping effect is lowered due to the uneven structure of the GaN and sapphire interface. The efficiency is improved.
하지만, PSS는 평탄한 사파이어 기판에 비해 가격이 고가이기 때문에 GaN 기반의 발광 다이오드를 제조하는 제조 비용이 상승하는 문제점이 있다.However, since PSS is more expensive than a flat sapphire substrate, manufacturing costs for manufacturing GaN-based light emitting diodes increase.
따라서, 광 도출 효율을 향상시키면서 발광 다이오드를 제조하는데 있어서 제조 비용을 줄일 수 있는 방법의 필요성이 대두된다.Therefore, there is a need for a method capable of reducing manufacturing costs in manufacturing light emitting diodes while improving light extraction efficiency.
본 발명은 상기와 같은 종래 기술의 문제점을 해결하고자 도출된 것으로서, 광 도출 효율을 향상시킬 수 있는 반도체 소자 및 그 제조 방법을 제공하는 것을 목적으로 한다.The present invention is derived to solve the problems of the prior art as described above, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can improve the light extraction efficiency.
또한, 본 발명은 활성층의 표면적을 개선하여 발광 효율을 향상시킬 수 있는 반도체 소자 및 그 제조 방법을 제공하는 것을 목적으로 한다.In addition, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can improve the luminous efficiency by improving the surface area of the active layer.
또한, 본 발명은 제조 비용을 줄이면서 광 도출 효율과 발광 효율을 향상시킬 수 있는 반도체 소자 및 그 제조 방법을 제공하는 것을 목적으로 한다.In addition, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can improve the light extraction efficiency and the light emission efficiency while reducing the manufacturing cost.
상기와 같은 목적을 달성하기 위하여, 본 발명의 일 실시예에 따른 반도체 소자는 제1 타입의 제1 반도체층; 제2 타입의 제2 반도체층; 및 상기 제1 반도체층과 상기 제2 반도체층 사이에 위치하는 활성층을 포함하며, 상기 활성층의 일면과 접하는 상기 제1 반도체층의 일면이 요철 형태로 형성된다.In order to achieve the above object, a semiconductor device according to an embodiment of the present invention is a first type of semiconductor layer; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, wherein one surface of the first semiconductor layer in contact with one surface of the active layer is formed in an uneven shape.
이때, 상기 활성층의 다른 일면이 상기 제1 반도체층의 일면의 요철 형태에 상응하는 요철 형태로 형성될 수 있고, 상기 활성층의 다른 일면과 이격되어 있는 상기 제2 반도체층의 일면이 요철 형태로 형성될 수 있다.In this case, the other surface of the active layer may be formed in an uneven form corresponding to the shape of the uneven surface of the first semiconductor layer, and one surface of the second semiconductor layer spaced apart from the other surface of the active layer may be formed in the form of unevenness. Can be.
나아가, 상기 반도체 소자를 지지하는 지지층을 더 포함하고, 상기 지지층은 상기 제2 반도체층 상에 형성될 수 있다.In addition, the semiconductor device may further include a support layer, wherein the support layer may be formed on the second semiconductor layer.
상기 반도체 소자는 다각형 또는 원형의 기둥 모양으로 형성될 수 있다.The semiconductor device may be formed in a polygonal or circular columnar shape.
본 발명의 다른 일 실시예에 따른 반도체 소자는 제1 타입의 제1 반도체층; 제2 타입의 제2 반도체층; 및 상기 제1 반도체층과 상기 제2 반도체층 사이에 위치하는 활성층을 포함하며, 상기 제2 반도체층은 광을 산란시키는 다수의 산란 수단을 포함한다.In accordance with another aspect of the present invention, a semiconductor device may include a first semiconductor layer of a first type; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer includes a plurality of scattering means for scattering light.
이때, 상기 산란 수단은 SiO2, Si3N4, TiO2, ZnO, MgZnO, Al2O3, AlN, In2O3 중 적어도 하나 이상의 물질로 구성될 수 있다.In this case, the scattering means may be composed of at least one material of SiO 2, Si 3 N 4, TiO 2, ZnO, MgZnO, Al 2 O 3, AlN, In 2 O 3.
이때, 상기 산란 수단은 상기 활성층과 접하는 상기 제2 반도체층의 일면에 위치하거나 상기 제2 반도체층의 다른 일면에 위치하거나 상기 제2 반도체층 내부에 위치할 수 있다.In this case, the scattering means may be located on one surface of the second semiconductor layer in contact with the active layer, on the other surface of the second semiconductor layer or in the second semiconductor layer.
본 발명의 일 실시예에 따른 반도체 소자 제조 방법은 기판 상에 제1 타입의 제1 반도체층을 형성하는 단계; 상기 제1 반도체층을 기 설정된 마스크 패턴에 따라 처리하여 상기 제1 반도체층의 일면을 요철 형태로 형성하는 단계; 상기 요철 형태로 형성된 상기 제1 반도체층의 일면 상에 활성층을 형성하는 단계; 및 상기 활성층 상부에 제2 타입의 제2 반도체층을 형성하는 단계를 포함한다.A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first semiconductor layer of a first type on a substrate; Treating the first semiconductor layer according to a preset mask pattern to form one surface of the first semiconductor layer in an uneven form; Forming an active layer on one surface of the first semiconductor layer formed in the uneven form; And forming a second semiconductor layer of a second type on the active layer.
상기 활성층을 형성하는 단계는 상기 제2 반도체층과 접하는 상기 활성층의 일면이 상기 제1 반도체층의 일면의 요철 형태에 상응하는 요철 형태가 되도록 상기 활성층을 형성할 수 있다.In the forming of the active layer, the active layer may be formed such that one surface of the active layer in contact with the second semiconductor layer has a concave-convex shape corresponding to the concave-convex shape of one surface of the first semiconductor layer.
상기 제2 반도체층을 형성하는 단계는 상기 활성층과 이격되어 있는 상기 제2 반도체층의 일면이 요철 형태가 되도록 상기 제2 반도체층을 형성할 수 있다.In the forming of the second semiconductor layer, the second semiconductor layer may be formed such that one surface of the second semiconductor layer spaced apart from the active layer has an uneven shape.
나아가, 상기 제2 반도체층 상에 상기 반도체 소자를 지지하기 위한 지지층을 형성하는 단계; 상기 기판을 상기 제1 반도체층으로부터 분리하는 단계; 및 상기 기판이 분리된 상기 제1 반도체층의 일면에 전극층을 형성하는 단계를 더 포함할 수 있다.Furthermore, forming a support layer for supporting the semiconductor device on the second semiconductor layer; Separating the substrate from the first semiconductor layer; And forming an electrode layer on one surface of the first semiconductor layer from which the substrate is separated.
본 발명의 다른 일 실시예에 따른 반도체 소자 제조 방법은 기판 상에 제1 타입의 제1 반도체층을 형성하는 단계; 상기 제1 반도체층 상에 활성층을 형성하는 단계; 및 상기 활성층 상에 광을 산란시키는 다수의 산란 수단을 포함하는 제2 타입의 제2 반도체층을 형성하는 단계를 포함한다.In another embodiment, a method of manufacturing a semiconductor device includes forming a first semiconductor layer of a first type on a substrate; Forming an active layer on the first semiconductor layer; And forming a second type of semiconductor layer comprising a plurality of scattering means for scattering light on the active layer.
상기 제2 반도체층을 형성하는 단계는 상기 활성층 상에 상기 활성층의 일부가 노출되도록 상기 다수의 산란 수단을 형성하는 단계; 및 상기 다수의 산란 수단이 형성된 상기 활성층 상에 상기 제2 반도체층을 형성하는 단계를 포함할 수 있다.The forming of the second semiconductor layer may include forming the plurality of scattering means on the active layer to expose a portion of the active layer; And forming the second semiconductor layer on the active layer in which the plurality of scattering means is formed.
상기 제2 반도체층을 형성하는 단계는 상기 제2 반도체층 상에 상기 제2 반도체층의 일부가 노출되도록 상기 다수의 산란 수단을 형성할 수 있다.In the forming of the second semiconductor layer, the plurality of scattering means may be formed on the second semiconductor layer so that a part of the second semiconductor layer is exposed.
상기 제2 반도체층을 형성하는 단계는 제1 높이의 상기 제2 반도체층을 형성하는 단계; 상기 제1 높이의 상기 제2 반도체층 상에 상기 다수의 산란 수단을 형성하는 단계 및 상기 다수의 산란 수단이 형성된 상기 제1 높이의 상기 제2 반도체층 상에 제2 높이의 상기 제2 반도체층을 형성하는 단계를 포함할 수 있다.The forming of the second semiconductor layer may include forming the second semiconductor layer having a first height; Forming the plurality of scattering means on the second semiconductor layer of the first height and the second semiconductor layer of the second height on the second semiconductor layer of the first height on which the plurality of scattering means is formed It may include forming a.
본 발명의 반도체 소자 및 그 제조 방법에 따르면, 기판 예를 들어, 사파이어 기판, SiC 기판 상에 반도체 소자 예를 들어, GaN 기반의 발광 다이오드를 제조한 후 기판을 분리하는 반도체 소자에 있어서, 활성층 및/또는 반도체층을 요철 형태로 형성함으로써, 광 가둠 효과를 낮춰 광 도출 효율을 향상시키고, 요철 형태의 활성층에 의하여 활성층의 표면적이 커지기 때문에 단위 면적당 발광 효율을 개선시켜 반도체 소자의 발광 효율을 향상시킬 수 있다.According to the semiconductor device of the present invention and a method of manufacturing the same, in the semiconductor device for manufacturing a semiconductor device, for example, GaN-based light-emitting diode on the substrate, for example, sapphire substrate, SiC substrate, and then separating the substrate, the active layer and By forming the semiconductor layer in the form of unevenness, the light confinement effect is reduced to improve the light extraction efficiency, and the surface area of the active layer is increased by the uneven shape of the active layer, thereby improving the light emitting efficiency per unit area to improve the light emitting efficiency of the semiconductor device. Can be.
또한, 본 발명은 활성층 상부에 형성되는 제2 반도체층에 광을 산란시키는 다수의 산란 수단을 형성함으로써, 광 가둠 효과를 낮춰 광 도출 효율을 향상시킬 수 있다.In addition, the present invention can improve the light extraction efficiency by lowering the light trapping effect by forming a plurality of scattering means for scattering light in the second semiconductor layer formed on the active layer.
본 발명은 (PSS 기판을 사용하지 않고) 평탄한 기판을 사용하는 경우에도, PSS를 사용하는 것과 같이 광 도출 효율을 향상시킬 수 있기 때문에 PSS를 사용한 반도체 소자에 비해 그 제조 비용을 줄일 수 있으며, 이를 통해 반도체 소자의 가격 경쟁력을 향상시킬 수 있다.In the present invention, even when using a flat substrate (without using a PSS substrate), since the light extraction efficiency can be improved as in the case of using the PSS, the manufacturing cost can be reduced compared to the semiconductor device using the PSS. Through this, the price competitiveness of semiconductor devices can be improved.
뿐만 아니라, 본 발명은 광 진행 경로 상의 광 가둠 효과를 낮출 뿐만 아니라, 활성층과 이웃한 GaN 반도체 층 간의 경계면의 표면적을 넓혀 발광 효율을 개선시킬 수 있는 효과가 있다.In addition, the present invention not only lowers the light confinement effect on the light propagation path, but also has the effect of improving the luminous efficiency by increasing the surface area of the interface between the active layer and the neighboring GaN semiconductor layer.
이런 본 발명의 반도체 소자 제조 방법은 수직형 반도체 소자 제조 방법에 한정되지 않으며, 수평형 반도체 소자에도 적용될 수 있는 것이다. Such a semiconductor device manufacturing method of the present invention is not limited to the vertical semiconductor device manufacturing method, it is also applicable to a horizontal semiconductor device.
도 1은 본 발명의 일 실시예에 따른 반도체 소자를 도시하는 도면이다.1 is a diagram illustrating a semiconductor device according to an embodiment of the present invention.
도 2는 본 발명의 일 실시예에 따른 반도체 소자의 단면도를 나타낸 것이다.2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
도 3은 도 1에 도시된 활성층과 인접하는 제1 반도체층의 일면에 대한 일 예의 평면도를 나타낸 것이다.3 is a plan view of an example of one surface of a first semiconductor layer adjacent to the active layer illustrated in FIG. 1.
도 4는 도 1에 도시된 활성층과 인접하는 제1 반도체층의 일면에 대한 다른 일 예의 평면도를 나타낸 것이다.4 is a plan view illustrating another example of one surface of a first semiconductor layer adjacent to the active layer illustrated in FIG. 1.
도 5 내지 도 7은 도 2에 도시된 반도체 소자 제조 방법의 공정 과정을 설명하기 위한 일 실시예 단면도를 나타낸 것이다.5 to 7 illustrate cross-sectional views of one embodiment for describing a process of the method of manufacturing the semiconductor device illustrated in FIG. 2.
도 8은 본 발명의 다른 일 실시예에 따른 반도체 소자를 도시하는 도면이다.8 is a diagram illustrating a semiconductor device according to another embodiment of the present invention.
도 9는 본 발명의 다른 일 실시예에 따른 반도체 소자의 단면도를 나타낸 것이다.9 is a sectional view of a semiconductor device according to another embodiment of the present invention.
도 10은 본 발명의 또 다른 일 실시예에 따른 반도체 소자의 단면도를 나타낸 것이다.10 is a sectional view of a semiconductor device according to another embodiment of the present invention.
도 11은 본 발명의 또 다른 일 실시예에 따른 반도체 소자의 단면도를 나타낸 것이다.11 is a sectional view of a semiconductor device according to another embodiment of the present invention.
도 12 내지 도 14는 도 9에 도시된 반도체 소자 제조 방법의 공정 과정을 설명하기 위한 일 실시예 단면도를 나타낸 것이다.12 to 14 illustrate cross-sectional views of one embodiment for describing a process of the method of manufacturing the semiconductor device illustrated in FIG. 9.
상기와 같은 목적을 달성하기 위하여, 본 발명의 일 실시예에 따른 반도체 소자는 제1 타입의 제1 반도체층; 제2 타입의 제2 반도체층; 및 상기 제1 반도체층과 상기 제2 반도체층 사이에 위치하는 활성층을 포함하며, 상기 활성층의 일면과 접하는 상기 제1 반도체층의 일면이 요철 형태로 형성된다.In order to achieve the above object, a semiconductor device according to an embodiment of the present invention is a first type of semiconductor layer; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, wherein one surface of the first semiconductor layer in contact with one surface of the active layer is formed in an uneven shape.
이때, 상기 활성층의 다른 일면이 상기 제1 반도체층의 일면의 요철 형태에 상응하는 요철 형태로 형성될 수 있고, 상기 활성층의 다른 일면과 이격되어 있는 상기 제2 반도체층의 일면이 요철 형태로 형성될 수 있다.In this case, the other surface of the active layer may be formed in an uneven form corresponding to the shape of the uneven surface of the first semiconductor layer, and one surface of the second semiconductor layer spaced apart from the other surface of the active layer may be formed in the form of unevenness. Can be.
나아가, 상기 반도체 소자를 지지하는 지지층을 더 포함하고, 상기 지지층은 상기 제2 반도체층 상에 형성될 수 있다.In addition, the semiconductor device may further include a support layer, wherein the support layer may be formed on the second semiconductor layer.
상기 반도체 소자는 다각형 또는 원형의 기둥 모양으로 형성될 수 있다.The semiconductor device may be formed in a polygonal or circular columnar shape.
본 발명의 다른 일 실시예에 따른 반도체 소자는 제1 타입의 제1 반도체층; 제2 타입의 제2 반도체층; 및 상기 제1 반도체층과 상기 제2 반도체층 사이에 위치하는 활성층을 포함하며, 상기 제2 반도체층은 광을 산란시키는 다수의 산란 수단을 포함한다.In accordance with another aspect of the present invention, a semiconductor device may include a first semiconductor layer of a first type; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer includes a plurality of scattering means for scattering light.
이때, 상기 산란 수단은 SiO2, Si3N4, TiO2, ZnO, MgZnO, Al2O3, AlN, In2O3 중 적어도 하나 이상의 물질로 구성될 수 있다.In this case, the scattering means may be composed of at least one material of SiO 2, Si 3 N 4, TiO 2, ZnO, MgZnO, Al 2 O 3, AlN, In 2 O 3.
이때, 상기 산란 수단은 상기 활성층과 접하는 상기 제2 반도체층의 일면에 위치하거나 상기 제2 반도체층의 다른 일면에 위치하거나 상기 제2 반도체층 내부에 위치할 수 있다.In this case, the scattering means may be located on one surface of the second semiconductor layer in contact with the active layer, on the other surface of the second semiconductor layer or in the second semiconductor layer.
본 발명의 일 실시예에 따른 반도체 소자 제조 방법은 기판 상에 제1 타입의 제1 반도체층을 형성하는 단계; 상기 제1 반도체층을 기 설정된 마스크 패턴에 따라 처리하여 상기 제1 반도체층의 일면을 요철 형태로 형성하는 단계; 상기 요철 형태로 형성된 상기 제1 반도체층의 일면 상에 활성층을 형성하는 단계; 및 상기 활성층 상부에 제2 타입의 제2 반도체층을 형성하는 단계를 포함한다.A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first semiconductor layer of a first type on a substrate; Treating the first semiconductor layer according to a preset mask pattern to form one surface of the first semiconductor layer in an uneven form; Forming an active layer on one surface of the first semiconductor layer formed in the uneven form; And forming a second semiconductor layer of a second type on the active layer.
상기 활성층을 형성하는 단계는 상기 제2 반도체층과 접하는 상기 활성층의 일면이 상기 제1 반도체층의 일면의 요철 형태에 상응하는 요철 형태가 되도록 상기 활성층을 형성할 수 있다.In the forming of the active layer, the active layer may be formed such that one surface of the active layer in contact with the second semiconductor layer has a concave-convex shape corresponding to the concave-convex shape of one surface of the first semiconductor layer.
상기 제2 반도체층을 형성하는 단계는 상기 활성층과 이격되어 있는 상기 제2 반도체층의 일면이 요철 형태가 되도록 상기 제2 반도체층을 형성할 수 있다.In the forming of the second semiconductor layer, the second semiconductor layer may be formed such that one surface of the second semiconductor layer spaced apart from the active layer has an uneven shape.
나아가, 상기 제2 반도체층 상에 상기 반도체 소자를 지지하기 위한 지지층을 형성하는 단계; 상기 기판을 상기 제1 반도체층으로부터 분리하는 단계; 및 상기 기판이 분리된 상기 제1 반도체층의 일면에 전극층을 형성하는 단계를 더 포함할 수 있다.Furthermore, forming a support layer for supporting the semiconductor device on the second semiconductor layer; Separating the substrate from the first semiconductor layer; And forming an electrode layer on one surface of the first semiconductor layer from which the substrate is separated.
본 발명의 다른 일 실시예에 따른 반도체 소자 제조 방법은 기판 상에 제1 타입의 제1 반도체층을 형성하는 단계; 상기 제1 반도체층 상에 활성층을 형성하는 단계; 및 상기 활성층 상에 광을 산란시키는 다수의 산란 수단을 포함하는 제2 타입의 제2 반도체층을 형성하는 단계를 포함한다.In another embodiment, a method of manufacturing a semiconductor device includes forming a first semiconductor layer of a first type on a substrate; Forming an active layer on the first semiconductor layer; And forming a second type of semiconductor layer comprising a plurality of scattering means for scattering light on the active layer.
상기 제2 반도체층을 형성하는 단계는 상기 활성층 상에 상기 활성층의 일부가 노출되도록 상기 다수의 산란 수단을 형성하는 단계; 및 상기 다수의 산란 수단이 형성된 상기 활성층 상에 상기 제2 반도체층을 형성하는 단계를 포함할 수 있다.The forming of the second semiconductor layer may include forming the plurality of scattering means on the active layer to expose a portion of the active layer; And forming the second semiconductor layer on the active layer in which the plurality of scattering means is formed.
상기 제2 반도체층을 형성하는 단계는 상기 제2 반도체층 상에 상기 제2 반도체층의 일부가 노출되도록 상기 다수의 산란 수단을 형성할 수 있다.In the forming of the second semiconductor layer, the plurality of scattering means may be formed on the second semiconductor layer so that a part of the second semiconductor layer is exposed.
상기 제2 반도체층을 형성하는 단계는 제1 높이의 상기 제2 반도체층을 형성하는 단계; 상기 제1 높이의 상기 제2 반도체층 상에 상기 다수의 산란 수단을 형성하는 단계 및 상기 다수의 산란 수단이 형성된 상기 제1 높이의 상기 제2 반도체층 상에 제2 높이의 상기 제2 반도체층을 형성하는 단계를 포함할 수 있다.The forming of the second semiconductor layer may include forming the second semiconductor layer having a first height; Forming the plurality of scattering means on the second semiconductor layer of the first height and the second semiconductor layer of the second height on the second semiconductor layer of the first height on which the plurality of scattering means is formed It may include forming a.
이하에서, 본 발명의 실시예를 첨부된 도면을 참조하여 상세하게 설명한다. 그러나, 본 발명이 실시예들에 의해 제한되거나 한정되는 것은 아니다. 각 도면에 제시된 동일한 참조 부호는 동일한 부재를 나타낸다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. Like reference numerals in the drawings denote like elements.
이하의 도면들은 본 발명의 특징을 두드러지게 나타내기 위하여 간략화되고, 다소 과장되게 그려졌으며, 이하의 도면들의 치수는 실제 본 발명의 제품들의 치수와 정확하게 일치하지 않을 수 있다. The following drawings are simplified and somewhat exaggerated to clearly show the features of the present invention, and the dimensions of the following drawings may not exactly match the dimensions of the actual products of the present invention.
해당 기술 분야의 통상의 기술자라면, 이하의 도면들의 기재로부터 각 구성 요소의 길이, 둘레, 두께 등 치수를 용이하게 변형하여 실제 제품에 적용할 수 있을 것이며, 이러한 변형은 본 발명의 권리 범위에 속할 것임은 해당 기술 분야의 통상의 기술자에게 자명하다.Those skilled in the art will be able to easily modify the dimensions, such as length, circumference, thickness, etc. of each component from the description of the drawings below, and apply them to the actual product, and such modifications may fall within the scope of the present invention. It will be apparent to those skilled in the art.
본 발명에 기재된 제1 반도체층, 활성층, 제2 반도체층은 GaN, AlGaN, AlGaAs, AlGaInP, GaAsP, GaP 또는 InGaN 중 적어도 하나를 포함하는 하나 이상의 물질로 구현될 수 있다.The first semiconductor layer, the active layer, and the second semiconductor layer described in the present invention may be implemented with one or more materials including at least one of GaN, AlGaN, AlGaAs, AlGaInP, GaAsP, GaP, or InGaN.
도 1은 본 발명의 일 실시예에 따른 반도체 소자를 도시하는 도면으로, 반도체 소자(100)는 지지층(110), 반사층(120), 제3 반도체층(130), 제2 반도체층(140), 활성층(150), 제1 반도체층(160) 및 전극층(170)을 포함하며, 정육각 기둥 모양을 가지고 있다.1 is a diagram illustrating a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 includes a support layer 110, a reflective layer 120, a third semiconductor layer 130, and a second semiconductor layer 140. , An active layer 150, a first semiconductor layer 160, and an electrode layer 170, and have a regular hexagonal pillar shape.
반도체 소자(100)를 구성하고 있는 층들에 대해서는 도 2에서 설명하며, 본 발명의 반도체 소자는 정육각 기둥 모양에 한정되지 않고, 다각형 모양을 가질 수 있다.The layers constituting the semiconductor device 100 will be described with reference to FIG. 2, and the semiconductor device of the present invention is not limited to a regular hexagonal column shape but may have a polygonal shape.
도 2는 본 발명의 일 실시예에 따른 반도체 소자의 단면도를 나타낸 것으로, 반도체 소자(200)는 지지층(210), 반사층(220), 제3 반도체층(230), 제2 반도체층(240), 활성층(250), 제1 반도체층(260) 및 전극층(270)을 포함한다.2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. The semiconductor device 200 includes a support layer 210, a reflective layer 220, a third semiconductor layer 230, and a second semiconductor layer 240. , An active layer 250, a first semiconductor layer 260, and an electrode layer 270.
제1 반도체층(260)은 제1 타입의 반도체층으로, 활성층(250)과 인접하는 일면이 요철 형태로 형성된다.The first semiconductor layer 260 is a first type of semiconductor layer, and one surface adjacent to the active layer 250 is formed in an uneven form.
여기서, 제1 반도체층(260)은 N 타입의 반도체층일 수 있으며, 일 예로 N 타입의 GaN층일 수 있다.Here, the first semiconductor layer 260 may be an N type semiconductor layer, for example, an N type GaN layer.
일 예로, 제1 반도체층(260)은 에피 성장(epitaxial growth)에 의하여 형성된 제1 반도체층의 일면에 일정 모양의 마스크 패턴을 형성한 후 식각함으로써, 요철 형태의 제1 반도체층(260)을 형성할 수 있다.For example, the first semiconductor layer 260 may form a mask pattern having a predetermined shape on one surface of the first semiconductor layer formed by epitaxial growth and then etch the first semiconductor layer 260 having an uneven shape. Can be formed.
다른 일 예로, 제1 반도체층(260)은 에피 성장을 이용하여 일정 두께를 갖는 평탄한 제1 반도체층을 형성한 후 제1 반도체층의 일면과 일정 거리 이격된 물리적인 마스크 패턴을 이용하여 제1 반도체층 상부에 다시 에피 성장함으로써, 요철 형태의 제1 반도체층(260)을 형성할 수도 있다.As another example, the first semiconductor layer 260 may be formed of a first semiconductor layer having a predetermined thickness by using epitaxial growth, and then may be formed using a physical mask pattern spaced apart from a surface of the first semiconductor layer by a predetermined distance. By epitaxially growing on the semiconductor layer again, the first semiconductor layer 260 having an uneven shape may be formed.
본 발명의 상세한 설명에서는 마스크 패턴을 이용하여 제1 반도체층을 식각함으로써, 제1 반도체층을 요철 형태로 형성하는 실시예를 중심으로으로 설명한다.In the detailed description of the present invention, the first semiconductor layer is etched using the mask pattern, and thus, the first semiconductor layer is formed in the form of irregularities.
제1 반도체층(260)은 도 3과 도 4에 도시된 제1 반도체층의 일면에 대한 평면도에서와 같이, 요철 형태의 돌출된 부분이 원형 또는 사각형 모양을 가질 수 있다.As shown in the plan view of one surface of the first semiconductor layer shown in FIGS. 3 and 4, the first semiconductor layer 260 may have a rounded or quadrangular shape with a protruding portion having a concave-convex shape.
물론, 제1 반도체층(260)의 요철 형태가 원형, 사각형에 한정되는 것은 아니며, 반원, 원기둥, 다각 기둥 등의 다양한 형태를 가질 수 있다.Of course, the shape of the concave-convex shape of the first semiconductor layer 260 is not limited to a circle or a rectangle, and may have various forms such as a semicircle, a cylinder, and a polygonal column.
활성층(250)은 요철 형태로 형성된 제1 반도체층(260)의 일면에 접하여 형성되며, 발광 다이오드 반도체 소자의 발광 효율을 높이기 위하여 제1 반도체층(260)과 제2 반도체층(240) 사이에 형성된다.The active layer 250 is formed in contact with one surface of the first semiconductor layer 260 formed in the uneven shape, and between the first semiconductor layer 260 and the second semiconductor layer 240 in order to increase the luminous efficiency of the LED semiconductor device. Is formed.
이때, 활성층(250)은 양자 우물접합층(MQW, multi-quantum well)으로 불리기도 한다.In this case, the active layer 250 may also be referred to as a quantum well bonding layer (MQW).
본 발명에서 활성층(250)은 단위 면적당 발광 효율을 향상시키기 위해, 제2 반도체층(240)과 접하는 일면이 요철 형태로 형성되며, 활성층(250)의 요철 형태는 제1 반도체층(260)의 요철 형태에 상응한다. 즉, 활성층(250)이 평탄한 상태에 비하여 그 표면적이 커지기 때문에 단위 면적당 발광 효율이 향상된다.In the present invention, in order to improve the luminous efficiency per unit area, the active layer 250 has one surface in contact with the second semiconductor layer 240 in a concave-convex shape, and the concave-convex shape of the active layer 250 is formed in the first semiconductor layer 260. Corresponds to the uneven form. That is, since the surface area of the active layer 250 is larger than that of the flat state, the luminous efficiency per unit area is improved.
활성층(250)의 일면을 요철 형태로 형성하는 방법이 다양할 수 있다. 일 예로, 요철 형태를 갖는 제1 반도체층(260)의 일면에 활성층(250)을 증착 또는 에피 성장하게 되면 활성층(250)의 일면이 제1 반도체층(260)의 요철 형태에 상응하는 요철 형태를 가지면서 형성될 수 있다. 다른 일 예로, 활성층을 형성한 후 마스크 패턴을 이용하여 식각함으로써, 요철 형태의 활성층(250)을 형성할 수도 있다.Various methods may be used to form one surface of the active layer 250 in an uneven form. For example, when the active layer 250 is deposited or epitaxially grown on one surface of the first semiconductor layer 260 having an uneven shape, one surface of the active layer 250 corresponds to the uneven shape of the first semiconductor layer 260. It can be formed while having. As another example, the active layer 250 may be formed by etching using a mask pattern after forming the active layer.
이와 같이, 다양한 방법에 의하여 활성층이 요철 형태를 갖도록 형성할 수 있지만, 공정 과정을 단순화하고 공정 비용을 줄이기 위해 요철 형태를 갖는 제1 반도체층(260)의 일면에 활성층(250)을 형성함으로써, 활성층이 자연스럽게 요철 형태를 갖도록 형성하는 실시예를 중심으로 이후의 과정을 설명한다.As described above, although the active layer may be formed to have an uneven shape by various methods, the active layer 250 is formed on one surface of the first semiconductor layer 260 having the uneven shape to simplify the process and reduce the process cost. The following process will be mainly described based on the embodiment in which the active layer is naturally formed to have an uneven shape.
제2 반도체층(240)은 제2 타입의 반도체층으로, 요철 형태로 형성된 활성층(250)의 일면에 형성되며, 제3 반도체층(230)과 인접하는 제2 반도체층(240)의 일면 또한 요철 형태로 형성된다.The second semiconductor layer 240 is a second type of semiconductor layer, which is formed on one surface of the active layer 250 formed in the uneven form, and also one surface of the second semiconductor layer 240 adjacent to the third semiconductor layer 230. It is formed in the form of unevenness.
여기서, 제2 반도체층(240)은 P 타입의 반도체층일 수 있으며, 일 예로 P 타입의 GaN층일 수 있다.Here, the second semiconductor layer 240 may be a P-type semiconductor layer, for example, may be a P-type GaN layer.
제3 반도체층(230)은 제2 반도체층(240)의 일면에 형성되며, 제3 반도체층(230)의 일면 또한 제2 반도체층(240)의 요철 형태에 상응하는 요철 형태로 형성될 수 있다.The third semiconductor layer 230 may be formed on one surface of the second semiconductor layer 240, and one surface of the third semiconductor layer 230 may also be formed in an uneven shape corresponding to the uneven shape of the second semiconductor layer 240. have.
여기서, 제3 반도체층(230)은 제2 반도체층(240) 상에 P 전극을 콘택 할 수 있는 반도체층으로, In1-xGaxN층일 수 있다.Here, the third semiconductor layer 230 is a semiconductor layer capable of contacting the P electrode on the second semiconductor layer 240, and may be an In 1-x Ga x N layer.
반사층(220)은 제3 반도체층(230)의 일면에 형성되며, 활성층(250)에서 발생되어 후방으로 진행하는 광을 전방으로 반사시키는 역할을 한다.The reflective layer 220 is formed on one surface of the third semiconductor layer 230 and serves to reflect the light generated in the active layer 250 and traveling backward.
이때, 반사층(220)의 일면은 평탄한 형태로 형성될 수 있다.In this case, one surface of the reflective layer 220 may be formed in a flat shape.
지지층(210)은 반도체 소자의 기계적 지지를 제공하는 층으로, 반사층(220)의 일면에 형성되며, 금속 지지층일 수 있다.The support layer 210 is a layer providing mechanical support of the semiconductor device, and is formed on one surface of the reflective layer 220 and may be a metal support layer.
지지층(210)은 전기 전도도 및 열 전도도가 높고, 기계적인 강도가 상대적으로 높은 금속, 예를 들어 구리 또는 구리 화합물 등이 이용 가능하다. The support layer 210 may be formed of a metal having high electrical conductivity and thermal conductivity and having a relatively high mechanical strength, for example, copper or a copper compound.
또한, 지지층(210)은 전기적 도금 방법을 통하여 형성될 수 있으며, 실시예에 따라서는 낮은 밀도를 가지며 스트레스를 완화시킬 수 있는 연성 구리층(도시되지 않음)과, 높은 밀도와 강도를 가지며 역학적인 지지(mechanical support)를 제공하는 경성 구리층(도시되지 않음)의 2층으로 구성될 수도 있다. 연성 구리층은 경성 구리층보다 느린 도금 속도를 가지는 도금 방법으로 형성될 수 있으며, 지지층(210)의 두께에 기인한 스트레스를 완화하기 위한 수단을 제공할 수 있다. 연성 구리층의 도금 방법의 예로는 황산염계 도금 방법을 들 수 있으며, 이 때 가능한 도금 속도는 3 내지 5 um/hour 이다. 경성 구리층의 도금 방법의 예로는 주석(Sn)과 철(Fe)을 포함하는 금속 합금 기반의 도금 방법을 들 수 있으며, 이 때 가능한 도금 속도는 20 um/hour 이다.In addition, the support layer 210 may be formed through an electroplating method, and according to the embodiment, a flexible copper layer (not shown) having a low density and alleviating stress, and a high density and strength, It may also consist of two layers of a hard copper layer (not shown) that provides mechanical support. The flexible copper layer may be formed by a plating method having a slower plating rate than the hard copper layer, and may provide a means for relieving stress due to the thickness of the support layer 210. Examples of the plating method of the flexible copper layer include a sulfate-based plating method, and the possible plating speed is 3 to 5 um / hour. An example of the plating method of the hard copper layer is a metal alloy-based plating method including tin (Sn) and iron (Fe), and the possible plating speed is 20 um / hour.
전극층(270)은 요철 형태를 갖는 제1 반도체층(260)의 다른 일면에 형성되며 반도체 소자에 전원을 인가하기 위한 층이다.The electrode layer 270 is formed on the other surface of the first semiconductor layer 260 having an uneven shape and is a layer for applying power to the semiconductor device.
이때, 전극층(270)은 금속 및 금속 화합물을 이용하여 형성할 수 있다.In this case, the electrode layer 270 may be formed using a metal and a metal compound.
이와 같이, 본 발명의 일 실시예에 따른 반도체 소자는 제1 반도체층, 활성층, 제2 반도체층 및 제3 반도체층이 요철 형태를 가지도록 형성함으로써, 광 가둠 효과를 낮춰 광 도출 효율을 향상시킬 수 있으며, 활성층의 표면적을 크게 하여 단위 면적당 발광 효율을 향상시킬 수 있다.As described above, the semiconductor device according to the embodiment of the present invention is formed such that the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer have an uneven shape, thereby lowering the light confinement effect and improving light extraction efficiency. The surface area of the active layer may be increased to improve luminous efficiency per unit area.
비록, 도 2에서 제1 반도체층, 활성층, 제2 반도체층 및 제3 반도체층이 모두 요철 형태를 가지는 것으로 도시하였지만, 이에 한정하지 않으며, 제1 반도체층만이 요철 형태로 형성되고, 활성층, 제2 반도체층 및 제3 반도체층은 평탄한 층으로 형성될 수도 있다. 즉, 본 발명은 제1 반도체층 예를 들어, N 타입의 GaN층만을 요철 형태로 형성할 수도 있고, 필요에 따라 활성층과 제2 반도체층 예를 들어, P 타입의 GaN층 및 제2 반도체층 상부에 형성되는 제3 반도체층 또한 요철 형태로 형성할 수도 있다.Although FIG. 2 illustrates that the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer all have a concave-convex shape, the present invention is not limited thereto. Only the first semiconductor layer is formed in the concave-convex shape. The second semiconductor layer and the third semiconductor layer may be formed of a flat layer. That is, in the present invention, only the first semiconductor layer, for example, an N type GaN layer may be formed in an uneven form, and if necessary, the active layer and the second semiconductor layer, for example, a P type GaN layer and a second semiconductor layer may be used. The third semiconductor layer formed on the upper portion may also be formed in an uneven form.
물론, 제1 반도체층과 활성층만이 요철 형태로 형성되고, 제2 반도체층 및 제3 반도체층은 평탄한 층으로 형성될 수도 있다. 활성층은 제1 반도체층의 요철 형태에 따라 요철 형태로 형성될 수도 있지만, 일정 이상의 두께로 성장되는 경우에는 평탄하게 형성될 수도 있다.Of course, only the first semiconductor layer and the active layer may be formed in an uneven form, and the second semiconductor layer and the third semiconductor layer may be formed as flat layers. The active layer may be formed in an uneven form according to the uneven form of the first semiconductor layer, but may be formed flat when grown to a predetermined thickness or more.
도 5 내지 도 7은 도 2에 도시된 반도체 소자 제조 방법의 공정 과정을 설명하기 위한 일 실시예 단면도를 나타낸 것이다.5 to 7 illustrate cross-sectional views of one embodiment for describing a process of the method of manufacturing the semiconductor device illustrated in FIG. 2.
도 5에서, 기판(510) 예를 들어, 사파이어 기판 또는 SiC 기판 상부에 에피 성장에 의하여 일정 두께를 갖는 제1 타입 예를 들어, N 타입의 제1 반도체층(520)을 형성한다.In FIG. 5, a first type semiconductor layer 520 having a predetermined thickness, for example, an N type, is formed on the substrate 510, for example, an sapphire substrate or an SiC substrate by epitaxial growth.
기판(510) 상에 형성된 제1 반도체층(520)은 기 설정된 마스크 패턴을 이용하여 식각함으로써, 제1 반도체층(520)의 상부가 요철 형태를 갖도록 형성한다.The first semiconductor layer 520 formed on the substrate 510 is etched using a preset mask pattern to form an upper portion of the first semiconductor layer 520 to have an uneven shape.
여기서, 제1 반도체층(520)의 요철 형태는 광 도출 효율과 발광 효율 등을 고려하여 그 모양 및 도출 간격이 결정될 수 있다.Here, the shape and the extraction interval of the uneven shape of the first semiconductor layer 520 may be determined in consideration of light extraction efficiency and luminous efficiency.
도 6에서, 요철 형태를 갖는 제1 반도체층(520) 상에 활성층(530), 제2 반도체층(540), 제3 반도체층(550), 반사층(560) 및 지지층(570)을 순차적으로 형성한다.In FIG. 6, the active layer 530, the second semiconductor layer 540, the third semiconductor layer 550, the reflective layer 560, and the support layer 570 are sequentially formed on the first semiconductor layer 520 having an uneven shape. Form.
여기서, 활성층(530), 제2 반도체층(540) 및 제3 반도체층(550)은 제1 반도체층(520)의 요철 형태에 상응하는 요철 형태로 형성될 수 있으며, 각 층마다 형성되는 요철 형태의 크기는 동일하거나 상이할 수 있다.Here, the active layer 530, the second semiconductor layer 540, and the third semiconductor layer 550 may be formed in an uneven shape corresponding to the uneven shape of the first semiconductor layer 520, and the unevenness is formed in each layer. The size of the shapes may be the same or different.
필요에 따라, 제1 반도체층(520) 상에 형성되는 활성층(530)은 발광 효율 등을 고려하여 제1 반도체층(520)의 요철 형태와 상이한 요철 형태를 갖도록 형성할 수도 있다. 즉, 제1 반도체층(520) 상에 활성층(530)을 일정 두께로 형성한 후 별도의 마스크 패턴을 이용하여 활성층(530)을 식각함으로써, 제1 반도체층(520)의 요철 형태와 상이한 요철 형태를 가질 수 있다.If necessary, the active layer 530 formed on the first semiconductor layer 520 may be formed to have a concave-convex shape different from the concave-convex shape of the first semiconductor layer 520 in consideration of luminous efficiency. That is, the active layer 530 is formed on the first semiconductor layer 520 to have a predetermined thickness, and then the active layer 530 is etched using a separate mask pattern, so that the unevenness of the first semiconductor layer 520 is different from that of the uneven shape of the first semiconductor layer 520. It may have a form.
도 7에서, 기판(510)과 제1 반도체층(520)을 분리하는 공정을 수행한 후 요철 형태로 형성된 제1 반도체층(520)의 다른 일면 즉, 제1 반도체층의 평탄한 면 상부에 반도체 소자에 전원을 공급하기 위한 전극층(580)을 형성한다.In FIG. 7, after the process of separating the substrate 510 and the first semiconductor layer 520, a semiconductor is formed on the other surface of the first semiconductor layer 520 formed in the uneven shape, that is, the flat surface of the first semiconductor layer. An electrode layer 580 for supplying power to the device is formed.
기판(510)과 제1 반도체층(520)을 분리하는 일 예의 방법은 레이저 리프트 오프(LLO, Laser Lift Off) 방법으로, 기판(510)을 투과할 수 있는 특정 주파수 대역의 레이저를 기판에 조사하면, 기판(510)을 투과한 레이저가 기판(510)과 제1 반도체층(520) 사이의 경계면에 흡수되어 열이 발생한다. 이때, 기판(510)과 제1 반도체층(520) 사이의 경계면이 용융되어 기판(510)과 제1 반도체층(520)이 분리된다. An example method of separating the substrate 510 and the first semiconductor layer 520 is a laser lift off (LLO) method, which irradiates the substrate with a laser of a specific frequency band that may pass through the substrate 510. When the laser beam penetrating the substrate 510 is absorbed by the interface between the substrate 510 and the first semiconductor layer 520, heat is generated. At this time, the interface between the substrate 510 and the first semiconductor layer 520 is melted to separate the substrate 510 and the first semiconductor layer 520.
기판(510)과 제1 반도체층(520)을 분리하는 다른 일 예의 방법은 화학적 리프트 오프(CLO, Chemical Lift Off) 방법으로, CLO 공정은 기판(510)과 제1 반도체층(520) 간의 경계 물질의 화학적 반응에 의하여 진행된다. Another example of separating the substrate 510 and the first semiconductor layer 520 is a chemical lift off (CLO) method, and the CLO process is a boundary between the substrate 510 and the first semiconductor layer 520. Proceed by chemical reaction of the material.
상기에서 알 수 있듯이, 본 발명의 반도체 소자는 기판을 포함하는 종래 반도체 소자와는 달리, 기판이 분리된 상태에서도 PSS 상에 형성된 반도체 소자와 같이 광 도출 효율을 향상시킬 수도 있으며, 활성층이 요철 형태로 형성되어 표면적이 커짐으로써 반도체 소자의 발광 효율을 향상시킬 수 있다. 즉, PSS가 아닌 평탄한 기판을 사용하여 제조가 가능하기 때문에 제조 비용을 줄일 수 있으면서, 고효율의 발광 다이오드를 제조할 수 있다.As can be seen from the above, the semiconductor device of the present invention, unlike the conventional semiconductor device including a substrate, may improve the light extraction efficiency like the semiconductor device formed on the PSS even when the substrate is separated, the active layer is irregular shape The light emitting efficiency of the semiconductor device can be improved by forming a larger surface area. That is, since manufacturing is possible using a flat substrate instead of PSS, it is possible to manufacture a light emitting diode with high efficiency while reducing manufacturing cost.
도 8은 본 발명의 다른 일 실시예에 따른 반도체 소자를 도시하는 도면이다. 반도체 소자(800)는 지지층(810), 반사층(820), 제3 반도체층(830), 제2 반도체층(840), 활성층(850), 제1 반도체층(860) 및 전극층(870)을 포함한다. 도 1에 도시된 반도체 소자(100)와 도 8에서 도시된 반도체 소자(800)는 형성된 모양이 각각 정육각형과 원이라는 점만 다르고 전체 구조는 매우 유사하다. 따라서 각 구성 요소에 대한 설명은 생략한다.8 is a diagram illustrating a semiconductor device according to another embodiment of the present invention. The semiconductor device 800 may include the support layer 810, the reflective layer 820, the third semiconductor layer 830, the second semiconductor layer 840, the active layer 850, the first semiconductor layer 860, and the electrode layer 870. Include. The semiconductor device 100 shown in FIG. 1 and the semiconductor device 800 shown in FIG. 8 differ only in that the formed shapes are regular hexagons and circles, respectively, and the overall structure is very similar. Therefore, description of each component is omitted.
도 9는 본 발명의 다른 일 실시예에 따른 반도체 소자의 단면도를 나타낸 것이다.9 is a sectional view of a semiconductor device according to another embodiment of the present invention.
도 9를 참조하면, 반도체 소자(900)는 지지층(910), 반사층(920), 제3 반도체층(930), 제2 반도체층(940), 활성층(960), 제1 반도체층(970) 및 전극층(980)을 포함한다.Referring to FIG. 9, the semiconductor device 900 includes a support layer 910, a reflective layer 920, a third semiconductor layer 930, a second semiconductor layer 940, an active layer 960, and a first semiconductor layer 970. And an electrode layer 980.
제1 반도체층(970)은 제1 타입의 반도체층으로, 일 예로, N 타입의 GaN층일 수 있으며, 에피 성장에 의하여 형성된다.The first semiconductor layer 970 is a first type semiconductor layer. For example, the first semiconductor layer 970 may be an N type GaN layer, and is formed by epitaxial growth.
여기서, 제1 반도체층(970)은 기판(도시되지 않음) 상에 형성되는데, 도 9에서는 제1 반도체층(970)과 기판이 분리된 상태의 단면도를 나타낸 것이다.Here, the first semiconductor layer 970 is formed on a substrate (not shown). In FIG. 9, a cross-sectional view of the first semiconductor layer 970 is separated from the substrate.
활성층(960)은 제1 반도체층(970) 상에 형성되며, 발광 다이오드 반도체 소자의 발광 효율을 높이기 위하여 제1 반도체층(970)과 제2 반도체층(940) 사이에 형성된다.The active layer 960 is formed on the first semiconductor layer 970, and is formed between the first semiconductor layer 970 and the second semiconductor layer 940 to increase the light emitting efficiency of the light emitting diode semiconductor device.
이때, 활성층(960)은 양자 우물접합층(MQW, multi-quantum well)으로 불리기도 한다.In this case, the active layer 960 may also be referred to as a quantum well bonding layer (MQW).
제2 반도체층(940)은 활성층(960) 상에 형성되는 제2 타입의 반도체층으로, 내부에 광을 산란시키는 다수의 산란 수단(950)을 포함한다.The second semiconductor layer 940 is a second type of semiconductor layer formed on the active layer 960 and includes a plurality of scattering means 950 for scattering light therein.
여기서, 제2 반도체층(940)은 P 타입의 GaN층일 수 있으며, 제1 반도체층(970)의 형성 방식과 같이 에피 성장에 의하여 형성될 수 있다.Here, the second semiconductor layer 940 may be a P-type GaN layer, and may be formed by epitaxial growth as in the method of forming the first semiconductor layer 970.
다수의 산란 수단(950)은 광을 산란시켜 반도체 소자의 광 도출 효율을 향상시키는 역할을 한다.The plurality of scattering means 950 serves to scatter the light to improve the light extraction efficiency of the semiconductor device.
제2 반도체층(940) 내부에 형성되는 다수의 산란 수단(950)은 SiO2, Si3N4, TiO2, ZnO, MgZnO, Al2O3, AlN, In2O3 중 적어도 하나 이상의 물질에 의하여 형성될 수 있다.The plurality of scattering means 950 formed in the second semiconductor layer 940 may be formed by at least one of SiO 2, Si 3 N 4, TiO 2, ZnO, MgZnO, Al 2 O 3, AlN, and In 2 O 3.
다수의 산란 수단(950)을 포함하는 제2 반도체층(940)은 일정 두께만큼 제2 반도체층을 형성한 후 그 상부에 다수의 산란 수단(950)을 형성한 후 그 상부에 다시 제2 반도체층을 형성함으로써, 형성될 수 있다.The second semiconductor layer 940 including the plurality of scattering means 950 forms a second semiconductor layer by a predetermined thickness, and then forms a plurality of scattering means 950 thereon, and then a second semiconductor on the top thereof. By forming a layer, it can be formed.
제3 반도체층(930)은 제2 반도체층(940) 상에 형성되며, 제2 반도체층(940) 상에 P 전극을 콘택 할 수 있는 반도체층으로, In1-xGaxN층일 수 있다.The third semiconductor layer 930 is formed on the second semiconductor layer 940 and may be an In 1-x Ga x N layer on the second semiconductor layer 940 that may contact the P electrode. .
반사층(920)은 제3 반도체층(930) 상에 형성되며, 활성층(960)에서 발생되어 후방으로 진행하는 광을 전방으로 반사시킨다.The reflective layer 920 is formed on the third semiconductor layer 930 and reflects light generated in the active layer 960 and traveling backward.
지지층(910)은 반도체 소자의 기계적 지지를 제공하는 층으로, 반사층(920) 상에 형성되며, 금속 지지층일 수 있다.The support layer 910 is a layer providing mechanical support of the semiconductor device. The support layer 910 is formed on the reflective layer 920 and may be a metal support layer.
지지층(910)은 전기 전도도 및 열 전도도가 높고, 기계적인 강도가 상대적으로 높은 금속, 예를 들어 구리 또는 구리 화합물 등이 이용 가능하다.The support layer 910 may be formed of a metal having high electrical conductivity and thermal conductivity and having a relatively high mechanical strength, for example, copper or a copper compound.
또한, 지지층(910)은 전기적 도금 방법을 통하여 형성될 수 있으며, 실시예에 따라서는 낮은 밀도를 가지며 스트레스를 완화시킬 수 있는 연성 구리층(도시되지 않음)과, 높은 밀도와 강도를 가지며 역학적인 지지를 제공하는 경성 구리층(도시되지 않음)의 2층으로 구성될 수도 있다.In addition, the support layer 910 may be formed through an electroplating method, and in some embodiments, a flexible copper layer (not shown) having a low density and relieving stress, and having a high density and strength, It may also consist of two layers of a hard copper layer (not shown) providing support.
전극층(980)은 활성층(960)과 인접하지 않는 제1 반도체층(970)의 일면에 형성되며 반도체 소자에 전원을 인가하기 위한 층으로, 금속 및 금속 화합물을 이용하여 형성할 수 있다.The electrode layer 980 is formed on one surface of the first semiconductor layer 970 which is not adjacent to the active layer 960 and is a layer for applying power to the semiconductor device. The electrode layer 980 may be formed using a metal and a metal compound.
도 10은 본 발명의 또 다른 일 실시예에 따른 반도체 소자의 단면도를 나타낸 것이다. 반도체 소자(1000)는 지지층(1010), 반사층(1020), 제3 반도체층(1030), 제2 반도체층(1040), 활성층(1060), 제1 반도체층(1070) 및 전극층(1080)을 포함한다. 도 10에 도시된 반도체 소자(1000)와 도 9에 도시된 반도체 소자(900)는 다수의 산란 수단(950, 1050)이 형성된 위치만 상이할 뿐 전체 구조는 매우 유사하다. 즉, 도 10에서의 다수의 산란 수단(1050)이 활성층(1060)과 제2 반도체층(1040) 사이에 형성된다. 여기서, 다수의 산란 수단(1050)이 활성층(1060)과 제2 반도체층(1040) 사이에 형성되기 때문에 제2 반도체층(1040)의 두께는 도 9에 도시된 제2 반도체층(940)의 두께와 상이할 수도 있다.10 is a sectional view of a semiconductor device according to another embodiment of the present invention. The semiconductor device 1000 may include a support layer 1010, a reflective layer 1020, a third semiconductor layer 1030, a second semiconductor layer 1040, an active layer 1060, a first semiconductor layer 1070, and an electrode layer 1080. Include. The semiconductor device 1000 shown in FIG. 10 and the semiconductor device 900 shown in FIG. 9 differ only in positions where a plurality of scattering means 950 and 1050 are formed, and the overall structure is very similar. That is, a plurality of scattering means 1050 in FIG. 10 is formed between the active layer 1060 and the second semiconductor layer 1040. Here, since the plurality of scattering means 1050 is formed between the active layer 1060 and the second semiconductor layer 1040, the thickness of the second semiconductor layer 1040 is the thickness of the second semiconductor layer 940 shown in FIG. It may differ from the thickness.
도 11은 본 발명의 또 다른 일 실시예에 따른 반도체 소자의 단면도를 나타낸 것이다. 반도체 소자(1100)는 지지층(1110), 반사층(1120), 제3 반도체층(1130), 제2 반도체층(1140), 활성층(1160), 제1 반도체층(1170) 및 전극층(1180)을 포함한다. 도 11에 도시된 반도체 소자(1100)와 도 9, 도 10에 도시된 반도체 소자(900, 1000)는 다수의 산란 수단(950, 1050, 1150)이 형성된 위치만 상이할 뿐 전체 구조는 매우 유사하다. 즉, 도 11에서의 다수의 산란 수단(1150)이 제2 반도체층(1140)과 제3 반도체층(1130) 사이에 형성된다.11 is a sectional view of a semiconductor device according to another embodiment of the present invention. The semiconductor device 1100 may include a support layer 1110, a reflective layer 1120, a third semiconductor layer 1130, a second semiconductor layer 1140, an active layer 1160, a first semiconductor layer 1170, and an electrode layer 1180. Include. The semiconductor device 1100 illustrated in FIG. 11 and the semiconductor devices 900 and 1000 illustrated in FIGS. 9 and 10 differ only in positions where a plurality of scattering means 950, 1050, and 1150 are formed, and the overall structure is very similar. Do. That is, a plurality of scattering means 1150 in FIG. 11 is formed between the second semiconductor layer 1140 and the third semiconductor layer 1130.
도 9 내지 도 11에서와 같이, 본 발명의 반도체 소자는 다수의 산란 수단을 포함하는 제2 반도체층에 의하여 광 도출 효율을 향상시킬 수 있기 때문에 광 도출 효율을 향상시키기 위한 기판 예를 들어, 고가의 PSS 기판을 사용하지 않아도 된다. 따라서, 저가의 사파이어 가판 등을 사용하여 광 도출 효율을 향상시킬 수 있으며, 이에 의하여 저가의 제조 비용으로 고효율의 LED를 제조할 수 있다.9 to 11, since the semiconductor device of the present invention can improve the light extraction efficiency by the second semiconductor layer including a plurality of scattering means, for example, a substrate for improving the light extraction efficiency is expensive. It is not necessary to use a PSS substrate. Therefore, the light extraction efficiency can be improved by using a low-cost sapphire substrate or the like, whereby a high-efficiency LED can be manufactured at low cost.
도 12 내지 도 14는 도 9에 도시된 반도체 소자 제조 방법의 공정 과정을 설명하기 위한 일 실시예 단면도를 나타낸 것이다.12 to 14 illustrate cross-sectional views of one embodiment for describing a process of the method of manufacturing the semiconductor device illustrated in FIG. 9.
도 12에서, 사파이어 기판 또는 SiC 기판 등의 기판(1210) 상부에 에피 성장에 의하여 일정 두께를 갖는 제1 타입 예를 들어, N 타입의 제1 반도체층(1220)을 형성한다.In FIG. 12, a first type semiconductor layer 1220 having a predetermined thickness, for example, an N type, is formed on the substrate 1210 such as a sapphire substrate or a SiC substrate by epitaxial growth.
제1 반도체층(1220) 상부에 활성층(1230)을 형성하고, 형성된 활성층(1230) 상부에 일정 두께의 제2 반도체층(1241)을 형성한다.An active layer 1230 is formed on the first semiconductor layer 1220, and a second semiconductor layer 1241 having a predetermined thickness is formed on the formed active layer 1230.
일정 두께를 갖는 제2 반도체층(1241) 상부에 다수의 산란 수단(1250)을 형성하는데, 다수의 산란 수단(1250)은 SiO2, Si3N4, TiO2, ZnO, MgZnO, Al2O3, AlN, In2O3 중 적어도 하나 이상의 물질에 의하여 형성될 수 있다.A plurality of scattering means 1250 is formed on the second semiconductor layer 1241 having a predetermined thickness. It may be formed by the above materials.
이때, 다수의 산란 수단(1250)은 제2 반도체층(1241) 상부에 산란층(도시되지 않음)을 형성한 후 마스크 패턴을 이용하여 제2 반도체층(1241) 상부 일부가 노출되도록 식각함으로써, 형성될 수 있다. 여기서, 상기 산란층은 MOCVD, PECVD 등과 같은 CVD 방법, 스퍼터링(sputtering) 등의 다양한 방법에 의해 형성될 수 있다.In this case, the plurality of scattering means 1250 is formed by forming a scattering layer (not shown) on the second semiconductor layer 1241 and then etching a portion of the upper portion of the second semiconductor layer 1241 by using a mask pattern. Can be formed. Here, the scattering layer may be formed by various methods such as CVD method such as MOCVD, PECVD, sputtering.
또한, 다수의 산란 수단(1250)이 부착된 필름을 제2 반도체층(1241) 상부에 라미네이팅(laminating)함으로써, 제2 반도체층(1241) 상부에 다수의 산란 수단(1250)을 형성할 수도 있다. 또한, 다수의 산란 수단(1250)은 제2 반도체층(1241) 상부에 패턴된 포토레지스트(PR)를 먼저 형성하고 그 상부에 산란층을 증착한 후 포토레지스트를 제거하는 리프트 오프(Lift off) 방법에 의해서도 형성될 수 있다. 물론, 다수의 산란 수단(1250)을 형성하는 방법이 상술한 방법으로만 한정되는 것은 아니며, 다수의 산란 수단(1250)을 형성할 수 있는 모든 방법이 본 발명에 적용될 수 있다는 것은 이 기술 분야에 종사하는 당업자에게 있어서 자명하다.In addition, a plurality of scattering means 1250 may be formed on the second semiconductor layer 1241 by laminating the film with the plurality of scattering means 1250 on the second semiconductor layer 1241. . In addition, the plurality of scattering means 1250 is a lift off for first forming a patterned photoresist PR on the second semiconductor layer 1241 and depositing a scattering layer thereon to remove the photoresist. It can also be formed by a method. Of course, the method of forming the plurality of scattering means 1250 is not limited to the above-described method, and all methods capable of forming the plurality of scattering means 1250 may be applied to the present invention. It is obvious to those skilled in the art.
도 13에서, 다수의 산란 수단(1250)이 형성되면 다수의 산란 수단(1250)이 형성된 제2 반도체층(1241) 상부에 제2 반도체층(1242)을 다시 형성한다.In FIG. 13, when the plurality of scattering means 1250 are formed, the second semiconductor layer 1242 is formed on the second semiconductor layer 1241 on which the plurality of scattering means 1250 is formed.
내부에 다수의 산란 수단(1250)을 포함하는 제2 반도체층(1240)이 형성되면, 제2 반도체층(1240) 상부에 제3 반도체층(1260), 반사층(1270) 및 지지층(1280)을 순차적으로 형성한다.When the second semiconductor layer 1240 including the plurality of scattering means 1250 is formed therein, the third semiconductor layer 1260, the reflective layer 1270, and the support layer 1280 are formed on the second semiconductor layer 1240. Form sequentially.
도 14에서, 기판(1210)과 제1 반도체층(1220)을 분리하는 공정을 수행한 후 활성층(1230)이 형성되지 않은 제1 반도체층(1220)의 일면 상부에 반도체 소자에 전원을 공급하기 위한 전극층(1290)을 형성한다.In FIG. 14, after the process of separating the substrate 1210 and the first semiconductor layer 1220, supplying power to the semiconductor device over one surface of the first semiconductor layer 1220 in which the active layer 1230 is not formed. To form an electrode layer 1290.
여기서, 기판(1210)과 제1 반도체층(1220)을 분리하는 방법은 LLO 공정, CLO 공정 등에 의해 수행될 수 있다.The method of separating the substrate 1210 and the first semiconductor layer 1220 may be performed by an LLO process, a CLO process, or the like.
본 발명의 반도체 소자 제조 방법을 설명하는데 있어서, 제1 반도체층이 기판 상부에 바로 형성되는 것으로 기재하였지만, 이에 한정되지 않는다. 즉, 기판과 제1 반도체층 사이에 적어도 하나의 다른 층이 형성될 수도 있으며, 이는 제조하고자 하는 반도체 소자에 따라 다를 수 있다.In describing the semiconductor device manufacturing method of the present invention, the first semiconductor layer is described as being directly formed on the substrate, but the present invention is not limited thereto. That is, at least one other layer may be formed between the substrate and the first semiconductor layer, which may vary depending on the semiconductor device to be manufactured.
또한, 발명에서 수직형 반도체 소자에 대해서만 설명하였지만, 이에 한정되지 않으며, 수평형 반도체 소자에 적용 가능하다는 것은 이 기술 분야에 종사하는 당업자에게 있어서 자명하다.In addition, although only the vertical semiconductor device has been described in the present invention, it is not limited thereto, and it is apparent to those skilled in the art that the present invention is applicable to a horizontal semiconductor device.
본 발명의 실시예에 따른 반도체 소자 제조 방법은 다양한 컴퓨터 수단을 통하여 수행될 수 있는 프로그램 명령 형태로 구현되어 컴퓨터 판독 가능 매체에 기록될 수 있다. The method of manufacturing a semiconductor device according to an embodiment of the present invention may be implemented in the form of program instructions that may be executed by various computer means, and may be recorded in a computer readable medium.
또한 상기 방법은 반도체 소자 제조 장비의 제어 신호를 발생하는 컨트롤러의 메모리에 미리 프로그램되는 소프트웨어/펌웨어의 형태로 제공될 수도 있으며, 프로그램된 순서에 따라 순차적으로 수행될 수 있다.In addition, the method may be provided in the form of software / firmware that is pre-programmed in a memory of a controller that generates a control signal of a semiconductor device manufacturing equipment, and may be sequentially performed in the programmed order.
상기 컴퓨터 판독 가능 매체는 프로그램 명령, 데이터 파일, 데이터 구조 등을 단독으로 또는 조합하여 포함할 수 있다. 상기 매체에 기록되는 프로그램 명령은 본 발명을 위하여 특별히 설계되고 구성된 것들이거나 컴퓨터 소프트웨어 해당 기술 분야의 통상의 기술자에게 공지되어 사용 가능한 것일 수도 있다. 컴퓨터 판독 가능 기록 매체의 예에는 하드 디스크, 플로피 디스크 및 자기 테이프와 같은 자기 매체(magnetic media), CD-ROM, DVD와 같은 광기록 매체(optical media), 플롭티컬 디스크(floptical disk)와 같은 자기-광 매체(magneto-optical media), 및 롬(ROM), 램(RAM), 플래시 메모리 등과 같은 프로그램 명령을 저장하고 수행하도록 특별히 구성된 하드웨어 장치가 포함된다. 프로그램 명령의 예에는 컴파일러에 의해 만들어지는 것과 같은 기계어 코드뿐만 아니라 인터프리터 등을 사용해서 컴퓨터에 의해서 실행될 수 있는 고급 언어 코드를 포함한다. 상기된 하드웨어 장치는 본 발명의 동작을 수행하기 위해 하나 이상의 소프트웨어 모듈로서 작동하도록 구성될 수 있으며, 그 역도 마찬가지이다.The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.
이상과 같이 본 발명에서는 구체적인 구성 요소 등과 같은 특정 사항들과 한정된 실시예 및 도면에 의해 설명되었으나 이는 본 발명의 보다 전반적인 이해를 돕기 위해서 제공된 것일 뿐, 본 발명은 상기의 실시예에 한정되는 것은 아니며, 본 발명이 속하는 분야에서 통상적인 지식을 가진 자라면 이러한 기재로부터 다양한 수정 및 변형이 가능하다. In the present invention as described above has been described by the specific embodiments, such as specific components and limited embodiments and drawings, but this is provided to help a more general understanding of the present invention, the present invention is not limited to the above embodiments. For those skilled in the art, various modifications and variations are possible from these descriptions.
따라서, 본 발명의 사상은 설명된 실시예에 국한되어 정해져서는 아니 되며, 후술하는 특허청구범위뿐 아니라 이 특허청구범위와 균등하거나 등가적 변형이 있는 모든 것들은 본 발명 사상의 범주에 속한다고 할 것이다.Accordingly, the spirit of the present invention should not be limited to the described embodiments, and all of the equivalents and equivalents of the claims as well as the claims to be described later belong to the scope of the present invention. .
반도체 소자 및 그 제조 방법이 개시된다. 본 발명의 일 실시예에 따른 반도체 소자는 제1 타입의 제1 반도체층; 제2 타입의 제2 반도체층; 및 상기 제1 반도체층과 상기 제2 반도체층 사이에 위치하는 활성층을 포함하며, 상기 활성층의 일면과 접하는 상기 제1 반도체층의 일면이 요철 형태로 형성될 수 있다. 또한, 본 발명의 다른 일 실시예에 따른 반도체 소자는 제1 타입의 제1 반도체층; 제2 타입의 제2 반도체층; 및 상기 제1 반도체층과 상기 제2 반도체층 사이에 위치하는 활성층을 포함하며, 상기 제2 반도체층은 광을 산란시키는 다수의 산란 수단을 포함함으로써, 광 도출 효율과 발광 효율을 향상시킬 수 있다.Disclosed are a semiconductor device and a method of manufacturing the same. A semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first type; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, and one surface of the first semiconductor layer in contact with one surface of the active layer may be formed in an uneven shape. In addition, according to another embodiment of the present invention, a semiconductor device may include a first semiconductor layer of a first type; A second semiconductor layer of a second type; And an active layer positioned between the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer includes a plurality of scattering means for scattering light, thereby improving light extraction efficiency and luminous efficiency. .

Claims (16)

  1. 제1 타입의 제1 반도체층; A first semiconductor layer of a first type;
    제2 타입의 제2 반도체층; 및A second semiconductor layer of a second type; And
    상기 제1 반도체층과 상기 제2 반도체층 사이에 위치하는 활성층An active layer positioned between the first semiconductor layer and the second semiconductor layer
    을 포함하며,Including;
    상기 활성층의 일면과 접하는 상기 제1 반도체층의 일면이 요철 형태로 형성되는 반도체 소자.A semiconductor device in which one surface of the first semiconductor layer in contact with one surface of the active layer is formed in an irregular shape.
  2. 제1항에 있어서,The method of claim 1,
    상기 활성층의 다른 일면이 상기 제1 반도체층의 일면의 요철 형태에 상응하는 요철 형태로 형성되는 반도체 소자.The other side of the active layer is a semiconductor device is formed in a concave-convex shape corresponding to the concave-convex shape of one surface of the first semiconductor layer.
  3. 제1항에 있어서,The method of claim 1,
    상기 활성층의 다른 일면과 이격되어 있는 상기 제2 반도체층의 일면이 요철 형태로 형성되는 반도체 소자.And a surface of the second semiconductor layer spaced apart from the other surface of the active layer in a concave-convex shape.
  4. 제1항에 있어서,The method of claim 1,
    상기 반도체 소자를 지지하는 지지층Support layer for supporting the semiconductor device
    을 더 포함하고,More,
    상기 지지층은 상기 제2 반도체층 상에 형성되는 반도체 소자.The support layer is formed on the second semiconductor layer.
  5. 제1항에 있어서,The method of claim 1,
    상기 반도체 소자는The semiconductor device
    다각형 또는 원형의 기둥 모양으로 형성되는 반도체 소자.A semiconductor device formed in a polygonal or circular columnar shape.
  6. 제1 타입의 제1 반도체층; A first semiconductor layer of a first type;
    제2 타입의 제2 반도체층; 및A second semiconductor layer of a second type; And
    상기 제1 반도체층과 상기 제2 반도체층 사이에 위치하는 활성층 An active layer positioned between the first semiconductor layer and the second semiconductor layer
    을 포함하며,Including;
    상기 제2 반도체층은 The second semiconductor layer
    광을 산란시키는 다수의 산란 수단을 포함하는 반도체 소자.A semiconductor device comprising a plurality of scattering means for scattering light.
  7. 제6항에 있어서,The method of claim 6,
    상기 산란 수단은The scattering means is
    SiO2, Si3N4, TiO2, ZnO, MgZnO, Al2O3, AlN, In2O3 중 적어도 하나 이상의 물질로 구성되는 반도체 소자.A semiconductor device comprising at least one of SiO 2, Si 3 N 4, TiO 2, ZnO, MgZnO, Al 2 O 3, AlN, and In 2 O 3.
  8. 제6항에 있어서,The method of claim 6,
    상기 산란 수단은The scattering means is
    상기 활성층과 접하는 상기 제2 반도체층의 일면에 위치하거나 상기 제2 반도체층의 다른 일면에 위치하거나 상기 제2 반도체층 내부에 위치하는 반도체 소자. The semiconductor device is disposed on one surface of the second semiconductor layer in contact with the active layer, located on the other surface of the second semiconductor layer, or located inside the second semiconductor layer.
  9. 기판 상에 제1 타입의 제1 반도체층을 형성하는 단계;Forming a first semiconductor layer of a first type on a substrate;
    상기 제1 반도체층을 기 설정된 마스크 패턴에 따라 처리하여 상기 제1 반도체층의 일면을 요철 형태로 형성하는 단계;Treating the first semiconductor layer according to a preset mask pattern to form one surface of the first semiconductor layer in an uneven form;
    상기 요철 형태로 형성된 상기 제1 반도체층의 일면 상에 활성층을 형성하는 단계; 및Forming an active layer on one surface of the first semiconductor layer formed in the uneven form; And
    상기 활성층 상부에 제2 타입의 제2 반도체층을 형성하는 단계Forming a second semiconductor layer of a second type on the active layer
    를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a.
  10. 제9항에 있어서,The method of claim 9,
    상기 활성층을 형성하는 단계는Forming the active layer
    상기 제2 반도체층과 접하는 상기 활성층의 일면이 상기 제1 반도체층의 일면의 요철 형태에 상응하는 요철 형태가 되도록 상기 활성층을 형성하는 반도체 소자 제조 방법.And forming the active layer such that one surface of the active layer in contact with the second semiconductor layer has a concave-convex shape corresponding to the concave-convex shape of one surface of the first semiconductor layer.
  11. 제9항에 있어서,The method of claim 9,
    상기 제2 반도체층을 형성하는 단계는Forming the second semiconductor layer
    상기 활성층과 이격되어 있는 상기 제2 반도체층의 일면이 요철 형태가 되도록 상기 제2 반도체층을 형성하는 반도체 소자 제조 방법.And forming the second semiconductor layer such that one surface of the second semiconductor layer spaced apart from the active layer has an uneven shape.
  12. 제9항에 있어서,The method of claim 9,
    상기 제2 반도체층 상에 상기 반도체 소자를 지지하기 위한 지지층을 형성하는 단계;Forming a supporting layer for supporting the semiconductor device on the second semiconductor layer;
    상기 기판을 상기 제1 반도체층으로부터 분리하는 단계; 및Separating the substrate from the first semiconductor layer; And
    상기 기판이 분리된 상기 제1 반도체층의 일면에 전극층을 형성하는 단계Forming an electrode layer on one surface of the first semiconductor layer from which the substrate is separated
    를 더 포함하는 반도체 소자 제조 방법.A semiconductor device manufacturing method further comprising.
  13. 기판 상에 제1 타입의 제1 반도체층을 형성하는 단계;Forming a first semiconductor layer of a first type on a substrate;
    상기 제1 반도체층 상에 활성층을 형성하는 단계; 및Forming an active layer on the first semiconductor layer; And
    상기 활성층 상에 광을 산란시키는 다수의 산란 수단을 포함하는 제2 타입의 제2 반도체층을 형성하는 단계Forming a second type of semiconductor layer of a second type comprising a plurality of scattering means for scattering light on said active layer
    를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a.
  14. 제13항에 있어서,The method of claim 13,
    상기 제2 반도체층을 형성하는 단계는Forming the second semiconductor layer
    상기 활성층 상에 상기 활성층의 일부가 노출되도록 상기 다수의 산란 수단을 형성하는 단계; 및Forming the plurality of scattering means on the active layer to expose a portion of the active layer; And
    상기 다수의 산란 수단이 형성된 상기 활성층 상에 상기 제2 반도체층을 형성하는 단계Forming the second semiconductor layer on the active layer having the plurality of scattering means formed thereon
    를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a.
  15. 제13항에 있어서,The method of claim 13,
    상기 제2 반도체층을 형성하는 단계는Forming the second semiconductor layer
    상기 제2 반도체층 상에 상기 제2 반도체층의 일부가 노출되도록 상기 다수의 산란 수단을 형성하는 반도체 소자 제조 방법.And forming the plurality of scattering means on the second semiconductor layer such that a portion of the second semiconductor layer is exposed.
  16. 제13항에 있어서,The method of claim 13,
    상기 제2 반도체층을 형성하는 단계는Forming the second semiconductor layer
    제1 높이의 상기 제2 반도체층을 형성하는 단계;Forming the second semiconductor layer of a first height;
    상기 제1 높이의 상기 제2 반도체층 상에 상기 다수의 산란 수단을 형성하는 단계; 및Forming the plurality of scattering means on the second semiconductor layer of the first height; And
    상기 다수의 산란 수단이 형성된 상기 제1 높이의 상기 제2 반도체층 상에 제2 높이의 상기 제2 반도체층을 형성하는 단계Forming the second semiconductor layer of a second height on the second semiconductor layer of the first height where the plurality of scattering means are formed
    를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a.
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