WO2012070170A1

WO2012070170A1 - Power supply control system and method of controlling power supply

Info

Publication number: WO2012070170A1
Application number: PCT/JP2011/003738
Authority: WO
Inventors: 貴夫吉田; 大佐細井; 章浩加藤; 達也小八木; 岩崎　俊文
Original assignee: パナソニック株式会社
Priority date: 2010-11-26
Filing date: 2011-06-29
Publication date: 2012-05-31
Also published as: JP2012113593A

Abstract

A test control unit (103), after detecting an idle state for a functional circuit block D (109) , issues a voltage step-down command to a power supply control unit (104) via an address/data bus (101). After the voltage step-down of a power supply domain D (113) is complete, the test control unit (103) transmits a test pattern to the functional circuit block D (109) via the address/data bus (101), and compares the result of the test to an anticipated value. If on the basis of the comparison result it is determined that a fault such as a delay error and so forth due to a voltage difference has occurred, in order to return the functional circuit block D (109) to a normal state, the test control unit (103) issues a voltage step-up command for the power supply domain D (113) to the power supply control unit (104). Accordingly, it is possible, while minimizing the circuit size of a semiconductor device provided with a plurality of functional circuit blocks, to individually control the power supply voltage supplied to the plurality of functional circuit blocks.

Description

Power supply control system and power supply control method

The present invention relates to a power supply control system and a power supply control method for individually controlling power supply voltages supplied to a plurality of functional circuit blocks constituting a semiconductor device.

In recent years, as mobile electronic devices such as mobile phones and smartphones have become widespread, miniaturization and high performance of functions of mobile electronic devices have been attempted. The mobile electronic device has various function modules and interfaces according to program control by the CPU and its application. The core device is provided as a system LSI in which various functions are mounted on a one-chip LSI in order to achieve further miniaturization and lower power consumption.

Generally, a system LSI is equipped with a CPU, a bus, various functional modules, and a memory, and executes various application processes such as communication and photographing. In recent years, system LSIs have been operated with a high-speed clock as the amount of processing increases, such as high-speed communication processing and image processing with a large number of pixels. However, when the system LSI is operated with a high-speed clock, power consumption increases. Since mobile electronic devices are generally driven by a battery, an increase in power consumption causes battery consumption. As a result, frequent charging and battery replacement are necessary, which is inconvenient for the user.

In recent years, various technologies have been proposed in order to suppress an increase in power consumption of the system LSI. As an example, there is a clock gating technique that suppresses the operation by stopping the supply of useless clocks by managing the operation state. However, with the recent miniaturization of semiconductor processes, the ratio of standby leakage current to operating current is increasing. For this reason, even if the clock supply is stopped, the leakage current cannot be reduced.

In mobile electronic devices, the amount of leakage current during standby in the standby state affects the length of usage time. For this reason, recently, it has been realized that the leakage current is reduced by turning off the power of a circuit not in use or lowering the voltage. In the system LSI, power consumption can be reduced by classifying the circuits to be used and the circuits not to be used according to the state, dividing each power domain and controlling the power supply. Yes. However, the signal propagating across the power domain becomes unstable because the driving power of the circuit is different between the signal output side and the signal reception side.

As a technique for solving this problem, for example, one described in Patent Document 1 is known. In the technique described in Patent Document 1, a storage circuit and a delay circuit are provided in two power supply blocks, and signals are transmitted and received between the storage circuits. At this time, since signals are transmitted / received via the respective delay circuits, if a state in which malfunction may occur due to instantaneous power supply noise, voltage drop, etc. occurs, the delay amount of the delay circuit is more than normal. Also grows. As a result, it is possible to detect the occurrence of a state in which a toggle state of signals transmitted and received between the storage circuits is broken and a malfunction may occur.

Japanese Unexamined Patent Publication No. 2008-31767

In the technique of Patent Document 1 described above, a state in which a malfunction may occur is determined based on input / output signals between functional circuit blocks arranged in different power supply domains, and error detection is performed. In order to realize this function, it is necessary to provide a memory circuit and a delay circuit for every two power supply domains. For this reason, it is necessary to insert a plurality of memory circuits and delay circuits into a functional circuit block that performs communication between a plurality of power domains and power domains. Therefore, the circuit scale of the system LSI including the functional blocks that perform communication between the power domains and the power domains increases.

In addition, since error detection determination is performed regardless of application execution, error detection determination is also performed for functional circuit blocks that do not necessarily operate. As described above, if wasteful error detection or wasteful recovery operation is performed, power consumption increases accordingly.

In addition, error detection is performed by the dedicated circuit without using data or control signals that are actually used, so if an error occurs in the dedicated circuit even if the actual path is normal, there is a concern about power consumption and performance degradation. The

An object of the present invention is to provide a power supply control system and a power supply control method capable of individually controlling power supply voltages supplied to a plurality of functional circuit blocks while suppressing the circuit scale of a semiconductor device including the plurality of functional circuit blocks. Is to provide.

The present invention is a power supply control system for individually controlling a power supply voltage from a power supply unit supplied to a plurality of functional circuit blocks constituting a semiconductor device, in a first power supply region to which a first power supply is supplied. A first functional circuit block that operates; a second functional circuit block that operates in a second power supply region to which a second power supply is supplied; and the first functional circuit block and the second functional circuit block. A bus that is connected and transmits data in a third power supply region to which a third power supply is supplied, and operates in the third power supply region, and operates through the bus during an operation period of the first functional circuit block. A test control unit that transmits test data to the second functional circuit block and confirms an operating state of the second functional circuit block based on a value obtained by transmitting the test data. To provide a beam.

In the power supply control system, the test control unit includes a detection unit that detects an idle state of the second functional circuit block, and the second functional circuit block that is supplied to the second functional circuit block in which the idle state is detected. A step-down instruction unit that instructs the power source unit to step down the voltage of the power source.

In the power supply control system, the test control unit transmits the test data to the second functional circuit block after the voltage of the second power supply is stepped down in accordance with an instruction from the step-down instruction unit. And an abnormality detection unit that compares an expected value with a value obtained by transmitting the test data, and detects an abnormality caused by reducing the voltage of the second power supply based on the comparison result.

In the power supply control system, the test control unit includes a boost instruction unit that instructs the power supply unit to boost the voltage of the second power source. When the abnormality detection unit detects the abnormality, the test control unit After the voltage of the second power source is boosted in accordance with an instruction from the instruction unit, the transmission unit transmits the test data again, and confirms that the abnormality is not detected by the abnormality detection unit.

In the power supply control system, the test control unit includes a storage unit that stores a voltage of the second power supply that is stepped down according to an instruction from the step-down instruction unit, and the step-up instruction unit includes the storage unit The power supply unit is instructed to boost the voltage of the second power supply to a voltage higher than the voltage stored in the memory.

In the power supply control system, the test control unit includes a selection unit that selects a data path that returns via the bus and the delay circuit in the second power supply region, and the data path that is selected by the selection unit. A receiver for transmitting the test data and receiving the test data returning from the second power supply region; comparing the test data received by the receiver with the test data transmitted by the test controller to determine a delay situation; A determination unit for determining, and confirming an operation state of the second functional circuit block based on the delay state.

In the power supply control system, a part of the second functional circuit block is used as the delay circuit.

The present invention provides a first functional circuit block that operates in a first power supply region to which a first power is supplied, and a second functional circuit block that operates in a second power supply region to which a second power is supplied. A bus connected to the first functional circuit block and the second functional circuit block for transmitting data in a third power supply region to which a third power supply is supplied, and operating in the third power supply region A power control method for individually controlling power supply voltages supplied to a plurality of functional circuit blocks constituting a semiconductor device having the test control unit, wherein the test control unit includes the first functional circuit block. A step of transmitting test data to the second functional circuit block via the bus during an operation period, and the test control unit based on a value obtained by transmitting the test data. To provide a power supply control method comprising the steps of check of the operation of the click, the.

According to the power supply control system and the power supply control method according to the present invention, it is possible to individually control the power supply voltages supplied to the plurality of functional circuit blocks while suppressing the circuit scale of the semiconductor device.

1 is a block diagram showing the configuration of a power supply control system for a system LSI in a first embodiment Flowchart showing the power control operation of the test control unit 103 of the constant power ON domain 114 A flowchart showing the operation of the power control unit 104 of the constant power ON domain 114 The block diagram which shows the structure of the test control part periphery in the power supply control system of the system LSI of 2nd Embodiment Flow chart showing power control operation of test control unit 203 The block diagram which shows the structure of the test control part periphery in the case of testing the several functional circuit block connected to the bus | bath 230 in order.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

A power supply control system and a power supply control method according to an embodiment of the present invention will be described with reference to the drawings. The power supply control system of the embodiment described below is applied to a power supply control system of a system LSI.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a power supply control system for a system LSI in the first embodiment. The power supply control system shown in FIG. 1 is a low power consumption system including a system LSI 100 and a power supply IC 105.

The system LSI 100 has a plurality of power domains that can be supplied with different power. As shown in FIG. 1, the plurality of power supply domains include a constant power ON domain 114, a power supply domain A110, a power supply domain B111, a power supply domain C112, and a power supply domain D113. Note that power is always supplied from the power supply IC 105 to the constant power ON domain 114.

The constant power ON domain 114 includes a general-purpose address / data bus 101 for transmitting data between functional circuit blocks described later, a power control unit 104, a test control unit 103, and a bus arbitration unit 102. The CPU 106 is provided in the power domain A110. In the power domain B111, a functional circuit block B107 is provided. In the power domain C112, a functional circuit block C108 is provided. In the power domain D113, a functional circuit block D109 is provided.

The power supply control unit 104 of the always-on power supply domain 114 functions as a power supply unit that can individually control the power supply of each power supply domain. When receiving a voltage change instruction for each power supply domain from the test control unit 103, the power supply control unit 104 controls the power supply IC 105 to increase or decrease the power supply voltage of each power supply domain 110 to 113 via the power supply line 116.

The test control unit 103 of the constant power ON domain 114 is a control circuit mainly composed of a processor (CPU) that executes a program to be described later, and has a memory 103a therein. When the test control unit 103 receives from the bus arbitration unit 102 an idle monitor signal 117 for notifying which functional circuit block is accessed and which functional circuit block is idle, the CPU 106 or each functional circuit block 107. 109 idle states are detected. The test control unit 103 instructs the power supply control unit 104 to perform voltage change control via the address / data bus 101. At this time, the test control unit 103 stores, in the built-in memory 103a, information indicating the power supply voltage of the power supply domain subjected to voltage change control. Further, the test control unit 103 exchanges data with the CPU 106 of the power domain A 110 via the address / data bus 101, and transmits / receives test patterns to / from the functional circuit blocks 107 to 109. Check the operating status of the block.

The operation of the power supply control system of the system LSI 100 will be described. FIG. 2 is a flowchart showing the power control operation of the test control unit 103 in the always power ON domain 114. This operation is repeated every predetermined period. FIG. 3 is a flowchart showing the operation of the power control unit 104 of the constant power ON domain 114. Hereinafter, as an example, a description will be given assuming that the CPU 106 is accessing the functional circuit block C108 via the address / data bus 101 and the functional circuit block D109 is not accessing anywhere.

First, the test control unit 103 determines the state of the CPU 106 or each of the functional circuit blocks 107 to 109 based on the idle monitor signal 117, and determines whether or not an idle functional circuit block has been detected (step S1). When the functional circuit block in the idle state is not detected, the test control unit 103 ends this operation. In this example, during the operation period of the functional circuit block C108, it is detected that the functional circuit block D109 is in an idle state.

After detecting that the functional circuit block D109 is in the idle state, the test control unit 103 uses the power supply control unit via the address / data bus 101 to lower the power supply voltage of the power domain D113 to which the functional circuit block D109 belongs. A voltage step-down instruction for power supply domain D113 is issued to 104 (step S2). At this time, the test control unit 103 sends a test status signal 118 to the bus arbitration unit 102 so that normal access to the functional circuit block D109 does not occur. The bus arbitration unit 102 that has received the test status signal 118 does not generate a normal access to the functional circuit block D109. Further, as described above, the memory 103a in the test control unit 103 stores information indicating the power supply voltage indicated by the voltage step-down instruction.

The power supply control unit 104 determines whether or not a voltage step-down instruction for the power supply domain D113 has been received from the test control unit 103 (step S11). When receiving the voltage step-down instruction, the power supply control unit 104 sends a control signal 115 to the power supply IC 105 to lower the power supply voltage of the power supply domain D113 to which the idle functional circuit block D109 belongs (step S12). On the other hand, when the voltage step-down instruction has not been received, the operation proceeds to step S13 described later.

After the power supply voltage step-down of the power domain D113 is completed, the test control unit 103 transmits a test pattern to the functional circuit block D109 via the address / data bus 101, and compares the result with an expected value (step S3). The test pattern may be an arbitrary pattern as long as it is a pattern for operating the functional circuit block D109. For example, the test pattern may be as simple as accessing a specific register that does not cause a problem even if the value is changed.

Specifically, the test control unit 103 writes an arbitrary value to an appropriate register of the functional circuit block D109 and issues a pattern for reading the value from this register. The test control unit 103 determines whether or not the value read by this pattern is equal to the expected value.

The test control unit 103 determines whether an abnormality such as a delay error due to a voltage difference has occurred based on the comparison result in step S3 (step S4). If no abnormality has occurred, the test control unit 103 ends this operation without performing anything on the power domain D113. On the other hand, if an abnormality has occurred, the test control unit 103 issues a voltage boost instruction for the power supply domain D113 to the power supply control unit 104 in order to return the functional circuit block D109 to a normal state (step S5). The memory 103a in the test control unit 103 stores information indicating the power supply voltage indicated by the voltage boost instruction. The voltage boost instruction is issued so as to output a voltage higher than the voltage stored in the memory 103a so far.

The power supply control unit 104 determines whether or not a voltage boost instruction for the power supply domain D113 is received from the test control unit 103 after reducing the voltage of the power supply domain D113 in step S12 (step S13). If the voltage boost instruction has not been received, the power supply control unit 104 ends this operation and does nothing until the next instruction is received from the test control unit 103. On the other hand, when receiving a voltage boost instruction, the power supply control unit 104 controls the power supply IC 105 to increase the power supply voltage of the power supply domain D113 (step S14). Thereafter, the power supply control unit 104 does nothing until the next instruction is received from the test control unit 103.

After completion of the power supply voltage boosting of the power domain D113, the test control unit 103 transmits a test pattern to the functional circuit block D109 via the address / data bus 101, and compares the result with an expected value, similarly to the time of the voltage step-down (step). S6). The test control unit 103 determines whether an abnormality such as a delay error due to a voltage difference has occurred based on the comparison result in step S6 (step S7). If no abnormality has occurred, the test control unit 103 ends this operation without performing anything on the power domain D113. On the other hand, if an abnormality has occurred, the process returns to step S5, and the test control unit 103 issues a voltage boost instruction for the power supply domain D113 to the power supply control unit 104 in order to return the functional circuit block D109 to a normal state. The voltage boost instruction described above is performed step by step.

As described above, according to the power supply control system of the system LSI 100 of the first embodiment, since the general-purpose address / data bus 101 is used to determine the states of the CPU 106 and the functional circuit blocks 107 to 109, the system The power supply voltage for reducing the power consumption of the system LSI 100 can be controlled without increasing the circuit scale of the LSI. Further, it is possible to determine the occurrence of an abnormality such as a delay error due to a voltage difference without providing a test circuit for each power domain and without always operating the test circuit. Therefore, an increase in circuit scale can be suppressed and power consumption can be reduced. Furthermore, since the operation of each functional circuit block is not stopped during the test, it is possible to determine the state of the CPU 106 and each functional circuit block while preventing the system from slowing down.

In addition, during normal application execution, data communication is confirmed for functional circuit blocks that are not operating in the background, and the power supply voltage of the power domain is controlled, reducing power consumption without affecting actual operation. Is planned. Further, since power consumption is reduced without interposing other software inside the system LSI, power control is not complicated.

In the present embodiment, the power control unit 104 is configured by a hardware circuit because it simply steps down or boosts the voltage of each power domain. However, the power control unit 104 controls each power source IC 105 by software. The domain voltage may be stepped down or boosted. Furthermore, a plurality of power supply voltages may be provided, and step-down or step-up of the power supply voltage may be controlled stepwise, or an arbitrary step control may be performed by arbitrarily determining an upper limit value or a lower limit value of the power supply voltage.

(Second Embodiment)
FIG. 4 is a block diagram showing a configuration around the test control unit in the power supply control system of the system LSI of the second embodiment. The system LSI 200 has a plurality of power domains that can be supplied with different power. FIG. 4 shows a constant power ON domain 201, a power domain X 202, and a power IC 215 that constitute the power control system of the system LSI of the second embodiment.

The constant power ON domain 201 is a power domain on the side where the operation check is performed. The constant power ON domain 201 is provided with a bus arbiter 204, a test control unit 203, a power control unit 205, and a normal / test selector 210A. In FIG. 4, the bus is omitted.

The power domain X202 is a power domain on the test target side. The power domain X202 is provided with a functional circuit block X206, a delay circuit 213, and a normal / test selector 210B, which are processing blocks for realizing hardware functions.

The test control unit 203 of the constant power ON domain 201 includes a pattern generation circuit 207, a delay circuit 208, and a comparison circuit 209. The test control unit 203 performs an operation test using a signal between the bus arbiter 204 in the always-on power supply domain 201 and the functional circuit block X206 in the power supply domain X202. In addition, the power control unit 205 of the constant power ON domain 201 controls the power IC 215 to increase or decrease the power voltage of the power domain X202.

When the test control unit 203 receives from the bus arbiter 204 the idle monitor signal 211 notifying that the functional circuit block X206 is in the idle state, the test control unit 203 controls the transition to the test mode, and the test control signal 212 performs normal / test The

selectors

210A and 210B are switched.

After switching to the test mode, the pattern generation circuit 207 of the test control unit 203 generates a test pattern that generates a fixed-length random pattern and sends the test pattern to the normal / test selector 210A. At this time, when the normal / test selector 210A is switched, the test pattern is input to the functional circuit block X206 and the delay circuit 213 of the power domain X202. The test pattern to which a certain amount of delay is added by the delay circuit 213 is looped back by being returned to the test control unit 203 of the power ON domain 201 through the normal / test selector 210B, and the comparison circuit of the test control unit 203 209 is input.

In this way, by switching between the normal /

test selectors

210A and 210B, the test pattern transmitted from the test control unit 203 of the always-on power supply domain 201 returns to the test control unit 203 via the delay circuit 213 of the power supply domain X202. A data path is formed (selected).

Similarly, the test control unit 203 uses the pattern generation circuit 207 to generate a reference pattern for comparison. The reference pattern generated by the pattern generation circuit 207 is input to the delay circuit 208 of the test control unit 203. Here, the delay circuit 208 has the same circuit configuration as the delay circuit 213. Therefore, the reference pattern is a signal with a delay added in the same power domain.

The test pattern to which the delay is added by the delay circuit 213 of the power domain X202 and the reference pattern to which the delay is added by the delay circuit 208 of the constant power ON domain 201 are respectively input to the comparison circuit 209. The comparison circuit 209 compares the timing of these signal changes to determine the delay situation. Here, the start time and end time for performing this comparison are determined from the time and pattern length at which the pattern is generated by the pattern generation circuit 207 and the delay value added by the delay circuit 208.

In the comparison circuit 209, when there is a difference in signal change timing, the comparison circuit 209 sets a flag. When the flag is set in the comparison circuit 209, an unexpected delay factor exists between the always-on power supply domain 201 and the power supply domain X202. At this time, the power supply control unit 205 controls the power supply IC 215 to boost the power supply domain X202. On the other hand, when the flag is not set in the comparison circuit 209, communication is always performed between the power supply ON domain 201 and the power supply domain X202 without any problem. Therefore, the power supply control unit 205 does nothing for the power supply domain X202. .

FIG. 5 is a flowchart showing the power control operation of the test control unit 203. This operation is repeatedly performed by the test control unit 203 every predetermined period. The test control unit 203 determines whether or not the idle signal 211 has been received from the bus arbiter 204 (step S21). When the idle signal has not been received, the test control unit 203 ends this operation. On the other hand, when the idle signal is received, the test control unit 203 instructs the power supply control unit 205 to step down the voltage of the power supply domain corresponding to the idle signal, for example, the power supply domain X202 (step S22).

The test control unit 203 switches the normal /

test selectors

210A and 210B for testing (step S23). Next, the pattern generation circuit 207 of the test control unit 203 generates a test pattern and sends it to the normal / test selector 210A (step S24). The pattern generation circuit 207 generates a reference pattern and sends it to the delay circuit 208 (step S25). In addition, although the test pattern and the reference pattern are generated and transmitted separately, when these patterns are the same pattern, one pattern may be generated and transmitted simultaneously. The comparison circuit 209 of the test control unit 203 compares signal change timings in the test pattern and the reference pattern (step S26).

The test control unit 203 determines whether or not there is an unexpected delay between the power supply domains from the timing of signal change in the test pattern and the reference pattern (step S27). If there is an unexpected delay, the test control unit 203 instructs the power supply control unit 205 to step up the voltage of the power supply domain X202 (step S28), and returns to step S24. On the other hand, when there is no unexpected delay, the test control unit 203 ends this operation.

The above operation is applicable to all functional circuit blocks connected to the bus. FIG. 6 is a block diagram showing a configuration around the test control unit when testing a plurality of functional circuit blocks connected to the bus 230 in order. The test control unit 203 receives the idle signal 211 from the bus arbiter 204, and sequentially tests a plurality of power supply domains connected to the bus 230. FIG. 6 shows the case where the functional circuit block X206 and the functional circuit block Y226 provided in the power domain X202 and the power domain Y222 are connected to the bus 230, respectively, but 3 provided in each of three or more power domains. The same applies when two or more functional circuit blocks are connected to the bus 230. The test of each functional circuit block is the same as the operation described above. In this case, priorities may be assigned to the power domains in advance, and tests may be executed in descending order.

As described above, according to the power supply control system of the second embodiment, a test circuit is not provided for each power supply domain, and further, a delay error due to a potential difference or the like is not caused without always operating the test circuit. The occurrence can be determined. Therefore, an increase in circuit scale can be suppressed and power consumption can be reduced. Furthermore, since the operation of each functional circuit block is not stopped during the test, the state of each functional circuit block can be determined while preventing the system from being slowed down.

The present invention is not limited to the configuration of the above-described embodiment, and any configuration can be used as long as the functions shown in the claims or the functions of the configuration of the present embodiment can be achieved. Is also applicable. For example, in the above embodiment, the delay circuit 213 is provided separately from the functional circuit block X206, but a part of the functional circuit block X206 may be used as a delay circuit. Thereby, an increase in circuit scale in the system LSI can be further suppressed.

Although the present invention has been described in detail and with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.

This application is based on a Japanese patent application filed on November 26, 2010 (Japanese Patent Application No. 2010-263316), the contents of which are incorporated herein by reference.

The power supply control system according to the present invention is useful as a power supply control system that individually controls the power supplied to a plurality of functional circuit blocks constituting the semiconductor device.

100 system LSI
102 Bus Arbitration Unit 103 Test Control Unit 104 Power Supply Control Unit 105 Power Supply IC
106 CPU
107 Functional circuit block B
108 Functional circuit block C
109 Functional circuit block D
110 Power Domain A
111 Power Domain B
112 Power Domain C
113 Power domain D
114 Constant power ON domain 115 Control signal 116 Power line 117 Idle monitor signal 118 Test status signal 200 System LSI
201 Always-on power domain 202 Power domain X
203 Test Control Unit 204 Bus Arbiter 205 Power Supply Control Unit 206 Functional Circuit Block X
207 Pattern generation circuit 208 Delay circuit 209

Comparison circuit

210A, 210B Normal / test selector 211 Idle monitor signal 212 Test control signal 213 Delay circuit 215 Power supply IC
222 Power domain Y
226 Functional circuit block Y
230 Bus

Claims

A power supply control system for individually controlling a power supply voltage from a power supply unit supplied to a plurality of functional circuit blocks constituting a semiconductor device,
A first functional circuit block operating in a first power supply region to which a first power supply is supplied;
A second functional circuit block that operates in a second power supply region to which a second power supply is supplied;
A bus connected to the first functional circuit block and the second functional circuit block and transmitting data in a third power supply region to which a third power supply is supplied;
A value obtained by transmitting test data to the second functional circuit block via the bus during the operation period of the first functional circuit block, operating in the third power supply region. A test control unit for confirming an operating state of the second functional circuit block based on
Having a power control system.
The power supply control system according to claim 1,
The test control unit
A detector for detecting an idle state of the second functional circuit block;
A step-down instruction unit that instructs the power source unit to step down the voltage of the second power source supplied to the second functional circuit block in which an idle state is detected;
Having a power control system.
The power supply control system according to claim 2,
The test control unit
A transmitter that transmits the test data to the second functional circuit block after the voltage of the second power source has been stepped down in accordance with an instruction from the step-down instruction unit;
An abnormality detection unit that compares an expected value with a value obtained by transmitting the test data, and detects an abnormality due to a voltage drop of the second power source based on the comparison result;
Having a power control system.
The power supply control system according to claim 3,
The test control unit
A boosting instruction unit that instructs the power supply unit to boost the voltage of the second power supply;
When the abnormality detection unit detects the abnormality, the transmitter unit transmits the test data again after the voltage of the second power source is boosted in accordance with an instruction from the boost instruction unit, and the abnormality detection A power supply control system for confirming that the abnormality is not detected by the unit.
The power supply control system according to claim 4,
The test control unit
A storage unit that stores the voltage of the second power source that is stepped down in accordance with an instruction from the step-down instruction unit;
The boosting instruction unit includes:
A power supply control system that instructs the power supply unit to step up the voltage of the second power supply to a voltage higher than the voltage stored in the storage unit.
The power supply control system according to claim 1,
The test control unit
A selection unit for selecting a data path that returns via the bus and via a delay circuit in the second power supply region;
A receiver that transmits the test data to the data path selected by the selector and receives the test data returned from the second power supply region;
A determination unit that compares the test data received by the reception unit and the test data transmitted by the test control unit to determine a delay state;
A power supply control system for confirming an operation state of the second functional circuit block based on the delay state.
The power supply control system according to claim 6,
A power supply control system using a part of the circuit of the second functional circuit block as the delay circuit.
A first functional circuit block operating in a first power supply region supplied with a first power supply; a second functional circuit block operating in a second power supply region supplied with a second power supply; A bus connected to one functional circuit block and the second functional circuit block and transmitting data in a third power supply region to which a third power supply is supplied; and a test control unit operating in the third power supply region A power supply control method for individually controlling power supply voltages supplied to a plurality of functional circuit blocks constituting a semiconductor device having:
The test control unit transmitting test data to the second functional circuit block via the bus during an operation period of the first functional circuit block;
The test control unit confirming an operating state of the second functional circuit block based on a value obtained by transmitting the test data;
A power supply control method.