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WO2011158360A1 - Burst-mode transimpedance amplifier - Google Patents

Burst-mode transimpedance amplifier Download PDF

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Publication number
WO2011158360A1
WO2011158360A1 PCT/JP2010/060279 JP2010060279W WO2011158360A1 WO 2011158360 A1 WO2011158360 A1 WO 2011158360A1 JP 2010060279 W JP2010060279 W JP 2010060279W WO 2011158360 A1 WO2011158360 A1 WO 2011158360A1
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WO
WIPO (PCT)
Prior art keywords
amplifier
signal
burst
detection circuit
equalization
Prior art date
Application number
PCT/JP2010/060279
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French (fr)
Japanese (ja)
Inventor
聡 吉間
雅樹 野田
正道 野上
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2012520218A priority Critical patent/JP5456162B2/en
Priority to PCT/JP2010/060279 priority patent/WO2011158360A1/en
Publication of WO2011158360A1 publication Critical patent/WO2011158360A1/en

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • H03F3/45071Differential amplifiers with semiconductor devices only
    • H03F3/45076Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H03F3/45085Long tailed pairs
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42Modifications of amplifiers to extend the bandwidth
    • H03F1/48Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
    • H03F1/486Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers with IC amplifier blocks
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/08Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
    • H03F3/087Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light with IC amplifier blocks
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/39Different band amplifiers are coupled in parallel to broadband the whole amplifying circuit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/435A peak detection being used in a signal measuring circuit in a controlling circuit of an amplifier
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2203/00Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45Indexing scheme relating to differential amplifiers
    • H03F2203/45372Indexing scheme relating to differential amplifiers the AAC comprising one or more potentiometers

Definitions

  • the present invention relates to a burst equalization amplifier that realizes a stable frequency response characteristic for a signal of any input optical power level.
  • Non-Patent Document 1 the amplifier connected to the subsequent stage of the preamplifier always maintains a constant gain and bandwidth, amplifies the analog amplitude input signal from the preamplifier to a constant amplitude, and passes it to the subsequent circuit.
  • the identification sensitivity of the subsequent amplifier can also affect the identification sensitivity of the entire receiver. There is sex. However, since the conventional amplifier has a constant gain and band for any signal, there is a possibility that reception sensitivity is deteriorated.
  • the present invention has been made to solve the above-described problems, and realizes a frequency response characteristic having a flat and the same band in the entire receiver for a signal of any input optical power level.
  • an object of the present invention is to obtain a burst equalization amplifier that realizes a wide band in the entire receiver and does not cause deterioration in reception sensitivity.
  • a burst equalizing amplifier adjusts the amplification amount of a specific frequency band based on a level detector that detects a signal amplitude level of an input signal and a signal amplitude level detected by the level detector, An amplifier with an equalizing function for outputting the amplified signal, an amplifier for amplifying the amplitude of the input signal to a desired amplitude based on the signal amplitude level detected by the level detector, and outputting a second amplified signal, etc.
  • a mixer that generates an output signal that compensates for the high frequency band of the input signal by mixing the first amplified signal output from the amplifier with the conversion function and the second amplified signal output from the amplifier It is.
  • the high frequency gain of the amplifier connected to the subsequent stage of the preamplifier is instantaneously increased as compared with other frequency bands in accordance with the input signal amplitude, and the preamplifier.
  • the entire receiver has a frequency response characteristic that is flat and has the same bandwidth, It is possible to obtain a burst equalization amplifier that realizes a wide band in the entire receiver and does not cause deterioration in reception sensitivity.
  • Embodiment 1 of this invention It is a block diagram of the burst equalization amplifier in Embodiment 1 of this invention. It is a block diagram of the high frequency gain variable amplifier in Embodiment 1 of this invention. It is a block diagram of the circuit relevant to the variable peaking amplifier in Embodiment 1 of this invention. It is a block diagram of the peak detection circuit in Embodiment 1 of this invention. It is a block diagram of the bottom detection circuit in Embodiment 1 of this invention. It is a conceptual diagram of the frequency response characteristic of each part in the receiver to which the burst equalizing amplifier according to Embodiment 1 of the present invention is applied. It is a block diagram of the circuit relevant to the variable peaking amplifier in Embodiment 2 of this invention.
  • Embodiment 3 of this invention It is a block diagram of the circuit relevant to the variable peaking amplifier in Embodiment 3 of this invention. It is a block diagram of the circuit relevant to the variable peaking amplifier in Embodiment 4 of this invention. It is a block diagram of the circuit relevant to the variable peaking amplifier in Embodiment 5 of this invention. It is a block diagram of the average value detection circuit in Embodiment 5 of this invention.
  • FIG. 1 is a configuration diagram of a burst equalization amplifier according to Embodiment 1 of the present invention.
  • the burst equalization amplifier 1 includes a high frequency gain variable amplifier 11, a multistage amplifier 12, an output amplifier 13, and an amplitude detection circuit 14. Note that the number of connection stages of the multistage amplifier 12 is not limited to that shown in FIG. 1, and the characteristics of the burst equalizing amplifier are not lost even if the number of dependent connection stages is increased.
  • the multistage amplifier 12 is not present and the high-frequency gain variable amplifier 11 is directly connected to the output amplifier 13 may be employed. Further, the multistage amplifier 12 and the output amplifier 13 may not exist, and the output from the high frequency gain variable amplifier 11 may be the output of the burst equalization amplifier circuit. Further, the amplitude detection circuit 14 may be configured to detect amplitude from a single-phase signal.
  • FIG. 2 is a configuration diagram of the high-frequency gain variable amplifier 11 according to the first embodiment of the present invention.
  • the high-frequency gain variable amplifier 11 includes a variable peaking amplifier 100, an amplifier 200, and a mixer 300.
  • the variable peaking amplifier 100 is an amplifier that can change the peaking amount of the frequency characteristic in accordance with the input signal amplitude.
  • the peaking frequency is f BW
  • f BW uses a frequency of about 0.6 to 1.0 times the baud rate.
  • the amplifier 200 is an amplifier that maintains a low frequency gain and has a bandwidth of about f BW .
  • a differential pair can be used.
  • the mixer 300 for example, two differential pairs having a common load resistance can be used.
  • FIG. 3 is a configuration diagram of a circuit related to the variable peaking amplifier 100 according to the first embodiment of the present invention.
  • the circuit including the variable peaking amplifier 100 of the first embodiment in FIG. 3 includes a peak detection circuit 101, a bottom detection circuit 102, a current source control circuit 103, load resistors 104a and 104b, a load inductor 105, a differential pair transistor 106a, 106b, and a variable current source 107.
  • the peak detection circuit 101 and the bottom detection circuit 102 correspond to the amplitude detection circuit 14 in FIG.
  • the peak detection circuit 101 is a circuit that can instantaneously hold the mark side voltage of the input voltage signal.
  • the bottom detection circuit 102 is a circuit that can instantaneously hold the space-side voltage of the input voltage signal.
  • FIG. 4 is a configuration diagram of the peak detection circuit 101 according to the first embodiment of the present invention.
  • the peak detection circuit 101 includes a diode 101a, a capacitor 101b that holds a voltage, and a MOS switch 101c that can discharge the charge of the capacitor 101b by an external reset signal.
  • FIG. 5 is a configuration diagram of the bottom detection circuit 102 according to Embodiment 1 of the present invention.
  • the bottom detection circuit 102 includes a diode 102a, a capacitor 102b that holds a voltage, and a MOS switch 102c that can discharge the charge of the capacitor 102b by an external reset signal.
  • the current source control circuit 103 shown in FIG. 3 controls the current value of the variable current source 107 according to the input signal amplitude value determined from the peak detection circuit 101 and the bottom detection circuit 102. More specifically, the current source control circuit 103 increases the current value of the variable current source 107 when the input signal amplitude is small, and decreases the current value of the variable current source 107 when the input signal amplitude is large. Thus, the peaking amount of the frequency characteristic can be changed.
  • the peak detection circuit 101 and the bottom detection circuit 102 are capable of a high-speed response of several ns to several hundreds ns, the response in the overhead part of each upstream packet signal in the one-to-multiple optical communication system to which the time division multiplexing method is applied. It is possible enough. Further, by releasing the charges held in the capacitors 101b and 102b of the peak detection circuit 101 and the bottom detection circuit 102 for each upstream packet signal by an external reset signal, upstream packet signals having different input optical powers are received. Even in such a case, an optimum receiver frequency characteristic can be obtained.
  • FIG. 6 is a conceptual diagram of the frequency response characteristics of each part in the receiver to which the burst equalizing amplifier according to Embodiment 1 of the present invention is applied. As shown in FIG. 6, since the preamplifier operates at a high gain when low optical power is input, the frequency band decreases. On the other hand, at the time of high power input, since the low gain operation is performed by suppressing the distortion amount of the output signal, the frequency band increases.
  • the high-frequency gain of the amplifier connected to the subsequent stage of the preamplifier is changed to the input signal amplitude. Accordingly, the gain is instantaneously increased as compared with other frequency bands, and the band that cannot be secured by the preamplifier can be compensated by the subsequent amplifier.
  • the entire receiver has a frequency response characteristic that is flat and has the same bandwidth, and the entire receiver has a wider bandwidth, resulting in poor reception sensitivity. It is possible to obtain a burst equalizing amplifier that does not cause the problem.
  • Embodiment 2 FIG. In the first embodiment, as shown in FIG. 3, the case where the peaking amount of the variable peaking amplifier 100 is changed by changing the current value of the variable current source 107 according to the input signal voltage amplitude has been described. . On the other hand, in the second embodiment, a case where the peaking amount is changed by changing the emitter resistance value connected to the differential pair transistors 106a and 106b in the variable peaking amplifier 100 will be described.
  • FIG. 7 is a configuration diagram of a circuit related to the variable peaking amplifier 100 according to the second embodiment of the present invention.
  • the circuit including the variable peaking amplifier 100 of the second embodiment in FIG. 7 includes a peak detection circuit 101, a bottom detection circuit 102, an emitter resistance control circuit 108, load resistors 104a and 104b, a load inductor 105, a differential pair transistor 106a, 106 b, variable emitter resistors 109 a and 109 b, and a current source 110.
  • the peak detection circuit 101 and the bottom detection circuit 102 correspond to the amplitude detection circuit 14 in FIG.
  • variable emitter resistors 109a and 109b for example, MOS transistors can be used.
  • the input to the amplifier is performed by the peak detection circuit 101 and the bottom detection circuit 102 as in the variable peaking amplifier 100 of the first embodiment.
  • the signal amplitude can be detected.
  • the emitter resistance control circuit 108 can change the peaking amount by changing the emitter resistance value according to the input signal amplitude value determined from the peak detection circuit 101 and the bottom detection circuit 102. More specifically, the emitter resistance control circuit 108 sets the emitter resistance to a high resistance, thereby reducing the gain of the variable peaking amplifier and reducing the peaking amount. On the other hand, by setting the emitter resistance to a low resistance by the emitter resistance control circuit 108, the gain of the variable peaking amplifier can be increased and the peaking amount can be increased.
  • the peak detection circuit 101 and the bottom detection circuit 102 can respond at a high speed of several ns to several hundreds ns. For this reason, in the one-to-many optical communication system to which the time division multiplexing system is applied, the emitter resistance change response in the overhead part of each uplink packet signal is sufficiently possible.
  • the high-frequency gain of the amplifier connected to the subsequent stage of the preamplifier is set according to the input signal amplitude.
  • the gain is increased instantaneously, and the band that cannot be secured by the preamplifier can be compensated for by the subsequent amplifier.
  • the entire receiver has a frequency response characteristic that is flat and has the same bandwidth, and the entire receiver has a wider bandwidth, resulting in poor reception sensitivity. It is possible to obtain a burst equalizing amplifier that does not cause the problem.
  • Embodiment 3 FIG.
  • the current source control circuit 103 uses the variable peaking amplifier 100 according to the input signal amplitude values detected by the peak detection circuit 101 and the bottom detection circuit 102. The case where the peaking amount is changed has been described.
  • the third embodiment instead of using the peak detection circuit 101, the bottom detection circuit 102, and the current source control circuit 103, a case where the peaking amount of the variable peaking amplifier 100 is changed by another configuration will be described. To do.
  • FIG. 8 is a configuration diagram of a circuit related to the variable peaking amplifier 100 according to the third embodiment of the present invention.
  • the circuit including the variable peaking amplifier 100 according to the third embodiment in FIG. 8 includes an amplitude detection circuit 111, a hysteresis comparator 112, load resistors 104a and 104b, a load inductor 105, differential pair transistors 106a and 106b, and a variable current source 107. It is configured with.
  • the amplitude detection circuit 111 corresponds to the amplitude detection circuit 14 in FIG.
  • the amplitude detection circuit 111 for example, the peak detection circuit 101 as shown in FIG. 4 can be used.
  • variable peaking amplifier 100 of the third embodiment having such a configuration, instead of using the peak detection circuit 101, the bottom detection circuit 102, and the current source control circuit 103, an amplitude detection circuit 111 and a hysteresis comparator 112 are provided.
  • a variable peaking amplifier is configured to vary the peaking amount.
  • the hysteresis comparator 112 sets the current value of the variable current source 107 so as to perform peaking when the amplitude of the input signal to the variable peaking amplifier 100 exceeds the reference voltage input from the outside. increase.
  • the hysteresis comparator 112 operates the variable peaking amplifier so as to decrease the current value so as not to perform peaking. As a result, a constant frequency response characteristic can be obtained as a receiver even if the input optical power changes.
  • the hysteresis comparator 112 it is possible to suppress the transition between the peaking operation and the peaking avoidance operation of the variable peaking amplifier 100 even when the power suddenly changes during the packet.
  • the amplitude detection circuit 111 is capable of a high-speed response of several ns to several hundreds ns. For this reason, in the one-to-many optical communication system to which the time division multiplexing system is applied, a response in the overhead part of each uplink packet signal is sufficiently possible.
  • the current value of the variable current source is changed in accordance with the input signal voltage amplitude, so that the high frequency of the amplifier connected to the subsequent stage of the preamplifier.
  • the gain is instantaneously increased in comparison with other frequency bands in accordance with the input signal amplitude, and a band that cannot be secured by the preamplifier can be compensated for in the subsequent amplifier.
  • the entire receiver has a frequency response characteristic that is flat and has the same band, and the entire receiver has a wider bandwidth, resulting in poor reception sensitivity. It is possible to obtain a burst equalizing amplifier that does not cause the problem.
  • Embodiment 4 FIG.
  • the case where the peaking amount of the variable peaking amplifier is determined by one hysteresis comparator 112 has been described.
  • the fourth embodiment a case where the peaking amount can be finely adjusted using a plurality of hysteresis comparators will be described.
  • FIG. 9 is a configuration diagram of a circuit related to the variable peaking amplifier 100 according to the fourth embodiment of the present invention.
  • the circuit including the variable peaking amplifier 100 of the fourth embodiment in FIG. 9 includes an amplitude detection circuit 111, n hysteresis comparators 112 (1) to 112 (n), load resistors 104a and 104b, load inductor 105, differential A pair of transistors 106a and 106b and a variable current source 107 are provided.
  • the amplitude detection circuit 111 corresponds to the amplitude detection circuit 14 in FIG.
  • the amplitude detection circuit 111 for example, the peak detection circuit 101 as shown in FIG. 4 can be used.
  • variable peaking amplifier 100 of the third embodiment having such a configuration, a plurality of different voltages are held as reference voltages of the hysteresis comparators 112 (1) to 112 (n) prepared in advance. Thereby, a plurality of threshold values of the input signal amplitude can be provided.
  • a plurality of threshold values of the input signal amplitude can be provided.
  • the transition between the peaking operation and the peaking avoidance operation of the variable peaking amplifier 100 can be suppressed even when the power suddenly changes during the packet. It becomes possible.
  • the amplitude detection circuit 111 can respond at a high speed of several ns to several hundreds ns. For this reason, in the one-to-many optical communication system to which the time division multiplexing method is applied, a response in the overhead part of each uplink packet signal is sufficiently possible.
  • the fourth embodiment by providing a plurality of hysteresis comparators, it becomes possible to finely adjust the peaking amount as compared with the case of using one hysteresis comparator.
  • Embodiment 5 FIG.
  • the case where the peaking amount of the variable peaking amplifier 100 is determined using the peak detection circuit 101 or the amplitude detection circuit 111 has been described.
  • the peaking amount is made variable by detecting the average value of the input signal and detecting the signal amplitude based on the difference from the signal off-level voltage input from the outside will be described. To do.
  • FIG. 10 is a configuration diagram of a circuit related to the variable peaking amplifier 100 according to the fifth embodiment of the present invention.
  • the circuit including the variable peaking amplifier 100 of the fifth embodiment in FIG. 10 includes an average value detection circuit 113, a current source control circuit 103, load resistors 104a and 104b, a load inductor 105, a differential pair transistors 106a and 106b, and a variable A current source 107 is provided.
  • the average value detection circuit 113 corresponds to the amplitude detection circuit 14 in FIG.
  • FIG. 11 is a configuration diagram of the average value detection circuit 113 according to the fifth embodiment of the present invention.
  • the average value detection circuit 113 shown in FIG. 11 includes a resistor 113a and a capacitor 113b, and can output an average voltage of an input signal by taking the form of an LPF.
  • the average value of the input signal is detected using the average value detection circuit 113, and the input signal amplitude value is detected from the difference between the detected average value and the signal off-level voltage input from the outside.
  • the average value detection circuit 113 always continues to detect the average value of the input signal. For this reason, the peaking amount of the amplifier can be continuously changed, and an operation can be performed for any signal amplitude without an external reset signal.
  • the average value detection circuit 113 is capable of high-speed response of several hundred ns. For this reason, in the one-to-many optical communication system to which the time division multiplexing method is applied, a response in the overhead part of each uplink packet signal is sufficiently possible.
  • the input signal amplitude value is constantly calculated using the average value detection circuit.
  • the peaking amount of the amplifier can be continuously changed, and a burst equalizing amplifier that can operate for any signal amplitude without an external reset signal can be obtained.
  • the peaking amount of the variable peaking amplifier 100 is changed by changing the current value of the variable current source 107 in accordance with the input signal voltage amplitude, as in the first embodiment.
  • the peaking is obtained by changing the emitter resistance values connected to the differential pair transistors 106a and 106b in the variable peaking amplifier 100 as in the second embodiment. The amount can be changed, and the same effect can be obtained.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

A burst-mode transimpedance amplifier that achieves flat frequency response characteristics in the same band throughout a receiver for any signal, regardless of input optical power level, broadens frequency range throughout the receiver, and does not cause receiving sensitivity degradation, is obtained by equipping a burst-mode transimpedance amplifier with: a level detector (14) that detects the signal amplitude level of an input signal; an equalization function-equipped amplifier (100) that adjusts amplification level in a specific frequency band and outputs a first amplified signal on the basis of the signal amplitude level detected by the level detector; an amplifier (200) that amplifies the amplitude signal to a desired amplitude and outputs a second amplified signal on the basis of the signal amplitude level detected by the level detector; and a mixer (300) that generates an output signal obtained by correcting the high-frequency band of the input signal, by mixing a first amplified signal output by the equalization function-equipped amplifier and a second amplified signal output by the amplifier.

Description

バースト等化増幅器Burst equalization amplifier
 本発明は、どのような入力光パワーレベルの信号に対しても、安定した周波数応答特性を実現するバースト等化増幅器に関する。 The present invention relates to a burst equalization amplifier that realizes a stable frequency response characteristic for a signal of any input optical power level.
 時分割多重方式を適用した1対多光通信システムのように、親局側受信器への入力信号強度が子局ごとに異なるようなシステムにおいては、親局側受信器における前置増幅器として、帰還抵抗値を入力信号強度ごとに変化させることで、入力ダイナミックレンジを確保する方式がよく用いられている(例えば、特許文献1)。 In a system in which the input signal strength to the master station side receiver is different for each slave station, such as a one-to-multiple optical communication system to which time division multiplexing is applied, as a preamplifier in the master station side receiver, A method of ensuring an input dynamic range by changing a feedback resistance value for each input signal intensity is often used (for example, Patent Document 1).
 この結果、最小受信感度付近の入力光パワーに対しては、帰還抵抗値を大きくすることで利得を高くし、出力振幅を増加させる。しかしながら、前置増幅器のGB積(Gain Band width product:利得帯域幅積)は一定であるため、出力信号の周波数特性は、狭帯域化される。よって、最小受信感度付近の入力光パワーの信号が受信器に入力された場合には、立ち上がり立ち下がりの遅い波形が出力されることとなる。 As a result, for input optical power near the minimum receiving sensitivity, increasing the feedback resistance value increases the gain and increases the output amplitude. However, since the GB product (Gain Band width product) of the preamplifier is constant, the frequency characteristic of the output signal is narrowed. Therefore, when an input optical power signal in the vicinity of the minimum reception sensitivity is input to the receiver, a waveform with a slow rise and fall is output.
 一方、前記前置増幅器の後段に接続される増幅器は、常に、一定の利得および帯域を保持しており、前置増幅器からのアナログ振幅入力信号を一定振幅まで増幅し、後段の回路へと受け渡していた(例えば、非特許文献1)。 On the other hand, the amplifier connected to the subsequent stage of the preamplifier always maintains a constant gain and bandwidth, amplifies the analog amplitude input signal from the preamplifier to a constant amplitude, and passes it to the subsequent circuit. (For example, Non-Patent Document 1).
特許第4361087号公報Japanese Patent No. 4310871
 しかしながら、従来技術には、以下のような課題がある。
 従来の増幅器は、常に、一定の利得および帯域を有しているため、入力信号として振幅値の大きな信号が入力された場合には、リミッティング動作により、出力振幅一定で、かつ立ち上がり立ち下がり時間が速い出力信号波形が得られる。
However, the prior art has the following problems.
Since conventional amplifiers always have a constant gain and bandwidth, when a signal with a large amplitude value is input as an input signal, the output amplitude is constant and the rise / fall time is limited by a limiting operation. A fast output signal waveform can be obtained.
 一方、入力信号として立ち上がり立ち下がり時間が遅く、振幅値の小さな信号が入力された場合には、リミッティング動作により、出力振幅は一定になるものの、立ち上がり立ち下がりは遅いままの信号となる。このために、前述した前置増幅器から最小受信感度付近の光パワーの信号が入力された場合には、受信器全体の利得が足りずに、受信感度劣化を引き起こすという問題がある。 On the other hand, when a signal with a small rise and fall time is input as an input signal and a signal having a small amplitude value is input, the output amplitude becomes constant due to the limiting operation, but the rise and fall remains a slow signal. For this reason, when an optical power signal in the vicinity of the minimum reception sensitivity is input from the preamplifier described above, there is a problem that the gain of the entire receiver is insufficient and the reception sensitivity is deteriorated.
 前置増幅器の高利得化が困難な10Gb/s以上の高速な時分割多重方式を適用した1対多光通信システムでは、後段の増幅器の識別感度も受信器全体の識別感度に影響を及ぼす可能性がある。しかしながら、従来の増幅器では、どのような信号に対しても一定の利得および帯域を有しているため、受信感度劣化を引き起こす可能性がある。 In a one-to-many optical communication system to which a high-speed time division multiplexing system of 10 Gb / s or more, in which it is difficult to increase the gain of the preamplifier, the identification sensitivity of the subsequent amplifier can also affect the identification sensitivity of the entire receiver. There is sex. However, since the conventional amplifier has a constant gain and band for any signal, there is a possibility that reception sensitivity is deteriorated.
 本発明は、前記のような課題を解決するためになされたものであり、どのような入力光パワーレベルの信号に対しても、受信器全体でフラットかつ同一の帯域を持つ周波数応答特性を実現するとともに、受信器全体での広帯域化を実現し、受信感度劣化を引き起こさないバースト等化増幅器を得ることを目的とする。 The present invention has been made to solve the above-described problems, and realizes a frequency response characteristic having a flat and the same band in the entire receiver for a signal of any input optical power level. In addition, an object of the present invention is to obtain a burst equalization amplifier that realizes a wide band in the entire receiver and does not cause deterioration in reception sensitivity.
 本発明に係るバースト等化増幅器は、入力信号の信号振幅レベルを検出するレベル検出器と、レベル検出器で検出された信号振幅レベルに基づいて、特定周波数帯の増幅量を調整し、第1の増幅信号を出力する等化機能付き増幅器と、レベル検出器で検出された信号振幅レベルに基づいて、所望振幅まで入力信号の振幅を増幅させ、第2の増幅信号を出力する増幅器と、等化機能付き増幅器から出力された第1の増幅信号と、増幅器から出力された第2の増幅信号とをミキシングすることで、入力信号の高周波帯域を補償した出力信号を生成するミキサとを備えるものである。 A burst equalizing amplifier according to the present invention adjusts the amplification amount of a specific frequency band based on a level detector that detects a signal amplitude level of an input signal and a signal amplitude level detected by the level detector, An amplifier with an equalizing function for outputting the amplified signal, an amplifier for amplifying the amplitude of the input signal to a desired amplitude based on the signal amplitude level detected by the level detector, and outputting a second amplified signal, etc. A mixer that generates an output signal that compensates for the high frequency band of the input signal by mixing the first amplified signal output from the amplifier with the conversion function and the second amplified signal output from the amplifier It is.
 本発明に係るバースト等化増幅器によれば、前置増幅器の後段に接続される増幅器の高周波利得を入力信号振幅に応じてその他周波数帯域と比較して瞬時に高利得化するとともに、前置増幅器で確保しきれなかった帯域を後段の増幅器において補償することにより、どのような入力光パワーレベルの信号に対しても、受信器全体でフラットかつ同一の帯域を持つ周波数応答特性を実現するとともに、受信器全体での広帯域化を実現し、受信感度劣化を引き起こさないバースト等化増幅器を得ることができる。 According to the burst equalizing amplifier according to the present invention, the high frequency gain of the amplifier connected to the subsequent stage of the preamplifier is instantaneously increased as compared with other frequency bands in accordance with the input signal amplitude, and the preamplifier. By compensating for the bandwidth that could not be secured in the amplifier in the subsequent stage, for the signal of any input optical power level, the entire receiver has a frequency response characteristic that is flat and has the same bandwidth, It is possible to obtain a burst equalization amplifier that realizes a wide band in the entire receiver and does not cause deterioration in reception sensitivity.
本発明の実施の形態1におけるバースト等化増幅器の構成図である。It is a block diagram of the burst equalization amplifier in Embodiment 1 of this invention. 本発明の実施の形態1における高周波利得可変増幅器の構成図である。It is a block diagram of the high frequency gain variable amplifier in Embodiment 1 of this invention. 本発明の実施の形態1における可変ピーキング増幅器に関連する回路の構成図である。It is a block diagram of the circuit relevant to the variable peaking amplifier in Embodiment 1 of this invention. 本発明の実施の形態1におけるピーク検波回路の構成図である。It is a block diagram of the peak detection circuit in Embodiment 1 of this invention. 本発明の実施の形態1におけるボトム検波回路の構成図である。It is a block diagram of the bottom detection circuit in Embodiment 1 of this invention. 本発明の実施の形態1におけるバースト等化増幅器を適用した受信器における各部の周波数応答特性の概念図である。It is a conceptual diagram of the frequency response characteristic of each part in the receiver to which the burst equalizing amplifier according to Embodiment 1 of the present invention is applied. 本発明の実施の形態2における可変ピーキング増幅器に関連する回路の構成図である。It is a block diagram of the circuit relevant to the variable peaking amplifier in Embodiment 2 of this invention. 本発明の実施の形態3における可変ピーキング増幅器に関連する回路の構成図である。It is a block diagram of the circuit relevant to the variable peaking amplifier in Embodiment 3 of this invention. 本発明の実施の形態4における可変ピーキング増幅器に関連する回路の構成図である。It is a block diagram of the circuit relevant to the variable peaking amplifier in Embodiment 4 of this invention. 本発明の実施の形態5における可変ピーキング増幅器に関連する回路の構成図である。It is a block diagram of the circuit relevant to the variable peaking amplifier in Embodiment 5 of this invention. 本発明の実施の形態5における平均値検出回路の構成図である。It is a block diagram of the average value detection circuit in Embodiment 5 of this invention.
 以下、本発明のバースト等化増幅器の好適な実施の形態につき図面を用いて説明する。 Hereinafter, preferred embodiments of the burst equalization amplifier of the present invention will be described with reference to the drawings.
 実施の形態1.
 図1は、本発明の実施の形態1におけるバースト等化増幅器の構成図である。図1において、バースト等化増幅器1は、高周波利得可変増幅器11、多段増幅器12、出力増幅器13、および振幅検波回路14を備えて構成されている。なお、多段増幅器12の接続段数は、図1に示すものだけではなく、従属接続段数が増加したとしても本バースト等化増幅器の特徴は失われない。
Embodiment 1 FIG.
FIG. 1 is a configuration diagram of a burst equalization amplifier according to Embodiment 1 of the present invention. In FIG. 1, the burst equalization amplifier 1 includes a high frequency gain variable amplifier 11, a multistage amplifier 12, an output amplifier 13, and an amplitude detection circuit 14. Note that the number of connection stages of the multistage amplifier 12 is not limited to that shown in FIG. 1, and the characteristics of the burst equalizing amplifier are not lost even if the number of dependent connection stages is increased.
 また、多段増幅器12が存在せず、高周波利得可変増幅器11が出力増幅器13に直接接続される構成でもよい。また、多段増幅器12および出力増幅器13が存在せず、高周波利得可変増幅器11からの出力がバースト等化増幅回路の出力となる構成でもよい。さらに、振幅検波回路14は、単相信号から振幅を検出する構成でもよい。 Alternatively, a configuration in which the multistage amplifier 12 is not present and the high-frequency gain variable amplifier 11 is directly connected to the output amplifier 13 may be employed. Further, the multistage amplifier 12 and the output amplifier 13 may not exist, and the output from the high frequency gain variable amplifier 11 may be the output of the burst equalization amplifier circuit. Further, the amplitude detection circuit 14 may be configured to detect amplitude from a single-phase signal.
 図2は、本発明の実施の形態1における高周波利得可変増幅器11の構成図である。図2において、高周波利得可変増幅器11は、可変ピーキング増幅器100、増幅器200、ミキサ300を備えて構成されている。 FIG. 2 is a configuration diagram of the high-frequency gain variable amplifier 11 according to the first embodiment of the present invention. In FIG. 2, the high-frequency gain variable amplifier 11 includes a variable peaking amplifier 100, an amplifier 200, and a mixer 300.
 可変ピーキング増幅器100は、入力信号振幅に応じて周波数特性のピーキング量を変更できる増幅器である。ここで、ピーキングを行う周波数をfBWとすると、fBWは、ボーレートの0.6倍~1.0倍程度の周波数を用いる。ボーレートの0.6倍~1.0倍程度の周波数にピーキングを行うことで、前置増幅器での帯域制限を補償でき、かつ不要な高周波雑音を抑圧可能な最適な周波数特性を受信器全体として得ることができる。 The variable peaking amplifier 100 is an amplifier that can change the peaking amount of the frequency characteristic in accordance with the input signal amplitude. Here, assuming that the peaking frequency is f BW , f BW uses a frequency of about 0.6 to 1.0 times the baud rate. By peaking at a frequency about 0.6 to 1.0 times the baud rate, the entire receiver can have the optimum frequency characteristics that can compensate for the band limitation of the preamplifier and suppress unnecessary high-frequency noise. Obtainable.
 増幅器200は、低周波利得を保持し、帯域幅は、fBW程度である増幅器である。この増幅器200としては、例えば、差動対を用いることができる。また、ミキサ300としては、例えば、負荷抵抗を共通化した2つの差動対を用いることができる。 The amplifier 200 is an amplifier that maintains a low frequency gain and has a bandwidth of about f BW . As this amplifier 200, for example, a differential pair can be used. In addition, as the mixer 300, for example, two differential pairs having a common load resistance can be used.
 図3は、本発明の実施の形態1における可変ピーキング増幅器100に関連する回路の構成図である。図3における本実施の形態1の可変ピーキング増幅器100を含む回路は、ピーク検波回路101、ボトム検波回路102、電流源制御回路103、負荷抵抗104a、104b、負荷インダクタ105、差動対トランジスタ106a、106b、および可変電流源107を備えて構成されている。 FIG. 3 is a configuration diagram of a circuit related to the variable peaking amplifier 100 according to the first embodiment of the present invention. The circuit including the variable peaking amplifier 100 of the first embodiment in FIG. 3 includes a peak detection circuit 101, a bottom detection circuit 102, a current source control circuit 103, load resistors 104a and 104b, a load inductor 105, a differential pair transistor 106a, 106b, and a variable current source 107.
 ここで、ピーク検波回路101およびボトム検波回路102は、先の図1における振幅検波回路14に相当する。そして、ピーク検波回路101は、入力電圧信号のマーク側電圧を瞬時に保持可能な回路である。一方、ボトム検波回路102は、入力電圧信号のスペース側電圧を瞬時に保持可能な回路である。 Here, the peak detection circuit 101 and the bottom detection circuit 102 correspond to the amplitude detection circuit 14 in FIG. The peak detection circuit 101 is a circuit that can instantaneously hold the mark side voltage of the input voltage signal. On the other hand, the bottom detection circuit 102 is a circuit that can instantaneously hold the space-side voltage of the input voltage signal.
 図4は、本発明の実施の形態1におけるピーク検波回路101の構成図である。図4において、ピーク検波回路101は、ダイオード101a、電圧を保持するキャパシタ101b、および外部リセット信号によりキャパシタ101bの電荷を放出可能なMOSスイッチ101cを備えて構成されている。このような構成により、入力信号電圧をキャパシタ101bに積算することで、数nsから数100nsという短時間でマーク側電圧分の電荷を保持することが可能である。 FIG. 4 is a configuration diagram of the peak detection circuit 101 according to the first embodiment of the present invention. In FIG. 4, the peak detection circuit 101 includes a diode 101a, a capacitor 101b that holds a voltage, and a MOS switch 101c that can discharge the charge of the capacitor 101b by an external reset signal. With such a configuration, by accumulating the input signal voltage in the capacitor 101b, it is possible to hold the charge corresponding to the mark side voltage in a short time of several ns to several hundreds ns.
 一方、図5は、本発明の実施の形態1におけるボトム検波回路102の構成図である。図5において、ボトム検波回路102は、ダイオード102a、電圧を保持するキャパシタ102b、および外部リセット信号によりキャパシタ102bの電荷を放出可能なMOSスイッチ102cを備えて構成されている。このような構成により、入力信号電圧をキャパシタ102bに積算することで、数nsから数100nsという短時間でスペース側電圧分の電荷を保持することが可能である。 On the other hand, FIG. 5 is a configuration diagram of the bottom detection circuit 102 according to Embodiment 1 of the present invention. In FIG. 5, the bottom detection circuit 102 includes a diode 102a, a capacitor 102b that holds a voltage, and a MOS switch 102c that can discharge the charge of the capacitor 102b by an external reset signal. With such a configuration, by accumulating the input signal voltage in the capacitor 102b, it is possible to hold the charge corresponding to the space side voltage in a short time of several ns to several hundreds ns.
 先の図3に示した電流源制御回路103は、ピーク検波回路101およびボトム検波回路102から判別した入力信号振幅値に応じて、可変電流源107の電流値を制御する。より具体的には、電流源制御回路103は、入力信号振幅が小さい場合には可変電流源107の電流値を大きくし、入力信号振幅が大きい場合には可変電流源107の電流値を小さくすることで、周波数特性のピーキング量を変更できる。 The current source control circuit 103 shown in FIG. 3 controls the current value of the variable current source 107 according to the input signal amplitude value determined from the peak detection circuit 101 and the bottom detection circuit 102. More specifically, the current source control circuit 103 increases the current value of the variable current source 107 when the input signal amplitude is small, and decreases the current value of the variable current source 107 when the input signal amplitude is large. Thus, the peaking amount of the frequency characteristic can be changed.
 ピーク検波回路101およびボトム検波回路102は、数nsから数100nsという高速応答が可能であるため、時分割多重方式を適用した1対多光通信システムにおける各上りパケット信号のオーバーヘッド部分での応答が、十分可能である。また、上りパケット信号ごとにピーク検波回路101およびボトム検波回路102のそれぞれのキャパシタ101b、102bに保持されている電荷を、外部リセット信号により開放することで、入力光パワーの異なる上りパケット信号が受信された場合においても、最適な受信器周波数特性を得ることができる。 Since the peak detection circuit 101 and the bottom detection circuit 102 are capable of a high-speed response of several ns to several hundreds ns, the response in the overhead part of each upstream packet signal in the one-to-multiple optical communication system to which the time division multiplexing method is applied. It is possible enough. Further, by releasing the charges held in the capacitors 101b and 102b of the peak detection circuit 101 and the bottom detection circuit 102 for each upstream packet signal by an external reset signal, upstream packet signals having different input optical powers are received. Even in such a case, an optimum receiver frequency characteristic can be obtained.
 図6は、本発明の実施の形態1におけるバースト等化増幅器を適用した受信器における各部の周波数応答特性の概念図である。図6に示すように、前置増幅器は、低光パワー入力時に高利得動作となるため、周波数帯域は減少する。一方、高パワー入力時には、出力信号の歪み量を抑制することで低利得動作となるため、周波数帯域は増加する。 FIG. 6 is a conceptual diagram of the frequency response characteristics of each part in the receiver to which the burst equalizing amplifier according to Embodiment 1 of the present invention is applied. As shown in FIG. 6, since the preamplifier operates at a high gain when low optical power is input, the frequency band decreases. On the other hand, at the time of high power input, since the low gain operation is performed by suppressing the distortion amount of the output signal, the frequency band increases.
 このような前置増幅器出力信号を、本実施の形態1におけるバースト等化増幅器へと入力した場合を考える。この場合、低光パワー入力時においては、低周波利得は一定にしつつ、ピーキング量を調整することで高周波利得を増大させ、バースト等化増幅器出力での帯域を増加させる。一方、高光パワー入力時においては、受信器出力の波形歪みを発生させないようにするためにバースト等化増幅器のピーク量を抑制し、フラットかつ高利得な周波数応答とすることで、低光パワー入力時と同一帯域を実現する。 Consider a case where such a preamplifier output signal is input to the burst equalization amplifier according to the first embodiment. In this case, at the time of low optical power input, the low frequency gain is kept constant, the peaking amount is adjusted to increase the high frequency gain, and the band at the burst equalizing amplifier output is increased. On the other hand, at the time of high optical power input, the peak amount of the burst equalization amplifier is suppressed so as not to generate waveform distortion of the receiver output, and the frequency response is flat and high gain. Realize the same bandwidth as time.
 以上のように、実施の形態1によれば、可変電流源の電流値を入力信号電圧振幅に応じて変更することで、前置増幅器の後段に接続される増幅器の高周波利得を、入力信号振幅に応じてその他周波数帯域と比較して瞬時に高利得化し、前置増幅器で確保しきれなかった帯域を後段の増幅器において補償することができる。この結果、どのような入力光パワーレベルの信号に対しても、受信器全体でフラットかつ同一の帯域を持つ周波数応答特性を実現するとともに、受信器全体での広帯域化を実現し、受信感度劣化を引き起こさないバースト等化増幅器を得ることができる。 As described above, according to the first embodiment, by changing the current value of the variable current source according to the input signal voltage amplitude, the high-frequency gain of the amplifier connected to the subsequent stage of the preamplifier is changed to the input signal amplitude. Accordingly, the gain is instantaneously increased as compared with other frequency bands, and the band that cannot be secured by the preamplifier can be compensated by the subsequent amplifier. As a result, for any input optical power level signal, the entire receiver has a frequency response characteristic that is flat and has the same bandwidth, and the entire receiver has a wider bandwidth, resulting in poor reception sensitivity. It is possible to obtain a burst equalizing amplifier that does not cause the problem.
 実施の形態2.
 先の実施の形態1では、図3に示したように、可変電流源107の電流値を入力信号電圧振幅に応じて変更することで、可変ピーキング増幅器100のピーキング量を変更する場合について説明した。これに対して、本実施の形態2では、可変ピーキング増幅器100内の差動対トランジスタ106a、106bに接続されるエミッタ抵抗値を変更することで、ピーキング量を変更する場合について説明する。
Embodiment 2. FIG.
In the first embodiment, as shown in FIG. 3, the case where the peaking amount of the variable peaking amplifier 100 is changed by changing the current value of the variable current source 107 according to the input signal voltage amplitude has been described. . On the other hand, in the second embodiment, a case where the peaking amount is changed by changing the emitter resistance value connected to the differential pair transistors 106a and 106b in the variable peaking amplifier 100 will be described.
 図7は、本発明の実施の形態2における可変ピーキング増幅器100に関連する回路の構成図である。図7における本実施の形態2の可変ピーキング増幅器100を含む回路は、ピーク検波回路101、ボトム検波回路102、エミッタ抵抗制御回路108、負荷抵抗104a、104b、負荷インダクタ105、差動対トランジスタ106a、106b、可変エミッタ抵抗109a、109b、および電流源110を備えて構成されている。ここで、ピーク検波回路101およびボトム検波回路102は、先の図1における振幅検波回路14に相当する。 FIG. 7 is a configuration diagram of a circuit related to the variable peaking amplifier 100 according to the second embodiment of the present invention. The circuit including the variable peaking amplifier 100 of the second embodiment in FIG. 7 includes a peak detection circuit 101, a bottom detection circuit 102, an emitter resistance control circuit 108, load resistors 104a and 104b, a load inductor 105, a differential pair transistor 106a, 106 b, variable emitter resistors 109 a and 109 b, and a current source 110. Here, the peak detection circuit 101 and the bottom detection circuit 102 correspond to the amplitude detection circuit 14 in FIG.
 また、可変エミッタ抵抗109a、109bとしては、例えば、MOSトランジスタを用いることができる。このような構成を備えた本実施の形態2の可変ピーキング増幅器100においては、先の実施の形態1の可変ピーキング増幅器100と同様に、ピーク検波回路101およびボトム検波回路102により、増幅器への入力信号振幅を検出することができる。 Further, as the variable emitter resistors 109a and 109b, for example, MOS transistors can be used. In the variable peaking amplifier 100 of the second embodiment having such a configuration, the input to the amplifier is performed by the peak detection circuit 101 and the bottom detection circuit 102 as in the variable peaking amplifier 100 of the first embodiment. The signal amplitude can be detected.
 従って、エミッタ抵抗制御回路108は、ピーク検波回路101およびボトム検波回路102から判別した入力信号振幅値に応じてエミッタ抵抗値を変更することで、ピーキング量を変更することができる。より具体的には、エミッタ抵抗制御回路108により、エミッタ抵抗を高抵抗と設定することで、可変ピーキング増幅器の利得を減少させ、ピーキング量を減少させることができる。一方、エミッタ抵抗制御回路108により、エミッタ抵抗を低抵抗と設定することで、可変ピーキング増幅器の利得を増加させ、ピーキング量を増加させることができる。 Therefore, the emitter resistance control circuit 108 can change the peaking amount by changing the emitter resistance value according to the input signal amplitude value determined from the peak detection circuit 101 and the bottom detection circuit 102. More specifically, the emitter resistance control circuit 108 sets the emitter resistance to a high resistance, thereby reducing the gain of the variable peaking amplifier and reducing the peaking amount. On the other hand, by setting the emitter resistance to a low resistance by the emitter resistance control circuit 108, the gain of the variable peaking amplifier can be increased and the peaking amount can be increased.
 先の実施の形態1と同じく、ピーク検波回路101およびボトム検波回路102は、数nsから数100nsという高速応答が可能である。このため、時分割多重方式を適用した1対多光通信システムにおいて、各上りパケット信号のオーバーヘッド部分でのエミッタ抵抗変更応答が、十分可能である。 As in the first embodiment, the peak detection circuit 101 and the bottom detection circuit 102 can respond at a high speed of several ns to several hundreds ns. For this reason, in the one-to-many optical communication system to which the time division multiplexing system is applied, the emitter resistance change response in the overhead part of each uplink packet signal is sufficiently possible.
 以上のように、実施の形態2によれば、エミッタ抵抗値を入力信号電圧振幅に応じて変更することで、前置増幅器の後段に接続される増幅器の高周波利得を、入力信号振幅に応じてその他周波数帯域と比較して瞬時に高利得化し、前置増幅器で確保しきれなかった帯域を後段の増幅器において補償することができる。この結果、どのような入力光パワーレベルの信号に対しても、受信器全体でフラットかつ同一の帯域を持つ周波数応答特性を実現するとともに、受信器全体での広帯域化を実現し、受信感度劣化を引き起こさないバースト等化増幅器を得ることができる。 As described above, according to the second embodiment, by changing the emitter resistance value according to the input signal voltage amplitude, the high-frequency gain of the amplifier connected to the subsequent stage of the preamplifier is set according to the input signal amplitude. Compared with other frequency bands, the gain is increased instantaneously, and the band that cannot be secured by the preamplifier can be compensated for by the subsequent amplifier. As a result, for any input optical power level signal, the entire receiver has a frequency response characteristic that is flat and has the same bandwidth, and the entire receiver has a wider bandwidth, resulting in poor reception sensitivity. It is possible to obtain a burst equalizing amplifier that does not cause the problem.
 実施の形態3.
 先の実施の形態1、2では、図3に示したように、ピーク検波回路101およびボトム検波回路102により検出された入力信号振幅値に応じて、電流源制御回路103より可変ピーキング増幅器100のピーキング量を変化させる場合について説明した。これに対して、本実施の形態3では、ピーク検波回路101、ボトム検波回路102、および電流源制御回路103を用いる代わりに、別の構成により可変ピーキング増幅器100のピーキング量を変化させる場合について説明する。
Embodiment 3 FIG.
In the first and second embodiments, as shown in FIG. 3, the current source control circuit 103 uses the variable peaking amplifier 100 according to the input signal amplitude values detected by the peak detection circuit 101 and the bottom detection circuit 102. The case where the peaking amount is changed has been described. In contrast, in the third embodiment, instead of using the peak detection circuit 101, the bottom detection circuit 102, and the current source control circuit 103, a case where the peaking amount of the variable peaking amplifier 100 is changed by another configuration will be described. To do.
 図8は、本発明の実施の形態3における可変ピーキング増幅器100に関連する回路の構成図である。図8における本実施の形態3の可変ピーキング増幅器100を含む回路は、振幅検波回路111、ヒステリシスコンパレータ112、負荷抵抗104a、104b、負荷インダクタ105、差動対トランジスタ106a、106b、および可変電流源107を備えて構成されている。 FIG. 8 is a configuration diagram of a circuit related to the variable peaking amplifier 100 according to the third embodiment of the present invention. The circuit including the variable peaking amplifier 100 according to the third embodiment in FIG. 8 includes an amplitude detection circuit 111, a hysteresis comparator 112, load resistors 104a and 104b, a load inductor 105, differential pair transistors 106a and 106b, and a variable current source 107. It is configured with.
 ここで、振幅検波回路111は、先の図1における振幅検波回路14に相当する。そして、振幅検波回路111としては、例えば、先の図4で示したようなピーク検波回路101を用いることができる。 Here, the amplitude detection circuit 111 corresponds to the amplitude detection circuit 14 in FIG. As the amplitude detection circuit 111, for example, the peak detection circuit 101 as shown in FIG. 4 can be used.
 このような構成を備えた本実施の形態3の可変ピーキング増幅器100においては、ピーク検波回路101、ボトム検波回路102、および電流源制御回路103を用いる代わりに、振幅検波回路111およびヒステリシスコンパレータ112を用いてピーキング量を可変とする可変ピーキング増幅器を構成している。 In the variable peaking amplifier 100 of the third embodiment having such a configuration, instead of using the peak detection circuit 101, the bottom detection circuit 102, and the current source control circuit 103, an amplitude detection circuit 111 and a hysteresis comparator 112 are provided. Thus, a variable peaking amplifier is configured to vary the peaking amount.
 本実施の形態3において、ヒステリシスコンパレータ112は、可変ピーキング増幅器100への入力信号振幅が外部から入力される基準電圧を超えた場合には、ピーキングを行うように、可変電流源107の電流値を増加させる。一方、入力信号振幅が基準電圧未満の場合には、ヒステリシスコンパレータ112は、ピーキングを行わないように電流値を減少させるように可変ピーキング増幅器を動作させる。これにより、入力光パワーが変化しても受信器として一定の周波数応答特性を得ることができる。 In the third embodiment, the hysteresis comparator 112 sets the current value of the variable current source 107 so as to perform peaking when the amplitude of the input signal to the variable peaking amplifier 100 exceeds the reference voltage input from the outside. increase. On the other hand, when the input signal amplitude is less than the reference voltage, the hysteresis comparator 112 operates the variable peaking amplifier so as to decrease the current value so as not to perform peaking. As a result, a constant frequency response characteristic can be obtained as a receiver even if the input optical power changes.
 さらに、ヒステリシスコンパレータ112を用いることで、パケットの途中で急激にパワーが変化した場合においても、可変ピーキング増幅器100のピーキング動作とピーキング回避動作の遷移を抑圧することが可能となる。 Furthermore, by using the hysteresis comparator 112, it is possible to suppress the transition between the peaking operation and the peaking avoidance operation of the variable peaking amplifier 100 even when the power suddenly changes during the packet.
 なお、振幅検波回路111は、数nsから数100nsという高速応答が可能である。このため、時分割多重方式を適用した1対多光通信システムにおいて、各上りパケット信号のオーバーヘッド部分での応答が、十分可能である。 Note that the amplitude detection circuit 111 is capable of a high-speed response of several ns to several hundreds ns. For this reason, in the one-to-many optical communication system to which the time division multiplexing system is applied, a response in the overhead part of each uplink packet signal is sufficiently possible.
 以上のように、実施の形態3によれば、ヒステリシスコンパレータを用いて、可変電流源の電流値を入力信号電圧振幅に応じて変更することで、前置増幅器の後段に接続される増幅器の高周波利得を、入力信号振幅に応じてその他周波数帯域と比較して瞬時に高利得化し、前置増幅器で確保しきれなかった帯域を後段の増幅器において補償することができる。この結果、どのような入力光パワーレベルの信号に対しても、受信器全体でフラットかつ同一の帯域を持つ周波数応答特性を実現するとともに、受信器全体での広帯域化を実現し、受信感度劣化を引き起こさないバースト等化増幅器を得ることができる。 As described above, according to the third embodiment, by using the hysteresis comparator, the current value of the variable current source is changed in accordance with the input signal voltage amplitude, so that the high frequency of the amplifier connected to the subsequent stage of the preamplifier. The gain is instantaneously increased in comparison with other frequency bands in accordance with the input signal amplitude, and a band that cannot be secured by the preamplifier can be compensated for in the subsequent amplifier. As a result, for any input optical power level signal, the entire receiver has a frequency response characteristic that is flat and has the same band, and the entire receiver has a wider bandwidth, resulting in poor reception sensitivity. It is possible to obtain a burst equalizing amplifier that does not cause the problem.
 実施の形態4.
 先の実施の形態3では、一台のヒステリシスコンパレータ112により可変ピーキング増幅器のピーキング量を決定する場合について説明した。これに対して、本実施の形態4では、複数のヒステリシスコンパレータを用いてピーキング量を微細に調整可能とする場合について説明する。
Embodiment 4 FIG.
In the third embodiment, the case where the peaking amount of the variable peaking amplifier is determined by one hysteresis comparator 112 has been described. On the other hand, in the fourth embodiment, a case where the peaking amount can be finely adjusted using a plurality of hysteresis comparators will be described.
 図9は、本発明の実施の形態4における可変ピーキング増幅器100に関連する回路の構成図である。図9における本実施の形態4の可変ピーキング増幅器100を含む回路は、振幅検波回路111、n台のヒステリシスコンパレータ112(1)~112(n)、負荷抵抗104a、104b、負荷インダクタ105、差動対トランジスタ106a、106b、および可変電流源107を備えて構成されている。 FIG. 9 is a configuration diagram of a circuit related to the variable peaking amplifier 100 according to the fourth embodiment of the present invention. The circuit including the variable peaking amplifier 100 of the fourth embodiment in FIG. 9 includes an amplitude detection circuit 111, n hysteresis comparators 112 (1) to 112 (n), load resistors 104a and 104b, load inductor 105, differential A pair of transistors 106a and 106b and a variable current source 107 are provided.
 ここで、振幅検波回路111は、先の図1における振幅検波回路14に相当する。そして、振幅検波回路111としては、例えば、先の図4で示したようなピーク検波回路101を用いることができる。 Here, the amplitude detection circuit 111 corresponds to the amplitude detection circuit 14 in FIG. As the amplitude detection circuit 111, for example, the peak detection circuit 101 as shown in FIG. 4 can be used.
 このような構成を備えた本実施の形態3の可変ピーキング増幅器100においては、あらかじめ用意するヒステリシスコンパレータ112(1)~112(n)の基準電圧として、複数の異なる電圧を保持している。これにより、入力信号振幅の閾値を複数設けることができる。これらのヒステリシスコンパレータ112(1)~112(n)の出力により、可変ピーキング増幅器100の電流値を変化させることで、1台のヒステリシスコンパレータ112を用いた先の実施の形態3の場合と比較して、ピーキング量を微細に調整することが可能となる。 In the variable peaking amplifier 100 of the third embodiment having such a configuration, a plurality of different voltages are held as reference voltages of the hysteresis comparators 112 (1) to 112 (n) prepared in advance. Thereby, a plurality of threshold values of the input signal amplitude can be provided. By changing the current value of the variable peaking amplifier 100 based on the outputs of the hysteresis comparators 112 (1) to 112 (n), it is possible to compare with the case of the third embodiment using a single hysteresis comparator 112. Thus, the peaking amount can be finely adjusted.
 さらに、ヒステリシスコンパレータ112(1)~112(n)を用いることで、パケットの途中で急激にパワーが変化した場合においても、可変ピーキング増幅器100のピーキング動作とピーキング回避動作の遷移を抑圧することが可能となる。 Further, by using the hysteresis comparators 112 (1) to 112 (n), the transition between the peaking operation and the peaking avoidance operation of the variable peaking amplifier 100 can be suppressed even when the power suddenly changes during the packet. It becomes possible.
 なお、振幅検波回路111は、数nsから数100nsという高速応答が可能である。このため、時分割多重方式を適用した1対多光通信システムにおいて、各上りパケット信号のオーバーヘッド部分での応答が、十分可能である。 It should be noted that the amplitude detection circuit 111 can respond at a high speed of several ns to several hundreds ns. For this reason, in the one-to-many optical communication system to which the time division multiplexing method is applied, a response in the overhead part of each uplink packet signal is sufficiently possible.
 以上のように、実施の形態4によれば、複数台のヒステリシスコンパレータを備えることで、1台のヒステリシスコンパレータを用いる場合と比較して、ピーキング量を微細に調整することが可能となる。 As described above, according to the fourth embodiment, by providing a plurality of hysteresis comparators, it becomes possible to finely adjust the peaking amount as compared with the case of using one hysteresis comparator.
 実施の形態5.
 先の実施の形態1~4では、ピーク検波回路101あるいは振幅検波回路111を用いて可変ピーキング増幅器100のピーキング量を決定する場合について説明した。これに対して、本実施の形態5では、入力信号の平均値を検出し、外部から入力される信号オフレベル電圧との差分により信号振幅を検出することでピーキング量を可変とする場合について説明する。
Embodiment 5 FIG.
In the first to fourth embodiments, the case where the peaking amount of the variable peaking amplifier 100 is determined using the peak detection circuit 101 or the amplitude detection circuit 111 has been described. On the other hand, in the fifth embodiment, the case where the peaking amount is made variable by detecting the average value of the input signal and detecting the signal amplitude based on the difference from the signal off-level voltage input from the outside will be described. To do.
 図10は、本発明の実施の形態5における可変ピーキング増幅器100に関連する回路の構成図である。図10における本実施の形態5の可変ピーキング増幅器100を含む回路は、平均値検出回路113、電流源制御回路103、負荷抵抗104a、104b、負荷インダクタ105、差動対トランジスタ106a、106b、および可変電流源107を備えて構成されている。ここで、平均値検出回路113は、先の図1における振幅検波回路14に相当する。 FIG. 10 is a configuration diagram of a circuit related to the variable peaking amplifier 100 according to the fifth embodiment of the present invention. The circuit including the variable peaking amplifier 100 of the fifth embodiment in FIG. 10 includes an average value detection circuit 113, a current source control circuit 103, load resistors 104a and 104b, a load inductor 105, a differential pair transistors 106a and 106b, and a variable A current source 107 is provided. Here, the average value detection circuit 113 corresponds to the amplitude detection circuit 14 in FIG.
 このような構成を備えた本実施の形態5の可変ピーキング増幅器100においては、平均値検出回路113を用いてピーキング量を可変とする。図11は、本発明の実施の形態5における平均値検出回路113の構成図である。図11に示す平均値検出回路113は、抵抗113aおよびキャパシタ113bから構成されており、LPFの形態を取ることにより、入力信号の平均電圧を出力するこができる。 In the variable peaking amplifier 100 of the fifth embodiment having such a configuration, the peaking amount is variable using the average value detection circuit 113. FIG. 11 is a configuration diagram of the average value detection circuit 113 according to the fifth embodiment of the present invention. The average value detection circuit 113 shown in FIG. 11 includes a resistor 113a and a capacitor 113b, and can output an average voltage of an input signal by taking the form of an LPF.
 本実施の形態5では、平均値検出回路113を用いて入力信号の平均値を検出し、検出した平均値と外部から入力される信号オフレベル電圧との差分から入力信号振幅値を検出する。ここで、平均値検出回路113は、常に、入力信号の平均値を検出し続ける。このため、増幅器のピーキング量を連続的に変更することができ、外部リセット信号なしに、どのような信号振幅に対しても動作が可能となる。 In the fifth embodiment, the average value of the input signal is detected using the average value detection circuit 113, and the input signal amplitude value is detected from the difference between the detected average value and the signal off-level voltage input from the outside. Here, the average value detection circuit 113 always continues to detect the average value of the input signal. For this reason, the peaking amount of the amplifier can be continuously changed, and an operation can be performed for any signal amplitude without an external reset signal.
 なお、平均値検出回路113は、数100nsという高速応答が可能である。このため、時分割多重方式を適用した1対多光通信システムにおいて、各上りパケット信号のオーバーヘッド部分での応答が、十分可能である。 Note that the average value detection circuit 113 is capable of high-speed response of several hundred ns. For this reason, in the one-to-many optical communication system to which the time division multiplexing method is applied, a response in the overhead part of each uplink packet signal is sufficiently possible.
 以上のように、実施の形態5によれば、平均値検出回路を用いて、入力信号振幅値を常時算出している。この結果、増幅器のピーキング量を連続的に変更することができ、外部リセット信号なしに、どのような信号振幅に対しても動作が可能なバースト等化増幅器を得ることができる。 As described above, according to the fifth embodiment, the input signal amplitude value is constantly calculated using the average value detection circuit. As a result, the peaking amount of the amplifier can be continuously changed, and a burst equalizing amplifier that can operate for any signal amplitude without an external reset signal can be obtained.
 なお、上述の実施の形態3~5においては、先の実施の形態1と同様に、可変電流源107の電流値を入力信号電圧振幅に応じて変更することで、可変ピーキング増幅器100のピーキング量を変更する場合について説明した。しかしながら、実施の形態3~5に係る発明は、先の実施の形態2と同様に、可変ピーキング増幅器100内の差動対トランジスタ106a、106bに接続されたエミッタ抵抗値を変更することで、ピーキング量を変更することも可能であり、同様の効果を得ることができる。 In the above-described third to fifth embodiments, the peaking amount of the variable peaking amplifier 100 is changed by changing the current value of the variable current source 107 in accordance with the input signal voltage amplitude, as in the first embodiment. Explained the case of changing. However, in the inventions according to the third to fifth embodiments, the peaking is obtained by changing the emitter resistance values connected to the differential pair transistors 106a and 106b in the variable peaking amplifier 100 as in the second embodiment. The amount can be changed, and the same effect can be obtained.

Claims (9)

  1.  入力信号の信号振幅レベルを検出するレベル検出器と、
     前記レベル検出器で検出された前記信号振幅レベルに基づいて、特定周波数帯の増幅量を調整し、第1の増幅信号を出力する等化機能付き増幅器と、
     前記レベル検出器で検出された前記信号振幅レベルに基づいて、所望振幅まで前記入力信号の振幅を増幅させ、第2の増幅信号を出力する増幅器と、
     前記等化機能付き増幅器から出力された前記第1の増幅信号と、前記増幅器から出力された前記第2の増幅信号とをミキシングすることで、前記入力信号の高周波帯域を補償した出力信号を生成するミキサと
     を備えたことを特徴とするバースト等化増幅器。
    A level detector for detecting the signal amplitude level of the input signal;
    Based on the signal amplitude level detected by the level detector, the amount of amplification in a specific frequency band is adjusted, and an amplifier with an equalizing function for outputting a first amplified signal;
    An amplifier that amplifies the amplitude of the input signal to a desired amplitude based on the signal amplitude level detected by the level detector and outputs a second amplified signal;
    By mixing the first amplified signal output from the amplifier with the equalizing function and the second amplified signal output from the amplifier, an output signal that compensates for the high frequency band of the input signal is generated. A burst equalizing amplifier characterized by comprising:
  2.  請求項1に記載のバースト等化増幅器において、
     前記等化機能付き増幅器は、差動増幅器を有して構成され、前記差動増幅器の負荷として抵抗およびインダクタを適用することで前記特性周波数帯の増幅量の調整を可能とし、前記レベル検出器で検出された前記信号振幅レベルに基づいて前記差動増幅器の電流量を調整することで前記第1の増幅信号を出力する
     ことを特徴とするバースト等化増幅器。
    The burst equalization amplifier according to claim 1,
    The amplifier with equalization function is configured to include a differential amplifier, and can adjust the amplification amount of the characteristic frequency band by applying a resistor and an inductor as a load of the differential amplifier, and the level detector A burst equalizing amplifier characterized in that the first amplified signal is output by adjusting a current amount of the differential amplifier based on the signal amplitude level detected in step (1).
  3.  請求項1に記載のバースト等化増幅器において、
     前記等化機能付き増幅器は、差動増幅器を有して構成され、前記差動増幅器の負荷として抵抗およびインダクタを適用することで前記特性周波数帯の増幅量の調整を可能とし、前記レベル検出器で検出された前記信号振幅レベルに基づいて前記差動増幅器のそれぞれの差動トランジスタに付加したエミッタ抵抗の抵抗値を調整することで前記第1の増幅信号を出力する
     ことを特徴とするバースト等化増幅器。
    The burst equalization amplifier according to claim 1,
    The amplifier with equalization function is configured to include a differential amplifier, and can adjust the amplification amount of the characteristic frequency band by applying a resistor and an inductor as a load of the differential amplifier, and the level detector The first amplified signal is output by adjusting a resistance value of an emitter resistor added to each differential transistor of the differential amplifier based on the signal amplitude level detected in step B. Amplifier.
  4.  請求項1ないし3のいずれか1項に記載のバースト等化増幅器において、
     前記レベル検出器は、ピーク検波回路およびボトム検波回路を有して構成され、前記信号振幅レベルを検出する
     ことを特徴とするバースト等化増幅器。
    The burst equalizing amplifier according to any one of claims 1 to 3,
    The level detector is configured to have a peak detection circuit and a bottom detection circuit, and detects the signal amplitude level.
  5.  請求項2項に記載のバースト等化増幅器において、
     前記等化機能付き増幅器は、前記レベル検出器で検出された前記信号振幅レベルに相当する出力電圧と基準電圧との比較結果に基づいて前記差動増幅器の電流量を調整するヒステリシスコンパレータを有する
     ことを特徴とするバースト等化増幅器。
    The burst equalization amplifier according to claim 2,
    The amplifier with equalization function includes a hysteresis comparator that adjusts the amount of current of the differential amplifier based on a comparison result between an output voltage corresponding to the signal amplitude level detected by the level detector and a reference voltage. A burst equalizing amplifier characterized by the following.
  6.  請求項3に記載のバースト等化増幅器において、
     前記等化機能付き増幅器は、前記レベル検出器で検出された前記信号振幅レベルに相当する出力電圧と基準電圧との比較結果に基づいて前記エミッタ抵抗の抵抗値を調整するヒステリシスコンパレータを有する
     ことを特徴とするバースト等化増幅器。
    The burst equalization amplifier according to claim 3,
    The amplifier with equalization function includes a hysteresis comparator that adjusts a resistance value of the emitter resistor based on a comparison result between an output voltage corresponding to the signal amplitude level detected by the level detector and a reference voltage. Features a burst equalization amplifier.
  7.  請求項5に記載のバースト等化増幅器において、
     前記ヒステリシスコンパレータは、複数のヒステリシスコンパレータで構成され、前記レベル検出器で検出された前記信号振幅レベルに相当する出力電圧と、前記複数のヒステリシスコンパレータのそれぞれに対応する複数の基準電圧との比較結果に基づいて前記差動増幅器の電流量を多段階に調整する
     ことを特徴とするバースト等化増幅器。
    The burst equalization amplifier according to claim 5,
    The hysteresis comparator includes a plurality of hysteresis comparators, and a comparison result between an output voltage corresponding to the signal amplitude level detected by the level detector and a plurality of reference voltages corresponding to each of the plurality of hysteresis comparators. A burst equalizing amplifier characterized in that the amount of current of the differential amplifier is adjusted in multiple stages based on the above.
  8.  請求項6に記載のバースト等化増幅器において、
     前記ヒステリシスコンパレータは、複数のヒステリシスコンパレータで構成され、前記レベル検出器で検出された前記信号振幅レベルに相当する出力電圧と、前記複数のヒステリシスコンパレータのそれぞれに対応する複数の基準電圧との比較結果に基づいて前記エミッタ抵抗の抵抗値を多段階に調整する
     ことを特徴とするバースト等化増幅器。
    The burst equalization amplifier according to claim 6,
    The hysteresis comparator includes a plurality of hysteresis comparators, and a comparison result between an output voltage corresponding to the signal amplitude level detected by the level detector and a plurality of reference voltages corresponding to each of the plurality of hysteresis comparators. A burst equalizing amplifier characterized in that the resistance value of the emitter resistor is adjusted in multiple stages based on the above.
  9.  請求項1ないし3のいずれか1項に記載のバースト等化増幅器において、
     前記レベル検出器は、前記入力信号の振幅の平均値を前記信号振幅レベルとして検出する平均値検出回路を有して構成され、前記信号振幅レベルを検出し、
     前記等化機能付き増幅器は、外部から入力されるオフレベルの信号電圧と、前記平均値検出回路で検出された前記信号振幅レベルに対応した出力信号電圧との差分に基づいて前記第2の増幅信号を出力することで前記特定周波数帯の増幅量を調整する
     ことを特徴とするバースト等化増幅器。
    The burst equalizing amplifier according to any one of claims 1 to 3,
    The level detector includes an average value detection circuit that detects an average value of the amplitude of the input signal as the signal amplitude level, and detects the signal amplitude level.
    The amplifier with equalization function is configured to perform the second amplification based on a difference between an off-level signal voltage input from the outside and an output signal voltage corresponding to the signal amplitude level detected by the average value detection circuit. A burst equalization amplifier characterized by adjusting an amplification amount of the specific frequency band by outputting a signal.
PCT/JP2010/060279 2010-06-17 2010-06-17 Burst-mode transimpedance amplifier WO2011158360A1 (en)

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JP2004032002A (en) * 2002-06-21 2004-01-29 Matsushita Electric Ind Co Ltd Amplifier
JP2004186842A (en) * 2002-12-02 2004-07-02 Nec Engineering Ltd Differential amplifier circuit
JP2008236455A (en) * 2007-03-22 2008-10-02 Nippon Telegr & Teleph Corp <Ntt> Transimpedance amplifier and control method of transimpedance amplifier

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Publication number Priority date Publication date Assignee Title
JPS63175510A (en) * 1987-01-16 1988-07-19 Hitachi Ltd Semiconductor circuit
JPH0983270A (en) * 1995-09-13 1997-03-28 Nec Corp Band split amplifier circuit
JP2003152649A (en) * 2001-11-16 2003-05-23 Sony Corp Optical receiver
JP2004032002A (en) * 2002-06-21 2004-01-29 Matsushita Electric Ind Co Ltd Amplifier
JP2004186842A (en) * 2002-12-02 2004-07-02 Nec Engineering Ltd Differential amplifier circuit
JP2008236455A (en) * 2007-03-22 2008-10-02 Nippon Telegr & Teleph Corp <Ntt> Transimpedance amplifier and control method of transimpedance amplifier

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