WO2011021411A1

WO2011021411A1 - Esd protection device

Info

Publication number: WO2011021411A1
Application number: PCT/JP2010/057859
Authority: WO
Inventors: 山田浩輔; 野間隆嗣
Original assignee: 株式会社村田製作所
Priority date: 2009-08-21
Filing date: 2010-05-10
Publication date: 2011-02-24
Also published as: TW201138052A

Abstract

Disclosed is an ESD protection device which can reliably perform ESD protection, while sufficiently ensuring an attenuation at a desired frequency. The ESD protection device is provided with a configuration wherein a resistor (R) and an LC parallel resonance circuit (1) are connected in series on a signal line. Both the ends of the series circuit of the resistor (R) and the LC parallel resonance circuit (1) are connected to the ground by means of ESD elements (ESD1, ESD2). In such circuit configuration, when a signal line has a surge of static electricity, the ESD elements (ESD1, ESD2) are in the ON-state, and static electricity is discharged to the ground. When the ESD elements (ESD1, ESD2) are in the OFF-state, the ESD protection device functions as a lowpass filter, which is composed of a π-type C-R-LC-C connection and has an attenuation pole with respect to the desired frequency.

Description

ESD protection device

This invention relates to an electrostatic protection device (ESD protection device) for protecting a semiconductor IC or the like from static electricity.

Currently, various electronic devices such as semiconductor integrated ICs are mounted on portable terminals and the like. In such a terminal, an electrostatic protection device (ESD (Electro Static Discharge) device) that protects the electronic device from static electricity is mounted.

Such an ESD protection device includes a π-type ESD protection circuit 10P ′ as shown in FIG. 12A and a T-type ESD protection circuit 10T ′ as shown in FIG. FIG. 12 is an equivalent circuit diagram showing an example of a conventional ESD protection circuit. FIGS. 12A and 12C are circuit diagrams of the respective ESD protection circuits. FIGS. 12B and 12D are ESD diagrams. It is an equivalent circuit diagram in the state where an element is OFF. 12A and 12B show a π-type ESD protection circuit, and FIGS. 12C and 12D show a T-type ESD protection circuit.

The π-type ESD protection circuit 10P ′ shown in FIG. 12A includes a resistor R and two ESD elements ESD1 and ESD2. The resistor R is inserted in a signal line between the input port Pi and the output port Po. Each of the two ESD elements ESD1, ESD2 has one end connected to both ends of the resistor R and the other end connected to the ground. This π-type ESD protection circuit is also described in Patent Document 1.

The T-type ESD protection circuit 10T ′ shown in FIG. 12C includes two resistors R connected in series and an ESD element ESD. Two resistors R connected in series are inserted in a signal line between the input port Pi and the output port Po. The ESD element ESD has one end connected to the connection point of the two resistors R and the other end connected to the ground.

JP 2005-354014 A

By the way, the π-type ESD protection circuit 10P ′ as shown in FIG. 12A and the T-type ESD protection circuit 10T ′ as shown in FIG. 12C function as the capacitor Cv when the ESD element is OFF. To do. Accordingly, the π-type ESD protection circuit 10P ′ shown in FIG. 12A functions as a CR-C type low pulse filter shown in FIG. 12B, and the T-type ESD protection shown in FIG. The circuit 10T ′ functions as an RCR type low pulse filter shown in FIG.

However, such a low-pass filter including the π-type ESD protection circuit 10P ′ and the T-type ESD protection circuit 10T ′ has a characteristic that the amount of attenuation increases monotonously at the high band end of the pass band. Therefore, for example, when high-frequency noise exists at a frequency with a small attenuation at the high end of the pass band, the high-frequency noise cannot be attenuated.

An object of the present invention is to realize an ESD protection device that can reliably perform ESD protection while sufficiently securing an attenuation amount of a desired frequency.

(1) An ESD protection device according to the present invention includes a resistor inserted in a signal line, two ESD elements for connecting both ends of the resistor and the ground, and a resistor connected in series on the signal line. An LC parallel resonator.

In this configuration, a resistor and two ESD elements constitute a π-type ESD protection circuit having an ESD protection function and a low-pass filter function. And the attenuation pole at the time of functioning as a low-pass filter is formed by LC parallel resonator. Here, if the resonance frequency of the LC parallel resonator is set to the frequency of the high frequency noise to be removed, an attenuation pole is formed at the frequency, and the high frequency noise is greatly attenuated. Further, even if the LC parallel resonator is inserted into the signal line, the line capacitance does not change, so that there is almost no influence on the transmission characteristics other than the formation of the attenuation pole.

(2) Further, the LC parallel resonator of the ESD protection device of the present invention is connected between one end of the resistor in the signal line and the ESD element connected to the one end.

In this configuration, the LC parallel resonator is arranged in the middle of two connection points where the two ESD elements are respectively connected to the signal line. Thereby, even if static electricity is superimposed from any direction of the signal line, it is discharged to the ground by the ESD element, and static electricity is not surged to the LC parallel resonator. Thereby, destruction of the capacitor of the LC parallel resonator can be prevented together with the normal ESD protection function. In particular, when the inductor of the LC parallel resonator is formed with a spiral electrode described later, the resistance component of the inductor increases and current flows easily through the capacitor. Therefore, using this structure can prevent electrostatic breakdown of the capacitor. It is valid.

(3) Further, the ESD protection device of the present invention connects two resistors inserted in a signal line and connected in series with each other, and a connection point between the two resistors connected in series and the ground. An ESD element, and an LC parallel resonator connected in series to a signal line between one of the resistors and the connection point.

In this configuration, a T-type ESD protection circuit having an ESD protection function and a low-pass filter function is configured by two resistors and an ESD element. And the attenuation pole at the time of functioning as a low-pass filter is formed by LC parallel resonator. Here, if the resonance frequency of the LC parallel resonator is set to the frequency of the high frequency noise to be removed, an attenuation pole is formed at the frequency, and the high frequency noise is greatly attenuated. Further, even if the LC parallel resonator is inserted into the signal line, the line capacitance does not change, so that there is almost no influence on the transmission characteristics other than the formation of the attenuation pole.

(4) Further, the inductor constituting the LC parallel resonator of the ESD protection device of the present invention comprises a conductive pattern formed on a silicon substrate on which a signal line is formed.

This configuration shows a specific method for forming an inductor of an LC parallel resonator, and can be formed integrally with a signal line by being formed on a silicon substrate. Further, by using the silicon substrate, it is possible to collectively form the capacitor of the LC parallel resonance circuit, the resistor R and the ESD element of the ESD protection device.

(5) The inductor of the ESD protection device according to the present invention includes a conductive pattern of a redistribution layer separated from a conductive pattern of a silicon substrate, a conductive pattern on the redistribution layer, and a silicon substrate. And a via hole that conducts the conductive pattern.

In this configuration, the inductor is formed of the conductive pattern on the surface of the silicon substrate and the conductive pattern of the rewiring layer formed at a position spaced apart from the conductive pattern on the surface of the silicon substrate. And since these are electrically connected by a via hole, an inductor is formed by the electrode over a plurality of layers. As a result, it is possible to make the electrode length of the inductor longer than that of the single layer structure, and a high inductance can be realized. As a result, the Q value of the LC parallel resonator can be increased, and a steeper attenuation pole can be realized.

(6) Further, the inductor of the ESD protection device of the present invention further includes a conductive pattern of at least one redistribution layer and a via hole that connects the conductive patterns of each redistribution layer.

In this configuration, a higher inductance can be realized by further increasing the conductive pattern of the rewiring layer and connecting the conductive pattern on the silicon substrate and the conductive pattern of each rewiring layer. Thereby, the Q value of the LC parallel resonator can be further increased, and a steeper attenuation pole can be realized.

(7) Further, the conductive pattern of the rewiring layer of the ESD protection device of the present invention has a thicker electrode than the conductive pattern on the silicon substrate.

In this configuration, it is possible to suppress an increase in resistance value by increasing the thickness of the rewiring layer while using a conductive pattern of the rewiring layer to increase the inductor length and improve the inductance. Thereby, the Q value of the LC parallel resonator can be made steeper, and a steeper attenuation pole can be realized.

(8) Further, the conductive pattern of the rewiring layer of the ESD protection device of the present invention is formed of a material having higher conductivity than the conductive pattern on the silicon substrate.

In this configuration, the conductive pattern of the rewiring layer is used to increase the inductance of the inductor by increasing the electrode length of the inductor, but the rewiring layer has a high conductivity to further suppress an increase in resistance value. Can do. Thereby, the Q value of the LC parallel resonator can be made steeper, and a steeper attenuation pole can be realized.

(9) Further, the conductive pattern on the silicon substrate of the ESD protection device of the present invention comprises a spiral electrode.

This configuration shows a case where a spiral electrode is used as an example of a conductive pattern inductor formation pattern. By using such a spiral electrode, the inductance can be made higher than that of the meander electrode having the same area. Thereby, the Q value of the LC parallel resonator can be increased, and a steeper attenuation pole can be realized.

(10) Further, the conductive pattern on the silicon substrate of the ESD protection device of the present invention and the conductive pattern of the redistribution layer have substantially the same shape and the same direction in the same region in a plan view of the silicon substrate. It consists of a spiral electrode wound around.

In this configuration, all the spiral electrodes formed in each layer are wound and connected in the same direction, so that an inductor having a larger number of turns can be realized than when the spiral electrode is formed only on the silicon substrate. Thereby, an inductance can be made high. Furthermore, the winding surfaces of the spiral electrodes of each layer, that is, the conductive patterns are close to each other and the spiral electrodes are magnetically coupled to each other, thereby generating mutual inductance and further increasing the inductance. As a result, the Q value of the LC parallel resonator can be further increased, and a steeper attenuation pole can be realized.

(11) Further, the ESD protection device of the present invention further includes a capacitor having one end connected to the signal line between the resistor and the LC parallel resonator and the other end connected to the ground.

In this configuration, since the ESD protection device is composed of a plurality of resonance circuits, it is possible to make the attenuation pole have a steeper characteristic.

(12) Further, in the ESD protection device of the present invention, the capacitor includes a third ESD element different from the two ESD elements.

This configuration shows a specific example of capacitor formation.

(13) Further, in the ESD protection device of the present invention, the resistor includes two partial resistors, and the two partial resistors are respectively connected to the two ESD elements from one end of the third ESD element. Individually connected on the signal line.

In this configuration, the ESD that flows into the third ESD element can be lowered by the partial resistor, and the destruction of the third ESD element can be prevented.

(14) In the ESD protection device of the present invention, the capacitor is separated from the conductive pattern formed on the silicon substrate on which the signal line is formed and the conductive pattern formed on the silicon substrate. And a conductive pattern of the rewiring layer.

This configuration shows a specific structure when the capacitor is not formed by an ESD element.

(15) In the ESD protection device of the present invention, the conductive pattern formed on the silicon substrate forming the capacitor also serves as the conductive pattern constituting the inductor of the LC parallel resonator.

This configuration also shows the specific structure of the capacitor. With such a structure, connection electrodes such as via holes for connecting the electrode pattern constituting the inductor of the LC parallel resonator on the Si substrate to the rewiring layer and the outside can be omitted, and the structure can be simplified.

According to the present invention, it is possible to realize an ESD protection device that forms an attenuation pole at the frequency of the high-frequency noise to be removed, can sufficiently attenuate the high-frequency noise, and can reliably perform ESD protection.

FIG. 4 is a circuit diagram of a π-type ESD protection circuit of the ESD protection device according to the present embodiment and an equivalent circuit diagram when an ESD element is in an OFF state. It is a passage characteristic figure of the ESD protection device concerning this embodiment, and the conventional ESD protection device. FIG. 4 is a circuit diagram of a T-type ESD protection circuit of the ESD protection device according to the present embodiment and an equivalent circuit diagram when an ESD element is in an OFF state. It is side surface sectional drawing for demonstrating the structure of the ESD protection device of this embodiment. It is the external appearance perspective view which shows the structure of the inductor Lr typically, and its exploded perspective view. FIG. 6 is a plan view and a side sectional view of the second spiral electrode 21B of the redistribution layer constituting the inductor Lr, and a plan view and a side sectional view of the first spiral electrode 21A formed on the surface of the Si substrate 20A. It is a passage characteristic diagram which shows the influence on the passage characteristic according to the number of spiral electrodes. It is a disassembled perspective view which shows typically the other structure of the inductor Lr. It is the circuit diagram of the ESD protection device which consists of another structure of this invention, and an equivalent circuit diagram in the state where an ESD element is OFF. It is a figure showing the passage characteristic of the ESD protection device which consists of a circuit of FIG. It is a circuit diagram of the ESD protection device which consists of other composition of the present invention. FIG. 6 is a circuit diagram of a conventional ESD protection circuit and an equivalent circuit diagram when an ESD element is in an OFF state.

An ESD protection device according to an embodiment of the present invention will be described with reference to the drawings. In the following circuit description, the input port Pi and the output port Po are described for convenience of description, and the circuit configuration of the present embodiment is applied even when there is no input port, that is, only a signal line. Can do.
(1) In the case of the π-type ESD protection circuit 10P FIG. 1A is a circuit diagram of the π-type ESD protection circuit 10P, and FIG. A circuit diagram is shown.

In the π-type ESD protection circuit 10P, a resistor R is connected between a predetermined position of the signal line, that is, the input port Pi and the output port Po of the signal line in FIG. One end of the resistor R is connected to one end of the ESD element ESD1, and the other end of the ESD element ESD1 is connected to the ground. One end of the ESD element ESD2 is connected to the other end of the resistor R via the LC parallel resonant circuit 1, and the other end of the ESD element ESD2 is connected to the ground.

The LC parallel resonator 1 includes a parallel circuit of an inductor Lr and a capacitor Cr, and is connected in series with a resistor R on a signal line. At this time, the LC parallel resonant circuit 1 is connected so as to be inserted between the end of the resistor R on the ESD element ESD2 side and the connection point where the ESD element ESD2 is connected to the signal line.

In the π-type ESD protection circuit 10P having such a circuit configuration, unless static electricity is superimposed on the signal line, the ESD elements ESD1 and ESD2 are turned off, and the ESD elements ESD1 and ESD2 each function as a capacitor Cv. Therefore, when the ESD elements ESD1 and ESD2 are in the OFF state, as shown in FIG. 1B, the π-type ESD protection circuit 10P includes the resistor R and the LC parallel resonant circuit 1 connected in series on the signal line. Both ends of the series circuit are connected to the ground by the capacitor Cv. As a result, the π-type ESD protection circuit 10P functions as a CR-LC-R type low-pass filter.

2 shows the pass characteristics of the π-type ESD protection circuit 10P of this embodiment and the conventional π-type ESD protection circuit 10P ′ shown in FIG. 12, and the T-type ESD protection circuit 10T of this embodiment shown in FIG. It is a figure which shows the passage characteristic of the conventional T type ESD protection circuit 10T 'shown in FIG.

Since the conventional π-type ESD protection circuit 10P ′ functions as a C—R—C type low-pass filter, as shown by a thick broken line in FIG. Characteristic that the passing amount decreases). However, the π-type ESD protection circuit 10P according to the present embodiment includes the LC parallel resonance circuit 1, and thus can provide an attenuation pole on the high band side of the pass band. Therefore, by setting the frequency of the attenuation pole to the desired high frequency noise frequency, the high frequency noise can be significantly attenuated. Then, the LC parallel resonant circuit 1 is connected in series to the signal line as in this embodiment, thereby forming the attenuation pole without changing the line capacitance, that is, the capacitance between the signal line and the ground. be able to. Thereby, generation | occurrence | production of the distortion of the signal which transmits the said (pi) -type ESD protection circuit 10P can be suppressed.

On the other hand, when static electricity is superimposed on the signal line from the input port Pi or the output port Po, the ESD elements ESD1 and ESD2 are turned on, and current flows from the signal line to the ground, so that the static electricity is discharged to the ground. .

Specifically, when static electricity is superimposed on the signal line from the input port Pi, the ESD element ESD1 first shifts to the ON state and is discharged through the ESD element ESD1. On the other hand, when static electricity is superimposed on the signal line from the output port Po, the ESD element ESD2 first shifts to the ON state and is discharged through the ESD element ESD2. Thereby, the π-type ESD protection circuit 10P functions as an ESD protection circuit.

As shown in FIG. 1A, the LC parallel resonant circuit 1 is arranged between the connection points of the two ESD elements ESD1 and ESD2 to the signal line, so that static electricity from the input port Pi is also output to the output port. Since static electricity from Po is also discharged by the ESD elements ESD1 and ESD2, static electricity is not superimposed on the LC parallel resonant circuit 1. Therefore, the capacitor Cr of the LC parallel resonant circuit 1 can also be protected from static electricity. In particular, as will be described later, when the inductor Lr of the LC parallel resonant circuit 1 is formed of a spiral electrode, the electrode length becomes long to obtain a large inductance, and the resistance component of the inductor Lr increases. In this case, when static electricity is surged into the LC parallel resonant circuit 1, a large current flows through the capacitor, and the capacitor is easily destroyed. Therefore, the above-described configuration is more effective for the destruction of the capacitor when the spiral electrode is used.

The LC parallel resonant circuit 1 is not limited to the configuration in which the two ESD elements ESD1 and ESD2 are arranged between the connection points to the signal line, but on the input port Pi side from the ESD element ESD1 in the signal line or in the signal line. You may arrange | position to the output port Po side rather than ESD element ESD2. In this case, if the LC parallel resonance circuit 1 is arranged on the input port Pi side, the destruction of the capacitor Cr of the LC parallel resonance circuit 1 due to static electricity from the output port Po can be prevented, and the LC parallel resonance circuit 1 is arranged on the output port Po side. This can prevent destruction of the capacitor Cr of the LC parallel resonant circuit 1 due to static electricity from the input port Pi.

(2) Case of T-type ESD Protection Circuit 10T FIG. 3A is a circuit diagram of the T-type ESD protection circuit 10T, and FIG. 3B is an equivalent circuit diagram of the ESD element ESD in the T-type ESD protection circuit 10T in an OFF state. Indicates.

In the T-type ESD protection circuit 10T, two resistors R and the LC parallel resonance circuit 1 are connected in series between predetermined positions of the signal line, that is, between the input port Pi and the output port Po of the signal line. For example, in the case of FIG. 3A, the resistor R, the LC parallel resonant circuit 1, and the resistor R are connected in this order from the input port Pi side to the output port Po side.

The one end of the ESD element ESD is connected to the connection point between the resistor R on the input port Pi side and the LC resonance circuit 1, and the other end of the ESD element ESD is connected to the ground.

In the T-type ESD protection circuit 10T having such a circuit configuration, unless static electricity is superimposed on the signal line, the ESD element ESD is turned off and functions as the capacitor Cv. Therefore, when the ESD element ESD is in the OFF state, as shown in FIG. 3B, the T-type ESD protection circuit 10T includes two resistors R and the LC parallel resonant circuit 1 connected in series on the signal line. A connection point between one resistor R of the series circuit and the LC parallel resonance circuit 1 is connected to the ground by a capacitor Cv. Thus, the T-type ESD protection circuit 10T functions as an RCLC-R-type low-pass filter.

Here, since the conventional T-type ESD protection circuit 10T ′ functions as an RCR type low-pass filter, the attenuation increases monotonously on the high band side of the passband as shown by the thin broken line in FIG. Characteristic (characteristic that the passing amount decreases). However, the T-type ESD protection circuit 10T according to the present embodiment includes the LC parallel resonance circuit 1, and thus can provide an attenuation pole on the high band side of the pass band. Therefore, similarly to the above-described π-type ESD protection circuit 10P, the high frequency noise can be greatly attenuated by setting the frequency of the attenuation pole to a desired frequency of the high frequency noise. Then, the LC parallel resonant circuit 1 is connected in series to the signal line as in this embodiment, thereby forming the attenuation pole without changing the line capacitance, that is, the capacitance between the signal line and the ground. be able to. Thereby, generation | occurrence | production of the distortion of the signal which transmits the said T type ESD protection circuit 10T can be suppressed.

On the other hand, when static electricity is superimposed on the signal line from the input port Pi or the output port Po, the ESD element ESD changes to the ON state, and current flows from the signal line to the ground, so that the static electricity is discharged to the ground. Thereby, the T-type ESD protection circuit 10T functions as an ESD protection circuit.

The connection relationship between the two resistors R, the ESD element ESD, and the LC parallel resonance circuit 1 shown in FIG. 3 is an example. As a basic configuration, two resistors R are provided on the signal line. The LC parallel resonance circuit 1 is further connected in series on the signal line, and the predetermined position between the two resistors R in the signal line is connected to the ground via the ESD element ESD. I just need it.

Thus, by using the circuit configuration in which the LC parallel resonant circuit is inserted into the signal line of the ESD protection circuit, the ESD protection can be surely functioned and also function as a low-pass filter having an attenuation pole at a desired frequency. it can. That is, it is possible to realize an ESD protection device that allows a signal having a desired frequency to pass therethrough with low loss, reliably removes desired high-frequency noise, and performs ESD protection.

Next, the structure of such an ESD protection device will be described with reference to the drawings.
FIG. 4 is a side sectional view for explaining a schematic structure of the ESD protection device of the present embodiment. FIG. 4 shows circuit portions of the ESD element ESD1, the resistor R, and the inductor Lr of the LC parallel resonance circuit of the π-type ESD protection circuit 10P described above.

In the following, a case where a p-type Si substrate 20A is used will be described as an example, but the following structure can be applied even to an n-type Si substrate.

The ESD protection device 10 of this embodiment is made of a so-called CSP (Chip Size Package) and includes a Si substrate 20A doped with p-type impurities. A predetermined position of one surface (the lower surface in FIG. 4) of the p-type Si substrate 20 is n-type doped in a predetermined area range at a predetermined depth from the one surface. Further, a P well layer is formed so as to surround a specific pair of n type doping layer n + (two n type doping layers n + near the left end in FIG. 4) in the p type Si substrate 20A. The P well layer is a layer in which the p-type impurity concentration is increased with respect to the Si substrate 20A. With this structure, the boundary between the p-type region (P well layer) and the n-type region can function as a diode or a capacitor, or the n-type region can function as a resistor. The P well layer is not necessarily formed, but it is desirable to form it.

The contact layer 200 and the conductive pattern 201 are sequentially formed on the surface of the partially n-type doped p-type Si substrate 20A from the surface side. The conductive pattern 201 is realized by vapor deposition of a metal material such as Al (aluminum).

The contact layer 200 and the conductive pattern 201 are patterned so as to realize a desired circuit configuration.

For example, the contact layer 200 and the conductive pattern 201 in the region where the ESD element ESD1 is formed are patterned on the surfaces of two n-type doping layers n + formed at a predetermined interval. Thereby, in this region, it is possible to realize a circuit configuration in which two diodes are connected in series in a state in which the forward directions do not match, and the ESD element ESD1 is realized.

More specifically, one pn junction is realized by one n-type doping layer n + and the P well, and another pn junction is realized by the other n-type doping layer n + and the P well. Is done. At this time, since the P-well is interposed between the two n-type doping layers n +, the structure is equivalent to a circuit in which two diodes are connected so that the forward directions are opposite to each other. Therefore, a diode having a predetermined threshold voltage positive and negative can be realized, and can function as an ESD protection circuit. That is, if the threshold voltage Vt is set higher than the voltage during normal operation, the diode is normally turned off (not turned on), and when static electricity exceeding the threshold voltage Vt is superimposed, the diode Becomes an ON state and functions as an ESD protection circuit that releases energy to the ground.

In addition, the contact layer 200 and the conductive pattern 201 in the region where the resistor R is formed are patterned in two predetermined area ranges on both ends of the n-type doping layer n +. Thereby, the resistor R using the resistance component of the n-type doping layer n + is realized. In the description of the present embodiment, the resistor R is realized by using the n-type doping layer n +, but the p-type doping layer p + surrounded by the N well is formed on the Si substrate 20A, and the p The resistor R may be formed of the type doping layer p +.

Further, the contact layer 200 and the conductive pattern 201 in the region where the inductor Lr is formed are patterned in a spiral shape having a predetermined number of turns and a predetermined electrode width. Thereby, the first spiral electrode 21A formed on the Si substrate 20A is realized.

The surface of the contact layer 200, the conductive pattern 201, and the Si substrate 20A on which the pattern is not formed is covered with the insulating passivation layer 20Bp except for the region where the UBM 40 is formed. It has been broken. And UBM40 is formed in the position which this passivation layer 20Bp opened.

Further, a rewiring layer made of a conductive pattern 202 having a predetermined pattern is formed so as to be connected to the UBM 40. Thereby, the UBM 40 functions as a via hole that electrically connects the conductive pattern 201 on the surface of the Si substrate 20A and the conductive pattern 202 constituting the rewiring layer.

The conductive pattern 202 of the rewiring layer has an electrode pattern that bridges the UBM 40 and the solder bump 50 that is an external connection bump as a CSP, and an electrode pattern that forms the second spiral electrode 21B. Here, the electrode pattern that bridges the UBM 40 and the solder bump 50 is formed so as to extend in a predetermined pattern from the position where the UBM 40 is formed to the position where the solder bump 50 is formed, as shown in the vicinity of the left end of FIG. On the other hand, the electrode pattern that forms the second spiral electrode 21B has the same winding direction as the electrode pattern that forms the first spiral electrode 21A on the surface of the Si substrate 20A when the ESD protection device 10, that is, the Si substrate 20A is viewed in plan. Moreover, they have substantially the same shape and are formed in overlapping regions. The first spiral electrode 21A and the second spiral electrode 21B are connected by a via hole made of UBM40. Thereby, an inductor Lr composed of the first spiral electrode 21A and the second spiral electrode 21B is realized.

The conductive pattern 202 of the rewiring layer is formed of a metal electrode such as a Cu electrode that is thicker than the conductive pattern 201 on the Si substrate 20A. Thereby, the resistance component of the second spiral electrode 21B can be lowered.

Further, an insulating protective layer 20Bi is formed so as to cover the conductive pattern 202 and the passivation layer 20Bp of the rewiring layer except for the solder bump formation position. This protective layer 20Bi is formed of polyimide, for example.

As described above, the ESD element ESD1, the resistor R, and the inductor Lr of the LC parallel resonant circuit 1 are formed, and the ESD element ESD2 and the capacitor Cr of the LC parallel resonant circuit 1 are formed in the same structure as the ESD element ESD1. Then, the ESD protection device 10 of this embodiment can be realized by CSP by appropriately patterning the conductive pattern 201 on the surface of the Si substrate 20A, the conductive pattern 202 of the rewiring layer, the UBM 40, and the solder bump 50. .

Next, the structure of the inductor Lr of the LC parallel resonant circuit 1 will be described in more detail with reference to the drawings. FIG. 5A is an external perspective view schematically showing the structure of the inductor Lr, and FIG. 5B is an exploded perspective view thereof. 6A is a plan view of the second spiral electrode 21B of the rewiring layer, and FIG. 6B is a side sectional view thereof. FIG. 6C is a plan view of the first spiral electrode 21A formed on the surface of the Si substrate 20A, and FIG. 6D is a side sectional view thereof. Note that the insulating material layer 20B in FIGS. 5 and 6 corresponds to the passivation layer 20Bp and the protective layer 20Bi shown in FIG. 4 described above, and is shown in the form of a substrate in order to clarify the structure. is doing.

As shown in FIG. 5, the inductor Lr of the LC parallel resonant circuit 1 includes a first spiral electrode 21A composed of a conductive pattern 201 formed in a wound shape on a Si substrate 20A, and a distance from the first spiral electrode 21A. The second spiral electrode 21 </ b> B made of the conductive pattern 202 that is also formed in a wound shape is provided at the position.

At this time, the first spiral electrode 21A and the second spiral electrode 21B are formed in substantially the same region in a plan view. The central opening regions of the first spiral electrode 21A and the second spiral electrode 21B are also formed so as to substantially coincide with each other.

The outer peripheral end of the first spiral electrode 21A is connected to a lead-out electrode 31 made of the conductive pattern 201 that is also formed on the Si substrate 20A. The first spiral electrode 21A is wound counterclockwise so that the diameter gradually decreases from the outer peripheral end to the inner peripheral end and in a plan view as shown in FIGS. 6 (C) and 6 (D). It is formed to turn. As shown in FIG. 6B, the inner peripheral end of the first spiral electrode 21A is connected to the inner peripheral end of the second spiral electrode 21B by a via hole 41 made of UBM 40.

The second spiral electrode 21B has a shape having substantially the same electrode width as that of the first spiral electrode 21A, and gradually increases in diameter from the inner peripheral end to the outer peripheral end. ), The electrode is formed to be wound counterclockwise in a plan view. As shown in FIGS. 5 and 6B, the outer peripheral end of the second spiral electrode 21B is connected to the lead-out electrode 32 made of the conductive pattern 201 on the Si substrate 20A by a conductive via hole.

With such a structure, the first spiral electrode 21A and the second spiral electrode 21B are formed as a spiral electrode having a two-layer structure in which they are connected so that their winding directions coincide with each other. Thereby, the directions of the magnetic fields generated by the first spiral electrode 21A and the second spiral electrode 21B coincide. And since the electrode surfaces of the first spiral electrode 21A and the second spiral electrode 21B are close to each other, these magnetic fields are coupled, strong magnetic coupling is obtained, and a large mutual inductance can be generated. As a result, the inductance of the inductor Lr composed of the first spiral electrode 21A and the second spiral electrode 21B can be increased. Therefore, the Q value of resonance of the LC parallel resonant circuit 1 using the inductor Lr can be increased, and the attenuation pole when the ESD protection device functions as a low-pass filter can be a steep characteristic pole. Therefore, desired high frequency noise can be effectively removed.

Furthermore, the second spiral electrode 21B uses the conductive pattern 202 of the rewiring layer. Here, the conductive pattern 202 of the rewiring layer is formed of Cu or the like as described above. Since Cu has a higher conductivity than Al deposited on the Si substrate 20A, the resistance value of the second spiral electrode 21B can be lowered, and the inductor Lr is formed by the first spiral electrode 21A rather than the entire inductor Lr. While increasing the inductance of Lr, it is possible to suppress an increase in resistance component. Further, the conductive pattern 202 of the rewiring layer can be formed thicker than the conductive pattern 201 made of Al or the like deposited on the Si substrate 20A. As a result, the resistance value of the second spiral electrode 21B can be further lowered, and the resistance component can be further increased while improving the inductance of the inductor Lr than when the entire inductor Lr is formed of the first spiral electrode 21A. Can be suppressed. Also by this, the Q value of the LC parallel resonant circuit 1 including the inductor Lr can be improved, and a steeper attenuation pole can be formed.

FIG. 7 is a pass characteristic diagram showing the influence on the pass characteristic according to the number of spiral electrodes. In FIG. 7, the thick solid line indicates the pass characteristic of the π-type ESD protection circuit 10P when the inductor Lr is configured by the first spiral electrode 21A on the Si substrate 20A, and the thin solid line indicates the first spiral electrode 21A on the Si substrate 21A. The pass characteristics of the T-type ESD protection circuit 10T when the inductor Lr is configured as shown in FIG. A thick broken line indicates a passing characteristic of the π-type ESD protection circuit 10P when the inductor Lr is configured by the first spiral electrode 21A on the Si substrate 20A and the second spiral electrode 21B of the rewiring layer, and the thin broken line indicates the Si substrate 20A. The pass characteristics of the T-type ESD protection circuit 10T when the inductor Lr is composed of the upper first spiral electrode 21A and the second spiral electrode 21B of the rewiring layer are shown.

As shown in FIG. 7, the attenuation pole can be obtained only by forming the first spiral electrode 21A on the Si substrate 20A. Further, by using the above-described two-layer structure of the first spiral electrode 21A and the second spiral electrode 21B, the attenuation amount of the attenuation pole can be further increased and steep characteristics can be obtained.

5 and 6 show an example in which one second spiral electrode 21B is provided by a rewiring layer. However, as shown in FIG. 8, the number of rewiring layers is further increased, and the second spiral electrode 21B is formed on the second spiral electrode 21B. On the other hand, a third spiral electrode 21C may be further formed on the side opposite to the Si substrate 20A. FIG. 8 is an exploded perspective view schematically showing another structure of the inductor Lr.

The first spiral electrode 21A and the second spiral electrode 21B are the same as those shown in FIGS. 5 and 6, and will not be described.

The third spiral electrode 21C has substantially the same electrode width as that of the first spiral electrode 21A and the second spiral electrode 21B, and substantially the same area. The outer peripheral end of the third spiral electrode 21C is connected to the outer peripheral end of the second spiral electrode 21B by a via hole 41 '. The third spiral electrode 21C is formed to be wound counterclockwise in a plan view so that the diameter gradually decreases from the outer peripheral end to the inner peripheral end. That is, the third spiral electrode 21C is formed in the same winding direction as the first spiral electrode 21A and the second spiral electrode 21B.

With such a shape, the length of the electrode as the inductor Lr can be further extended to increase the inductance, and the mutual relationship between the first spiral electrode 21A, the second spiral electrode 21B, and the third spiral electrode 21C can be increased. By the inductance, the inductance as the inductor Lr can be further increased. Thereby, the Q value of the LC parallel resonance circuit 1 can be further increased, and a steeper attenuation pole can be formed. The number of spiral electrodes of the rewiring layer to be formed is not limited to one and two as described above, but may be three or more according to product specifications. At this time, as described above, the winding direction of each spiral electrode coincides, that is, the directions of the generated magnetic fields are the same, and the magnetic fields are strengthened to increase the inductance, The Q value of the LC parallel resonant circuit can be increased.

As described above, by using the circuit configuration and structure of the present embodiment, it is possible to realize an ESD protection device that functions as a low-pass filter having an attenuation pole at a desired frequency when the ESD protection function is not activated. . That is, an ESD protection device that attenuates desired high-frequency noise while discharging a signal (communication signal) in a frequency band to be passed with low loss, and discharges the static electricity to the ground when the static electricity is superimposed on the signal line. Can be realized. At this time, by realizing the ESD protection device by CSP, such a multifunctional and high-performance ESD protection device can be formed in a small size.

In the above description, the π-type ESD protection circuit 10P functioning as a CR-LC-R type low-pass filter has been described as an example. However, the ESD protection circuit 11P having the following configuration may be used. FIG. 9A is a circuit diagram of an ESD protection circuit 11P having the configuration of the present invention, and FIG. 9B is an equivalent circuit diagram when the ESD elements ESD1, ESD2, and ESD3 of the ESD protection circuit 11P are in an OFF state. .

In the ESD protection circuit 11P shown in FIG. 9, the connection point between the resistor R and the LC resonance circuit 1 is further connected to the ground by the ESD element ESD3 with respect to the ESD protection circuit 10P shown in FIG. It has a configuration. With this configuration, three low-pass filters can be configured in the ESD protection circuit 11P. Specifically, a first filter 1A composed of ESD elements ESD1, ESD3 and a resistor R, a second filter 1B composed of ESD elements ESD2, ESD3 and an inductor Lr and a capacitor Cr of the LC resonance circuit 1, The ESD elements ESD1, ESD2, the resistor R, and the third filter 1C including the inductor Lr and the capacitor Cr of the LC resonance circuit 1 are configured.

The first filter 1A has a configuration in which both ends of the resistor R are connected to the ground by ESD elements ESD1 and ESD3, respectively. This circuit is a C—R—C π-type filter when the ESD elements ESD1 and ESD3 are OFF.

The second filter 1B has a configuration in which both ends of the parallel circuit of the inductor Lr and the capacitor Cr are connected to the ground by ESD2 and ESD3, respectively. This circuit is a C-LC-C π-type filter when the ESD elements ESD2 and ESD3 are OFF.

The third filter 1C has a configuration in which both ends of a circuit in which a resistor R and a parallel circuit of an inductor Lr and a capacitor Cr are connected in series are connected to the ground by ESD elements ESD1 and ESD2, respectively. This circuit is a CR-LC-C π-type filter when the ESD elements ESD1 and ESD2 are OFF.

As described above, by adopting a structure including a plurality of low-pass filters and appropriately setting the element value of each element, a steep attenuation pole can be formed on the high-pass side of the low-pass as shown in FIG. FIG. 10 is a diagram showing pass characteristics of an ESD protection device including the circuits of FIGS. As described above, by using the configuration of FIG. 9, an ESD protection device having a superior high-frequency attenuation characteristic can be formed.

Further, as shown in FIG. 11, the configuration of the resistor connected in series between the input port Pi and the output port Po may be changed from the configuration of FIG. 9 described above. FIG. 11 is a circuit diagram of an ESD protection device having still another configuration according to the present invention.

In the ESD protection circuit 12P shown in FIG. 11A, a resistor Rb is connected between one end of the ESD element ESD3 and the LC resonance circuit 1. In the ESD protection circuit 13P shown in FIG. 11B, a resistor Rb is connected between one end of the ESD element ESD3 and one end of the ESD element ESD2. In these cases, the resistance value of the resistor Ra connected between the ESD element ESD1 and the ESD element ESD3 is appropriately adjusted by inserting the resistor Rb. For example, if the resistor R in FIG. 1 has a resistance value of 100Ω, the resistor Ra may be set to 90Ω and the resistor Rb to 10Ω.

In this way, by inserting the resistors Ra and Rb on the input port Pi side and the output port Po side with respect to one end (signal line side) of the ESD element ESD3, either of the input port Pi and the output port Po is selected. Even if ESD from the port is input, it is attenuated to some extent by the resistors Ra and Rb before reaching the ESD element ESD3. Therefore, even if the capacitance of the ESD element ESD3 connected for adjusting the attenuation pole is small, the ESD element ESD3 can be prevented from being destroyed. In other words, even if the ESD element ESD3 is formed in the same configuration as the ESD elements ESD1 and ESD2 without forming the capacitor for adjusting the attenuation pole in a different configuration from the other ESD elements ESD1 and ESD2, The destruction of the ESD element ESD3 can be prevented. Thereby, a highly reliable ESD protection device with excellent attenuation characteristics can be realized.

By the way, as described above, the ESD element ESD3 may be simply constituted by a capacitor. In this case, the capacitor may be formed by an electrode pattern on the surface of the Si substrate and an electrode pattern on the rewiring layer. Thereby, a capacitor for adjusting the attenuation pole can be formed with a simple configuration. Further, the inductor Lr formed on the Si substrate is formed by using the electrode pattern of the inductor Lr formed on the Si substrate as one counter electrode of the capacitor and forming the other counter electrode on the rewiring layer. There is no need to form a connection electrode (such as a conductive via hole) for connecting to the rewiring layer. Thereby, an ESD protection device can be realized with a simpler configuration.

In the above description, an example using a spiral electrode has been shown, but a meander electrode can also be used as the inductor Lr of the LC parallel resonant circuit.

In the above description, the inductor Lr of the LC parallel resonant circuit is formed using the rewiring layer. However, the inductor Lr may be formed only by the conductive pattern on the Si substrate.

Further, even when the inductor Lr of the LC parallel resonant circuit is formed using the rewiring layer, the two spiral electrodes do not necessarily have to be formed in the same shape, the same region, and the same direction. .

In the above description, an example in which the ESD element is realized by a series circuit of diodes has been shown. However, if a Si substrate is used, a Zener diode or FET may be used, or a varistor may be used. Moreover, although the example which implement | achieves an ESD protection device by CSP using Si substrate was shown, the above-mentioned ESD protection circuit is comprised from the resin-type laminated substrate, the pattern electrode formed in the said laminated substrate, and mounting components. May be.

1-LC parallel resonant circuit, 10-ESD protection device, 10P, 10P ′, 11P, 12P, 13P-π type ESD protection circuit, 10T, 10T′-T type ESD protection circuit, 20A-Si substrate, 20B-insulating Material layer, 20Bp-passivation layer, 20Bi-protective layer, 21A-first spiral electrode, 21B-second spiral electrode, 21C-third spiral electrode, 31,32-leading electrode, 40-UBM, 41,41 ', 42-via hole, 50-solder bump, 200-contact layer, 201-conductive pattern, 202-conductive pattern

Claims

A resistor inserted in the signal line;
Two ESD elements connecting both ends of the resistor and the ground, respectively;
An LC parallel resonator connected in series with the resistor on the signal line;
ESD protection device.
The ESD protection device according to claim 1,
The LC parallel resonator is
An ESD protection device connected between one end of the resistor in the signal line and the ESD element connected to the one end.
Two resistors inserted in the signal line and connected in series with each other;
An ESD element for connecting the connection point of the two resistors connected in series and the ground;
An LC parallel resonator connected in series to a signal line between any one of the resistors and the connection point;
ESD protection device.
The ESD protection device according to any one of claims 1 to 3,
The inductor constituting the LC parallel resonator is:
An ESD protection device comprising a conductive pattern formed on a silicon substrate on which the signal line is formed.
The ESD protection device according to claim 4,
The inductor is
A conductive pattern of a redistribution layer spaced from a conductive pattern formed on the silicon substrate;
An ESD protection device further comprising: a conductive pattern of the rewiring layer; and a via hole that conducts the conductive pattern on the silicon substrate.
The ESD protection device according to claim 5,
The inductor is
A further at least one conductive pattern of the redistribution layer;
An ESD protection device further comprising a via hole connecting the conductive patterns of each redistribution layer.
An ESD protection device according to claim 5 or claim 6,
The ESD protection device, wherein the conductive pattern of the redistribution layer has a larger electrode thickness than the conductive pattern on the silicon substrate.
An ESD protection device according to any one of claims 5 to 7,
The ESD protection device, wherein the conductive pattern of the redistribution layer is formed of a material having higher conductivity than the conductive pattern on the silicon substrate.
An ESD protection device according to any one of claims 4 to 8,
The conductive pattern on the silicon substrate is an ESD protection device comprising a spiral electrode.
An ESD protection device according to any one of claims 5 to 8,
The conductive pattern on the silicon substrate and the conductive pattern on the rewiring layer have substantially the same shape, and are ESDs comprising spiral electrodes that are wound in the same direction in the same region in a plan view of the silicon substrate. Protective device.
An ESD protection device according to claim 2,
An ESD protection device further comprising a capacitor having one end connected to a signal line between the resistor and the LC parallel resonator and the other end connected to the ground.
An ESD protection device according to claim 11, comprising:
The capacitor is an ESD protection device including a third ESD element different from the two ESD elements.
An ESD protection device according to claim 12, comprising:
The resistors are composed of two partial resistors, and the two partial resistors are individually connected on respective signal lines from one end of the third ESD element to the two ESD elements. An ESD protection device.
An ESD protection device according to claim 11, comprising:
The capacitor is
A conductive pattern formed on a silicon substrate on which the signal line is formed; and a conductive pattern on a redistribution layer spaced from the conductive pattern formed on the silicon substrate. ESD protection device.
An ESD protection device according to claim 14, comprising:
The ESD protection device, wherein a conductive pattern formed on the silicon substrate forming the capacitor also serves as a conductive pattern constituting an inductor of the LC parallel resonator.