WO2011018114A1

WO2011018114A1 - Transistor

Info

Publication number: WO2011018114A1
Application number: PCT/EP2009/060509
Authority: WO
Inventors: Yong Hai Hu; Tiong Michael; Manfred Froehlich
Original assignee: X-Fab Semiconductor Foundries Ag
Priority date: 2009-08-13
Filing date: 2009-08-13
Publication date: 2011-02-17

Abstract

A transistor arranged to have an improved Safe Operating Area. The transistor has a Source, Drain, insulator and a Gate comprising one or more discrete Gate structures located at least partly over a second well, wherein at least one of the one or more discrete Gate structures does not substantially overlap with the insulator. The transistor may also be arranged such that the Source is disposed substantially between the Drain and the Gate.

Description

Transistor

The present invention is concerned with transistors, particularly Metal Oxide Semiconductor (MOS) Transistors, and more particularly Laterally Diffused MOS transistors for use in high voltage applications. Embodiments of the invention are concerned with improving Hot Carrier Injection (HCI) performance and Safe Operating Area (SOA) of the transistor.

High voltage applications exist for transistors such as charge pumps, programming non-volatile memory circuits, on-chip LCD (liquid crystal display) drivers, on-chip field emission display drivers, and the like. High voltages are also of increasing importance for application in automotive electronics for Smart Power ICs. The use of

Complementary MOS (CMOS) in high voltage applications can suffer problems with degradation of the constituent materials. By incorporating reduced surface field (RESURF) technology and a laterally diffused MOS (LDMOS) architecture, the maximum operating voltage of otherwise standard CMOS transistors can be extended to around 70V-100V.

However, current technology based on standard CMOS processes still suffers from problems such as Hot Carrier Injection (HCI), which reduces the Safe Operating Area (SOA) and the life of the transistor. The SOA is defined as the voltage and current conditions over which the device can be expected to operate without significant damage. Hot carriers are holes or electrons that have gained sufficient kinetic energy to cross a potential barrier e.g. between a well and an oxide. Carriers are accelerated in the presence of an electric field, so designs with high voltages over a short distance will create a strong field and increase the presence of Hot Carriers. This can lead to charges entering and becoming trapped in an oxide layer, which can degrade the oxide and also give the oxide a residual charge. Electron and hole traps formed within a Gate oxide will increase subthreshold leakage and shift the threshold voltage.

A lateral transistor is one in which the components such as Drain, Source and Gate are laid out on the same surface of the transistor and the carriers travel substantially in a direction parallel to said surface. Conversely in a vertically arranged transistor, the components such as the Source and Drain may be disposed on opposite ends of the transistor substrate and the carriers flow vertically between them, i.e. perpendicular to the end surfaces.

A typical (High Voltage) Laterally Diffused Metal Oxide Transistor ((HV)-LDMOS) cross- section is shown in Figure A1 of the accompanying drawings. Transistor 5 is an N- Type LDMOS, fabricated in a p-substrate 10. An n- doped layer is formed as Nwell 28 within the substrate, and a p doped layer is disposed within the Nwell forming a Pwell region 21. A Drain 25 is formed as an n+ doped active area inside the Nwell 28. A Source 23 is also formed as an n+ doped area inside the Pwell region 21 , the Source 23 being laterally connected to a channel through an n-doped Lightly Doped Drain (LDD) 24, as explained below. A high voltage shallow trench isolation oxide (STI) 132 is located between the Drain 25 and the Pwell 21. A Gate 27, made of polysilicon, is disposed on the surface between the Drain 25 and the Source 23. A Gate oxide layer 153 is located under the Gate. L-shaped spacers are formed on the left 151 and right 151 a sides of the Gate, respectively. The LDMOS has a p+ doped active area 22 to form a pick-up contact for the Pwell region 21. Disposed between the n+ Source 23 and pick-up 22 there is an STI 131 for isolation purposes. A p+ pick-up 26 is provided for the p-substrate 10 and another STI 131 a isolates the Drain 25 from the p-substrate pick-up 26.

The transistor is in the on-state when a voltage is applied to the Gate, causing a channel to form in Pwell 21 , allowing current to flow between Source and Drain. Specifically the channel forms between the LDD 24 and the interface between Pwell 21 and Nwell 28, in a region immediately under the Gate. The carriers flow from the Source, through the LDD, through the channel, through the Nwell 28 to the Drain 25.

In accordance with Figure A1 , the Gate is arranged to substantially overlap with an insulator isolating Drain 25 from Gate 27. The insulator is in the form of the STI 132. When a voltage is applied to the Gate 27, there is an electric potential coupling capacitance between the Gate 27 and the semiconductor layer under gate oxide layer 153. This coupling capacitance can be regarded as being divided into Gate-Pwell and Gate-Nwell capacitances. The inventors have appreciated that as the Gate 27 extends substantially over the STI 132, the relatively large length of the Gate results in a high voltage drop across the channel. As a consequence, the corresponding coupling capacitance between Gate 27 and Nwell 28 increases the channel electric field to result in a current increase which in turn increases the HCI effect. This phenomenon is illustrated in Figure A2 via numerically simulated I_DS-V_DS characteristics in the ON-state for the conventional LDMOS shown in Figure A1 for a specific example of a set of structural and process parameters for the LDMOS design. As shown within the circled area in Figure A2, a sudden increase in current at V_DS ~ 70V takes place. Depending on different design parameters, the sudden increase in current can take place at a voltage within a range of about V_DS~20V-70V.

The inventors have appreciated that by restructuring the Gate configuration, it is possible to address one or more of the aforementioned problems. In some embodiments, a substantial improvement in HCI and SOA can be achieved by reducing the Gate length such that the Gate does not overlap with the STI (or at least not to a significant extent). In other embodiments, the Gate can be configured into discrete Gate structures, in which at least one of the Gate structures does not overlap with the STI. Accordingly, in a first aspect the present invention provides a transistor comprising: a Source;

a Gate;

a Drain, and

an insulator,

the Drain being located in or on a first well located in or on a substrate;

the Source being located in or on a second well located in the first well;

the insulator being located in or on the first well between the Drain and the second well;

wherein the Gate comprises one or more discrete Gate structures located at least partly over the second well, wherein at least one of the one or more discrete Gate structures does not substantially overlap with the insulator.

Whilst in certain embodiments the abovementioned Gate structure does not overlap with the insulator, the person skilled in the art will appreciate that according to some embodiments of the invention the gate structure may overlap with the insulator to a small extent. For example, a particular transistor could be designed such that the edge of the Gate structure which is located towards the insulator is in line with the edge of the insulator which is located towards the Gate structure so that there is no overlap. However due to precision tolerances of the manufacturing process this might be difficult to achieve so that there could be a (small) overlap due to such tolerances. Preferably, at least one or more Gate structures of the transistor are positioned and/or dimensioned to substantially improve Hot Carrier Injection (HCI) performance and Safe Operating Area (SOA). The strong electric field created by the high voltages applied between Source and Drain accelerates carriers under the Gate, which can result in Hot Carriers. The path taken by the carriers tends to follow the shortest course, passing along the contours of the oxide regions to reach the Drain. Hot carriers may cut across the edges of the oxide corners, which can erode the corner of STI 132. Hot carriers may also enter and degrade the Gate oxide 153.

The inventors have appreciated that by rearranging the Gate, Drain, and Source, a carrier path results which may avoid the above mentioned problems. According to a second aspect of the invention there is provided a metal oxide semiconductor (MOS) transistor comprising a Source, a Gate, and a Drain; the Source being disposed substantially between the Drain and the Gate.

According to a third aspect of the invention there is provided a metal oxide semiconductor (MOS) transistor comprising a Gate, a Drain, and a Source disposed in or on a first well; the Source, first well, Gate, and Drain being arranged such that a channel created in the first well is on the opposite side of the Source as the Drain.

According to a fourth aspect of the invention there is provided a metal oxide semiconductor (MOS) transistor comprising a Gate, a Drain and a Source disposed in or on a first well; the Source, first well, Gate, and Drain being arranged such that, in use, at least a portion of carriers between the Source and the Drain flow under the first well. Accord ing to a fifth aspect of the invention there is provided a metal oxide semiconductor (MOS) transistor comprising a Source disposed in or on a first well, a Gate and a Drain; the Source, first well, Gate and Drain being arranged so as to allow carriers to flow between the Source and the Drain and the direction of the flow of the carriers over a first portion is substantially opposite to the direction of the flow of the carriers over a second portion.

Further aspects of the invention are set out in the accompanying dependent claims. Some preferred embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which: Figure A1 is a schematic cross-section of a known LDNMOS transistor;

Figure A2 shows numerically simulated I_DS-V_DS characteristics for the transistor of

Figure A1 ;

Figure A3 is a schematic cross-section of a LDNMOS transistor in accordance with an embodiment of the present invention;

Figure A4 is a schematic cross-section of a LDNMOS transistor in accordance with a further embodiment of the present invention;

Figure A5 illustrates numerically simulated I_DS-V_DS characteristics for the LDNMOS transistor of Figure A4;

Figure B1 is a schematic cross-section illustrating current flow in a known MOS transistor;

Figure B2 is a schematic cross-section of an embodiment of the invention;

Figure B3 is a schematic cross-section of an alternative embodiment of the invention;

Figure B4 is a schematic cross-section of an alternative embodiment of the invention showing a symmetrical layout;

Figure B5 is a plan view of an embodiment of the invention;

Figure B6 is a schematic cross-section illustrating electron flow in an embodiment of the invention;

Figure B7 is a schematic cross-section of an embodiment of the invention showing a repeated layout a) with solid Gates and b) with split Gates;

Figure B8 is a plan view of an embodiment of the invention showing a repeated layout;

Figure B9 is a schematic cross-section of an embodiment of the invention showing a split Gate; and

Figure B10 is a plan view of an embodiment of the invention showing a split Gate. Figure A3 shows a schematic cross-section of a LDNMOS transistor in accordance with an embodiment of the present invention. Many features are the same as in Figure A1 , carry the same reference and have the same or a similar function. However, the Gate 27 is recessed such that it does not overlap with the STI 132. Through such an arrangement the HCI and SOA performance of the transistor can be significantly improved. In Figure A3, the Gate 27 is arranged to consist of one discrete Gate structure 27, which occupies the entire space between L-shaped spacers 151. It will be appreciated that the spacers can also be D-shaped, in one example. The Gate structure 27 overlaps with the Nwell 28 and has an edge towards the STI 132. The distance between this edge and the Pwell 21 at the surface of the transistor is defined as Z. The distance Z may for example be between 0 μm and 5 μm, preferably between 0 μm and 3 μm, and more preferably between 0 μm and 1 μm. Good HCI and SOA performance has been achieved with a distance Z of 0 μm, although a distance Z of 0 μm may be difficult to achieve due to precision tolerances of the manufacturing process.

In some embodiments the distance Z is such that there is a very small overlap between Gate 27 and STI 132 due to precision tolerances of the manufacturing process.

It will be appreciated that, as a variant of the embodiment shown in Figure A3, the Gate structure 27 may be recessed such that it does not overlap with Nwell 28. In such an arrangement, the Gate structure 27 is (fully) located on Pwell 21 and the distance Z is between 0 μm and 0.3 μm, preferably between 0 μm and 0.1 μm. Good results have been also achieved with a distance Z of 0 μm.

In the ON-state, the recessed Gate structure 27 of Figure A3 has less coupling capacitance between the Gate and the Nwell 28 compared with an arrangement in which Gate structure 27 overlaps with the STI 132 (Figure A1 ). This reduces the channel electric field. As a result, sudden increase in current as shown in Figure A2 can be avoided and a significant improvement in HCI performance and SOA can be achieved. In an OFF-state, the recessed Gate structure 27 of Figure A3 operates as a field plate, which results in a more uniform electric field distribution for a high breakdown voltage. It will be appreciated that the breakdown voltage may be degraded when the distance Z is reduced compared to what is shown in Figure A3. Figure A4 shows a schematic cross-section of a LDNMOS transistor according to a further embodiment. Most features are the same as in Figure A3, but the Gate is different from that of Figure A3. The Gate comprises two discrete Gate structures 27 and 27A. These structures 27, 27A are arranged to be separated by L-shaped spacers 151 and have a distance G between them. The distance G may for example be between 0.1 μm and 5 μm, preferably between 0.1 μm and 3 μm and more preferably between 0.1 μm and 1 μm. The Gate structure 27 is arranged to form the channel and does not overlap with the STI 132. The Gate structure 27 has an edge towards the STI 132 and the distance between this edge and the Pwell 21 at the surface of the transistor is defined as Z. This distance Z relates to the distance Z of Figure A3 and the examples of values of distance Z mentioned in connection with Figure A3 are also applicable to distance Z of Figure A4.

In Figure A4, in the ON-state, the Gate structure 27A is not electrically connected so as to be floating, whereas the Gate structure 27 is arranged to form the channel when a voltage is applied to it. Since the Gate structure 27A is floating, it does not contribute towards any Gate-Nwell coupling capacitance. Only the Gate structure 27 contributes towards the Gate-Nwell coupling capacitance but the effect of this is much less than in the situation shown in Figure A1. This is due to the Gate structure 27 not overlapping with the STI 132. As a result, the voltage drop across the channel is reduced, which in turn reduces the channel electric field. Figure A5 shows the numerically simulated I_DS-V_DS characteristics for various voltages applied to the Gate structure 27 of the transistor of Figure A4. As the channel electric field is reduced by the arrangement of Gate structure 27, the sudden increase in current as shown in Figure A2 is avoided so that the transistor of Figure A4 has substantially better HCI with wider SOA.

In Figure A4, the Gate structure 27A is arranged to operate as an extended field plate in the OFF-state. This results in a more uniform electric field distribution which results in a high breakdown voltage. Since the discrete Gate structure 27A is an extended field plate, any variation of the distance Z does not influence the breakdown voltage (or only to a small extent).

For the discrete (or split) Gate structures 27, 27A in Figure A4, no additional mask is required during the transistor fabrication since the Gate structures 27, 27A can be formed using a mask which would be used during the transistor fabrication anyway. This simplifies the process technique whilst achieving better HCI and SOA performances.

Embodiments of the second to fifth aspects of the invention aim to improve the SOA of a High Voltage transistor by arrangement of the transistor constituents so as to create a novel pathway for the carriers between Source and Drain. The novel pathway moves the location of impact ionization deeper into the transistor body, compared to previous transistor designs, and generally reduces or avoids problems with HCI in areas that would normally be damaged.

An embodiment is now described in which features similar to those of Figure A1 carry like numbers. A cross-section of the embodiment of a (High Voltage) Laterally Diffused

Metal Oxide Transistor ((HV)-LDMOS), according to an aspect of the invention, is shown in Figure B2. The transistor is an N-Type LDMOS, fabricated in a p-substrate

10. An n- doped layer is formed as Nwell 28 within the substrate, and a p doped layer is disposed within the Nwell forming a Pwell region 21. A Source 23 is also formed as an n+ doped area inside the said Pwell region 21 , the Source 23 being laterally connected to the channel through an n doped Lightly Doped Drain (LDD) 24.

A Drain 25 is formed as an n+ doped active area inside the Nwell 28. Notably the Drain is located on the same side of the Gate 27 as the Source, when viewed in cross- section. The Source is thus disposed between the Drain and Gate, whereas previous transistor designs have disposed the Gate between Source and Drain. The Drain 25 is laterally separated from the Pwell and Source by a high voltage, Shallow Trench Isolation (STI) RESURF field plate 132. A Gate 27 made of polysilicon (poly) is disposed on the device surface above part of the Pwell 21. A Gate oxide layer 153 is located under the Gate. L-shaped spacers are formed on the left 151 and right 151 a sides of the Gate, respectively. The LDMOS has a p+ doped active area 22 to form a pick-up contact for the Pwell region 21. There is a p+ pick-up 26 for the p-substrate 10 and there is another STI field 131 for isolating the Drain 25 from the p-substrate pick-up 26.

In the Off-State, no voltage is present at the Gate 27 and ideally no current flows between Source and Drain. I n the on-state, a voltage is applied to the Gate, creating a channel in Pwell 21 , between the LDD 24 and the interface between Pwell 21 and Nwell 28, in a region under the Gate. This allows current to flow between the Source and the Drain. As shown in Figure B6 the carriers flow from the Source, through the LDD, through the channel, then (substantially) vertically under the Gate in the Nwell 28, and then under the Pwell 21 to the Drain 25. The carrier path is thus more tortuous compared to paths of prior art transistors. As shown in Figure B6, the current path changes direction considerably, which helps to relieve some of the problems associated with HCI. Changes in direction of the electric field reduce the momentum of carriers in any single direction, which reduces the likelihood of Hot Carriers. The carriers are required to change direction and, in fact, under the Pwell 21 , they flow in a direction (right to left in the left half of Figure B6) counter to the flow inside the Pwell (left to right in Figure B6). The change of direction means that the carriers take a wider path, deep through the Nwell.

It can be seen in Figure B6 that the carrier path turns to flow under the Pwell, deep within the Nwell. This portion is known as the drift region. The carriers are diverted into the Nwell and away from oxides 132 and 132a. Whilst some carriers will closely follow the contour of the Pwell, Hot Carriers entering the Pwell will not damage it, unlike Hot Carriers entering the oxides in prior art transistors. In conventional transistors the path length from Source to Drain can be increased by spreading the Drain and Source further apart but the side effect is increased overall size of the transistor. An advantageous result of the novel path created by the present arrangement of Drain, Source and Gate is that the path length is longer and forces more carriers to flow deeper within well 28 compared to a similarly sized MOSFET of the type shown in Figure 1 . This provides advantages such as a reduction in the electric field strength by spreading the field over a greater length, and the use of a larger volume of the body (Nwell 28) to handle larger current.

As indicated by the enlarged arrow in Figure B6, the current flow below the Gate is largely vertical as the current can not flow directly laterally from channel to Drain, and is constrained to flow between bodies 29 and 21. This vertical flow draws the carriers deeper into well 28 and prevents them from colliding with an STI such as 132 and 132a. Figure B3 shows a cross-section of a transistor of an embodiment of the invention. In addition to the components of the transistor of Figure B2, a p-doped body 29 (Pbody) is added, opposite the Pwell 21 , with respect to the Gate. The Pbody partially encloses the STI 131 a, providing protection for the STI from Hot Carriers. This Pbody can be an additional layer with a specific doping profile or can be doped the same as Pwell 21 , removing the need for an additional mask. The formation of the Pbody opposite the Pwell creates a vertical channel under the Gate of width W, which further aids in the creation of a vertical electric field and vertical carrier path. This results in further HCI improvement.

The width of the Pbody 29 under the Gate Oxide is X μm and extends under the STI by an amount Yμm. Suggested values for X and Y are given in Table A below.

Figure B4 shows a cross-section of a transistor of an embodiment of the invention, whereby the Pbody 29 of the embodiment shown in Figure B3 is modified to become a second Pwell having therewithin a second Source 23a. A second Drain 25a may be disposed in Nwell 28, separated from the second Pwell by a RESURF STI 132a. The Figure B4 cross-section illustrates that the halves of the transistor, centered about a vertical line bisecting the Gate, are mirror images, although in other embodiments they do not necessarily have to be (exact) mirror images. In a preferred embodiment, the first and second Sources are portions of a continuous Source region and the first and second Drains are portions of a continuous Drain region. These regions may form rings (when viewed in plan view) on the surface of the transistor. In Figure B5, a plan view illustrates how a continuous Drain region 25 in the form of an oval ring surrounds a continuous Source region 23, which in turn surrounds a Gate region 27. The Source region is disposed within Pwell 21 and is isolated from the Drain region by STI field region 132.

It can be seen that in the embodiments in Figure B4 and B5, each Drain or Drain portion is located on the same side of the Gate as a corresponding Source or Source portion. Alternatively, these embodiment can be perceived as having a Source or Source region disposed between the Gate and a Drain or Drain region.

Figure B7a) shows a cross-section of a transistor having a repeating arrangement of adjoining sub-transistors according to the embodiments above. The sub-transistors, centered about PoIyI- Poly N, may be repeated as many times as needed to achieve the desired performance. As best seen in Figure B8, each Gate 27 is surrounded by a Source region 23; all of the Source regions are disposed within Pwell 21 ; and Drain region 25, disposed within the Nwell 28 (not shown in Figure B8), surrounds the Sources and Gates.

Figures B9 and B10 show an embodiment having repeated adjoining sub-transistors and a Split Gate structure. The Split Gate structure is described in the first aspect of the invention above. The Split Gate structure may be used with other transistor embodiments, such as those described with reference to Figures B2 to B8.

The electrical characteristics of the transistor of Figure B10 are qualitatively similar to the characteristics shown in Figure A5, which demonstrates the improvement in HCI and SOA performance.

Table A lists preferred values of elements described above and in the drawings, whereby "urn" means micrometer.

The skilled person will understand that in the preceding description and appended claims, positional terms such as 'above', 'overlap', 'under', 'lateral', 'vertical', etc. are made with reference to conceptual illustrations of a transistor, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a transistor when in an orientation as shown in the accompanying drawings. It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with the present invention. It will be appreciated that the Source, Drain and Gate could be arranged to be out-of-plane or to be differently aligned so that the direction of the carriers is not exactly as described above, the resulting devices still being in accordance with the present invention.

Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:

1. A transistor comprising:

a Source;

a Gate;

a Drain, and

an insulator,

the Drain being located in or on a first well located in or on a substrate;

the Source being located in or on a second well located in the first well;

2. The transistor according to claim 1 , wherein said at least one structure overlaps with the first well and has an edge towards the insulator, wherein the distance between the second well and said edge is between 0 μm and 5 μm, preferably between 0 μm and 3 μm, more preferably between 0 μm and 1 μm.

3. The transistor according to claim 1 , wherein, at the surface of the transistor, said at least one Gate structure does not overlap with the first well, wherein the distance between the first well and said at least one Gate structure is between 0 μm and 0.3 μm, preferably between 0 μm and 0.1 μm, more preferably substantially 0 μm.

4. The transistor according to any preceding claim, wherein a distance between two adjacent Gate structures is between 0.1 μm and 5 μm, preferably between 0.1 μm and 3.0 μm, more preferably 0.1 μm and 1 μm.

5. The transistor according to any preceding claim, wherein a channel is arranged to be formed within the second well by the at least one of the one or more discrete Gate structures.

6. The transistor according to claim 5, wherein one or more Gate structures not arranged to form the channel are not electrically connected so as to be floating in an ON-state.

7. The transistor according to claim 5 or 6, wherein one or more Gate structures not arranged to form the channel are arranged to operate as a field plate in an OFF- state.

8. The transistor according to any preceding claim, wherein the at least one or more Gate structures are arranged to substantially improve Hot Carrier Injection (HCI) performance and Safe Operating Area (SOA).

9. The transistor according to any preceding claim, wherein the first well is of a first doping polarity, and the second well is of a second doping polarity opposite to the first doping polarity.

10. The transistor according to claim 9, wherein the substrate is of the second doping polarity.

1 1. The transistor according to any preceding claim, wherein the transistor is a Metal Oxide Semiconductor (MOS) transistor, preferably a Laterally Diffused Metal Oxide (LDMOS) transistor, and most preferably a high voltage LDMOS transistor.

12. The transistor according to any preceding claim, wherein said at least one Gate structure is disposed to substantially reduce the electric potential coupling capacitance between the Gate structure and the first well.

13. The transistor according to any preceding claim, wherein the one or more Gate structures are each provided with at least two insulating spacers.

14. The transistor according to claim 13, wherein the insulating spacers are L- shaped or D-shaped.

15. A metal oxide semiconductor (MOS) transistor comprising: a Source, a Gate, and a Drain;

wherein the Source is disposed substantially between the Drain and the Gate.

16. The transistor of claim 15, further comprising a first well, the Source being disposed on or in the first well.

17. A metal oxide semiconductor (MOS) transistor comprising:

a Source disposed in or on a first well;

a Gate; and

a Drain,

wherein the Source, first well, Gate and Drain are arranged such that a channel arranged to be created in the first well is on the opposite side of the Source as the Drain.

18. A metal oxide semiconductor (MOS) transistor comprising:

a Source disposed in or on a first well;

a Gate; and

a Drain,

wherein the Source, first well, Gate and Drain are arranged such that, in use, at least a portion of carriers between the Source and the Drain flow under the first well.

19. A metal oxide semiconductor (MOS) transistor comprising:

a Source disposed in or on a first well;

a Gate; and

a Drain,

wherein the Source, first well, Gate and Drain are arranged so as to allow carriers to flow between the Source and the Drain and the direction of the flow of the carriers over a first portion is substantially opposite to the direction of the flow of the carriers over a second portion.

20. The transistor of claim 19, wherein the first portion is within the first well.

21. The transistor of any one of claims 16 to 20, wherein the first well is of a first doping polarity and the first well, Gate and Drain are disposed in or on a second well, of a second doping polarity opposite the first doping polarity, disposed in or on a substrate.

22. The transistor of claim 21 when dependent on claim 17, wherein the channel created in the first well is under the Gate, between the Source and the second well.

23. The transistor of any one of claims 15 to 22, wherein the Source, Drain and Gate are substantially laterally arranged on a surface of the transistor.

24. The transistor of any one of claims 15 to 23, wherein the transistor is a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor.

25. The transistor of any one of claims 15 to 24, wherein the transistor is a High Voltage transistor.

26. The transistor of any one of claims 15 to 25, wherein the flow of carriers under the Gate is substantially perpendicular with respect to a significant portion of a surface on which the Drain, Gate, and Source are disposed.

27. The transistor of claim 21 , or of any one of claims 22 to 26 when directly or indirectly dependent on claim 21 , further comprising a semiconductor body of the first doping polarity disposed in or on the second well, located at least partly under the Gate.

28. The transistor of claim 27, wherein the semiconductor body and the first well are generally arranged at opposite sides of the Gate.

29. The transistor of claim 27 or 28, wherein the semiconductor body at least party encases and/or is adjacent to an insulator disposed further from the Gate than the semiconductor body.

30. The transistor of claim 29, wherein the semiconductor body is arranged to substantially reduce impact ionisation within the insulator.

31. The transistor of any one of claims 27 to 30, wherein the doping level of the semiconductor body is substantially the same as that of the first well.

32. The transistor of any one of claims 27 to 31 , further comprising a second Source disposed on or in the semiconductor body, the semiconductor body being a third well.

33. The transistor of claim 32, wherein the Gate is arranged to create a channel in the third well.

34. The transistor of claim 32, wherein the Gate forms a first Gate portion of a Gate assembly, the Gate assembly further comprising a second Gate portion arranged to create a channel in the third well.

35. The transistor of any one of claims 15 to 31 , wherein the Source is a continuous region at least partly surrounding the Gate, and the Drain is a continuous region at least partly surrounding the Source.

36. A transistor structure comprising a plurality of adjoining transistors according to any one of claims 15 to 35, wherein a common Drain shared by the plurality of transistors is provided instead of individual Drains for each of the plurality of transistors.