WO2011094218A2

WO2011094218A2 - Hierarchical multi-bank multi-port memory organization

Info

Publication number: WO2011094218A2
Application number: PCT/US2011/022435
Authority: WO
Inventors: Richard S. Roy; Dipak Kumar Sikdar
Original assignee: Mosys, Inc.
Priority date: 2010-01-29
Filing date: 2011-01-25
Publication date: 2011-08-04
Also published as: US8547774B2; TW201145306A; US20130336074A1; WO2011094218A3; US9030894B2; US20110188335A1

Abstract

A memory system includes multiple (N)memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each, of the simultaneously access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory hank performs an access to an array of single-port memory cells. Simultaneously accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.

Description

HIERARCHICAL MULTI-BANK MULTI-PORT MEMORY ORGANIZATION

Richard S. Roy

Dipak Kumar Sikdar

Field of the Invention

[0001] The present invention relates to the addition of multiple ports to a hierarchical multi-bank structure to multiply the available cyclic random bandwidth.

Related Art

[0002] Prior art has introduced the concept of multiple ports in static random access memory (SRAM) technology to increase the available random bandwidth of a memory system. Multiple ports increase the available transaction

generation frequency by the number of ports. However, there is enormous area overhead due to the required use of a multi-port SRAM bit cell.

[0003] Fig. 1 is a block diagram of a conventional multi-port SRAM 100, which includes memory cell array 101 and three separate access ports 111-113. Memory cell array 101 is made of a plurality of 3-port SRAM cells.

The multi-port nature of the SRAM cells in array 101 allows simultaneous accesses to be performed on each of the three access ports 111-113. For example, a first read access can be performed on access port 111, a second read access can be simultaneously performed on access port 112, and a write access can be simultaneously performed on access port 113. The 3-port SRAM cells of array 101 are much larger than a conventional single port SRAM cell.

The large size of the 3-port SRAM cells restricts the usage of multi-port SRAM 100 to small memory instances

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SUBSTITUTE SHEET RULE 26 (typically embedded memory) . It would therefore be

desirable to have an improved multi-port memory system.

SUMMARY

[0004] The present invention introduces a memory system that includes a plurality of memory banks, each having multiple ports. Each of the memory banks includes a

corresponding memory array, which is single port in nature. That is, the individual memory arrays are made of single- port memory cells. These single-port memory cells can be, for example, dynamic random access memory (DRAM) cells, embedded DRAM (EDRAM) cells, or flash memory cells.

[0005] Simultaneous accesses may be performed on all of the multiple ports at the top (chip) level. However, none of these simultaneous accesses may address the same

individual memory bank. Each of the individual memory banks may be accessed from any one of the multiple ports. However, each of the individual memory banks is only

accessed from (at most) one of the multiple ports during any given access cycle. In one embodiment, a multiplexer structure within each memory bank couples the

corresponding memory array to each of the multiple ports.

[0006] In one embodiment, the multi-bank multi-port memory system can be expanded to include an additional level of hierarchy (i.e., partitions), which allows

further multiplication of the number of simultaneously accessed ports, with minimal area overhead. All ports at the partition level may be simultaneously accessed. In this embodiment, the number of concurrent accesses per cycle equals the number of partitions times the number of ports. For example, in a memory system having three ports and four partitions, the cyclic random bandwidth is

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SUBSTITUTE SHEET RULE 26 multiplied by 12, while the area overhead is increased by less than five percent, compared to a single port memory structure .

[0007] The present invention will be more fully

understood in view of the following description and

drawings .

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Fig. 1 is a block diagram of a conventional three-port memory system, which includes an array of three-port memory cells.

[0009] Fig. 2 is a block diagram of a multi-port multi- bank memory system in accordance with one embodiment of the present invention.

[0010] Fig. 3 is a block diagram illustrating a memory bank of the multi-port multi-bank memory system of Fig. 2, in accordance with one embodiment of the present invention.

[0011] Fig. 4 is a block diagram of a memory system that includes four memory partitions, in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION

[0012] Fig. 2 is a block diagram of a multi-port multi- bank memory system 200 in accordance with one embodiment of the present invention. Memory system 200 includes four memory banks B00-B03 and three access ports P1-P3. Although memory system 200 includes four memory banks and three access ports, it is understood that memory system 200 can include other numbers of memory banks and other numbers of ports, as long as the number of memory banks is greater than or equal to the number of ports.

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SUBSTITUTE SHEET RULE 26 [0013] In the embodiment illustrated by Fig. 2, ports Pi and P2 are read ports, and port P3 is a write port.

The first read port PI includes a first read address bus RA 01 and a first read data bus RD 01. The second read port P2 includes a second read address bus RA 02 and a second read data bus RD_02. The write port P3 includes a write address bus WA 0 and a write data bus WD 0.

[0014] Each of the memory banks B₀o^_Bo3 is coupled to each of the three ports P1-P3. More specifically, each memory bank B_xx includes a first read port Ρΐχχ (which is coupled to port PI), a second read port P2_XX (which is coupled to port P2) and a write port P3_XX (which is coupled to port P3), wherein XX = 00, 01, 02 and 03.

[0015] The first read address bus RA 01 provides read addresses to the first read ports ΈΊ₀₀, PIQ_I, P I 02 and PI₀₃, through bus connections labeled Al . The first read data bus RD 01 receives read data values from the first read ports Ploo, Ploi/ P I 02 and P I 03 , through bus connections labeled Rl .

[0016] The second read address bus RA 02 provides read addresses to the second read ports P2₀c, P2oi, P2o2 and P2₀3_f through bus connections labeled A2. The second read data bus RD 01 receives read data values from the second read ports P2oo, P oi/ P2o2 and P2₀3, through bus connections labeled R2.

[0017] The write address bus WA 0 provides write addresses to the write ports P 3 o o , P 3 oi , P3 o2 and P3 o3 , through bus connections labeled WA. The write data bus WD_0 provides write data values to write ports P 3 o o , P 3 o i , P 3 o2 and P 3 os , through bus connections labeled WD.

[0018] An external device (or devices) may initiate accesses to memory system 200 in the following manner.

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SUBSTITUTE SHEET RULE 26 Accesses may be simultaneously initiated on ports PI, P2 and/or P3, as long as none of these simultaneous accesses specify the same memory bank. For example, a read access on port PI may access memory bank Boo at the same time that a read access on port P2 accesses memory bank and a write access on port P3 accesses memory bank B₀₃. Because each of the memory banks Β₀ο-Β₀3 is accessed by, at most, one of the ports P1-P3 at any given time, the memory banks B00-B03 can be implemented using single-port memory cells. The internal structure of memory banks Boo^~Bo3 is described in more detail below.

[0019] Fig. 3 is a block diagram illustrating memory bank B₀o in more detail, in accordance with one embodiment of the present invention. Memory banks B₀i, B₃₂ and B₀₃ are identical to memory bank B₀o in the described embodiments. Memory bank B₀o includes multiplexer 201, de-multiplexer 202, access control logic 205, and memory array M₀Q.

Memory array M₀o includes an array of single-port memory cells. These single-port memory cells can be, for example, dynamic random access memory (DRAM) cells, static random access memory (SRAM) cells, embedded DRAM (EDRAM) cells, or flash memory cells. Multiplexer 201 and access control logic 205 are coupled to receive the read address on the first read address bus RA_01 (via bus connections Al), the read address on the second read address bus RA 02 (via bus connections A2) , and the write address on the write

address bus WA_0 (via bus connections WA) . Each of these received addresses includes a bank address (which

specifies one of the memory banks Boo^~Bo3) and a local address (which specifies a row/column location within the memory array of the memory bank) . Access control logic 205 determines whether one of the received read addresses

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SUBSTITUTE SHEET RULE 26 or the received write address includes a bank address that specifies the memory bank Bo o - In one embodiment, memory bank B₀o is assigned a unigue address, and access control logic 205 compares the bank addresses received on buses RA 01, RA 02 and WA 0 with this unigue address to

determine whether memory bank B₀ o is specified for an access. During any given access cycle, only one (or none) of the buses RA 01, RA 02 and WA 0 will carry a bank address that specifies memory bank Β₀ ο ·

[0020] If access control logic 205 determines that one of the buses RA 01, RA 02 and WA 0 carries a bank address that specifies memory bank B₀₀ , then access control logic 205 will cause multiplexer 201 to route the associated local (row/column) address to memory array M₀ o , as the array address signal ADR₀ o . For example, if access control logic 205 detects that the bank address on read address bus RA 01 specifies memory bank B₀ o , then access control logic 205 will cause multiplexer 201 to route the local (row/column) address from read address bus RA 01 to single-port memory array Mo o -

[0021] Access control logic 205 also generates a read/write access control signal (R/W) in response to the received addresses. If access control logic 205

determines that a matching bank address is received on one of the read address buses RA 01 or RA 02, then access control logic 205 generates a R/W access control signal that specifies a read operation. If access control logic 205 determines that a matching bank address was received on the write address bus WA 0, then access control logic 205 generates a R/W access control signal that specifies a write operation. If access control logic 205 determines that no matching bank address was received on address

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SUBSTITUTE SHEET RULE 26 buses RA 01, RA 02 or WA 0, then access control logic 205 generates a R/W access control signal that specifies an idle cycle (no operation) .

[ 0022 ] If the R/W control signal indicates that a matching bank address was received on one of the read address buses RA_01 or RA_02, then memory array M₀o

performs a read operation to the address location

specified by the array address ADRQQ. The resulting read data value DOUT₀o is provided from memory array M₀o to de^¬ multiplexer 202. Access control logic 205 causes de^¬ multiplexer 202 to route the read data value DOUTQ_O to the read data bus associated with the read access. For example, if the matching bank address was received on the first read address bus RA 01 (i.e., port PI), then de^¬ multiplexer 202 routes the read data value DOUT₀o to the first read data bus RD 01 (i.e., port PI). Conversely, if the matching bank address was received on the second read address bus RA_02 (i.e., port P2) , then de-multiplexer 202 routes the read data value DOUToo to the second read data bus RD_02 (i.e., port P2).

[ 0023 ] If the R/W control signal indicates that a matching bank address was received on the write address bus WA 0, then memory array Moo performs a write operation, whereby the write data value on write data bus WD_0 (i.e., DINoo) is written to the address location specified by the array address ADRoo.

[ 0024 ] Assuming that each of the memory banks B₀o -B₀₃ operates at a frequency F, then memory system 200 may operate at a maximum frequency of 3xF. That is, two read operations may be simultaneously performed at frequency F on ports PI and P2, while one write operation is

simultaneously performed at frequency F on port P3.

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SUBSTITUTE SHEET RULE 26 [0025] Fig. 4 is a block diagram of a memory system 400 that includes four memory partitions MP₀-MP₃, in accordance with another embodiment of the present invention. In the described embodiment, memory partition MPo is identical to memory system 200 (Figs. 2-3) . Thus, memory partition MPQ includes memory banks B₀o-B₀₃ and ports P1- P3 , as described above. Memory partitions MP₁-MP₃ are identical to memory partition MPQ. Memory partitions MPi , MP₂ and MP₃ include memory banks B₁₀ -B13 , B20 -B23 and B30 -B33 , respectively, and ports P4 -P 6 , P7 - P 9 and P10-P12, respectively. Memory banks B₁₀-B₁₃, B₂o-B₂₃ and B30 -B33 are identical to memory banks B₀₀-B₀₃. Ports P4 -P5 , P7 - P 8 and P10-P11 are read ports, similar to read ports P1-P2. Ports P 6 , P 9 and P12 are write ports, similar to write port P3 .

[0026] Up to eight read operations and four write operations may be performed simultaneously within memory system 400. More specifically, eight read operations may be initiated by providing read addresses on the read address buses RA_01, RA_02, RA_11, RA_12, RA_21, RA_22, RA_31 and RA_32 of ports PI, P2, P4 , P5 , P7 , P 8 , P10 and Pll, respectively. Each of these read operations must specify different memory banks within the corresponding memory partitions. In response, eight read data values are provided on read data buses RD_01, RD_02, RD_11, RD_12, RD_21, RD_22, RD_31 and RD_32 of ports PI, P2, P4 , P5 , P7 , P 8 , P10 and Pll, respectively.

[0027] Similarly, four write operations may be

initiated by providing write addresses on the write

address buses WA_0, WA_1, WA_2 and WA_3 of ports P3, P6, P9 and P12, respectively, and providing write data values on the write data buses WD 0, WD 1, WD 2 and WD 3 of ports P3, P6, P9 and P12, respectively.

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SUBSTITUTE SHEET RULE 26 [ 0028 ] The use of memory partitions MP₀-MP₃ in memory system 400 adds an additional level of hierarchy to the structure of memory system 200, thereby allowing for multiplication of the number of simultaneously accessible ports, with minimal area overhead. The additional area overhead associated with memory system 400 is less than 5 percent, when compared with a conventional single-ported memory structure having the same capacity.

[ 0029] The maximum operating frequency of memory system 400 is equal to the operating frequency of the memory banks times the number of ports per memory partition, times the number of memory partitions. Assuming that each of the memory banks of memory system 400 operates at a frequency F, then memory system 400 may operate at a maximum frequency of 3 x 4 x F. That is, eight read operations may be simultaneously performed at frequency F on ports PI, P2, P4, P5, P7, P8, P10 and Pll, while four write operations are simultaneously performed at frequency F on ports P3, P6, P9 and P12.

[ 0030 ] Although memory system 400 includes four memory partitions, with three ports per memory partition, it is understood that memory system 400 can include other

numbers of memory partitions, having other numbers of ports per memory partition, in other embodiments.

[ 0031 ] Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. Accordingly, the present invention is limited only by the following claims.

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SUBSTITUTE SHEET RULE 26

Claims

CLAIMS We Claim:

1. A memory system comprising:

a first plurality of ports; and

a first plurality of memory banks, wherein each of the first plurality of memory banks is coupled to each of the first plurality of ports, and each of the first plurality of memory banks comprises an array of single port memory cells.

2. The memory system of Claim 1, wherein the number of memory banks in the first plurality of memory banks is greater than or egual to the number of ports in the first plurality of ports.

3. The memory system of Claim 1, wherein the first plurality of ports comprise one or more read ports and one or more write ports.

4. The memory system of Claim 3, wherein the first plurality of ports comprises a first read port for initiating read accesses to the first plurality of memory banks, a second read port for initiating read accesses to the first plurality of memory banks, and a write port for initiating write accesses to the first plurality of memory banks .

5. The memory system of Claim 1, wherein each of the first plurality of memory banks comprises a

multiplexer having inputs coupled to receive an access address from each of the first plurality of ports, and an output that provides one the received access addresses to a corresponding array single port memory cells.

6. The memory system of Claim 1, wherein each of the first plurality of memory banks further comprises a de-multiplexer having an input coupled to receive a read data value from a corresponding array of single port memory cells, and a plurality of outputs coupled to a corresponding plurality of the first plurality of ports.

7. The memory system of Claim 1, further

comprising :

a second plurality of ports; and

a second plurality of memory banks, wherein each of the second plurality of memory banks is coupled to each of the second plurality of ports, and each of the second plurality of memory banks comprises an array of single port memory cells.

8. A method comprising:

simultaneously transmitting a plurality of access requests on a corresponding plurality of ports ;

receiving the plurality of access requests within each of a plurality of memory banks, wherein each of the plurality of memory banks is coupled to each of the plurality of ports; and

simultaneously performing accesses within the plurality of memory banks in response to the

plurality of access requests, wherein each of the memory banks performs, at most, one access at a time.

9. The method of Claim 8, wherein there are more memory banks than ports.

10. The method of Claim 8, wherein the accesses within the plurality of memory banks comprise accessing single port memory arrays.