JP4116801B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device having a plurality of ports.
[Prior art]
There are several types of multi-port memories, which are semiconductor storage devices having a plurality of ports. In the following, the term “multi-port memory” refers to a memory that has a plurality of ports and can independently access a common memory array from each port. In such a memory, for example, an A port and a B port are provided, and a CPU connected to the A port and a CPU connected to the B port can independently read and write to a common memory array.
[0002]
The multi-port memory includes an arbitration circuit called an arbiter. This arbiter determines the priority order of access requests received from a plurality of ports, and the control circuit of the memory array sequentially executes access according to this priority order. For example, the input to each port is executed preferentially in order from the earlier access.
[0003]
Conventionally, SRAM has generally been used as a memory array of a multi-port memory. This is because the SRAM can be randomly accessed and nondestructive reading is possible.
[0004]
For example, in a 2-port multiport memory, two sets of word lines and bit line pairs are provided for one SRAM memory cell. One port performs a read / write operation using a set of one word line and bit line pair, and the other port executes a read / write operation using a set of the other word line and bit line pair. As a result, reading and writing can be performed independently from the two ports. However, when there is a write instruction from the two ports at the same time in the same cell, it is impossible to carry out simultaneously, so one port is given priority and a BUSY signal is generated at the other port. This is called a BUSY state.
[Problems to be solved by the invention]
As the performance of the system increases, the amount of data handled increases, and a large capacity is required for the multiport memory. However, the SRAM type multi-port memory as described above has a problem that the area of the memory cell is large.
[0005]
In order to solve this problem, it is conceivable to employ a DRAM array for a multi-port memory. In order to achieve a large degree of integration for a multi-port SRAM, as in the case of a general DRAM cell, one memory cell of a DRAM used for a multi-port memory has one word line and one It is necessary to be connected only to the bit line. When a memory block is configured using DRAM cells as described above, when a read or write operation is executed from a certain port to a memory cell of a certain block, the block is accessed from another port during the operation. I can't. This is because the DRAM cell is destructive read. That is, once the information is read, it is not possible to select another word line in the same block without amplifying this information and writing it back to the cell and precharging the word lines and bit lines.
[0006]
In addition, unlike an SRAM type multi-port memory, a DRAM type multi-port memory needs to be periodically refreshed to retain information. Therefore, it is necessary to manage the refresh timing inside the memory device.
[0007]
In view of the above, an object of the present invention is to provide a DRAM type multi-port memory having the same specifications as those of an SRAM.
[Means for Solving the Problems]
A semiconductor memory device according to the present invention includes: plural Volatile memory cell Each bank is defined as a portion comprising a plurality of word lines and a plurality of sense amplifiers and related to sense amplifiers that are simultaneously activated. A cell array including a plurality of banks; A column decoder provided in common to the plurality of banks, a data bus connected to the sense amplifier of a column selected by the column decoder, and via the data bus A plurality of external ports each capable of accessing an independent address with respect to the cell array; an arbitration circuit for determining an access order between the plurality of external ports; A control circuit is included that outputs a busy signal to the port that requested the access when the access request is made to the bank and the one bank is executing the core operation. Thus, the plurality of access operations requested from the plurality of external ports are sequentially executed in the order determined by the arbitration circuit regardless of the presence or absence of the busy signal. It is characterized by that.
[0008]
The semiconductor memory device is configured to output a busy signal to a port to which a request is input when an access is requested to the same bank as the core operating. With this busy signal notification function, it can be determined that it takes more time than usual to access outside the semiconductor memory device.
[0009]
Further, according to an aspect of the present invention, the semiconductor memory device further includes a refresh timing generation circuit for internally designating a refresh operation timing for the cell array.
[0010]
As a result, a refresh command can be automatically generated inside the multiport semiconductor memory device, and a refresh operation can be periodically performed on the cell array.
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0011]
FIG. 1 is a diagram showing an example of the configuration of a dual port semiconductor memory device according to the present invention.
[0012]
1 includes a command buffer 11, an address buffer 12, a data input / output buffer 13, a data holding buffer 14, an address decoder 15, a command buffer 21, an address buffer 22, a data input / output buffer 23, and data holding. Buffer 24, address decoder 25, arbitration logic 31, timing generator 32, column decoder 33, cell array 34, word decoder 35, data bus amplifier & write amplifier 36, switch 37, switch 38, internal address generation circuit 39, and refresh timing generation A circuit 40 is included.
[0013]
The command buffer 11, the address buffer 12, and the data input / output buffer 13 constitute the left port L-port, and the data holding buffer 14 and the address decoder 15 are provided for the port L-port. The command buffer 21, the address buffer 22, and the data input / output buffer 23 constitute the right port R-port, and the data holding buffer 24 and the address decoder 25 are provided for the port R-port. The cell array 34 includes DRAM type memory cells (volatile memory cells) made of memory capacitors.
[0014]
In the port L-port, the command buffer 11 receives a control signal and a clock signal from the outside, and supplies them to the timing generator 32 via the arbitration logic 31. The address buffer 12 receives an address signal from the outside, and supplies an address to the address decoder 15 at an appropriate timing. The address decoder 15 decodes the received address and supplies the decoded result to the timing generator 32.
[0015]
In the port R-port, the command buffer 21 receives a control signal and a clock signal from the outside, and supplies them to the timing generator 32 via the arbitration logic 31. The address buffer 22 receives an address signal from the outside, and supplies an address to the address decoder 25 at an appropriate timing. The address decoder 25 decodes the received address and supplies the decoded result to the timing generator 32.
[0016]
The arbitration logic 31 determines the priority of the access request between the port L-port and the port R-port according to the control signal received from the port L-port and the port R-port. For example, the access request is preferentially selected in order from the access with the fastest input to the port.
[0017]
The timing generator 32 receives a control signal and a clock signal from the port L-port and the port R-port via the arbitration logic 31, generates a timing signal for controlling various operations, a column decoder 33, a cell array 34, a word The data is supplied to the core and core peripheral circuits such as the decoder 35, the data bus amplifier & write amplifier 36, the switch 37, and the switch 38. The timing generator 32 holds the supplied decode address and supplies it to the column decoder 33 and the word decoder 35 at an appropriate timing.
[0018]
The word decoder 35 activates the word line of the word specified by the decode address, and supplies the data selected by the column line among the memory cells connected to the word line to the sense amplifier via the bit line. These word lines, bit lines, sense amplifiers, and the like are provided inside the cell array 34. Column decoder 33 activates a column selection line of a column designated by the decode address, and connects a sense amplifier connected to the column selection line to the data bus. Data transfer is performed between the sense amplifier and the data bus amplifier & write amplifier 36 via the data bus.
[0019]
The data bus amplifier of the data bus amplifier & write amplifier 36 supplies the read data to the data input / output buffer 13 or the data input / output buffer 23 via the switch 38. Which data input / output buffer is supplied with data is controlled by which port the read data corresponds to. The data input / output buffer 13 or 23 supplies the read data to the outside of the dual port semiconductor memory device 10.
[0020]
The data input / output buffer 13 or 23 also receives data to be written from the outside. The write data is written from the write amplifier of the data bus amplifier / write amplifier 36 to the cell selected by the column line among the memory cells of the selected word via the data bus, sense amplifier, bit line and the like. Selection between the port L-port and the port R-port during the write operation is performed by the switch 37. In addition, data holding buffers 14 and 24 are provided to perform a late write operation corresponding to each of the port L-port and the port R-port.
[0021]
In the late write operation, the data and address input from the outside of the apparatus are temporarily held in the buffer, and the buffer data is written in the corresponding cell in the next write operation. That is, the data and address input from the outside of the device at a certain write operation are temporarily held in the buffer, and the data in the buffer is written to the memory cell position designated by the address in the buffer at the next write operation. Similarly, the data and address input for the write operation are held in the buffer to prepare for the next write operation. In this way, the actual write operation to the memory cell is shifted backward one by one between a series of write operations to enable access to the memory core from the beginning of the write operation cycle. The same interface can be realized.
[0022]
The refresh timing generation circuit 40 includes an oscillator 41 and a frequency divider 42. The oscillator 41 generates a periodic pulse by an oscillation operation. By dividing the generated periodic pulse, the frequency divider 42 generates a refresh activation signal every fixed refresh cycle.
[0023]
The internal address generation circuit 39 generates an address for executing the refresh operation in response to the refresh activation signal and supplies it to the address decoder 15. The refresh activation signal is supplied to the timing generator 32. The timing generator 32 generates each timing pulse for executing the refresh operation at an appropriate timing in response to the refresh activation signal, and supplies the generated timing pulse to the column decoder 33, the word decoder 35, and the like.
[0024]
As a result, it is possible to automatically generate a refresh command within the dual port semiconductor memory device 10 and periodically perform a refresh operation on the cell array 34.
[0025]
In the dual port semiconductor memory device 10 according to the present invention, when the same bank is simultaneously accessed from the port L-port and the port R-port, a Busy signal is generated and supplied to the outside. It has become.
[0026]
FIG. 2 is a diagram illustrating a configuration of the timing generator 32 with respect to Busy signal generation.
[0027]
As shown in FIG. 2, the timing generator 32 includes a plurality of timing generator units 51 provided independently for each of the plurality of banks # 0 to #n. A bank activation signal generated by the input address of the port L-port or the port R-port is input from the address decoder 15 or 25 to the timing generator unit 51 corresponding to each bank. If the core circuit is already activated in the timing generator unit 51 when the bank activation signal is supplied, the timing generator unit 51 determines that the Busy_int _L Signal or Busy_int _R Generate a signal. Generated Busy_int _L Signal or Busy_int _R The signal is supplied to the arbitration logic 31 and is output to the outside via the arbitration logic 31. The timing generator unit 51 holds the input address and activates the core immediately after the already operating core operation is completed. If the bank activation signal is continuously input from the other port, that address is also held, but it has a function such as FIFO 52 so that the previously held address is activated first. When the bank activation signal is input to the timing generator unit 51, if the bank is not activated, the core operation is started as it is.
[0028]
FIG. 3 is a configuration diagram showing a detailed configuration of the timing generator unit 51.
[0029]
The timing generator unit 51 of FIG. 3 includes a FIFO circuit 52, an R / W holding circuit 53, a latch 54, and a timing generation circuit 55.
[0030]
The FIFO circuit 52 functions as an address holding circuit, and in response to a row activation signal supplied from the command buffer 11 or 21 via the arbitration logic 31, the address decode signal supplied from the address decoder 15 or 25 is received in the order of arrival. Store. Here, the row activation signal is a signal instructing activation of a row (word), that is, execution of an access operation. The address decode signal held by the FIFO circuit 52 is supplied to the column decoder 33 and the word decoder 35. If the core circuit is already activated when the access is requested, the FIFO circuit 52 _L Signal or Busy_int _R Generate a signal.
[0031]
The R / W holding circuit 53 holds the Read / Write activation signal supplied from the command buffer 11 or 21 via the arbitration logic 31 in response to the row activation signal. The Read / Write activation signal is a signal that is activated when a Read operation or a Write operation is instructed by a command signal input from the outside. The R / W holding circuit 53 holds the access state (write state or read state) for the input address in accordance with the Read / Write activation signal. The access state held by the R / W holding circuit 53 is supplied to the timing generation circuit 55 as a signal R / W indicating the access state.
[0032]
Switches 61 and 62 are provided on the input side of the FIFO circuit 52 and the R / W holding circuit 53. The switches 61 and 62 are controlled by a left / right selection signal supplied from the arbitration logic 31. When the left side is selected, a signal corresponding to L-port is selected, and when the right side is selected, a signal corresponding to R-port. Select.
[0033]
The latch 54 is a latch circuit that holds a refresh activation signal from the refresh timing generation circuit 40. The refresh activation signal held in the latch 54 is supplied to the timing generation circuit 55.
[0034]
In response to the row activation signal, the timing generation circuit 55 generates a predetermined timing signal necessary for core activation in accordance with the access state indicated by the R / W holding circuit 53 and the refresh instruction indicated by the latch 54. The timing signals are, for example, csaz, wdz, twlz, wdrz, sbez, and wbez. The timing signal csaz is a signal that is supplied to the column decoder 33 and determines the activation and reset timing of the column line. The timing signals twlz and wdrz are signals for determining activation and reset timing of the cell array 34 such as a sense amplifier, and control the cell array 34 via the word decoder 35. The timing signal wdz is a signal that determines the activation and reset timing of the word line, and is supplied to the word decoder 35. The timing signal sbez is a signal for activating the data bus amplifier of the data bus amplifier & write amplifier 36, and the timing signal wbez is a signal for activating the write amplifier of the data bus amplifier & write amplifier 36.
[0035]
When the core operation ends, the timing generation circuit 55 supplies a signal indicating the end of the core operation to the FIFO circuit 52, the R / W holding circuit 53, and the latch. In response to the core operation end signal, the FIFO circuit 52 and the R / W holding circuit 53 output the next held content, and the latch 54 latches the state of the next refresh activation signal. That is, control is performed so that the next core operation is executed immediately after the currently executing core operation is completed.
[0036]
FIG. 4 is a diagram illustrating a configuration of the arbitration logic 31 with respect to Busy signal generation.
[0037]
The arbitration logic 31 of FIG. 4 includes a busy logic circuit 71, a busy logic circuit 72, an interrupt generation circuit 73, and a port selection circuit 74.
[0038]
The interrupt generation circuit 73 receives the address signal Address, the write enable signal / WE, the output enable signal / OE, and the chip enable signal / CE from the left and right ports, and receives the interrupt signal / INT. _L Or interrupt signal / INT _R Is generated and output to the outside. Specifically, by executing a write operation from one port to a predetermined address, the interrupt signal of the opposite port is activated. Further, when a read operation is executed for a predetermined address from the port where the interrupt signal is activated, the activated interrupt signal is reset. When interrupting from L_port to R_port, for example, by writing from L_port to the highest address, an interrupt signal / INT is sent to R_port side. _R Is generated. Further, when interrupting from R_port to L_port, for example, by writing from R_port to the address of highest-order -1 (one before the highest-order), an interrupt signal / INT is sent to the L_port side. _L Is generated.
[0039]
The port selection circuit 74 receives the chip enable signal / CE from the left and right ports, and generates a left and right selection signal according to the arrival order of the chip enable signals / CE. This left / right selection signal is supplied to the switches 61 and 62 in FIG. 3 and the switches 37 and 38 in FIG.
[0040]
The Busy logic circuit 71 includes a NAND circuit 81, an inverter 82, and an OR circuit 83. The Busy logic circuit 72 includes a NAND circuit 84, an inverter 85, and an OR circuit 86.
[0041]
In the Busy logic circuit 71 corresponding to the left port L-port, the OR circuit 83 combines Busy_int signals from a plurality of timing generator units 51 corresponding to a plurality of banks into one Busy signal. Chip enable signal / CE to left port L-port _L When this signal is asserted (LOW), this Busy signal is a negative logic signal / Busy. _L Is output from the NAND circuit 81. The operation of the Busy logic circuit 72 corresponding to the right port R-port is the same.
[0042]
FIG. 5 is a timing chart showing the operation when the same bank is accessed from both the left and right ports.
[0043]
The address on the first arrival port side (R-port side) is # 1, and the address on the second arrival port side (L-port side) is # 2. As shown in FIG. 5 as “Core operation”, the core operation is executed in the order of # 1, # 2 without any interval. Here, “corresponding BL pair” indicates the activation state of the corresponding bit line. The data read in the core operation for address # 1 is Dout _R Is output to the first arrival port side (R-port side). Also, the data read by the core operation for address # 2 is Dout _L Is output to the later arrival port side (L-port side).
[0044]
Since the core is already operating for address # 1 when address # 2 for L-port is input, a busy signal is output to the later port (/ Busy). _L = LOW). After the core operation related to the first arrival port is completed, the busy signal on the second arrival port side is canceled (/ Busy _L = HIGH).
[0045]
FIG. 6 is a timing chart showing an operation in the case where access to the same bank from both the left and right ports and refresh are executed substantially simultaneously.
[0046]
In this example, a case where refresh to address # 0 is performed prior to access from both ports is shown. When the address # 1 is input to the first arrival port side (R-port side), since the core is already operating for the refresh address # 0, a busy signal is output to the first arrival port (/ Busy _R = LOW). Furthermore, when address # 2 is input to the opposite port (L-port side), there is an access waiting in response to that the core is operating for refresh address # 0 or already. In response to this, a busy signal is output to the later arrival port (/ Busy _L = LOW). Immediately after the refresh operation is completed, the core starts accessing the first port (address # 1) and simultaneously releases the busy signal of the first port (R-port). Furthermore, the operation of the late arrival port (address # 2) is started immediately after the operation of address # 1 is completed. The timing for releasing the busy signal at the last port (L-port) may be a certain time after the busy signal at the first port is released. Alternatively, the timing of releasing the busy signal at the later port may be when the core operation of the first port is completed.
[0047]
FIG. 7 is a timing diagram showing an operation when a refresh operation is requested during the core operation.
[0048]
As described above, the refresh activation signal Ref-Act is generated by the refresh timing generation circuit 40 at regular intervals, and the refresh address to be subjected to the refresh operation is generated by the internal address generation circuit 39. If the core operation is not performed in the same bank as the address to be refreshed when the refresh operation is requested, the refresh operation is immediately started. In the operation example of FIG. 7, when the refresh activation signal Ref-Act is generated for the address # 0, the core operation for the same bank is already being executed for the address # 1. In this case, the refresh operation is performed immediately after the already performed core operation.
[0049]
At this time, the refresh address is supplied from the address decoder 15 on the L-port side as shown in FIG. Therefore, the timing generator 32 uses the Busy_int on the L-port side. _L A signal will be generated. However, since the chip enable signal / CE is not asserted at this time on the L-port side, the busy signal / Busy _L Is not output outside the device.
[0050]
As described above, in the present invention, when an access is requested to the same bank as the core in operation, a busy signal is output to the port to which the request is input. By this busy signal notification function, it is possible to determine that the semiconductor memory device is in a standby state.
[0051]
In the present invention, attention is paid to a word line group related to sense amplifiers that are simultaneously activated, and a memory array portion composed of the word line group is referred to as a bank.
[0052]
FIG. 8 is a diagram showing various bank configurations. In FIG. 8, the sense amplifier is indicated by S / A. A straight line extending in the horizontal direction connected to the sense amplifier S / A is a bit line, and a straight line extending in the vertical direction intersecting the bit line is a word line. A memory cell is arranged at the intersection of the word line and the bit line. Note that the word lines WL are usually repeated in units of four, and are arranged as 128, 256, 512, etc., and therefore, in FIG. Actually, a large number of WLs exist in a region sandwiched between sense amplifiers.
[0053]
In FIG. 8A, the sense amplifier rows indicated by bold lines are activated simultaneously. The word line groups related to these sense amplifier columns are a cell array sandwiched between two sense amplifier columns indicated by bold lines, and a cell array adjacent to both sides of the sense amplifier strings indicated by bold lines. Therefore, in this case, a region surrounded by a dotted line is a bank.
[0054]
In FIG. 8B, since sense amplifiers are not shared between adjacent cell arrays, the sense amplifiers activated at the same time are only the sense amplifier rows indicated by bold lines. A related word line group is a cell array sandwiched between two sense amplifier rows indicated by bold lines. Therefore, in this case, a region surrounded by a dotted line is a bank.
[0055]
In FIG. 8C, the sense amplifier is shared between adjacent cell arrays. However, since the connection between the bit line and the word line is different from the case of FIG. 8A, the word line group related to the sense amplifier indicated by the bold line is the two word lines at both ends of the cell array on both sides sandwiching the sense amplifier row. It is. Therefore, in this case, a word line group indicated by a bold line is a bank unit.
[0056]
In FIG. 8D, the connection method between the bit line and the sense amplifier is the same as in FIG. 8C, but the sense amplifier row is not shared between adjacent cell arrays. In this case, two word lines indicated by bold lines serve as a bank unit for the sense amplifier rows indicated by bold lines that are simultaneously activated.
[0057]
As described above, in the present invention, a bank is not defined as a partition or a group of parts on a cell array, but is defined as a group of word lines related to sense amplifiers that are simultaneously activated.
[0058]
In the above embodiment, the case where two ports L_port and R_port are provided has been described. However, in the present invention, the number of ports is not limited to two. In the case of three or more ports, it is possible to apply the configuration of the above embodiment with a slight modification, and such a configuration is also intended to be within the scope of the present invention. .
[0059]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
【The invention's effect】
The semiconductor memory device according to the present invention is configured to output a busy signal to the port to which a request has been input when access is requested to the same bank as the bank in which the core is operating. By this busy signal notification function, it is possible to determine that the semiconductor memory device is in a standby state.
[0060]
The semiconductor memory device according to the present invention further includes a refresh timing generation circuit for internally designating the timing of the refresh operation for the cell array, thereby automatically generating a refresh command inside the device and periodically for the cell array. A refresh operation can be executed.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a configuration of a dual port semiconductor memory device according to the present invention.
FIG. 2 is a diagram illustrating a configuration of a timing generator with respect to Busy signal generation.
FIG. 3 is a configuration diagram showing a detailed configuration of a timing generator unit.
FIG. 4 is a diagram showing a configuration of arbitration logic with respect to Busy signal generation.
FIG. 5 is a timing chart showing an operation when the same bank is accessed from both the left and right ports;
FIG. 6 is a timing chart showing an operation when access to the same bank from both the left and right ports and refresh are executed substantially simultaneously.
FIG. 7 is a timing chart showing an operation when a refresh operation is requested during a core operation.
FIG. 8 is a diagram showing various bank configurations;
[Explanation of symbols]
10 Dual port semiconductor memory device
11 Command buffer
12 Address buffer
13 Data input / output buffer
14 Data holding buffer
15 Address decoder
21 Command buffer
22 Address buffer
23 Data input / output buffer
24 Data holding buffer
25 Address decoder
31 Arbitration logic
32 Timing Generator
33 Column decoder
34 Cell array
35 word decoder
36 Data Bus Amplifier & Write Amplifier
37, 38 switches
39 Internal address generation circuit
40 Refresh timing generation circuit

Claims (9)

A cell array including a plurality of banks including a plurality of volatile memory cells , a plurality of word lines, and a plurality of sense amplifiers, each bank being defined as a part of a group of word lines related to sense amplifiers that are activated simultaneously ;
A column decoder provided in common to the plurality of banks;
A data bus connected to the sense amplifier of the column selected by the column decoder;
A plurality of external ports each capable of accessing an independent address to the cell array via the data bus ;
An arbitration circuit for determining an access order between the plurality of external ports;
Control that outputs a busy signal to the port that requested the access when the one bank is executing a core operation when an access request is made from one port of the plurality of external ports to one bank of the cell array A semiconductor memory device including a circuit, wherein a plurality of access operations requested from the plurality of external ports are sequentially executed in an order determined by the arbitration circuit regardless of the presence or absence of the busy signal. The control circuit includes a separate timing circuit for controlling the timing of the core operation for each of the plurality of banks, and determines whether or not a bank corresponding to each timing circuit is operating in the core. The semiconductor memory device according to claim 1. 3. The semiconductor memory device according to claim 2, wherein the timing circuit includes a FIFO circuit that holds and outputs addresses in the order of arrival. 2. The semiconductor memory device according to claim 1, further comprising a refresh timing generation circuit for internally designating a refresh operation timing for the cell array. 5. The semiconductor device according to claim 4, wherein when the one bank is executing a core operation, the one bank includes a case where the one bank is executing a refresh operation at a timing designated by the refresh timing generation circuit. Storage device. The control circuit performs a core operation when a refresh operation is performed on one bank of the cell array at a timing specified by the refresh timing generation circuit, and when a bank targeted for the refresh operation is performing a core operation. 5. The semiconductor memory device according to claim 4, wherein the refresh operation is executed after the process is completed. 2. The semiconductor memory device according to claim 1, wherein the control circuit outputs an interrupt signal to the second port in response to a request from the first port of the plurality of external ports. 8. The semiconductor device according to claim 7, wherein the control circuit outputs the interrupt signal to the second port in response to a write operation from the first port to a predetermined address of the cell array. Storage device. 8. The semiconductor according to claim 7, wherein the control circuit deactivates the interrupt signal to the second port in response to a read operation for the predetermined address from the second port. Storage device.

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