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WO2011092910A1 - Power amplifier - Google Patents

Power amplifier Download PDF

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Publication number
WO2011092910A1
WO2011092910A1 PCT/JP2010/068908 JP2010068908W WO2011092910A1 WO 2011092910 A1 WO2011092910 A1 WO 2011092910A1 JP 2010068908 W JP2010068908 W JP 2010068908W WO 2011092910 A1 WO2011092910 A1 WO 2011092910A1
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WO
WIPO (PCT)
Prior art keywords
amplifier
bias
inductor
amplifiers
impedance
Prior art date
Application number
PCT/JP2010/068908
Other languages
French (fr)
Japanese (ja)
Inventor
俊二 吉見
真悟 柳原
和幸 渡辺
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2011092910A1 publication Critical patent/WO2011092910A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

Definitions

  • the present invention relates to a power amplifier that amplifies a high frequency signal of, for example, several tens of MHz or more.
  • a power amplifier that is provided in a wireless communication device such as a mobile phone and can amplify a high-frequency signal is known (for example, see Patent Document 1).
  • a power amplifier is provided with a bias circuit for supplying a bias voltage.
  • a 1/4 wavelength series inductance and a 1/4 wavelength open stub are provided between the bias power source and the amplifier, and the bias circuit is made high frequency. Opened.
  • the 1/4 wavelength series inductance etc. is frequency dependent, when a wideband signal is amplified even within the same communication frequency band, the bias circuit is not necessarily opened at a high frequency for the signal. I can't.
  • multiband power amplifiers that amplify signals over a plurality of communication frequency bands tend to be susceptible to bias circuits.
  • the present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a power amplifier capable of suppressing the influence of a bias circuit.
  • the present invention is a multiband power amplifier that amplifies a signal of one communication frequency among a plurality of communication frequency bands based on frequency setting information transmitted from a base station.
  • a plurality of amplifiers connected in series with each other, and a bias circuit connected to at least one of the plurality of amplifiers to supply a bias voltage from a bias power supply, and at least one of the plurality of amplifiers includes At least one bias circuit connected is connected between an amplifier connected to the bias circuit and the bias power supply, and a connection point between the inductor and the bias power supply and a ground.
  • the inductor is formed by winding a thick and short winding made of a conductor material around a ferrite core. Made which are characterized in that the direct current resistance is small, and which is the all large chip coil impedance at the communication frequency band.
  • the bias circuit since the bias circuit includes the inductor connected between the amplifier and the bias power supply, when one communication frequency is specified from among a plurality of communication frequency bands by the frequency setting information, The bias circuit can be opened by increasing the impedance of the inductor with respect to the signal of the communication frequency.
  • the inductor since the inductor is constituted by a chip coil in which a winding is wound around a ferrite core, the number of windings can be reduced by forming the winding with a thick wire.
  • the chip coil can use a thicker and shorter winding compared to, for example, the one without the ferrite core, and can reduce the DC resistance and increase the impedance in all communication frequency bands.
  • the bias circuit can be opened in high frequency using a small chip coil.
  • the DC resistance of the inductor is 1 ⁇ or less, and the impedance in all the communication frequency bands is 200 ⁇ or more.
  • the direct current resistance of the inductor is 1 ⁇ or less, a large current can be supplied to the amplifier through the inductor.
  • the impedance of the inductor is set to 200 ⁇ or higher in all communication frequency bands, for example, it can be set to a sufficiently large value compared with the output impedance of the transistor used in the amplifier, and the influence of the bias circuit can be suppressed.
  • the present invention is a single-band power amplifier that amplifies a signal of one communication frequency in a communication frequency band based on frequency setting information transmitted from a base station, and a plurality of amplifiers connected in series with each other;
  • a bias circuit connected to at least one amplifier of the plurality of amplifiers and supplying a bias voltage from a bias power supply, and at least one bias circuit connected to at least one amplifier of the plurality of amplifiers,
  • An inductor connected between an amplifier to which a bias circuit is connected and the bias power supply, and a bypass capacitor connected between a connection point of the inductor and the bias power supply and a ground,
  • the ferrite core is made by winding a thick and short winding made of a conductive material, has a low DC resistance, and is It is characterized in that the impedance at the communication frequency band is large chip coil.
  • the bias circuit since the bias circuit includes the inductor connected between the amplifier and the bias power source, when one communication frequency in the communication frequency band is specified by the frequency setting information, the one communication By increasing the impedance of the inductor with respect to the frequency signal, the bias circuit can be opened.
  • the inductor is constituted by a chip coil in which a winding is wound around a ferrite core, the number of windings can be reduced by forming the winding using a thick wire.
  • the chip coil can use a thicker and shorter winding compared to, for example, the one without the ferrite core, and can reduce the DC resistance and increase the impedance in the communication frequency band.
  • the bias circuit can be opened in high frequency using a small chip coil.
  • the inductor has a DC resistance of 1 ⁇ or less and an impedance in the communication frequency band of 200 ⁇ or more.
  • the direct current resistance of the inductor is 1 ⁇ or less, a large current can be supplied to the amplifier through the inductor.
  • the impedance of the inductor is set to 200 ⁇ or more in the communication frequency band, for example, it can be set to a sufficiently large value compared to the output impedance of the transistor used in the amplifier, and the influence of the bias circuit can be suppressed.
  • FIG. 1 and FIG. 2 show a first embodiment.
  • a wireless communication device 1 includes a transmission device 2, first and second duplexers 3 and 4, first and second reception devices 5 and 6, a diplexer 7, an antenna 8, and the like.
  • the transmission device 2 includes a multiband power amplifier 11 to be described later, and selects and outputs one of the first and second transmission signals TX1 and TX2. Then, the transmission device 2 outputs the first transmission signal TX1 to the first duplexer 3, and outputs the second transmission signal TX2 to the second duplexer 4.
  • the first transmission signal TX1 is transmitted at any frequency belonging to the first transmission frequency band (“824 to 849 MHz” or “824 to 830 MHz”) according to the US-Cellular system, for example.
  • the second transmission signal TX2 is transmitted at any frequency belonging to the second transmission frequency band (898 to 925 MHz) according to the J-CDMA system, for example.
  • the first and second transmission signals TX1, TX2 are signals in different communication frequency bands.
  • the communication frequencies f1 1 to f1 m related to the first transmission signal TX1 and the communication frequencies f2 1 to f2 related to the second transmission signal TX2 are determined by the frequency setting information Sp transmitted from the base station BS to the wireless communication device 1.
  • a specific communication frequency of the transmission signal is set from n .
  • the transmission device 2 is configured to transmit a signal having any one of (m + n) types of communication frequencies obtained by adding the communication frequencies f1 1 to f1 m and the communication frequencies f2 1 to f2 n. Yes.
  • the number of types (m types) of communication frequencies f1 1 to f1 m related to the first transmission signal TX1 and the number of types (n types) of communication frequencies f2 1 to f2 n related to the second transmission signal TX2 The numbers may be different from each other or the same number.
  • the first duplexer 3 is connected to the output side of the transmission device 2 and the input side of the first reception device 5, and is connected to the antenna 8 via the diplexer 7.
  • the second duplexer 4 is connected to the output side of the transmission device 2 and the input side of the second reception device 6, and is connected to the antenna 8 via the diplexer 7.
  • the diplexer 7 connects the antenna 8 to the first duplexer 3 when performing US-Cellular communication, and connects the antenna 8 to the second duplexer 4 when performing J-CDMA communication.
  • the power amplifier 11 includes, for example, amplifiers 12 and 13 composed of two stages of heterojunction bipolar transistors, an interstage matching circuit 14 provided between the amplifiers 12 and 13, and an input stage (driver stage).
  • the input stage matching circuit 15 provided on the input side of the amplifier 12
  • the output stage matching circuit 16 provided on the output side of the amplifier 13 in the output stage (final stage), the interstage matching circuit 14, and the input stage matching.
  • a control circuit 17 that controls impedance values Zm, Zi, and Zo of the circuit 15 and the output stage matching circuit 16 and bias circuits 18 and 21 are provided.
  • the amplifiers 12 and 13 are used to amplify signals in both the communication frequency bands of the first and second transmission signals TX1 and TX2 and obtain a gain over a wide band of, for example, 100 MHz or more.
  • the impedance value Zm of the interstage matching circuit 14 is set by the control circuit 17 described later, and impedance matching between the amplifiers 12 and 13 is achieved according to the first and second transmission signals TX1 and TX2. Specifically, the impedance value Zm of the interstage matching circuit 14 is adjusted to an optimum value so as to obtain a desired characteristic according to the control signal output from the control circuit 17. At this time, the optimum value of the impedance value Zm is a state in which distortion is reduced from the amplifier 13 at the output stage using a method called predistortion, for example, when the first and second transmission signals TX1 and TX2 are input. The first and second transmission signals TX1 and TX2 amplified in step 1 are obtained.
  • the predistortion will be described in detail.
  • the amplifiers 12 and 13 are used at an operating point close to a gain saturation point in order to improve power efficiency.
  • the amplifiers 12 and 13 have (1) distortion of amplitude component called input amplitude / output amplitude nonlinearity (AM / AM) and (2) input as the output power approaches the saturation power.
  • a distortion of a phase component called amplitude / output phase nonlinearity (AM / PM) occurs.
  • an interstage matching circuit 14 is provided between the amplifier 12 and the amplifier 13 so that the nonlinear distortion generated in the amplifier 12 at the front stage and the amplifier 13 at the rear stage have opposite characteristics. The impedance is adjusted. As a result, non-linear distortion generated in the front-stage amplifier 12 and the rear-stage amplifier 13 is canceled, and the transmission signal is amplified with low distortion.
  • the amplitude component distortion and the phase component distortion of the amplifiers 12 and 13 are different for the communication frequencies f1 1 to f1 m and f2 1 to f2 n related to the first and second transmission signals TX1 and TX2, respectively.
  • the impedance value Zm of the interstage matching circuit 14 is set according to the control signal output from the control circuit 17, and the communication frequencies f1 1 to f1 m , related to the first and second transmission signals TX1 and TX2 are set. Adjustment is made for each of f2 1 to f2 n .
  • the impedance value Zi of the input stage matching circuit 15 is set by the control circuit 17 described later. Specifically, the input stage matching circuit 15 adjusts the impedance value Zi to an optimum value so as to obtain a desired characteristic according to the control signal output from the control circuit 17. Thereby, impedance matching between the amplifier 12 and the input load ZLi connected to the input side thereof is achieved according to the first and second transmission signals TX1 and TX2.
  • the input load ZLi is a circuit connected to the input side of the amplifier 12, and is configured by, for example, a modulation circuit that generates first and second transmission signals TX1 and TX2, a baseband processing circuit, and the like.
  • the output stage matching circuit 16 has its impedance value Zo set by the control circuit 17 described later. Specifically, like the input stage matching circuit 15, the output stage matching circuit 16 has an optimum impedance value Zo so that desired characteristics can be obtained according to the control signal output from the control circuit 17. Adjusted to Thereby, impedance matching between the amplifier 13 and the output load ZLo connected to the output side is achieved in accordance with the first and second transmission signals TX1 and TX2.
  • the output load ZLo is composed of, for example, first and second duplexers 3 and 4, a diplexer 7 and an antenna 8 connected to the output side of the amplifier 13.
  • the control circuit 17 controls the impedance values Zm, Zi, Zo of the interstage matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit 16 according to the frequency setting information Sp input to the control circuit 17. Specifically, the control circuit 17 outputs, for example, a digital control signal (bit signal) corresponding to the frequency setting information Sp.
  • the impedance values Zm, Zi, Zo of the interstage matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit 16 are variable, so that the first and second transmission signals TX1, TX2 have desired characteristics. Is set.
  • Desired characteristics include, for example, reducing the nonlinear distortion of the first and second transmission signals TX1 and TX2 as much as possible. For this reason, the control circuit 17 sets the impedance value Zm of the interstage matching circuit 14 so as to cancel the non-linear distortion. Further, the control circuit 17 sets the impedance value Zi of the input stage matching circuit 15 so that the impedance is most matched between the amplifier 12 and the input load ZLi, and the impedance between the amplifier 13 and the output load ZLo. Is set so that the impedance value Zo of the output stage matching circuit 16 is the most matched.
  • the bias circuit 18 is connected to the output terminal of the amplifier 12 and supplies a bias voltage Vdd to the amplifier 12.
  • the bias circuit 18 includes an inductor 19 connected between the amplifier 12 and the bias power supply VB, and a bypass capacitor 20 connected between a connection point between the inductor 19 and the bias power supply VB and the ground. ing.
  • the bias circuit 18 is open at high frequencies with respect to the first and second transmission signals TX1, TX2.
  • the bias circuit 21 is connected to the output terminal of the amplifier 13 and supplies a bias voltage Vdd to the amplifier 13.
  • the bias circuit 21 is connected between an inductor 22 connected between the amplifier 13 and the bias power source VB, and a connection point between the inductor 22 and the bias power source VB and the ground, almost like the bias circuit 18.
  • a bypass capacitor 23 is open at high frequencies at all the communication frequencies f1 1 to f1 m and f2 1 to f2 n of the first and second transmission signals TX1 and TX2.
  • the inductor 22 is constituted by a chip coil 24 in which a winding 24B made of a conductor material such as copper is wound around a ferrite core 24A made of a ferrite material.
  • the ferrite core 24A of the chip coil 24 includes a pair of leg portions 24C located on both ends, and the leg portions 24C are provided with external electrodes 24D. Then, both ends of the winding 24B are connected to the pair of external electrodes 24D, respectively.
  • a coating 24E made of an insulating resin material is provided on the upper surface of the ferrite core 24A opposite to the leg 24C, and the coating 24E covers the upper surfaces of the ferrite core 24A and the winding 24B. Also good.
  • the amplifier 13 at the final stage among the amplifiers 12 and 13 tends to flow the largest current. For this reason, in order to supply a large direct current to the amplifier 13, the direct current resistance Rdc of the inductor 22 of the bias circuit 21 should be as small as possible.
  • a communication frequency band for example, 800 MHz to 2 GHz
  • product number LQW18CNR10K00L manufactured by Murata Manufacturing Co., Ltd. can be applied as the chip coil 24, for example.
  • the impedance Z of the chip coil 24 has frequency characteristics shown in FIG. 6, for example.
  • the bias circuit 21 can be opened in high frequency with respect to signals of all the communication frequencies f1 1 to f1 m and f2 1 to f2 n using the small chip coil 24.
  • the wireless communication device 1 has the above-described configuration, and the operation thereof will be described next.
  • the baseband signal is modulated into the high-frequency first transmission signal TX1 according to the frequency setting information Sp, and the first transmission signal TX1 is output.
  • the multiband power amplifier 11 amplifies the first transmission signal TX1 and outputs it to the first duplexer 3.
  • the first transmission signal TX1 after power amplification is supplied to the antenna 8 via the duplexer 3 and the diplexer 7, and is transmitted from the antenna 8 to the outside.
  • the baseband signal is modulated into the high-frequency second transmission signal TX2 according to the frequency setting information Sp, and the second transmission signal TX2 is output.
  • the multiband power amplifier 11 amplifies the second transmission signal TX2 and outputs it to the second duplexer 4.
  • the second transmission signal TX2 after power amplification is transmitted to the outside via the duplexer 4, the diplexer 7, and the antenna 8.
  • the weak reception signal RX 1 received from the antenna 8 is sent to the first reception device 5 via the diplexer 7 and the duplexer 3.
  • the reception signal RX2 is sent to the second reception device 6 via the diplexer 7 and the duplexer 4.
  • the received signals RX1 and RX2 are double-tuned into baseband signals by the first and second receiving devices 5 and 6.
  • the inductors 19 and 22 are connected between the amplifiers 12 and 13 and the bias power source VB, any of the first and second transmission signals TX1 and TX2 is detected.
  • the bias circuits 18 and 21 can be opened in high frequency.
  • the bias circuit 21 connected to the amplifier 13 through which a large current flows is constituted by a chip coil 24 in which the inductor 22 is wound around a ferrite core 24A and a winding 24B. For this reason, compared with the case where the ferrite core 24A is omitted, the thick and short winding 24B can be used, and the total number of the windings 24B can be shortened by reducing the number of turns of the winding 24B.
  • the chip coil 24 has a DC resistance Rdc of 1 ⁇ or less and an impedance Z of 200 ⁇ at all communication frequencies f1 1 to f1 m and f2 1 to f2 n related to the first and second transmission signals TX1 and TX2. This can be done. As a result, a large current can be supplied to the amplifier 13 through the inductor 22, and the bias circuit 21 can be opened in a high frequency using the small chip coil 24, and the power amplifier 11 as a whole can be downsized. be able to.
  • the control circuit 17 interstages according to the communication frequencies f1 1 to f1 m and f2 1 to f2 n related to the first and second transmission signals TX1 and TX2 specified by the frequency setting information Sp.
  • the impedance values Zm, Zi, Zo of the matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit 16 are controlled.
  • impedance matching can be achieved at each of the communication frequencies f1 1 to f1 m and f2 1 to f2 n .
  • the bias circuits 18 and 21 are opened in high frequency with respect to the signals 1 to f2 n . Therefore, even when the bias circuits 18 and 21 are connected to the interstage matching circuit 14, the input stage matching circuit 15, or the output stage matching circuit 16 through the amplifiers 12 and 13, the bias circuits are connected to the matching circuits 14 to 16. The influence of the impedances 18 and 21 can be reduced, and each of the matching circuits 14 to 16 can maintain the optimum state set by the control circuit 17.
  • the impedance values Zm, Zi, and Zo of the interstage matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit 16 are controlled by the control circuit 17, the amplifiers 12 and 13 and the input side and output side are controlled.
  • the efficiency of the amplifiers 12 and 13 and the distortion of the first and second transmission signals TX1 and TX2 can be preferentially improved.
  • the first and second transmission signals TX1 and TX2 having desired characteristics are output using the amplifiers 12 and 13 regardless of what first and second transmission signals TX1 and TX2 are input. can do.
  • the control circuit 17 is configured to control the impedance value Zm of the interstage matching circuit 14 together with the impedance values Zi and Zo of the input stage matching circuit 15 and the output stage matching circuit 16. For this reason, not only the input side and output side of the power amplifier 11, but also inside the power amplifier 11, impedance matching between the amplifiers 12 and 13 can be achieved according to the first and second transmission signals TX1 and TX2. As a result, for example, attenuation and reflection of the first and second transmission signals TX1 and TX2 can be prevented, noise can be suppressed, and the output levels of the first and second transmission signals TX1 and TX2 can be increased. it can.
  • the desired characteristic is the characteristic that reduces the nonlinear distortion of the first and second transmission signals TX1, TX2. For this reason, the control circuit 17 sets the impedance value Zm of the interstage matching circuit 14 so as to cancel the non-linear distortion.
  • Desired characteristics include, for example, when the output levels of the first and second transmission signals TX1 and TX2 are maximized, between the amplifiers 12 and 13, the input side, and the output side.
  • the impedance values Zm, Zi, and Zo of the interstage matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit 16 may be set so that the impedances are most matched with each other. Further, as a desired characteristic, the amplifiers 12 and 13 may be configured to operate at maximum efficiency.
  • the optimum values of the impedance values Zm, Zi, and Zo are determined with priority given to any one of the characteristics, for example. Is.
  • the interstage matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit. 16 may be configured to be shifted from a value that maximizes the output level by the impedance value Zo of the output stage matching circuit 16, that is, a value that has the highest matching.
  • the interstage matching circuit provided between the amplifier through which the largest current flows (for example, the amplifier at the final stage) and the amplifier at the preceding stage has a desired characteristic.
  • a configuration in which priority is given to the reduction of nonlinear distortion, and another interstage matching circuit may be configured to give priority to impedance matching between amplifiers in order to maximize the output level as a desired characteristic.
  • an interstage matching circuit When three or more amplifiers are connected in series, there is no need to provide an interstage matching circuit between all amplifiers. For example, the amplifier having the highest amplification factor (for example, the final stage amplifier) and the preceding stage amplifier are not required.
  • An interstage matching circuit may be provided only between the amplifier and the amplifier. Furthermore, even when a plurality of interstage matching circuits are provided, it is not necessary to variably control the impedance values of all the interstage matching circuits. For example, the interstage matching circuit connected to the amplifier having the largest amplification factor. The impedance value may be variably controlled, and the impedance values of other interstage matching circuits may be fixed.
  • the power amplifier 11 is applied to the dual-band transmission device 2 that outputs the first and second transmission signals TX1 and TX2 in two communication frequency bands. You may apply to the transmitter which outputs the transmission signal of the above communication frequency band.
  • the first and second transmission signals TX1 and TX2 are configured to use signals in the 800 MHz band, for example, signals in other communication frequency bands such as 1.5 GHz band, 1.7 GHz band, and 2 GHz band are used. It is good also as a structure.
  • FIG. 7 and FIG. 8 show a second embodiment of the present invention.
  • a feature of this embodiment is that a bias circuit composed of a chip coil is applied to a single-band power amplifier whose communication frequency band is specified in advance.
  • the wireless communication device 31 includes a transmission device 32, a duplexer 33, a reception device 34, an antenna 35, and the like.
  • the transmission device 32 includes a single-band power amplifier 41, which will be described later, and is connected to a duplexer 33.
  • the transmission device 32 generates a transmission signal TX in a high-frequency communication frequency band of, for example, 800 MHz or higher, and outputs the transmission signal TX toward the duplexer 33.
  • the transmission signal TX is composed of, for example, a J-CDMA system signal and has a transmission frequency band of 898 to 925 MHz.
  • the transmission apparatus 32 outputs the transmission signal TX according to the pilot signal including the frequency setting information Sp transmitted from the base station BS.
  • the pilot signal specifies a specific communication frequency of the transmission signal TX among the communication frequencies f 1 to f n included in the range of the transmission frequency band.
  • the transmission device 32 is configured to transmit a signal of any one frequency among, for example, n types of communication frequencies f 1 to f n .
  • the duplexer 33 is connected to the output side of the transmission device 32 and the input side of the reception device 34 and to the antenna 35.
  • the transmission device 32 modulates the baseband signal into a high-frequency transmission signal TX, amplifies the transmission signal TX using the power amplifier 41, and transmits the signal from the antenna 35 to the outside. To do.
  • the reception signal RX received from the antenna 35 is sent to the reception device 34 via the duplexer 33.
  • the receiving device 34 multiplies the received signal RX into a baseband signal.
  • the power amplifier 41 is provided in the transmission device 32 and amplifies the transmission signal TX. Further, as shown in FIG. 8, the power amplifier 41 includes amplifiers 42 and 43 composed of, for example, two stages of heterojunction bipolar transistors, an interstage matching circuit 44 provided between the amplifiers 42 and 43, and an input stage ( The input stage matching circuit 45 provided on the input side of the amplifier 42 of the driver stage), the output stage matching circuit 46 provided on the output side of the amplifier 43 of the output stage (final stage), the interstage matching circuit 44, and the input A control circuit 47 that controls impedance values Zm, Zi, and Zo of the stage matching circuit 45 and the output stage matching circuit 46, and bias circuits 48 and 51 are provided.
  • amplifiers 42 and 43 composed of, for example, two stages of heterojunction bipolar transistors
  • an interstage matching circuit 44 provided between the amplifiers 42 and 43
  • an input stage The input stage matching circuit 45 provided on the input side of the amplifier 42 of the driver stage
  • the output stage matching circuit 46 provided on the output side of the amplifier 43 of the output stage
  • the interstage matching circuit 44 has its impedance value Zm set by a control circuit 47 to be described later, and performs impedance matching between the amplifiers 42 and 43 in accordance with the transmission signal TX. Specifically, the interstage matching circuit 44 cancels the non-linear distortion generated in the front-stage amplifier 42 and the rear-stage amplifier 43 by, for example, predistortion, similarly to the interstage matching circuit 14 according to the first embodiment. To do. For this reason, the impedance value Zm of the interstage matching circuit 44 is adjusted by the control circuit 47 to an optimum value at which the amplified transmission signal TX can be obtained in a state where distortion is reduced from the amplifier 43 at the output stage by predistortion.
  • the impedance value Zi of the input stage matching circuit 45 is set by the control circuit 47 described later. Specifically, like the input stage matching circuit 15 according to the first embodiment, the input stage matching circuit 45 is connected to the amplifier 42 with respect to the transmission signal TX according to the control signal output from the control circuit 47.
  • the impedance value Zi is adjusted to an optimum value so as to achieve impedance matching with the input load ZLi connected to the input side.
  • the input load ZLi is configured as a circuit connected to the input side of the amplifier 42, for example, a modulation circuit that generates a transmission signal TX, a baseband processing circuit, or the like.
  • the impedance value Zo of the output stage matching circuit 46 is set by a control circuit 47 described later. Specifically, similarly to the output stage matching circuit 16 according to the first embodiment, the output stage matching circuit 46 is connected to the amplifier 43 with respect to the transmission signal TX according to the control signal output from the control circuit 47.
  • the impedance value Zo is adjusted to an optimum value so as to achieve impedance matching with the output load ZLo connected to the output side.
  • the output load ZLo is constituted by, for example, a duplexer 33, an antenna 35, and the like connected to the output side of the amplifier 43.
  • the control circuit 47 receives the frequency setting information Sp and controls the impedance values Zm, Zi, Zo of the interstage matching circuit 44, the input stage matching circuit 45, and the output stage matching circuit 46 according to the frequency setting information Sp. Specifically, like the control circuit 17 according to the first embodiment, the control circuit 47 outputs, for example, a digital control signal (bit signal) corresponding to the frequency setting information Sp, and the interstage matching circuit 44. The impedance values Zm, Zi, Zo of the input stage matching circuit 45 and the output stage matching circuit 46 are changed.
  • the control circuit 47 allows the interstage matching circuit to obtain a desired characteristic according to the transmission signal TX. 44, the impedance values Zm, Zi, Zo of the input stage matching circuit 45 and the output stage matching circuit 46 are set to optimum values.
  • the bias circuit 48 is connected to the amplifier 42 and supplies a bias voltage Vdd to the amplifier 42.
  • the bias circuit 48 includes an inductor 49 connected between the amplifier 42 and the bias power supply VB, and a bypass capacitor 50 connected between a connection point between the inductor 49 and the bias power supply VB and the ground. ing.
  • the bias circuit 48 is open at a high frequency with respect to the transmission signal TX.
  • the bias circuit 51 is connected to the amplifier 43 and supplies a bias voltage Vdd to the amplifier 43.
  • the bias circuit 51 includes an inductor 52 connected between the amplifier 43 and the bias power source VB, and a terminal on the bias power source VB side of both ends of the inductor 52 and the ground. And a bypass capacitor 53 connected thereto.
  • the bias circuit 51 is open at high frequencies with respect to the transmission signals TX of all the communication frequencies f 1 to f n .
  • the chip coil 54 is formed in substantially the same manner.
  • the present embodiment can provide the same operational effects as those of the first embodiment.
  • the bias circuits 48 and 51 include inductors 49 and 52 connected between the amplifiers 42 and 43 and the bias power supply VB side, the transmission signal TX of the communication frequencies f 1 to f n is provided.
  • the impedances of the inductors 49 and 52 can be increased to open the bias circuits 48 and 51 in terms of high frequency.
  • the bias circuit 51 connected to the amplifier 43 through which a large current flows is formed by using the chip coil 54 having the DC resistance Rdc of 1 ⁇ or less and the impedance Z of 200 ⁇ or more in the communication frequency band. Therefore, a large current can be supplied to the amplifier 43 through the inductor 52, and the bias circuit 51 can be opened in a high frequency using a small chip coil 54, so that the entire power amplifier 41 is downsized. be able to.
  • the transmission signal TX is configured to use an 800 MHz band signal.
  • a signal in another communication frequency band such as a 1.5 GHz band, a 1.7 GHz band, or a 2 GHz band is used. It is good also as a structure.
  • the bias circuits 18, 21, 48, 51 are connected to the plurality of amplifiers 12, 13, 42, 43, respectively.
  • the present invention is not limited to this.
  • the bias circuits 21 and 51 are connected to only the final stage amplifiers 13 and 43 through which the largest current flows among the plurality of amplifiers 12, 13, 42, and 43.
  • the bias circuits 18 and 48 connected to the amplifiers 12 and 42 may be omitted.
  • the inductors 22 and 52 of the bias circuits 21 and 51 connected to the final stage amplifiers 13 and 43 through which the largest current flows among the plurality of amplifiers 12, 13, 42, and 43 are provided.
  • the chip coils 24 and 54 are used.
  • the present invention is not limited to this.
  • the inductors 19 and 49 of the bias circuits 18 and 48 connected to the amplifier 12 on the front stage side may be configured by using the chip coils 24 and 54, and a plurality of amplifiers 12.
  • 13, 42, 43, the inductors 19, 22, 49, 52 of the bias circuits 18, 21, 48, 51 may be configured using chip coils 24, 54.
  • the case where the power amplifiers 11 and 41 are applied to the wireless communication devices 1 and 31 has been described as an example.
  • a device that amplifies a high-frequency signal such as a wireless LAN device, for example. It can be widely applied to.

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Abstract

To amplifiers (12 and 13) of a power amplifier (11), bias circuits (18 and 21) are connected. In addition, upon the bias circuit (21) connected to the amplifier (13), an indictor (22) constituted by a chip coil (24) is provided. The chip coil (24) is formed by winding a thick and short winding wire (24B) around a ferrite core (24A). Therefore, the chip coil (24) has a DC resistance (Rdc) of less than or equal to 1Ω, and at communications frequencies (f11 to f1m, and f21 to f2n) of first and second transmission signals (TX1 and TX2), the impedance (Z) is greater than or equal to 200Ω. As a result, it is possible for the bias circuit (21) to supply a large current to the amplifier (13), and to be in an open state with respect to the first and second transmission signals (TX1 and TX2).

Description

電力増幅器Power amplifier
　本発明は、例えば数十ＭＨｚ以上の高周波の信号を増幅する電力増幅器に関する。 The present invention relates to a power amplifier that amplifies a high frequency signal of, for example, several tens of MHz or more.
　一般に、携帯電話等の無線通信機に設けられ、高周波の信号を増幅することができる電力増幅器が知られている（例えば、特許文献１参照）。このような電力増幅器には、バイアス電圧を供給するバイアス回路が設けられている。 Generally, a power amplifier that is provided in a wireless communication device such as a mobile phone and can amplify a high-frequency signal is known (for example, see Patent Document 1). Such a power amplifier is provided with a bias circuit for supplying a bias voltage.
特開昭５９－１５３１３号公報JP 59-15313 A
　ところで、従来技術による電力増幅器では、バイアス回路による損失を低減するために、バイアス電源と増幅器との間に１／４波長直列インダクタンスと１／４波長開放スタブとを設け、バイアス回路を高周波的に開放状態にしている。しかし、１／４波長直列インダクタンス等は周波数依存性があるため、同一の通信周波数帯内であっても広帯域の信号を増幅する場合には、信号に対して必ずしもバイアス回路を高周波的に開放状態にすることができない。特に、複数の通信周波数帯にわたる信号を増幅するマルチバンド用の電力増幅器では、バイアス回路の影響を受け易い傾向がある。 By the way, in the conventional power amplifier, in order to reduce the loss due to the bias circuit, a 1/4 wavelength series inductance and a 1/4 wavelength open stub are provided between the bias power source and the amplifier, and the bias circuit is made high frequency. Opened. However, because the 1/4 wavelength series inductance etc. is frequency dependent, when a wideband signal is amplified even within the same communication frequency band, the bias circuit is not necessarily opened at a high frequency for the signal. I can't. In particular, multiband power amplifiers that amplify signals over a plurality of communication frequency bands tend to be susceptible to bias circuits.
　本発明は上述した従来技術の問題に鑑みなされたもので、本発明の目的は、バイアス回路の影響を抑制することができる電力増幅器を提供することにある。 The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a power amplifier capable of suppressing the influence of a bias circuit.
　（１）．上述した課題を解決するために、本発明は、基地局から発信される周波数設定情報に基づいて複数の通信周波数帯のうち一の通信周波数の信号を増幅するマルチバンド用の電力増幅器であって、互いに直列接続された複数の増幅器と、該複数の増幅器のうち少なくとも一の増幅器に接続されてバイアス電源からバイアス電圧を供給するバイアス回路とを備え、前記複数の増幅器のうち少なくとも一の増幅器に接続された少なくとも一のバイアス回路は、該バイアス回路が接続された増幅器と前記バイアス電源との間に接続されたインダクタと、該インダクタと前記バイアス電源との接続点とグランドとの間に接続されたバイパスコンデンサとによって構成し、前記インダクタは、フェライトコアに導体材料からなる太くて短い巻線を巻回して構成され、直流抵抗が小さく、かつ前記全ての通信周波数帯でインピーダンスが大きいチップコイルであることを特徴としている。 (1). In order to solve the above-described problem, the present invention is a multiband power amplifier that amplifies a signal of one communication frequency among a plurality of communication frequency bands based on frequency setting information transmitted from a base station. A plurality of amplifiers connected in series with each other, and a bias circuit connected to at least one of the plurality of amplifiers to supply a bias voltage from a bias power supply, and at least one of the plurality of amplifiers includes At least one bias circuit connected is connected between an amplifier connected to the bias circuit and the bias power supply, and a connection point between the inductor and the bias power supply and a ground. The inductor is formed by winding a thick and short winding made of a conductor material around a ferrite core. Made which are characterized in that the direct current resistance is small, and which is the all large chip coil impedance at the communication frequency band.
　本発明によれば、バイアス回路は、増幅器とバイアス電源との間に接続されたインダクタを備えるから、周波数設定情報によって複数の通信周波数帯のうち一の通信周波数が特定されたときに、該一の通信周波数の信号に対してインダクタのインピーダンスを高めて、バイアス回路を開放状態にすることができる。また、インダクタは、フェライトコアに巻線を巻回したチップコイルによって構成したから、太いワイヤによって巻線を形成することによって、巻線の巻き数を減らすことができる。これにより、チップコイルは、例えばフェライトコアを省いたものに比べて、太くて短い巻線を用いることができ、直流抵抗を小さくし、かつ全ての通信周波数帯でインピーダンスを大きくすることができる。この結果、小型のチップコイルを用いてバイアス回路を高周波的に開放状態にすることができる。 According to the present invention, since the bias circuit includes the inductor connected between the amplifier and the bias power supply, when one communication frequency is specified from among a plurality of communication frequency bands by the frequency setting information, The bias circuit can be opened by increasing the impedance of the inductor with respect to the signal of the communication frequency. In addition, since the inductor is constituted by a chip coil in which a winding is wound around a ferrite core, the number of windings can be reduced by forming the winding with a thick wire. As a result, the chip coil can use a thicker and shorter winding compared to, for example, the one without the ferrite core, and can reduce the DC resistance and increase the impedance in all communication frequency bands. As a result, the bias circuit can be opened in high frequency using a small chip coil.
　（２）．本発明では、前記インダクタの直流抵抗は１Ω以下で、全ての前記通信周波数帯でのインピーダンスが２００Ω以上である構成としている。 (2). In the present invention, the DC resistance of the inductor is 1Ω or less, and the impedance in all the communication frequency bands is 200Ω or more.
　本発明によれば、インダクタの直流抵抗は１Ω以下にしたから、インダクタを通じて大きな電流を増幅器に供給することができる。また、全ての通信周波数帯でインダクタのインピーダンスは２００Ω以上にしたから、例えば増幅器に用いるトランジスタの出力インピーダンスに比べて十分に大きな値にすることができ、バイアス回路の影響を抑制することができる。 According to the present invention, since the direct current resistance of the inductor is 1Ω or less, a large current can be supplied to the amplifier through the inductor. Further, since the impedance of the inductor is set to 200Ω or higher in all communication frequency bands, for example, it can be set to a sufficiently large value compared with the output impedance of the transistor used in the amplifier, and the influence of the bias circuit can be suppressed.
　（３）．本発明は、基地局から発信される周波数設定情報に基づいて通信周波数帯のうち一の通信周波数の信号を増幅するシングルバンド用の電力増幅器であって、互いに直列接続された複数の増幅器と、該複数の増幅器のうち少なくとも一の増幅器に接続されてバイアス電源からバイアス電圧を供給するバイアス回路とを備え、前記複数の増幅器のうち少なくとも一の増幅器に接続された少なくとも一のバイアス回路は、該バイアス回路が接続された増幅器と前記バイアス電源との間に接続されたインダクタと、該インダクタと前記バイアス電源との接続点とグランドとの間に接続されたバイパスコンデンサとによって構成し、前記インダクタは、フェライトコアに導体材料からなる太くて短い巻線を巻回して構成され、直流抵抗が小さく、かつ前記通信周波数帯でインピーダンスが大きいチップコイルであることを特徴としている。 (3). The present invention is a single-band power amplifier that amplifies a signal of one communication frequency in a communication frequency band based on frequency setting information transmitted from a base station, and a plurality of amplifiers connected in series with each other; A bias circuit connected to at least one amplifier of the plurality of amplifiers and supplying a bias voltage from a bias power supply, and at least one bias circuit connected to at least one amplifier of the plurality of amplifiers, An inductor connected between an amplifier to which a bias circuit is connected and the bias power supply, and a bypass capacitor connected between a connection point of the inductor and the bias power supply and a ground, The ferrite core is made by winding a thick and short winding made of a conductive material, has a low DC resistance, and is It is characterized in that the impedance at the communication frequency band is large chip coil.
　本発明によれば、バイアス回路は、増幅器とバイアス電源との間に接続されたインダクタを備えるから、周波数設定情報によって通信周波数帯内の一の通信周波数が特定されたときに、該一の通信周波数の信号に対してインダクタのインピーダンスを高めて、バイアス回路を開放状態にすることができる。また、インダクタは、フェライトコアに巻線を巻回したチップコイルによって構成したから、太いワイヤを用いて巻線を形成することによって、巻線の巻き数を減らすことができる。これにより、チップコイルは、例えばフェライトコアを省いたものに比べて、太くて短い巻線を用いることができ、直流抵抗を小さくし、かつ通信周波数帯でインピーダンスを大きくすることができる。この結果、小型のチップコイルを用いてバイアス回路を高周波的に開放状態にすることができる。 According to the present invention, since the bias circuit includes the inductor connected between the amplifier and the bias power source, when one communication frequency in the communication frequency band is specified by the frequency setting information, the one communication By increasing the impedance of the inductor with respect to the frequency signal, the bias circuit can be opened. In addition, since the inductor is constituted by a chip coil in which a winding is wound around a ferrite core, the number of windings can be reduced by forming the winding using a thick wire. As a result, the chip coil can use a thicker and shorter winding compared to, for example, the one without the ferrite core, and can reduce the DC resistance and increase the impedance in the communication frequency band. As a result, the bias circuit can be opened in high frequency using a small chip coil.
　（４）．本発明では、前記インダクタの直流抵抗は１Ω以下で、前記通信周波数帯でのインピーダンスが２００Ω以上である構成としている。 (4). In the present invention, the inductor has a DC resistance of 1Ω or less and an impedance in the communication frequency band of 200Ω or more.
　本発明によれば、インダクタの直流抵抗は１Ω以下にしたから、インダクタを通じて大きな電流を増幅器に供給することができる。また、通信周波数帯でインダクタのインピーダンスは２００Ω以上にしたから、例えば増幅器に用いるトランジスタの出力インピーダンスに比べて十分に大きな値にすることができ、バイアス回路の影響を抑制することができる。 According to the present invention, since the direct current resistance of the inductor is 1Ω or less, a large current can be supplied to the amplifier through the inductor. In addition, since the impedance of the inductor is set to 200Ω or more in the communication frequency band, for example, it can be set to a sufficiently large value compared to the output impedance of the transistor used in the amplifier, and the influence of the bias circuit can be suppressed.
本発明の第１の実施の形態による電力増幅器が適用される無線通信機を示すブロック図である。It is a block diagram which shows the radio | wireless communication apparatus with which the power amplifier by the 1st Embodiment of this invention is applied. 図１中の電力増幅器を示すブロック図である。It is a block diagram which shows the power amplifier in FIG. 増幅器の入力振幅に対する利得および位相の関係を示す特性線図である。It is a characteristic diagram which shows the relationship of the gain and phase with respect to the input amplitude of an amplifier. 段間整合回路によるプリディストーションを示す説明図である。It is explanatory drawing which shows the predistortion by an interstage matching circuit. 図２中のインダクタに用いるチップコイルを示す斜視図である。It is a perspective view which shows the chip coil used for the inductor in FIG. 図５中のチップコイルの周波数とインピーダンスとの関係を示す特性線図である。FIG. 6 is a characteristic diagram showing the relationship between the frequency and impedance of the chip coil in FIG. 5. 第２の実施の形態による電力増幅器が適用される無線通信機を示すブロック図である。It is a block diagram which shows the radio | wireless communication apparatus with which the power amplifier by 2nd Embodiment is applied. 図７中の電力増幅器を示すブロック図である。It is a block diagram which shows the power amplifier in FIG.
　以下、本発明の実施の形態による電力増幅器を携帯電話等の無線通信機に適用した場合を例に挙げて、添付図面を参照しつつ詳細に説明する。 Hereinafter, an example in which the power amplifier according to the embodiment of the present invention is applied to a wireless communication device such as a mobile phone will be described in detail with reference to the accompanying drawings.
　まず、図１および図２は、第１の実施の形態を示している。図において、無線通信機１は、送信装置２、第１，第２のデュプレクサ３，４、第１，第２の受信装置５，６、ダイプレクサ７、アンテナ８等によって構成されている。 First, FIG. 1 and FIG. 2 show a first embodiment. In the figure, a wireless communication device 1 includes a transmission device 2, first and second duplexers 3 and 4, first and second reception devices 5 and 6, a diplexer 7, an antenna 8, and the like.
　送信装置２は、後述するマルチバンドの電力増幅器１１を備え、第１，第２の送信信号ＴＸ1，ＴＸ2のうちいずれか一方を選択して出力する。そして、送信装置２は、第１の送信信号ＴＸ1を第１のデュプレクサ３に出力し、第２の送信信号ＴＸ2を第２のデュプレクサ４に出力する。 The transmission device 2 includes a multiband power amplifier 11 to be described later, and selects and outputs one of the first and second transmission signals TX1 and TX2. Then, the transmission device 2 outputs the first transmission signal TX1 to the first duplexer 3, and outputs the second transmission signal TX2 to the second duplexer 4.
　このとき、第１の送信信号ＴＸ1は、例えばＵＳ－Ｃｅｌｌｕｌａｒ方式に係る第１の送信周波数帯域（「８２４～８４９ＭＨｚ」または「８２４～８３０ＭＨｚ」）に属するいずれかの周波数で送信される。一方、第２の送信信号ＴＸ2は、例えばＪ－ＣＤＭＡ方式に係る第２の送信周波数帯域（８９８～９２５ＭＨｚ）に属するいずれかの周波数で送信される。このように、第１，第２の送信信号ＴＸ1，ＴＸ2は、互いに異なる通信周波数帯の信号となっている。 At this time, the first transmission signal TX1 is transmitted at any frequency belonging to the first transmission frequency band (“824 to 849 MHz” or “824 to 830 MHz”) according to the US-Cellular system, for example. On the other hand, the second transmission signal TX2 is transmitted at any frequency belonging to the second transmission frequency band (898 to 925 MHz) according to the J-CDMA system, for example. Thus, the first and second transmission signals TX1, TX2 are signals in different communication frequency bands.
　なお、基地局ＢＳから無線通信機１に送信される周波数設定情報Ｓpによって、第１の送信信号ＴＸ1に係る通信周波数ｆ11～ｆ1m、第２の送信信号ＴＸ2に係る通信周波数ｆ21～ｆ2nから具体的な送信信号の通信周波数が設定される。 Note that the communication frequencies f1 1 to f1 m related to the first transmission signal TX1 and the communication frequencies f2 1 to f2 related to the second transmission signal TX2 are determined by the frequency setting information Sp transmitted from the base station BS to the wireless communication device 1. A specific communication frequency of the transmission signal is set from n .
　即ち、送信装置２は、通信周波数ｆ11～ｆ1mと通信周波数ｆ21～ｆ2nとを合計した（ｍ＋ｎ）種類の通信周波数のうちのいずれか１つの周波数の信号を送信する構成となっている。このとき、第１の送信信号ＴＸ1に係る通信周波数ｆ11～ｆ1mの種類数（ｍ種類）と第２の送信信号ＴＸ2に係る通信周波数ｆ21～ｆ2nの種類数（ｎ種類）とは、互いに異なる数でもよく、同じ数でもよい。 That is, the transmission device 2 is configured to transmit a signal having any one of (m + n) types of communication frequencies obtained by adding the communication frequencies f1 1 to f1 m and the communication frequencies f2 1 to f2 n. Yes. At this time, the number of types (m types) of communication frequencies f1 1 to f1 m related to the first transmission signal TX1 and the number of types (n types) of communication frequencies f2 1 to f2 n related to the second transmission signal TX2 The numbers may be different from each other or the same number.
　第１のデュプレクサ３は、図１に示すように、送信装置２の出力側と第１の受信装置５の入力側とに接続されると共に、ダイプレクサ７を介してアンテナ８に接続されている。一方、第２のデュプレクサ４は、送信装置２の出力側と第２の受信装置６の入力側とに接続されると共に、ダイプレクサ７を介してアンテナ８に接続されている。そして、ダイプレクサ７は、ＵＳ－Ｃｅｌｌｕｌａｒ方式の通信を行うときには、アンテナ８を第１のデュプレクサ３に接続し、Ｊ－ＣＤＭＡ方式の通信を行うときには、アンテナ８を第２のデュプレクサ４に接続する。 As shown in FIG. 1, the first duplexer 3 is connected to the output side of the transmission device 2 and the input side of the first reception device 5, and is connected to the antenna 8 via the diplexer 7. On the other hand, the second duplexer 4 is connected to the output side of the transmission device 2 and the input side of the second reception device 6, and is connected to the antenna 8 via the diplexer 7. The diplexer 7 connects the antenna 8 to the first duplexer 3 when performing US-Cellular communication, and connects the antenna 8 to the second duplexer 4 when performing J-CDMA communication.
　電力増幅器１１は、図２に示すように、例えば２段のヘテロ接合バイポーラトランジスタ等からなる増幅器１２，１３と、増幅器１２，１３間に設けられた段間整合回路１４と、入力段（ドライバ段）の増幅器１２の入力側に設けられた入力段整合回路１５と、出力段（ファイナル段）の増幅器１３の出力側に設けられた出力段整合回路１６と、段間整合回路１４、入力段整合回路１５および出力段整合回路１６のインピーダンス値Ｚm，Ｚi，Ｚoを制御する制御回路１７と、バイアス回路１８，２１とを備えている。 As shown in FIG. 2, the power amplifier 11 includes, for example, amplifiers 12 and 13 composed of two stages of heterojunction bipolar transistors, an interstage matching circuit 14 provided between the amplifiers 12 and 13, and an input stage (driver stage). The input stage matching circuit 15 provided on the input side of the amplifier 12), the output stage matching circuit 16 provided on the output side of the amplifier 13 in the output stage (final stage), the interstage matching circuit 14, and the input stage matching. A control circuit 17 that controls impedance values Zm, Zi, and Zo of the circuit 15 and the output stage matching circuit 16 and bias circuits 18 and 21 are provided.
　ここで、増幅器１２，１３は、第１，第２の送信信号ＴＸ1，ＴＸ2の両方の通信周波数帯の信号を増幅するために、例えば１００ＭＨｚ以上の広帯域に亘って利得が得られるものが使用される。 Here, the amplifiers 12 and 13 are used to amplify signals in both the communication frequency bands of the first and second transmission signals TX1 and TX2 and obtain a gain over a wide band of, for example, 100 MHz or more. The
　また、後述の制御回路１７によって段間整合回路１４のインピーダンス値Ｚmが設定され、第１，第２の送信信号ＴＸ1，ＴＸ2に応じて増幅器１２，１３間のインピーダンス整合が図られる。具体的には、制御回路１７から出力される制御信号に応じて、所望な特性が得られるように、段間整合回路１４のインピーダンス値Ｚmが最適な値に調整される。このとき、インピーダンス値Ｚmの最適な値は、第１，第２の送信信号ＴＸ1，ＴＸ2が入力されたときに、例えばプリディストーションと呼ばれる方法を用いて出力段の増幅器１３から歪みが低下した状態で増幅した第１，第２の送信信号ＴＸ1，ＴＸ2が得られる値である。 Further, the impedance value Zm of the interstage matching circuit 14 is set by the control circuit 17 described later, and impedance matching between the amplifiers 12 and 13 is achieved according to the first and second transmission signals TX1 and TX2. Specifically, the impedance value Zm of the interstage matching circuit 14 is adjusted to an optimum value so as to obtain a desired characteristic according to the control signal output from the control circuit 17. At this time, the optimum value of the impedance value Zm is a state in which distortion is reduced from the amplifier 13 at the output stage using a method called predistortion, for example, when the first and second transmission signals TX1 and TX2 are input. The first and second transmission signals TX1 and TX2 amplified in step 1 are obtained.
ここで、プリディストーションについて詳細に説明する。一般に、無線通信機の送信系に設けられるマルチバンド電力増幅器１１では、電力効率を向上させるため、増幅器１２，１３は利得の飽和点に近い動作点で使用される。一方、増幅器１２，１３は、図３に示すように、出力電力が飽和電力に近付くに従って、（１）入力振幅／出力振幅非線形（ＡＭ／ＡＭ）と呼ばれる振幅成分の歪みと、（２）入力振幅／出力位相非線形（ＡＭ／ＰＭ）と呼ばれる位相成分の歪みとが発生する。 Here, the predistortion will be described in detail. In general, in a multiband power amplifier 11 provided in a transmission system of a wireless communication device, the amplifiers 12 and 13 are used at an operating point close to a gain saturation point in order to improve power efficiency. On the other hand, as shown in FIG. 3, the amplifiers 12 and 13 have (1) distortion of amplitude component called input amplitude / output amplitude nonlinearity (AM / AM) and (2) input as the output power approaches the saturation power. A distortion of a phase component called amplitude / output phase nonlinearity (AM / PM) occurs.
　これらの非線形歪みが生じると、伝送特性が劣化すると共に、隣接チャネル干渉が生じるという問題がある。このため、図４に示すように、前段の増幅器１２と後段の増幅器１３とでそれぞれ発生する非線形歪みが逆特性となるように、増幅器１２と増幅器１３の間に段間整合回路１４を設けると共に、そのインピーダンスが調整される。これにより、前段の増幅器１２と後段の増幅器１３とで発生する非線形歪みがキャンセルされ、低歪みで送信信号が増幅される。 When these nonlinear distortions occur, there is a problem that transmission characteristics deteriorate and adjacent channel interference occurs. For this reason, as shown in FIG. 4, an interstage matching circuit 14 is provided between the amplifier 12 and the amplifier 13 so that the nonlinear distortion generated in the amplifier 12 at the front stage and the amplifier 13 at the rear stage have opposite characteristics. The impedance is adjusted. As a result, non-linear distortion generated in the front-stage amplifier 12 and the rear-stage amplifier 13 is canceled, and the transmission signal is amplified with low distortion.
　なお、増幅器１２，１３の振幅成分の歪みと位相成分の歪みは、第１，第２の送信信号ＴＸ1，ＴＸ2に係る通信周波数ｆ11～ｆ1m，ｆ21～ｆ2nのそれぞれで異なる。このため、段間整合回路１４のインピーダンス値Ｚmは、制御回路１７から出力される制御信号に応じて設定され、第１，第２の送信信号ＴＸ1，ＴＸ2に係る通信周波数ｆ11～ｆ1m，ｆ21～ｆ2nのそれぞれに対して調整される。 The amplitude component distortion and the phase component distortion of the amplifiers 12 and 13 are different for the communication frequencies f1 1 to f1 m and f2 1 to f2 n related to the first and second transmission signals TX1 and TX2, respectively. For this reason, the impedance value Zm of the interstage matching circuit 14 is set according to the control signal output from the control circuit 17, and the communication frequencies f1 1 to f1 m , related to the first and second transmission signals TX1 and TX2 are set. Adjustment is made for each of f2 1 to f2 n .
　入力段整合回路１５は、後述の制御回路１７によってそのインピーダンス値Ｚiが設定される。具体的には、入力段整合回路１５は、制御回路１７から出力される制御信号に応じて、所望な特性が得られるように、インピーダンス値Ｚiが最適な値に調整される。これにより、第１，第２の送信信号ＴＸ1，ＴＸ2に応じて、増幅器１２とその入力側に接続された入力負荷ＺLiとの間のインピーダンス整合が図られる。なお、入力負荷ＺLiは、増幅器１２の入力側に接続された回路であり、例えば第１，第２の送信信号ＴＸ1，ＴＸ2を生成する変調回路、ベースバンド処理回路等によって構成されている。 The impedance value Zi of the input stage matching circuit 15 is set by the control circuit 17 described later. Specifically, the input stage matching circuit 15 adjusts the impedance value Zi to an optimum value so as to obtain a desired characteristic according to the control signal output from the control circuit 17. Thereby, impedance matching between the amplifier 12 and the input load ZLi connected to the input side thereof is achieved according to the first and second transmission signals TX1 and TX2. The input load ZLi is a circuit connected to the input side of the amplifier 12, and is configured by, for example, a modulation circuit that generates first and second transmission signals TX1 and TX2, a baseband processing circuit, and the like.
　出力段整合回路１６は、後述の制御回路１７によってそのインピーダンス値Ｚoが設定される。具体的には、出力段整合回路１６は、入力段整合回路１５と同様に、制御回路１７から出力される制御信号に応じて、所望な特性が得られるように、インピーダンス値Ｚoが最適な値に調整される。これにより、第１，第２の送信信号ＴＸ1，ＴＸ2に応じて増幅器１３とその出力側に接続された出力負荷ＺLoとの間のインピーダンス整合が図られる。なお、出力負荷ＺLoは、例えば増幅器１３の出力側に接続された第１，第２のデュプレクサ３，４、ダイプレクサ７、アンテナ８等によって構成されている。 The output stage matching circuit 16 has its impedance value Zo set by the control circuit 17 described later. Specifically, like the input stage matching circuit 15, the output stage matching circuit 16 has an optimum impedance value Zo so that desired characteristics can be obtained according to the control signal output from the control circuit 17. Adjusted to Thereby, impedance matching between the amplifier 13 and the output load ZLo connected to the output side is achieved in accordance with the first and second transmission signals TX1 and TX2. The output load ZLo is composed of, for example, first and second duplexers 3 and 4, a diplexer 7 and an antenna 8 connected to the output side of the amplifier 13.
　制御回路１７は、制御回路１７に入力された周波数設定情報Ｓpに応じて段間整合回路１４、入力段整合回路１５および出力段整合回路１６のインピーダンス値Ｚm，Ｚi，Ｚoを制御する。具体的には、制御回路１７は、周波数設定情報Ｓpに対応して例えばデジタルの制御信号（ビット信号）を出力する。これにより、段間整合回路１４、入力段整合回路１５および出力段整合回路１６のインピーダンス値Ｚm，Ｚi，Ｚoが可変し、第１，２の送信信号ＴＸ1，ＴＸ2が所望の特性となるように設定される。 The control circuit 17 controls the impedance values Zm, Zi, Zo of the interstage matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit 16 according to the frequency setting information Sp input to the control circuit 17. Specifically, the control circuit 17 outputs, for example, a digital control signal (bit signal) corresponding to the frequency setting information Sp. As a result, the impedance values Zm, Zi, Zo of the interstage matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit 16 are variable, so that the first and second transmission signals TX1, TX2 have desired characteristics. Is set.
　所望な特性としては、例えば第１，第２の送信信号ＴＸ1，ＴＸ2の非線形歪みをできるだけ低下させることである。このため、制御回路１７は、非線形歪みをキャンセルするように、段間整合回路１４のインピーダンス値Ｚmを設定する。また、制御回路１７は、増幅器１２と入力負荷ＺLiとの間でインピーダンスが最も整合するように、入力段整合回路１５のインピーダンス値Ｚiを設定すると共に、増幅器１３と出力負荷ＺLoとの間でインピーダンスが最も整合するように、出力段整合回路１６のインピーダンス値Ｚoが設定される。 Desired characteristics include, for example, reducing the nonlinear distortion of the first and second transmission signals TX1 and TX2 as much as possible. For this reason, the control circuit 17 sets the impedance value Zm of the interstage matching circuit 14 so as to cancel the non-linear distortion. Further, the control circuit 17 sets the impedance value Zi of the input stage matching circuit 15 so that the impedance is most matched between the amplifier 12 and the input load ZLi, and the impedance between the amplifier 13 and the output load ZLo. Is set so that the impedance value Zo of the output stage matching circuit 16 is the most matched.
　バイアス回路１８は、増幅器１２の出力端に接続され、増幅器１２にバイアス電圧Ｖddを供給する。このバイアス回路１８は、増幅器１２とバイアス電源ＶＢとの間に接続されたインダクタ１９と、該インダクタ１９とバイアス電源ＶＢとの接続点とグランドとの間に接続されたバイパスコンデンサ２０とによって構成されている。そして、バイアス回路１８は、第１，第２の送信信号ＴＸ1，ＴＸ2に対して高周波的に開放状態となっている。 The bias circuit 18 is connected to the output terminal of the amplifier 12 and supplies a bias voltage Vdd to the amplifier 12. The bias circuit 18 includes an inductor 19 connected between the amplifier 12 and the bias power supply VB, and a bypass capacitor 20 connected between a connection point between the inductor 19 and the bias power supply VB and the ground. ing. The bias circuit 18 is open at high frequencies with respect to the first and second transmission signals TX1, TX2.
　バイアス回路２１は、増幅器１３の出力端に接続され、増幅器１３にバイアス電圧Ｖddを供給する。このバイアス回路２１は、バイアス回路１８とほぼ同様に、増幅器１３とバイアス電源ＶＢとの間に接続されたインダクタ２２と、該インダクタ２２とバイアス電源ＶＢとの接続点とグランドとの間に接続されたバイパスコンデンサ２３とによって構成されている。そして、バイアス回路２１は、第１，第２の送信信号ＴＸ1，ＴＸ2の全ての通信周波数ｆ11～ｆ1m，ｆ21～ｆ2nで高周波的に開放状態となっている。 The bias circuit 21 is connected to the output terminal of the amplifier 13 and supplies a bias voltage Vdd to the amplifier 13. The bias circuit 21 is connected between an inductor 22 connected between the amplifier 13 and the bias power source VB, and a connection point between the inductor 22 and the bias power source VB and the ground, almost like the bias circuit 18. And a bypass capacitor 23. The bias circuit 21 is open at high frequencies at all the communication frequencies f1 1 to f1 m and f2 1 to f2 n of the first and second transmission signals TX1 and TX2.
　ここで、インダクタ２２は、図５に示すように、フェライト材料からなるフェライトコア２４Ａに銅等の導体材料からなる巻線２４Ｂを巻回したチップコイル２４によって構成されている。このチップコイル２４のフェライトコア２４Ａは、両端側に位置して一対の脚部２４Ｃを備えると共に、これらの脚部２４Ｃには外部電極２４Ｄが設けられている。そして、巻線２４Ｂの両端側は、これら一対の外部電極２４Ｄにそれぞれ接続されている。なお、フェライトコア２４Ａのうち脚部２４Ｃとは反対側に位置する上面側には、絶縁樹脂材料からなるコーティング２４Ｅを設け、該コーティング２４Ｅによってフェライトコア２４Ａおよび巻線２４Ｂの上面側を覆う構成としてもよい。 Here, as shown in FIG. 5, the inductor 22 is constituted by a chip coil 24 in which a winding 24B made of a conductor material such as copper is wound around a ferrite core 24A made of a ferrite material. The ferrite core 24A of the chip coil 24 includes a pair of leg portions 24C located on both ends, and the leg portions 24C are provided with external electrodes 24D. Then, both ends of the winding 24B are connected to the pair of external electrodes 24D, respectively. Note that a coating 24E made of an insulating resin material is provided on the upper surface of the ferrite core 24A opposite to the leg 24C, and the coating 24E covers the upper surfaces of the ferrite core 24A and the winding 24B. Also good.
　また、増幅器１２，１３のうち例えば最終段の増幅器１３には、最も大きな電流が流れる傾向がある。このため、増幅器１３に大きな直流電流を供給するために、バイアス回路２１のインダクタ２２の直流抵抗Ｒdcは、できるだけ小さい方がよい。一方、出力段整合回路１６等に対するバイアス回路２１の影響を小さくするためには、通信周波数ｆ11～ｆ1m，ｆ21～ｆ2nでのインダクタ２２のインピーダンスＺは、増幅器１３に用いるトランジスタの出力インピーダンスＺtr（例えばＺtr＝３～５Ω程度）に比べてできるだけ大きい方がよい。 Further, for example, the amplifier 13 at the final stage among the amplifiers 12 and 13 tends to flow the largest current. For this reason, in order to supply a large direct current to the amplifier 13, the direct current resistance Rdc of the inductor 22 of the bias circuit 21 should be as small as possible. On the other hand, in order to reduce the influence of the bias circuit 21 on the output stage matching circuit 16 and the like, the impedance Z of the inductor 22 at the communication frequencies f1 1 to f1 m and f2 1 to f2 n is determined by the output of the transistor used in the amplifier 13. It should be as large as possible compared with the impedance Ztr (for example, Ztr = about 3 to 5Ω).
　このため、チップコイル２４は、直流抵抗Ｒdcが例えば１Ωよりも小さく、通信周波数帯（例えば８００ＭＨｚ～２ＧＨｚ）でインピーダンスＺが数百Ω（例えばＺ＝４００Ω～８００Ω程度）となるものが使用される。具体的には、チップコイル２４としては、例えば株式会社村田製作所製の商品番号ＬＱＷ１８ＣＮＲ１０Ｋ００Ｌ等が適用可能である。このチップコイル２４のインピーダンスＺは、例えば図６に示す周波数特性を有する。 For this reason, a chip coil 24 having a DC resistance Rdc smaller than, for example, 1Ω and an impedance Z of several hundreds of Ω (for example, Z = 400Ω to about 800Ω) in a communication frequency band (for example, 800 MHz to 2 GHz) is used. . Specifically, as the chip coil 24, for example, product number LQW18CNR10K00L manufactured by Murata Manufacturing Co., Ltd. can be applied. The impedance Z of the chip coil 24 has frequency characteristics shown in FIG. 6, for example.
　一般的なインダクタ素子を用いた場合には、ストリップラインの幅を広げて直流抵抗Ｒdcを小さくするため、バイアス回路が大型化して小型な携帯電話等には適用し難い傾向がある。これに対し、本実施の形態によるインダクタ２２では、フェライトコア２４Ａに巻線２４Ｂを施して高周波側のインピーダンスＺを高めると共に、フェライトコア２４Ａを省いたときに比べて太くて短い巻線２４Ｂを用いることで巻線２４Ｂの巻数を減らして、直流抵抗Ｒdcの低抵抗化（例えばＲdc＜０．１Ω程度）を図っている。このため、小型なチップコイル２４を用いて全ての通信周波数ｆ11～ｆ1m，ｆ21～ｆ2nの信号に対して、バイアス回路２１を高周波的に開放状態にすることができる。 When a general inductor element is used, since the width of the strip line is widened to reduce the DC resistance Rdc, the bias circuit tends to be large and difficult to be applied to a small mobile phone or the like. On the other hand, in the inductor 22 according to the present embodiment, the winding 24B is applied to the ferrite core 24A to increase the impedance Z on the high frequency side, and the winding 24B that is thicker and shorter than when the ferrite core 24A is omitted is used. Thus, the number of turns of the winding 24B is reduced to reduce the direct current resistance Rdc (for example, about Rdc <0.1Ω). For this reason, the bias circuit 21 can be opened in high frequency with respect to signals of all the communication frequencies f1 1 to f1 m and f2 1 to f2 n using the small chip coil 24.
　本実施の形態による無線通信機１は上述の如き構成を有するもので、次にその作動について説明する。 The wireless communication device 1 according to the present embodiment has the above-described configuration, and the operation thereof will be described next.
　まず、無線通信機１の送信時には、周波数設定情報Ｓpに応じてベースバンド信号を高周波の第１の送信信号ＴＸ1に変調し、第１の送信信号ＴＸ1を出力する。このとき、マルチバンド電力増幅器１１は、第１の送信信号ＴＸ1を増幅し、第１のデュプレクサ３に向けて出力する。これにより、電力増幅後の第１の送信信号ＴＸ1は、デュプレクサ３、ダイプレクサ７を介してアンテナ８に供給され、アンテナ８から外部に向けて送信される。 First, at the time of transmission of the wireless communication device 1, the baseband signal is modulated into the high-frequency first transmission signal TX1 according to the frequency setting information Sp, and the first transmission signal TX1 is output. At this time, the multiband power amplifier 11 amplifies the first transmission signal TX1 and outputs it to the first duplexer 3. Thus, the first transmission signal TX1 after power amplification is supplied to the antenna 8 via the duplexer 3 and the diplexer 7, and is transmitted from the antenna 8 to the outside.
　同様に、周波数設定情報Ｓpに応じてベースバンド信号を高周波の第２の送信信号ＴＸ2に変調し、第２の送信信号ＴＸ2を出力する。このとき、マルチバンド電力増幅器１１は、第２の送信信号ＴＸ2を増幅し、第２のデュプレクサ４に向けて出力する。これにより、電力増幅後の第２の送信信号ＴＸ2は、デュプレクサ４、ダイプレクサ７、アンテナ８を介して外部に向けて送信される。 Similarly, the baseband signal is modulated into the high-frequency second transmission signal TX2 according to the frequency setting information Sp, and the second transmission signal TX2 is output. At this time, the multiband power amplifier 11 amplifies the second transmission signal TX2 and outputs it to the second duplexer 4. As a result, the second transmission signal TX2 after power amplification is transmitted to the outside via the duplexer 4, the diplexer 7, and the antenna 8.
　一方、無線通信機１の受信時には、アンテナ８から受信した微弱な受信信号ＲＸ1は、ダイプレクサ７、デュプレクサ３を介して第１の受信装置５に送られる。また、アンテナ８が第２の受信信号ＲＸ2を受信したときには、受信信号ＲＸ2は、ダイプレクサ７、デュプレクサ４を介して第２の受信装置６に送られる。そして、受信信号ＲＸ1，ＲＸ2は、第１，第２の受信装置５，６により、ベースバンド信号に複調される。 On the other hand, at the time of reception by the wireless communication device 1, the weak reception signal RX 1 received from the antenna 8 is sent to the first reception device 5 via the diplexer 7 and the duplexer 3. When the antenna 8 receives the second reception signal RX2, the reception signal RX2 is sent to the second reception device 6 via the diplexer 7 and the duplexer 4. The received signals RX1 and RX2 are double-tuned into baseband signals by the first and second receiving devices 5 and 6.
　本実施の形態では、増幅器１２，１３とバイアス電源ＶＢとの間に接続されたインダクタ１９，２２を備える構成としたから、第１，第２の送信信号ＴＸ1，ＴＸ2のいずれの信号に対してもバイアス回路１８，２１を高周波的に開放状態にすることができる。また、大きな電流が流れる増幅器１３に接続したバイアス回路２１は、そのインダクタ２２をフェライトコア２４Ａに巻線２４Ｂを巻回したチップコイル２４によって構成した。このため、フェライトコア２４Ａを省いたときに比べて、太くて短い巻線２４Ｂを用いることができ、巻線２４Ｂの巻き数を減らして巻線２４Ｂの全長を短くすることができる。 In the present embodiment, since the inductors 19 and 22 are connected between the amplifiers 12 and 13 and the bias power source VB, any of the first and second transmission signals TX1 and TX2 is detected. In addition, the bias circuits 18 and 21 can be opened in high frequency. Further, the bias circuit 21 connected to the amplifier 13 through which a large current flows is constituted by a chip coil 24 in which the inductor 22 is wound around a ferrite core 24A and a winding 24B. For this reason, compared with the case where the ferrite core 24A is omitted, the thick and short winding 24B can be used, and the total number of the windings 24B can be shortened by reducing the number of turns of the winding 24B.
　これにより、チップコイル２４は、直流抵抗Ｒdcが１Ω以下で、かつ第１，第２の送信信号ＴＸ1，ＴＸ2に係る全ての通信周波数ｆ11～ｆ1m，ｆ21～ｆ2nでインピーダンスＺを２００Ω以上とすることができる。この結果、インダクタ２２を通じて大きな電流を増幅器１３に供給することができると共に、小型のチップコイル２４を用いてバイアス回路２１を高周波的に開放状態にすることができ、電力増幅器１１全体を小型化することができる。 As a result, the chip coil 24 has a DC resistance Rdc of 1Ω or less and an impedance Z of 200Ω at all communication frequencies f1 1 to f1 m and f2 1 to f2 n related to the first and second transmission signals TX1 and TX2. This can be done. As a result, a large current can be supplied to the amplifier 13 through the inductor 22, and the bias circuit 21 can be opened in a high frequency using the small chip coil 24, and the power amplifier 11 as a whole can be downsized. be able to.
　本実施の形態では、制御回路１７は、周波数設定情報Ｓpによって特定された第１，２の送信信号ＴＸ1，ＴＸ2に係る通信周波数ｆ11～ｆ1m，ｆ21～ｆ2nに応じて、段間整合回路１４、入力段整合回路１５および出力段整合回路１６のインピーダンス値Ｚm，Ｚi，Ｚoをそれぞれ制御する。この結果、第１，第２の送信信号ＴＸ1，ＴＸ2をチューニングする場合、各通信周波数ｆ11～ｆ1m，ｆ21～ｆ2nのそれぞれにおいてインピーダンス整合を取ることができる。 In the present embodiment, the control circuit 17 interstages according to the communication frequencies f1 1 to f1 m and f2 1 to f2 n related to the first and second transmission signals TX1 and TX2 specified by the frequency setting information Sp. The impedance values Zm, Zi, Zo of the matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit 16 are controlled. As a result, when tuning the first and second transmission signals TX1 and TX2, impedance matching can be achieved at each of the communication frequencies f1 1 to f1 m and f2 1 to f2 n .
　また、周波数設定情報Ｓpによって第１，第２の送信信号ＴＸ1，ＴＸ2に係る通信周波数ｆ11～ｆ1m，ｆ21～ｆ2nが特定されたときに、この通信周波数ｆ11～ｆ1m，ｆ21～ｆ2nの信号に対してバイアス回路１８，２１が高周波的に開放状態になる。このため、バイアス回路１８，２１が増幅器１２，１３を通じて段間整合回路１４、入力段整合回路１５または出力段整合回路１６に接続されているときでも、各整合回路１４～１６に対してバイアス回路１８，２１のインピーダンスの影響を小さくすることができ、各整合回路１４～１６は制御回路１７によって設定された最適な状態を保持することができる。 The first by the frequency setting information Sp, when the second transmission signal TX1, the communication frequency according to TX2 f1 1 ~ f1 m, f2 1 ~ f2 n is identified, the communication frequency f1 1 ~ f1 m, f2 The bias circuits 18 and 21 are opened in high frequency with respect to the signals 1 to f2 n . Therefore, even when the bias circuits 18 and 21 are connected to the interstage matching circuit 14, the input stage matching circuit 15, or the output stage matching circuit 16 through the amplifiers 12 and 13, the bias circuits are connected to the matching circuits 14 to 16. The influence of the impedances 18 and 21 can be reduced, and each of the matching circuits 14 to 16 can maintain the optimum state set by the control circuit 17.
　また、段間整合回路１４、入力段整合回路１５および出力段整合回路１６のインピーダンス値Ｚm，Ｚi，Ｚoは制御回路１７によって制御する構成としたから、増幅器１２，１３間や入力側、出力側の整合を取るだけでなく、例えば増幅器１２，１３の効率や第１，第２の送信信号ＴＸ1，ＴＸ2の歪み等を優先的に改善することができる。この結果、どのような第１，第２の送信信号ＴＸ1，ＴＸ2が入力されたときでも、増幅器１２，１３を用いて所望な特性となった第１，第２の送信信号ＴＸ1，ＴＸ2を出力することができる。 Further, since the impedance values Zm, Zi, and Zo of the interstage matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit 16 are controlled by the control circuit 17, the amplifiers 12 and 13 and the input side and output side are controlled. For example, the efficiency of the amplifiers 12 and 13 and the distortion of the first and second transmission signals TX1 and TX2 can be preferentially improved. As a result, the first and second transmission signals TX1 and TX2 having desired characteristics are output using the amplifiers 12 and 13 regardless of what first and second transmission signals TX1 and TX2 are input. can do.
　また、制御回路１７は、入力段整合回路１５および出力段整合回路１６のインピーダンス値Ｚi，Ｚoと一緒に段間整合回路１４のインピーダンス値Ｚmを制御する構成とした。このため、電力増幅器１１の入力側および出力側に限らず、電力増幅器１１の内部でも第１，第２の送信信号ＴＸ1，ＴＸ2に応じて増幅器１２，１３間のインピーダンス整合を取ることができる。これにより、例えば第１，第２の送信信号ＴＸ1，ＴＸ2の減衰や反射を防止して、ノイズの発生を抑制できると共に、第１，第２の送信信号ＴＸ1，ＴＸ2の出力レベルを高めることができる。 The control circuit 17 is configured to control the impedance value Zm of the interstage matching circuit 14 together with the impedance values Zi and Zo of the input stage matching circuit 15 and the output stage matching circuit 16. For this reason, not only the input side and output side of the power amplifier 11, but also inside the power amplifier 11, impedance matching between the amplifiers 12 and 13 can be achieved according to the first and second transmission signals TX1 and TX2. As a result, for example, attenuation and reflection of the first and second transmission signals TX1 and TX2 can be prevented, noise can be suppressed, and the output levels of the first and second transmission signals TX1 and TX2 can be increased. it can.
　なお、前記第１の実施の形態では、所望な特性として、第１，第２の送信信号ＴＸ1，ＴＸ2の非線形歪みを低下させる特性とした。このため、制御回路１７は、非線形歪みをキャンセルするように、段間整合回路１４のインピーダンス値Ｚmを設定した。 In the first embodiment, the desired characteristic is the characteristic that reduces the nonlinear distortion of the first and second transmission signals TX1, TX2. For this reason, the control circuit 17 sets the impedance value Zm of the interstage matching circuit 14 so as to cancel the non-linear distortion.
　しかし、本発明はこれに限らず、所望な特性としては、例えば第１，第２の送信信号ＴＸ1，ＴＸ2の出力レベルを最大にする場合には、増幅器１２，１３間や入力側、出力側との間でインピーダンスが最も整合するように、段間整合回路１４、入力段整合回路１５および出力段整合回路１６のインピーダンス値Ｚm，Ｚi，Ｚoを設定する構成としてもよい。また、所望な特性として、増幅器１２，１３を最大効率で動作させる構成としてもよい。 However, the present invention is not limited to this. Desired characteristics include, for example, when the output levels of the first and second transmission signals TX1 and TX2 are maximized, between the amplifiers 12 and 13, the input side, and the output side. The impedance values Zm, Zi, and Zo of the interstage matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit 16 may be set so that the impedances are most matched with each other. Further, as a desired characteristic, the amplifiers 12 and 13 may be configured to operate at maximum efficiency.
　また、増幅器１２，１３の出力レベル、歪み、効率の特性は互いにトレードオフの関係があるから、インピーダンス値Ｚm，Ｚi，Ｚoの最適な値としては、例えばいずれか一つの特性を優先させて決めるものである。 Since the output level, distortion, and efficiency characteristics of the amplifiers 12 and 13 are in a trade-off relationship with each other, the optimum values of the impedance values Zm, Zi, and Zo are determined with priority given to any one of the characteristics, for example. Is.
　また、所望な特性として、増幅器１２，１３の効率や第１，第２の送信信号ＴＸ1，ＴＸ2の歪みを優先させる場合には、段間整合回路１４、入力段整合回路１５および出力段整合回路１６のうち出力段整合回路１６のインピーダンス値Ｚoだけ出力レベルを最大にする値、即ち最も整合性が高い値からずらす構成としてもよい。 Further, as the desired characteristics, when priority is given to the efficiency of the amplifiers 12 and 13 and the distortion of the first and second transmission signals TX1 and TX2, the interstage matching circuit 14, the input stage matching circuit 15, and the output stage matching circuit. 16 may be configured to be shifted from a value that maximizes the output level by the impedance value Zo of the output stage matching circuit 16, that is, a value that has the highest matching.
　さらに、３個以上の増幅器を直列接続した場合には、例えば最も大きな電流が流れる増幅器（例えば最終段の増幅器）とその前段の増幅器との間に設けた段間整合回路は、所望な特性として非線形歪みの低下を優先させる構成とし、他の段間整合回路は、所望な特性として出力レベルを最大にするために増幅器間のインピーダンスの整合性を優先させる構成としてもよい。 Further, when three or more amplifiers are connected in series, for example, the interstage matching circuit provided between the amplifier through which the largest current flows (for example, the amplifier at the final stage) and the amplifier at the preceding stage has a desired characteristic. A configuration in which priority is given to the reduction of nonlinear distortion, and another interstage matching circuit may be configured to give priority to impedance matching between amplifiers in order to maximize the output level as a desired characteristic.
　また、３個以上の増幅器を直列接続した場合には、全ての増幅器の間に段間整合回路を設ける必要はなく、例えば増幅率が一番大きい増幅器（例えば最終段の増幅器）とその前段の増幅器との間にのみ段間整合回路を設ける構成としてもよい。さらに、複数の段間整合回路を設ける場合であっても、全ての段間整合回路のインピーダンス値を可変に制御する必要はなく、例えば増幅率が一番大きい増幅器に接続された段間整合回路のインピーダンス値は可変に制御され、他の段間整合回路のインピーダンス値は固定する構成としてもよい。 When three or more amplifiers are connected in series, there is no need to provide an interstage matching circuit between all amplifiers. For example, the amplifier having the highest amplification factor (for example, the final stage amplifier) and the preceding stage amplifier are not required. An interstage matching circuit may be provided only between the amplifier and the amplifier. Furthermore, even when a plurality of interstage matching circuits are provided, it is not necessary to variably control the impedance values of all the interstage matching circuits. For example, the interstage matching circuit connected to the amplifier having the largest amplification factor. The impedance value may be variably controlled, and the impedance values of other interstage matching circuits may be fixed.
　また、第１の実施の形態では、電力増幅器１１を２つの通信周波数帯の第１，第２の送信信号ＴＸ1，ＴＸ2を出力するデュアルバンドの送信装置２に適用する構成としたが、３つ以上の通信周波数帯の送信信号を出力する送信装置に適用してもよい。さらに、第１，第２の送信信号ＴＸ1，ＴＸ2は、８００ＭＨｚ帯の信号を用いる構成としたが、例えば１．５ＧＨｚ帯、１．７ＧＨｚ帯、２ＧＨｚ帯等の他の通信周波数帯の信号を用いる構成としてもよい。 In the first embodiment, the power amplifier 11 is applied to the dual-band transmission device 2 that outputs the first and second transmission signals TX1 and TX2 in two communication frequency bands. You may apply to the transmitter which outputs the transmission signal of the above communication frequency band. Furthermore, although the first and second transmission signals TX1 and TX2 are configured to use signals in the 800 MHz band, for example, signals in other communication frequency bands such as 1.5 GHz band, 1.7 GHz band, and 2 GHz band are used. It is good also as a structure.
　次に、図７および図８は本発明の第２の実施の形態を示している。そして、本実施の形態の特徴は、チップコイルからなるバイアス回路を、通信周波数帯が予め特定されたシングルバンド用の電力増幅器に適用したことにある。 Next, FIG. 7 and FIG. 8 show a second embodiment of the present invention. A feature of this embodiment is that a bias circuit composed of a chip coil is applied to a single-band power amplifier whose communication frequency band is specified in advance.
　無線通信機３１は、送信装置３２、デュプレクサ３３、受信装置３４、アンテナ３５等によって構成されている。 The wireless communication device 31 includes a transmission device 32, a duplexer 33, a reception device 34, an antenna 35, and the like.
　送信装置３２は、後述するシングルバンド用の電力増幅器４１を備えると共に、デュプレクサ３３に接続されている。この送信装置３２は、例えば８００ＭＨｚ以上の高周波の通信周波数帯の送信信号ＴＸを生成し、この送信信号ＴＸをデュプレクサ３３に向けて出力する。このとき、送信信号ＴＸは、例えばＪ－ＣＤＭＡ方式の信号からなり８９８～９２５ＭＨｚの送信周波数帯域を有している。 The transmission device 32 includes a single-band power amplifier 41, which will be described later, and is connected to a duplexer 33. The transmission device 32 generates a transmission signal TX in a high-frequency communication frequency band of, for example, 800 MHz or higher, and outputs the transmission signal TX toward the duplexer 33. At this time, the transmission signal TX is composed of, for example, a J-CDMA system signal and has a transmission frequency band of 898 to 925 MHz.
　また、送信装置３２は、基地局ＢＳから送信される周波数設定情報Ｓpを含んだパイロット信号に応じた送信信号ＴＸを出力する。このとき、パイロット信号は、送信周波数帯域の範囲内に含まれる通信周波数ｆ1～ｆnのうち送信信号ＴＸの具体的な通信周波数を特定する。このため、送信装置３２は、例えばｎ種類の通信周波数ｆ1～ｆnのうちいずれか１つの周波数の信号を送信する構成となっている。 Moreover, the transmission apparatus 32 outputs the transmission signal TX according to the pilot signal including the frequency setting information Sp transmitted from the base station BS. At this time, the pilot signal specifies a specific communication frequency of the transmission signal TX among the communication frequencies f 1 to f n included in the range of the transmission frequency band. For this reason, the transmission device 32 is configured to transmit a signal of any one frequency among, for example, n types of communication frequencies f 1 to f n .
　また、デュプレクサ３３は、図７に示すように、送信装置３２の出力側と受信装置３４の入力側とに接続されると共に、アンテナ３５に接続されている。そして、無線通信機３１の送信時には、送信装置３２は、ベースバンド信号を高周波の送信信号ＴＸに変調し、この送信信号ＴＸを電力増幅器４１を用いて増幅し、アンテナ３５から外部に向けて送信する。一方、無線通信機３１の受信時には、アンテナ３５から受信した受信信号ＲＸは、デュプレクサ３３を介して受信装置３４に送られる。このとき、受信装置３４は、受信信号ＲＸをベースバンド信号に複調する。 Further, as shown in FIG. 7, the duplexer 33 is connected to the output side of the transmission device 32 and the input side of the reception device 34 and to the antenna 35. At the time of transmission by the wireless communication device 31, the transmission device 32 modulates the baseband signal into a high-frequency transmission signal TX, amplifies the transmission signal TX using the power amplifier 41, and transmits the signal from the antenna 35 to the outside. To do. On the other hand, at the time of reception by the wireless communication device 31, the reception signal RX received from the antenna 35 is sent to the reception device 34 via the duplexer 33. At this time, the receiving device 34 multiplies the received signal RX into a baseband signal.
　電力増幅器４１は、送信装置３２に設けられ、送信信号ＴＸを増幅する。また、電力増幅器４１は、図８に示すように、例えば２段のヘテロ接合バイポーラトランジスタ等からなる増幅器４２，４３と、増幅器４２，４３間に設けられた段間整合回路４４と、入力段（ドライバ段）の増幅器４２の入力側に設けられた入力段整合回路４５と、出力段（ファイナル段）の増幅器４３の出力側に設けられた出力段整合回路４６と、段間整合回路４４、入力段整合回路４５および出力段整合回路４６のインピーダンス値Ｚm，Ｚi，Ｚoを制御する制御回路４７と、バイアス回路４８，５１とを備えている。 The power amplifier 41 is provided in the transmission device 32 and amplifies the transmission signal TX. Further, as shown in FIG. 8, the power amplifier 41 includes amplifiers 42 and 43 composed of, for example, two stages of heterojunction bipolar transistors, an interstage matching circuit 44 provided between the amplifiers 42 and 43, and an input stage ( The input stage matching circuit 45 provided on the input side of the amplifier 42 of the driver stage), the output stage matching circuit 46 provided on the output side of the amplifier 43 of the output stage (final stage), the interstage matching circuit 44, and the input A control circuit 47 that controls impedance values Zm, Zi, and Zo of the stage matching circuit 45 and the output stage matching circuit 46, and bias circuits 48 and 51 are provided.
　段間整合回路４４は、後述の制御回路４７によってそのインピーダンス値Ｚmが設定され、送信信号ＴＸに応じて増幅器４２，４３間のインピーダンス整合を取る。具体的には、段間整合回路４４は、第１の実施の形態による段間整合回路１４と同様に、例えばプリディストーションによって、前段の増幅器４２と後段の増幅器４３とで発生する非線形歪みをキャンセルする。このため、段間整合回路４４のインピーダンス値Ｚmは、プリディストーションによって出力段の増幅器４３から歪みが低下した状態で増幅した送信信号ＴＸが得られる最適な値に、制御回路４７によって調整される。 The interstage matching circuit 44 has its impedance value Zm set by a control circuit 47 to be described later, and performs impedance matching between the amplifiers 42 and 43 in accordance with the transmission signal TX. Specifically, the interstage matching circuit 44 cancels the non-linear distortion generated in the front-stage amplifier 42 and the rear-stage amplifier 43 by, for example, predistortion, similarly to the interstage matching circuit 14 according to the first embodiment. To do. For this reason, the impedance value Zm of the interstage matching circuit 44 is adjusted by the control circuit 47 to an optimum value at which the amplified transmission signal TX can be obtained in a state where distortion is reduced from the amplifier 43 at the output stage by predistortion.
　入力段整合回路４５は、後述の制御回路４７によってそのインピーダンス値Ｚiが設定される。具体的には、入力段整合回路４５は、第１の実施の形態による入力段整合回路１５と同様に、制御回路４７から出力される制御信号に応じて、送信信号ＴＸに対して増幅器４２とその入力側に接続された入力負荷ＺLiとの間のインピーダンス整合を取るように、インピーダンス値Ｚiが最適な値に調整される。この場合、入力負荷ＺLiは、増幅器４２の入力側に接続された回路として、例えば送信信号ＴＸを生成する変調回路、ベースバンド処理回路等によって構成されている。 The impedance value Zi of the input stage matching circuit 45 is set by the control circuit 47 described later. Specifically, like the input stage matching circuit 15 according to the first embodiment, the input stage matching circuit 45 is connected to the amplifier 42 with respect to the transmission signal TX according to the control signal output from the control circuit 47. The impedance value Zi is adjusted to an optimum value so as to achieve impedance matching with the input load ZLi connected to the input side. In this case, the input load ZLi is configured as a circuit connected to the input side of the amplifier 42, for example, a modulation circuit that generates a transmission signal TX, a baseband processing circuit, or the like.
　出力段整合回路４６は、後述の制御回路４７によってそのインピーダンス値Ｚoが設定される。具体的には、出力段整合回路４６は、第１の実施の形態による出力段整合回路１６と同様に、制御回路４７から出力される制御信号に応じて、送信信号ＴＸに対して増幅器４３とその出力側に接続された出力負荷ＺLoとの間のインピーダンス整合を取るように、インピーダンス値Ｚoが最適な値に調整される。この場合、出力負荷ＺLoは、例えば増幅器４３の出力側に接続されたデュプレクサ３３、アンテナ３５等によって構成されている。 The impedance value Zo of the output stage matching circuit 46 is set by a control circuit 47 described later. Specifically, similarly to the output stage matching circuit 16 according to the first embodiment, the output stage matching circuit 46 is connected to the amplifier 43 with respect to the transmission signal TX according to the control signal output from the control circuit 47. The impedance value Zo is adjusted to an optimum value so as to achieve impedance matching with the output load ZLo connected to the output side. In this case, the output load ZLo is constituted by, for example, a duplexer 33, an antenna 35, and the like connected to the output side of the amplifier 43.
　制御回路４７は、周波数設定情報Ｓpが入力され、該周波数設定情報Ｓpに応じて段間整合回路４４、入力段整合回路４５および出力段整合回路４６のインピーダンス値Ｚm，Ｚi，Ｚoを制御する。具体的には、制御回路４７は、第１の実施の形態による制御回路１７と同様に、周波数設定情報Ｓpに対応して例えばデジタルの制御信号（ビット信号）を出力し、段間整合回路４４、入力段整合回路４５および出力段整合回路４６のインピーダンス値Ｚm，Ｚi，Ｚoを変化させる。 The control circuit 47 receives the frequency setting information Sp and controls the impedance values Zm, Zi, Zo of the interstage matching circuit 44, the input stage matching circuit 45, and the output stage matching circuit 46 according to the frequency setting information Sp. Specifically, like the control circuit 17 according to the first embodiment, the control circuit 47 outputs, for example, a digital control signal (bit signal) corresponding to the frequency setting information Sp, and the interstage matching circuit 44. The impedance values Zm, Zi, Zo of the input stage matching circuit 45 and the output stage matching circuit 46 are changed.
　このとき、周波数設定情報Ｓpは送信する通信周波数ｆ1～ｆnを特定するものであるから、制御回路４７は、送信信号ＴＸに応じて、所望な特性が得られるように、段間整合回路４４、入力段整合回路４５および出力段整合回路４６のインピーダンス値Ｚm，Ｚi，Ｚoを最適な値に設定する。 At this time, since the frequency setting information Sp specifies the communication frequencies f 1 to f n to be transmitted, the control circuit 47 allows the interstage matching circuit to obtain a desired characteristic according to the transmission signal TX. 44, the impedance values Zm, Zi, Zo of the input stage matching circuit 45 and the output stage matching circuit 46 are set to optimum values.
　バイアス回路４８は、増幅器４２に接続され、増幅器４２にバイアス電圧Ｖddを供給する。このバイアス回路４８は、増幅器４２とバイアス電源ＶＢとの間に接続されたインダクタ４９と、該インダクタ４９とバイアス電源ＶＢとの接続点とグランドとの間に接続されたバイパスコンデンサ５０とによって構成されている。そして、バイアス回路４８は、送信信号ＴＸに対して高周波的に開放状態となっている。 The bias circuit 48 is connected to the amplifier 42 and supplies a bias voltage Vdd to the amplifier 42. The bias circuit 48 includes an inductor 49 connected between the amplifier 42 and the bias power supply VB, and a bypass capacitor 50 connected between a connection point between the inductor 49 and the bias power supply VB and the ground. ing. The bias circuit 48 is open at a high frequency with respect to the transmission signal TX.
　バイアス回路５１は、増幅器４３に接続され、増幅器４３にバイアス電圧Ｖddを供給する。このバイアス回路５１は、バイアス回路４８とほぼ同様に、増幅器４３とバイアス電源ＶＢとの間に接続されたインダクタ５２と、該インダクタ５２の両端のうちバイアス電源ＶＢ側の端子とグランドとの間に接続されたバイパスコンデンサ５３とによって構成されている。そして、バイアス回路５１は、全ての通信周波数ｆ1～ｆnの送信信号ＴＸに対して高周波的に開放状態となっている。 The bias circuit 51 is connected to the amplifier 43 and supplies a bias voltage Vdd to the amplifier 43. In substantially the same manner as the bias circuit 48, the bias circuit 51 includes an inductor 52 connected between the amplifier 43 and the bias power source VB, and a terminal on the bias power source VB side of both ends of the inductor 52 and the ground. And a bypass capacitor 53 connected thereto. The bias circuit 51 is open at high frequencies with respect to the transmission signals TX of all the communication frequencies f 1 to f n .
　また、増幅器４２，４３のうち例えば最終段の増幅器４３に最も大きな電流が流れる場合には、少なくともこの増幅器４３に接続されたバイアス回路５１のインダクタ５２は、第１の実施の形態によるチップコイル２４とほぼ同様に形成されたチップコイル５４によって構成されている。このとき、チップコイル５４は、直流抵抗Ｒdcが例えば１Ωよりも小さく、送信信号ＴＸの通信周波数帯（通信周波数ｆ1～ｆn）でインピーダンスＺが数百Ω（例えばＺ＝４００Ω～８００Ω程度）となっている。 Further, when the largest current flows through, for example, the final stage amplifier 43 among the amplifiers 42 and 43, at least the inductor 52 of the bias circuit 51 connected to the amplifier 43 is connected to the chip coil 24 according to the first embodiment. The chip coil 54 is formed in substantially the same manner. At this time, the chip coil 54 has a DC resistance Rdc smaller than, for example, 1Ω, and an impedance Z of several hundred Ω in the communication frequency band (communication frequency f 1 to f n ) of the transmission signal TX (for example, Z = 400Ω to about 800Ω). It has become.
　かくして、本実施の形態でも第１の実施の形態と同様の作用効果を得ることができる。特に、本実施の形態では、バイアス回路４８，５１は、増幅器４２，４３とバイアス電源ＶＢ側との間に接続されたインダクタ４９，５２を備えるから、通信周波数ｆ1～ｆnの送信信号ＴＸに対してインダクタ４９，５２のインピーダンスを高めて、バイアス回路４８，５１を高周波的に開放状態にすることができる。 Thus, the present embodiment can provide the same operational effects as those of the first embodiment. In particular, in the present embodiment, since the bias circuits 48 and 51 include inductors 49 and 52 connected between the amplifiers 42 and 43 and the bias power supply VB side, the transmission signal TX of the communication frequencies f 1 to f n is provided. On the other hand, the impedances of the inductors 49 and 52 can be increased to open the bias circuits 48 and 51 in terms of high frequency.
　また、大きな電流が流れる増幅器４３に接続したバイアス回路５１は、そのインダクタ５２を、直流抵抗Ｒdcが１Ω以下で、かつ通信周波数帯でインピーダンスＺが２００Ω以上のチップコイル５４を用いて形成した。このため、インダクタ５２を通じて大きな電流を増幅器４３に供給することができると共に、小型のチップコイル５４を用いてバイアス回路５１を高周波的に開放状態にすることができ、電力増幅器４１全体を小型化することができる。 Further, the bias circuit 51 connected to the amplifier 43 through which a large current flows is formed by using the chip coil 54 having the DC resistance Rdc of 1Ω or less and the impedance Z of 200Ω or more in the communication frequency band. Therefore, a large current can be supplied to the amplifier 43 through the inductor 52, and the bias circuit 51 can be opened in a high frequency using a small chip coil 54, so that the entire power amplifier 41 is downsized. be able to.
　なお、第２の実施の形態では、送信信号ＴＸは、８００ＭＨｚ帯の信号を用いる構成としたが、例えば１．５ＧＨｚ帯、１．７ＧＨｚ帯、２ＧＨｚ帯等の他の通信周波数帯の信号を用いる構成としてもよい。 In the second embodiment, the transmission signal TX is configured to use an 800 MHz band signal. However, for example, a signal in another communication frequency band such as a 1.5 GHz band, a 1.7 GHz band, or a 2 GHz band is used. It is good also as a structure.
　また、前記各実施の形態では、複数の増幅器１２，１３，４２，４３にバイアス回路１８，２１，４８，５１をそれぞれ接続する構成とした。しかし、本発明はこれに限らず、例えば複数の増幅器１２，１３，４２，４３のうち最も大きな電流が流れる最終段の増幅器１３，４３にのみバイアス回路２１，５１を接続して設け、他の増幅器１２，４２に接続したバイアス回路１８，４８は省く構成としてもよい。 In each of the above embodiments, the bias circuits 18, 21, 48, 51 are connected to the plurality of amplifiers 12, 13, 42, 43, respectively. However, the present invention is not limited to this. For example, the bias circuits 21 and 51 are connected to only the final stage amplifiers 13 and 43 through which the largest current flows among the plurality of amplifiers 12, 13, 42, and 43. The bias circuits 18 and 48 connected to the amplifiers 12 and 42 may be omitted.
　また、前記各実施の形態では、複数の増幅器１２，１３，４２，４３のうち最も大きな電流が流れる最終段の増幅器１３，４３に接続されたバイアス回路２１，５１について、そのインダクタ２２，５２をチップコイル２４，５４によって構成するものとした。しかし、本発明はこれに限らず、例えば前段側の増幅器１２に接続されたバイアス回路１８，４８のインダクタ１９，４９を、チップコイル２４，５４を用いて構成してもよく、複数の増幅器１２，１３，４２，４３に接続された全てのバイアス回路１８，２１，４８，５１のインダクタ１９，２２，４９，５２をチップコイル２４，５４を用いて構成してもよい。 In each of the embodiments, the inductors 22 and 52 of the bias circuits 21 and 51 connected to the final stage amplifiers 13 and 43 through which the largest current flows among the plurality of amplifiers 12, 13, 42, and 43 are provided. The chip coils 24 and 54 are used. However, the present invention is not limited to this. For example, the inductors 19 and 49 of the bias circuits 18 and 48 connected to the amplifier 12 on the front stage side may be configured by using the chip coils 24 and 54, and a plurality of amplifiers 12. , 13, 42, 43, the inductors 19, 22, 49, 52 of the bias circuits 18, 21, 48, 51 may be configured using chip coils 24, 54.
　また、前記各実施の形態では、電力増幅器１１，４１を無線通信機１，３１に適用した場合を例に挙げて説明したが、例えば無線ＬＡＮ装置等のように、高周波の信号を増幅する装置に広く適用できるものである。 In each of the above embodiments, the case where the power amplifiers 11 and 41 are applied to the wireless communication devices 1 and 31 has been described as an example. However, a device that amplifies a high-frequency signal, such as a wireless LAN device, for example. It can be widely applied to.
　１１，４１　電力増幅器
　１２，４２　入力段の増幅器
　１３，４３　出力段の増幅器
　１４，４４　段間整合回路
　１５，４５　入力段整合回路
　１６，４６　出力段整合回路
　１７，４７　制御回路
　１８，２１，４８，５１　バイアス回路
　１９，２２，４９，５２　インダクタ
　２４，５４　チップコイル
　２４Ａ　フェライトコア
　２４Ｂ　巻線 11, 41 Power amplifier 12, 42 Input stage amplifier 13, 43 Output stage amplifier 14, 44 Interstage matching circuit 15, 45 Input stage matching circuit 16, 46 Output stage matching circuit 17, 47 Control circuit 18, 21, 48 , 51 Bias circuit 19, 22, 49, 52 Inductor 24, 54 Chip coil 24A Ferrite core 24B Winding

Claims (4)

  1. 　基地局から発信される周波数設定情報に基づいて複数の通信周波数帯のうち一の通信周波数の信号を増幅するマルチバンド用の電力増幅器であって、
    　互いに直列接続された複数の増幅器と、該複数の増幅器のうち少なくとも一の増幅器に接続されてバイアス電源からバイアス電圧を供給するバイアス回路とを備え、
    　前記複数の増幅器のうち少なくとも一の増幅器に接続された少なくとも一のバイアス回路は、該バイアス回路が接続された増幅器と前記バイアス電源との間に接続されたインダクタと、該インダクタと前記バイアス電源との接続点とグランドとの間に接続されたバイパスコンデンサとによって構成し、
    　前記インダクタは、フェライトコアに導体材料からなる太くて短い巻線を巻回して構成され、直流抵抗が小さく、かつ前記全ての通信周波数帯でインピーダンスが大きいチップコイルであることを特徴とする電力増幅器。     A multiband power amplifier that amplifies a signal of one communication frequency among a plurality of communication frequency bands based on frequency setting information transmitted from a base station,
    A plurality of amplifiers connected in series with each other, and a bias circuit connected to at least one of the plurality of amplifiers to supply a bias voltage from a bias power source,
    At least one bias circuit connected to at least one amplifier of the plurality of amplifiers includes an inductor connected between the amplifier to which the bias circuit is connected and the bias power source, the inductor and the bias power source, And a bypass capacitor connected between the connection point of
    The inductor is a chip coil configured by winding a thick and short winding made of a conductor material around a ferrite core, and having a small DC resistance and a large impedance in all the communication frequency bands. .
  2. 　前記インダクタの直流抵抗は１Ω以下で、全ての前記通信周波数帯でのインピーダンスが２００Ω以上である請求項１に記載の電力増幅器。 The power amplifier according to claim 1, wherein the DC resistance of the inductor is 1Ω or less, and the impedance in all the communication frequency bands is 200Ω or more.
  3. 　基地局から発信される周波数設定情報に基づいて通信周波数帯のうち一の通信周波数の信号を増幅するシングルバンド用の電力増幅器であって、
    　互いに直列接続された複数の増幅器と、該複数の増幅器のうち少なくとも一の増幅器に接続されてバイアス電源からバイアス電圧を供給するバイアス回路とを備え、
    　前記複数の増幅器のうち少なくとも一の増幅器に接続された少なくとも一のバイアス回路は、該バイアス回路が接続された増幅器と前記バイアス電源との間に接続されたインダクタと、該インダクタと前記バイアス電源との接続点とグランドとの間に接続されたバイパスコンデンサとによって構成し、
    　前記インダクタは、フェライトコアに導体材料からなる太くて短い巻線を巻回して構成され、直流抵抗が小さく、かつ前記通信周波数帯でインピーダンスが大きいチップコイルであることを特徴とする電力増幅器。     A power amplifier for a single band that amplifies a signal of one communication frequency in a communication frequency band based on frequency setting information transmitted from a base station,
    A plurality of amplifiers connected in series with each other, and a bias circuit connected to at least one of the plurality of amplifiers to supply a bias voltage from a bias power source,
    At least one bias circuit connected to at least one amplifier of the plurality of amplifiers includes an inductor connected between the amplifier to which the bias circuit is connected and the bias power source, the inductor and the bias power source, And a bypass capacitor connected between the connection point of
    The inductor is a chip coil configured by winding a thick and short winding made of a conductor material around a ferrite core, and having a small DC resistance and a large impedance in the communication frequency band.
  4. 　前記インダクタの直流抵抗は１Ω以下で、前記通信周波数帯でのインピーダンスが２００Ω以上である請求項３に記載の電力増幅器。 4. The power amplifier according to claim 3, wherein the inductor has a DC resistance of 1Ω or less and an impedance in the communication frequency band of 200Ω or more.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10189344A (en) * 1996-12-25 1998-07-21 Tdk Corp Chip inductor
JP2002171143A (en) * 2000-11-30 2002-06-14 Mitsubishi Electric Corp High frequency power amplifier
JP2007312031A (en) * 2006-05-17 2007-11-29 Matsushita Electric Ind Co Ltd Electronic device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10189344A (en) * 1996-12-25 1998-07-21 Tdk Corp Chip inductor
JP2002171143A (en) * 2000-11-30 2002-06-14 Mitsubishi Electric Corp High frequency power amplifier
JP2007312031A (en) * 2006-05-17 2007-11-29 Matsushita Electric Ind Co Ltd Electronic device

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