WO2011088853A1

WO2011088853A1 - Transmission channel, in particular for ultrasound applications

Info

Publication number: WO2011088853A1
Application number: PCT/EP2010/005927
Authority: WO
Inventors: Sandro Rossi; Giulio Ricotti; Davide Ugo Ghisu; Antonio Ricciardo
Original assignee: Stmicroelectronics S.R.L.
Priority date: 2009-12-30
Filing date: 2010-09-29
Publication date: 2011-07-28
Also published as: CN102668380A; CN102668380B

Abstract

A transmission channel (1) is described comprising at least one high voltage buffer block (4) comprising buffer transistors (MB1, MB2, MB3, MB4) and respective buffer diodes (DB1, DB2, DB3, DB4), being inserted between respective voltage references (HVP0, HVP1, HVM0, HVM1), a clamping circuit (10) being connected to a first output terminal (HVout) of the transmission channel (1), an antinoise block (6) being connected between the first output terminal (HVout) and a connection terminal (Xdcr) of the transmission channel (1); as well as a switching circuit (30) being inserted between the connection terminal (Xdcr) and a second output terminal (LVout) of the transmission channel (1). Advantageously according to the invention, the clamping circuit (10) comprises a clamping core (11), a reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4 ) inserted between circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) of the high voltage buffer block (4) and of the clamping circuit (10), the circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2 ) being in correspondance with conduction terminals of said transistors (MB1,MB2,MB3,MB4,MC1,MC2) comprised into the high voltage buffer block(4) and into the clamping circuit (10), and a switching circuit (30).

Description

Title: Transmission channel, in particular for ultrasound applications

DESCRIPTION

Technical Field

The present invention relates to a transmission channel.

The invention particularly, but not exclusively, relates to a transmission channel, in particular for ultrasound applications and the following description is made with reference to this field of application by way of illustration only.

Background Art

As it is well known, the sonography or ultrasonography is a system of medical diagnostic testing that uses ultrasonic waves or ultrasounds and is based on the principle of the transmission of the ultrasounds and of the emission of echo and is widely used in the internist, surgical and radiological field.

The ultrasounds normally used are comprised between 2 and 20 MHz. The frequency is chosen by taking into consideration that higher frequencies have a greater image resolving power, but penetrate less in depth in the subject under examination.

These ultrasounds are being normally generated by a piezoceramic crystal inserted in a probe maintained in direct contact with the skin of the subject with the interposition of a suitable gel (being suitable for eliminating the air between probe and subject's skin, allowing the ultrasounds to penetrate in the anatomic segment under examination). The same probe is able to collect a return signal or echo, which is suitably processed by a computer and displayed on a monitor.

In particular, the ultrasounds that reach a variation point of the acoustic impedance, and thus for example an internal organ, are partially reflected and the reflected percentage conveys information about the impedance difference between the crossed tissues. It is to be noted that, the big impedance difference between a bone and a tissue being considered, with the sonography it is not possible to see behind a bone, which causes a total reflection of the ultrasounds, while air or gas zones give "shade", causing a partial reflection of the ultrasounds.

The time employed by an ultrasonic wave for carrying out the path of going, reflection and return is provided to the computer, which calculates the depth wherefrom the echo has come, thus identifying the division surface between the crossed tissues (corresponding to the variation point of the acoustic impedance and thus to the depth wherefrom the echo comes).

Substantially, an ultrasonographer, in particular a diagnostic apparatus based on the ultrasound sonography, essentially comprises three parts:

a probe comprising at least one transducer, in particular of the ultrasonic type, which transmits and receives an ultrasound signal;

an electronic system that drives the transducer for the generation of the - - ultrasound signal or pulse to be transmitted and receives an echo signal of return at the probe of this pulse, processing in consequence the received echo signal; and

a displaying system of a corresponding sonography image processed starting from the echo signal received by the probe.

In particular, the word transducer generally indicates an electric or electronic device that converts a type of energy relative to mechanical and physical quantities into electric signals. In a broad sense, a transducer is sometimes defined as any device that converts energy from one form to another, so that this latter can be re-processed either by men or by other machines. Many transducers are both sensors and actuators. An ultrasonic transducer usually comprises a piezoelectric crystal that is suitably biased for causing its deformation and the generation of the ultrasound signal or pulse.

A typical transmission channel or TX channel being used in these applications is schematically shown in Figure 1 , globally indicated with 1.

In particular, the transmission channel 1 comprises an input logic 2 that drives, in correspondence with an input bus BUS™, a level shifter 3, in turn connected to a high voltage buffer block 4. The high voltage buffer block 4 is inserted between pairs of high voltage references, respectively higher HVPO and HVP1 and lower HVMO and HVM 1 , and has a pair of input terminals, INB1 and INB2, connected to the level shifter 3, as well as a pair of output terminals, OUTB 1 and OUTB2, connected to a corresponding pair of input terminals, INC 1 and INC2 of a clamping block 5.

Furthermore, the clamping block 5 is connected to a clamp voltage reference PGND and has an output terminal corresponding to a first output terminal HVout of the transmission channel 1 , in turn connected, through an antinoise block 6, to a connection terminal Xdcr for the transducer to be driven through the transmission channel 1.

Finally, a high voltage switch 7 is inserted between the connection terminal Xdcr and a second output terminal LVout of the transmission channel 1. This high voltage switch 7 is able to transmit an output signal being at the output of the antinoise block 6 to the second output terminal LVout during the receiving step of the transmission channel 1.

It is to be noted that the switch 7 is a high voltage one since, during the transmission step of the transmission channel 1, a signal being on the connection terminal Xdcr, always indicated with Xdcr, is a high voltage signal although the switch 7 is off. When this switch 7 is instead on, i.e. during the reception step of the transmission channel 1, the signal Xdcr is generally at a voltage value next to zero since the piezoelectric transducer connected to the - - transmission channel 1 is sensing small return echoes of ultrasound pulse signals, as shown in Figure 2.

Typically, in fact, an ultrasonic transducer transmits a high voltage pulse of the duration of a few us, and receives the echo of this pulse, generated by the reflection on the organs of a subject under examination, for the duration of about 250us, to go back to the transmission of a new high voltage pulse.

For example, a first pulse IM 1 and a second pulse IM2 are transmitted with a peak to peak excursion equal, in the example shown, to 190Vpp with reception by the transducer of corresponding echoes shown in Figure 2 and indicated with El and E2.

The high voltage switch 7 is shown in greater detail in Figure 3A, while its equivalent circuit according to working conditions (ON) is shown in Figure 3B.

In particular, the high voltage switch 7 comprises a first MS I and a second switching transistor MS2, being inserted, in series to each other, between the connection terminal Xdcr and the second output terminal LVout of the transmission channel 1 and having respective control or gate terminals connected, at the turning-on of the switch 7 itself, to a first and to a second supply voltage reference, VDD_M and VDD_P respectively. Figure 3A also shows the equivalent diodes, DS 1 and DS2, of the switching transistors, MS I and MS2, as well as their gate-source capacities, Cgl and Cg2 respectively.

In particular, the first capacity Cgl of the first switching transistor MSI is connected between the corresponding gate terminal, in turn connected to the first supply voltage reference VDD_M and a first switching node XS 1 , corresponding to a source terminal of the first switching transistor MS I . Similarly, the second capacity Cg2 of the second switching transistor MS2 is connected between the relative gate terminal, in turn connected to the second supply voltage reference VDD_P and a second switching node XS2, corresponding to a source terminal of the second switching transistor MS2.

As shown in the equivalent circuit of Figure 3B, when the high voltage switch 7 is on and thus the gate terminals of the switching transistors MS I and MS2 are connected to the first VDD_M and to the second supply voltage reference VDD_P as indicated in Figure 3 A (which in Figure 3B, for sake of simplicity, have been shown as a single reference voltage, in particular the ground, being these first and second supply voltage references fix supplies), these switching transistors behave as respective resistances Rl and R2, that are inserted between the connection terminal Xdcr and the second output terminal LVout of the transmission channel 1 (the second output terminal LVout coinciding with the second switching node XS2) and interconnected in correspondence with the first switching node XS 1. - -

According to these conditions, the first capacity Cgl is connected between the first connection node XS 1 and the first supply voltage reference VDD_M, while the second capacity Cg2 is connected between the second connection node XS2 and the second supply voltage reference VDD_P, being these first and second supply voltage references fix supplies, shown by way of simplicity in Figure 3B as a single reference voltage, in particular the ground GND. This parallel of capacities introduces unwillingly a strong mitigation of the signal at the input of the high voltage switch 7, i.e. of the signal at the output of the transmission channel 1 after the antinoise block 6.

In general, then, the switch 7 should be a high voltage one so as not to break itself during the transmission step but it is in practice on always with low voltages during the receiving step.

Further, the high voltage buffer block 4 comprises a first branch comprising a first buffer transistor MB 1 and a first buffer diode DB 1 , being inserted, in series to each other, between a first higher voltage reference HVPO and a buffer central node XBc, as well as a second buffer diode DB2 and a second buffer transistor MB2, inserted, in series to each other, between the buffer central node XBc and a first lower voltage reference HVMO. The first and second buffer transistors, MB 1 and MB2, have respective control or gate terminals in correspondence with a first XB 1 and with a second inner circuit node XB2 of the high voltage buffer block 4 and connected to, and driven by, a first DRB 1 and a second buffer input driver DRB2, in turn connected to the level shifter 3 in correspondence with the first and second input terminals, INB 1 and INB2, of the high voltage buffer block 4.

The high voltage buffer block 4 also comprises, in parallel to the first branch, a second branch in turn comprising a third buffer transistor MB3 and a third buffer diode DB3, being inserted, in series to each other, between a second higher voltage reference HVP1 and the buffer central node XBc, as well as a fourth buffer diode DB4 and a fourth buffer transistor MB4, inserted, in series to each other, between the buffer central node XBc and a second lower voltage reference HVM 1. The third and fourth buffer transistors, MB3 and MB4, have respective control or gate terminals in correspondence with a third XB3 and a fourth inner circuit node XB4 of the high voltage buffer block 4 and connected to, and driven by, a third DRB3 and a fourth buffer input driver DRB4, in turn connected to the first XB 1 and to the second inner circuit node XB2 and then to the first DRB 1 and to the second buffer input driver DRB2, respectively, as well as to a first OUTB 1 and to a second output terminal OUTB2.

In particular, in the example of the figure, the first and third buffer transistors, MB 1 and MB3, are high voltage P-channel MOS transistors (HV Pmos) while the second and fourth buffer transistors, MB2 and MB4, are high - - voltage N-channel MOS transistors (HV Nmos). Moreover, the buffer diodes, DB 1, DB2, DB3 and DB4, are high voltage diodes (HV diode).

The clamping block 5 has in turn a first INC1 and a second input terminal INC2, respectively connected to the first OUTB 1 and second output terminal OUTB2 of the high voltage buffer block 4.

In particular, the clamping block 5 comprises a first clamp driver DRC1 connected between the first input terminal INC 1 and a control or gate terminal of a first clamp transistor MC I, in turn inserted, in series with a first clamp diode DC1, between the clamp voltage reference PGND, in particular a ground, and a clamp central node XC. The first clamp transistor MC I and the first clamp diode DC 1 are interconnected in correspondence with a first clamp circuit node XC 1.

The clamping block 5 also comprises a second clamp driver DRC2 connected between the second input terminal INC2 and a control or gate terminal of a second clamp transistor MC2, in turn inserted, in series with a second clamp diode DC2, between the clamp central node XCc and the clamp voltage reference PGND. The second clamp transistor MC2 and the second clamp diode DC2 are interconnected in correspondence with a second clamp circuit node XC2.

The clamp central node XCc is also connected to the first output terminal HVout of the transmission channel 1 , in turn connected to the connection terminal Xdcr through an antinoise block 6 comprising respective first and second antinoise diodes, DN1 and DN2, connected in antiparallel, i.e. by having the anode terminal of the first diode connected to the cathode terminal of the second diode and vice versa, between the first output terminal HVout and the connection terminal Xdcr.

In particular, in the example of the figure, the first clamp transistor MC I is a high voltage P-channel MOS transistor (HV Pmos) while the second clamp transistor MC2 is a high voltage N-channel MOS transistor (HV Nmos). Moreover, the clamp diodes, DC 1 and DC2, are high voltage diodes (HV diode) while the antinoise diodes, DN 1 and DN2, are low voltage diodes (LV diode).

The clamping block 5 is also shown in Figure 4, in the case of a clamping operation to a ground voltage reference GND, i.e. during the receiving step of the transmission channel 1. It is to be noted that the clamping to the ground voltage reference GND should be ensured also when the load is mainly capacitive. In this case, the output terminal of the transmission channel should be brought back to this ground value after the transmission.

Furthermore, the correct clamping to the ground is important in applications in which the high voltage wave form to be transmitted, besides oscillating between a positive value of high voltage and a negative value of high voltage, sta3's for determined periods of time at the ground value. - -

Also the antinoise block 6 is indicated too, being connected between the first output terminal HVout and the connection terminal Xdcr of the transmission channel 1.

In particular, this Figure 4 also shows the equivalent diodes, DMC 1 and DMC2, of the clamp transistors, MC I and MC2, respectively, the first and second clamp input drivers, DRC l and DRC2, being connected between a first and a second clamp supply voltage reference, higher VDD_P and lower VDD_M, respectively, and the ground GND, whereto also the clamp central node XCc is connected.

It is evident from the scheme of Figure 4, that, when the clamping block 5 is on, the first output terminal HVout is at a voltage value, corresponding to the value of ground voltage GND plus or minus a diode voltage and the connection terminal Xdcr to a value of ground voltage GND plus or minus two diode voltages.

In reality, the optimal working condition would have this first output terminal HVout at a value equal to the ground GND, condition in which the distortions of the transmitted signal by the transmission channel 1 are minimum. In fact, the real working conditions of the clamping block 5 above illustrated show worsening in the performances of second harmonic, especially under conditions of low supply voltages.

In case of connection of a load of great value, a high current can circulate through the high voltage clamp diodes DC1 and DC2, charging the junction intrinsic capacities of the same diodes and causing a malfunction.

In fact, during the reception step of the transmission channel 1 , it is necessary to wait that the connection terminal Xdcr is at zero. Any leakage current of the first output terminal HVout, caused by the noise introduced by the charges being in the clamp diodes DC 1 and DC2, causes a raising of the voltage value also on this connection terminal Xdcr and thus a receiving disturbance.

In particular, once the high voltage buffer block 4 has been turned on again, the first output terminal HVout does not immediately respond since most of the current supplied by this high voltage buffer block 4 is used for the discharge of the junction capacities of the clamp diodes DC 1 and DC2, precharged during the clamping step. This malfunction is particularly felt in case of short pulses.

Moreover, during the reception step in which the clamping block 5 is on and the connection terminal Xdcr has a voltage value next to but not equal to the ground GND, a leakage current could charge the first output terminal HVout at a voltage higher than the threshold voltage of the antinoise diodes, DN 1 and DN2, of the antinoise block 6 and, in consequence, disturb a reception exactly on the connection terminal Xdcr.

After a cycle of pulses, the anode terminals of the first DB1 and of the third - - buffer diode DB3 and the cathode terminals of the second DB2 and of the fourth buffer diode DB4 stabilise at a voltage depending on different factors such as the value of a supply voltage, the value of the inner capacities, which one and how many transistors are used for the switching, the switching frequency etc..

This means that each successive pulse train finds a different and non defined initial condition.

By changing the initial status also the output wave form is modified with the consequence that, the input control being identical, it is possible to obtain different outputs. In other words, the wave form of the output signal is function of the input signals and of the initial condition resulting from the switches previously occurred thus creating a sort of "memory effect".

The technical problem of the present invention is that of providing a configuration for a transmission channel able to ensure correct and predictable switching initial conditions, provided with a clamping circuit able to ensure a correct clamping to a voltage reference, in particular of ground and with a switching circuit between a receiving mode and a transmission mode able to avoid undesired mitigations of a signal at its input during the receiving step, thus suitable for being used for ultrasound applications and having such structural and functional features as to overcome the limits and the drawbacks still affecting the channels realised according to the prior art.

Disclosure of Invention

The solution idea underlying the present invention is that of using suitable high voltage diodes connected to the inner nodes of the high voltage buffer block of the transmission channel for correctly biasing its condition between a pulse cycle and another one so as to eliminate the memory effect of this buffer block, as well as of associating the clamp transistors to corresponding high voltage MOS transistors able to close themselves when the clamping circuit is active and likewise able to sustain positive and negative high voltages when instead the clamping circuit is not active and the transistors are in open configuration and of realising a switching circuit of the type comprising switching transistors and provided with suitable bootstrap circuitry able to correctly drive the control terminals of these switching transistors with a correct "following" of a signal at the input of the switching circuit itself towards its output.

On the basis of this solution idea the technical problem is solved by a transmission channel of the type comprising at least:

a high voltage buffer block comprising buffer transistors and respective buffer diodes, being inserted between respective voltage references, said high voltage buffer block having at least one first and one second output terminal, as well as a buffer central node; - - a clamping circuit being connected to a first output terminal of said transmission channel and having at least one first and one second input terminal connected to said first and second output terminals of said high voltage buffer block, a first and a second clamp circuit node, as well as a clamp central node connected to said buffer central node;

an antinoise block being connected between said first output terminal and a connection terminal of said transmission channel; as well as

a switching circuit being inserted between said connection terminal and a second output terminal of said transmission channel

characterised in that

said clamping circuit comprises a clamping core in turn including at least one first and one second clamp transistor, connected to said central node and to said first and second clamp circuit node, respectively, through diodes connected to prevent the body diodes of said clamping transistors from conducting and having respective control terminals, as well as at least one first switching off transistor connected to said output terminal and to said first clamp transistor and a second switching off transistor connected to said output terminal and to said clamp transistor, said first and second clamp transistors being high voltage MOS transistors of complementary type and said first and second switching off transistors being high voltage MOS transistors of complementary type connected to said first and second clamp transistors by having the respective equivalent or body diodes in anti-series so as to close themselves when said clamping circuit is active and to sustain positive and negative high voltages when said clamping circuit is not active;

said reset circuit comprising diodes and being inserted between circuit nodes of said high voltage buffer block and of said clamping circuit, said circuit nodes being in correspondence with conduction terminals of said transistors comprised into said high voltage buffer block and into said clamping circuit, and

said switching circuit comprising at least one first and one second switching transistor which are high voltage MOS transistors of complementary type being inserted, in series to each other and by having respective equivalent or body diodes in anti-series, between said connection terminal and said second output terminal, as well as at least one bootstrap circuit connected to respective first and second control terminals of said at least one first and one second switching transistor, as well as to respective first and second voltage references and having values of parasite capacities between said first and second control terminals and at least one first and one second bootstrap node of at least one order of magnitude lower with respect to the gate-source capacities of said at least one first and one second switching transistor. - -

More in particular, the invention comprises the following supplementary and optional characteristics, taken alone or in combination, if needed.

According to an aspect of the invention, said first switching off transistor can be a high voltage P-channel MOS transistor and said second switching off transistor can be a high voltage N-channel MOS transistor.

According to another aspect of the invention, said transmission channel can further comprise a driving circuit connected to respective control terminals of said first and second clamp transistors and of said first and second switching off transistors and suitable for closing said first and second switching off transistors when said clamping circuit is active.

According to this aspect of the invention, said driving circuit can comprise a first and a second driving transistor, being inserted, in a crossed way, between said control terminals of said first and second clamp transistors, and respective control terminals of said first and second switching off transistors.

Further according to this aspect of the invention, said first driving transistor can be inserted between said control terminal of said first clamp transistor and a control terminal of said second switching off transistor and said second driving transistor can be inserted between a control terminal of said first switching off transistor and said control terminal of said second clamp transistor.

Still according to this aspect of the invention, said first and second driving transistors can have respective control terminals connected to said clamp central node.

Furthermore, according to an aspect of the invention, said clamping core can be connected at the input to an input driver block comprising a first and a second driver inserted between a first and a second supply voltage reference and having respective output terminals connected to said control terminals of said first and second clamp transistors.

Still according to another aspect of the invention, said first clamp transistor can be a high voltage N-channel MOS transistor and said second clamp transistor can be a high voltage P-channel MOS transistor.

Furthermore, according to an aspect of the invention, said first and second driving transistors can be high voltage MOS transistors of a type similar to said first and second switching off transistors.

Moreover, according to an aspect of the invention, said first switching off transistor can be a high voltage N-channel MOS transistor and said second switching off transistor can be a high voltage P-channel MOS transistor.

According to another aspect of the invention, in which said high voltage buffer block comprises at least one first branch in turn including a first buffer transistor and a first buffer diode, being inserted, in series to each other, between - - a first higher voltage reference and a buffer central node and interconnected in correspondence with a first memory node, as well as a second buffer diode and a second buffer transistor, being inserted, in series to each other, between said buffer central node and a first lower voltage reference and interconnected in correspondence with a second memory node, said reset circuit can comprise:

a first memory diode, being inserted between said first memory node and said first clamp circuit node; and

a second memory diode, being inserted between said second memory node and said second clamp circuit node.

According to this aspect of the invention, said first memory diode can have a cathode terminal connected to said first memory node and an anode terminal connected to said first clamp circuit node and said second memory diode can have an anode terminal connected to said second memory node and a cathode terminal connected to said second clamp circuit node.

Also according to this aspect of the invention, said first memory node can be connected to an anode terminal of said first buffer diode and said first clamp circuit node can be connected to an anode terminal of said first clamp diode and said second memory node can be connected to a cathode terminal of said second buffer diode and said second clamp circuit node can be connected to a cathode terminal of said second clamp diode.

According to another aspect of the invention, said first memory node can be in correspondence with a drain terminal of said first buffer transistor and said second memory node can be in correspondence with a drain terminal of said second buffer transistor.

Moreover, according to an aspect of the invention in which said high voltage buffer block also comprises, in parallel to said first branch, a second branch in turn including a third buffer transistor and a third buffer diode, being inserted, in series to each other, between a second higher voltage reference and said buffer central node and interconnected in correspondence with a third memory node, as well as a fourth buffer diode and a fourth buffer transistor, being inserted, in series to each other, between said buffer central node and a second lower voltage reference and interconnected in correspondence with a fourth memory node, said reset circuit can further comprise:

a third memory diode, being inserted between said third memory node and said first clamp circuit node; and

a fourth memory diode, being inserted between said fourth memory node and said second clamp circuit node.

According to an aspect of the invention, said third memory diode can have a cathode terminal connected to said third memory node and an anode terminal - - connected to said first clamp circuit node and said fourth memory diode can have an anode terminal connected to said fourth memory node and a cathode terminal connected to said second clamp circuit node.

Furthermore, according to an aspect of the invention, said third memory node can be connected to an anode terminal of said third buffer diode and said first clamp circuit node can be connected to an anode terminal of said first clamp diode and said fourth memory node can be connected to a cathode terminal of said fourth buffer diode and said second clamp circuit node can be connected to a cathode terminal of said second clamp diode.

According to another aspect of the invention, said third memory node can be in correspondence with a drain terminal of said third buffer transistor and said fourth memory node can be in correspondence with a drain terminal of said fourth buffer transistor.

Furthermore, according to this aspect of the invention, said high voltage buffer block can comprise respective buffer drivers connected to control terminals of said buffer transistors.

According to another aspect of the invention, said bootstrap circuit of said switching circuit can comprise at least one first biasing generator inserted between said first control terminal and said first bootstrap node, as well as a second biasing generator inserted between said second bootstrap node and said second control terminal as first and second parasite capacities of said bootstrap circuit.

According to this aspect of the invention, said at least one first and second biasing generator can supply respective first and second biasing current.

Moreover, according to an aspect of the invention, said bootstrap circuit can further comprise a first bootstrap transistor being inserted, in series to a first bootstrap resistive element, between said first control terminal of said first switching transistor and said second bootstrap node, as well as a second bootstrap transistor being inserted, in series to a second bootstrap resistive element, between said second control terminal of said second switching transistor and said first bootstrap node.

Furthermore, according to this aspect of the invention, said first bootstrap transistor can have a control terminal connected to a first inner circuit node of said switching circuit, corresponding to a source terminal of said first switching transistor and said second bootstrap transistor can have a control terminal connected to a second inner circuit node of said switching circuit, corresponding to a source terminal of said second switching transistor.

According to another aspect of the invention, said first bootstrap transistor can be a low voltage N-channel MOS transistor and said second bootstrap - - transistor can be a low voltage P-channel MOS transistor.

Moreover, according to an aspect of the invention, said first and second bootstrap nodes can be connected to said first and second voltage references, respectively.

Finally, according to an aspect of the invention, said values of parasite capacities of said bootstrap circuit can be of at least some orders of magnitude, preferably three, lower with respect to the gate-source capacities of said at least one first and one second switching transistor.

The characteristics and the advantages of the transmission channel according to the invention will be apparent from the following description of an embodiment thereof given by way of indicative and non limiting example with reference to the annexed drawings.

Brief Description of Drawings

In these drawings:

- Figure 1 schematically shows a transmission channel for ultrasound applications realised according to the prior art;

Figure 2 schematically shows a first and a second ultrasound pulse used in an ultrasonic transducer;

Figure 3A shows in greater detail a high voltage switch during a turn-on step and being comprised within the transmission channel of Figure 1 ;

Figure 3B shows an equivalent circuit of the switch of Figure 3A under turn-on conditions;

Figure 4 shows in greater detail a block comprised within the transmission channel of Figure 1 ;

- Figure 5 schematically shows a transmission channel, in particular for ultrasound applications, realised according to the invention;

Figure 6 schematically shows a clamping circuit comprised within the transmission channel of Figure 5;

Figure 7 A shows in greater detail a switching circuit comprised within the transmission channel of Figure 5; and

Figure 7B shows an equivalent circuit of the switching circuit of Figure 7A according to turning-on conditions.

Modes for Carrying Out the Invention

With reference to these figures, and in particular to Figure 5, a transmission channel for ultrasound applications is described, being globally indicated with 1.

Elements being structurally and functionally correspondent to the transmission channel described in relation to the prior art and shown in Figure 1 will be given the same alphanumeric references for sake of simplicity.

In its more general form, the transmission channel 1 is of the type - - comprising at least one high voltage buffer block 4 in turn comprising buffer transistors and respective buffer diodes, being inserted between respective voltage references. The buffer transistors are also connected to a clamping circuit 10, in turn comprising clamping transistors connected to internal nodes of the transmission channel 1 through diodes connected to prevent the body diodes of the clamping transistors from conducting. Moreover, the transmission channel 1 comprises at least one reset circuit 20 comprising diodes and being inserted between circuit nodes of the high voltage buffer block 4 and of the clamping circuit 10, said circuit nodes being in correspondence with conduction terminals of the transistors comprised into the high voltage buffer block 4 and into the clamping circuit 10.

According to an embodiment of the invention, the transmission channel 1 comprises:

a clamping circuit 10 connected to a clamp voltage reference PGND and comprising a clamping core 1 1 connected to a first output terminal HVout and having a clamp central node XC connected to a buffer central node XB of a high voltage buffer block 4;

a reset circuit 20, comprising diodes and suitably connected to the inner nodes of the high voltage buffer block 4 and of the clamping circuit 10 that are to be correctly "repositioned", as well as

a switching circuit 30 inserted between a connection terminal Xdcr to a load and a second output terminal LVout of the transmission channel 1.

More in detail, the reset circuit 20 is connected to the interconnection circuit nodes between the transistors and the buffer diodes of the high voltage buffer block 4 and to a first and to a second clamp circuit node, XC1 and XC2, of the clamping circuit 10. In particular, the reset circuit 20 is connected:

to a first memory node XME1 , between the first buffer transistor MB 1 and the first buffer diode DB 1 ;

to a second memory node XME2, between the second buffer transistor MB2 and the second buffer diode DB2;

to a third memory node XME3, between the third buffer transistor MB3 and the third buffer diode DB3;

to a fourth memory node XME4, between the fourth buffer transistor MB4 and the fourth buffer diode DB4;

- to the first clamp circuit node XC 1 ; and

to the second clamp circuit node XC2.

As previously seen, the high voltage buffer block 4 comprises at least one first branch in turn including the first buffer transistor MB1 and the first buffer diode DB1 , being inserted, in series to each other, between a first higher voltage - - reference HVPO and the buffer central node XB and interconnected in correspondence with the first memory node XME1, as well as the second buffer diode DB2 and the second buffer transistor MB2, being inserted, in series to each other, between the buffer central node XB and a first lower voltage reference HVMO and interconnected in correspondence with the second memory node XME2.

The high voltage buffer block 4 also has a first OUTB 1 and a second output terminal OUTB2 respectively connected to a first INC1 and to a second input terminal INC2 of the clamping circuit 10.

The reset circuit 20 comprises respective memory nodes being inserted between these circuit nodes and in particular at least:

one first memory diode DME1, being inserted between the first memory node XME 1 and the first clamp circuit node XC 1 ; and

one second memory diode DME2, being inserted between the second memory node XME2 and the second clamp circuit node XC2.

In particular, the first memory diode DME1 has a cathode terminal connected to the first memory node XME1 and an anode terminal connected to the first clamp circuit node XC1. In a dual way, the second memory diode DME2 has an anode terminal connected to the second memory node XME2 and a cathode terminal connected to the second clamp circuit node XC2.

Moreover, as previously seen, the high voltage buffer block 4 comprises, in parallel to the first branch, a second branch in turn including the third buffer transistor MB3 and the third buffer diode DB3, being inserted, in series to each other, between a second higher voltage reference HVP1 and the buffer central node XB and interconnected in correspondence with the third memory node XME3, as well as the fourth buffer diode DB4 and the fourth buffer transistor MB4, being inserted, in series to each other, between the buffer central node XB and a second lower voltage reference HVM1 and interconnected in correspondence with the fourth memory node XME4.

Further, the reset circuit 20 thus comprises:

a third memory diode DME3, being inserted between the third memory node XME3 and the first clamp circuit node XC 1 ; and

a fourth memory diode DME4, being inserted between the fourth memory node XME4 and the second clamp circuit node XC2.

In particular, the third memory diode DME3 has a cathode terminal connected to the third memory node XME3 and an anode terminal connected to the first clamp circuit node XC1. In a dual way, the fourth memory diode DME4 has an anode terminal connected to the fourth memory node XME4 and a cathode terminal connected to the second clamp circuit node XC2. - -

The memory diodes DME1, DME2, DME3 and DME4 are high voltage diodes (HV diode).

In substance, the reset circuit 20 forces all the circuit nodes it is connected to in a neighbourhood of a value of ground reference and allows the transmission channel 1 to restart according to a same condition at any pulse cycle.

It is to be noted that the memory circuit nodes correspond to the drain terminals of the corresponding buffer transistors of the high voltage buffer block 4. Moreover, the memory diodes are connected so as to have terminals being not homologue with the buffer diodes.

In particular, the first memory diode DME1 has the cathode terminal connected to the anode terminal of the first buffer diode DB 1 , the second memory diode DME2 has the anode terminal connected to the cathode terminal of the second buffer diode DB2, the third memory diode DME3 has the cathode terminal connected to the anode terminal of the third buffer diode DB3, and the fourth memory diode DME4 has the anode terminal connected to the cathode terminal of the fourth buffer diode DB4.

As previously seen, the high voltage buffer block 4 comprises respective buffer drivers connected to control terminals of the buffer transistors.

Furthermore, the transmission channel 1 comprises an antinoise block 6 being inserted between the first output terminal HVout and the connection terminal Xdcr.

As shown in greater detail in Figure 6, the clamping circuit 10 comprises the clamping core 1 1 , connected to the first output terminal HVout and in turn comprising a first and a second clamp transistor, MC I and MC2, connected to the clamp central node XC and having respective control or gate terminals, XG1 and XG2.

These first and second clamp transistor, MC I and MC2, have respective first and second equivalent diodes, DMC1 and DMC2, also indicated in the figure. In particular, in the example of the figure, the first clamp transistor MC I is a high voltage N-channel MOS transistor (HV Nmos) while the second clamp transistor MC2 is a high voltage P-channel MOS transistor (HV Pmos).

The clamping core 1 1 also comprises a first and a second switching off transistor, MSI and MS2. In particular, the first switching off transistor MSI is inserted in series to the first clamp transistor MC I and connected to the first output terminal HVout. Moreover, the second switching off transistor MS2 is inserted in series to the second clamp transistor MC2 and also connected to the first output terminal HVout.

These first and second switching off transistors, MSI and MS2, have respective first and second equivalent diodes, DMS 1 and DMS2, also indicated in - - the figure. In particular, the first and second switching off transistors, MS I and MS2, are high voltage MOS transistors of the opposed type with respect to the clamp transistors, MCI and MC2. In the example of the figure, the first switching off transistor MSI is a high voltage P-channel MOS transistor (HV Pmos), while the second switching off transistor MS2 is a high voltage N-channel MOS transistor (HV Nmos). Moreover, the first equivalent or body diodes, DMS 1 and DMC1, of the first switching off transistor MS I and of the first clamping transistor MCI , respectively, are connected in anti-series in correspondence with a first clamp circuit node XC1. Analogously, the second equivalent or body diodes, DMS2 and DMC2, of the second switching off transistor MS2 and of the second clamping transistor MC2, respectively, are connected in anti-series in correspondence with a second clamp circuit node XC2.

These first and second switching off transistors, MSI and MS2, are MOS transistors able to close themselves when the clamping circuit 10 is active and to sustain positive and negative high voltages when the clamping circuit 10 is not active and the transistors are in open configuration, in particular also thanks to the use of a suitable driving circuit, as it will be clarified hereafter.

Further, the clamping core 1 1 is then connected at the input to an input driver block 13 through a driving circuit 14 of the switching off transistors MS I and MS2, suitable for closing the first and second switching off transistors, MS I and MS2 when the clamping circuit 10 is active, as it will be clarified hereafter in the description.

In particular, the input driver block 13 is of the low voltage type and comprises a first driver DRC1 inserted between a first and a second clamp supply voltage reference, higher VDD_P and lower VDD_M, respectively, and having an output terminal connected to the first control terminal XG1 of the first clamp transistor MCI as well as a second driver DRC2, in turn inserted between the first and second clamp supply voltage references, higher VDDJP and lower VDD_M, respectively, and having an output terminal connected to the second control terminal XG2 of the second clamp transistor MC2.

The driving circuit 14 comprises a first and a second driving transistor, M l and M2, inserted, in a crossed way, between the control terminals of the first and second clamp transistors, MCI and MC2, and of the first and second switching off transistors, MS I and MS2.

In particular, the first driving transistor M l is inserted between the first control terminal XG1 of the first clamp transistor MC I and a control or gate terminal XS2 of the second driving transistor MS2, while the second driving transistor M2 is inserted between a control or gate terminal XS1 of the first driving transistor MS I and the control terminal XG2 of the second clamp - - transistor MC2.

Furthermore, the first and the second driving transistor, Ml and M2, have respective control or gate terminals, XI and X2, connected to the clamp central node XC.

In particular, the first and second driving transistors, M l and M2, are high voltage MOS transistors of a similar type with respect to the switching off transistors MSI and MS2. In particular, in the example of the figure, the first driving transistor M 1 is a high voltage P-channel MOS transistor (HV Pmos) while the second driving transistor M2 is a high voltage N-channel MOS transistor (HV Nmos). These first and second driving transistors, Ml and M2, have respective first and second equivalent diodes, DM 1 and DM2, as indicated in the figure.

In this way, the driving circuit 14 ensures the switching off of the switching off transistors MS I and MS2. In particular, the driving circuit 14 drives correctly at high voltage the first and second switching off transistors, MSI and MS2, forcing their closure during the clamping step, while the first and second clamp transistors, MC I and MC2, are driven at low voltage (with voltage that varies between 0 and 3 V) directly by the input driver block 13.

The first output terminal HVout is thus forced to ground and kept to ground thanks to the switching off transistors MS 1 and MS2 driven by the driving circuit 14, in particular at the turning-on and switching off of the first and of the second switching off transistors MS 1 and MS2 by the first and second driving transistors M l and M2.

It is to be noted that, during the clamping step, also with a high load value (and according to receiving conditions in case of application to a transmission channel), the current flows through the channel of the transistors of the clamping circuit 10 without charging the intrinsic diodes DMS l and DMS2 of the switching off transistors MSI and MS2, overcoming in this way the problems seen in relation to the prior art. In pai ticular, the load current does not flow through the junction of the equivalent diodes DMS l and DMS2 of the switching off transistors MSI and MS2, but through their channel, avoiding to charge possible junction capacities that would be present with the diodes of the known circuit shown in Figure 4.

The transmission channel 1 also comprises a switching circuit 30 in turn including at least one first switching transistor MSW1 and a second switching transistor MSW2 inserted, in series to each other, between the connection terminal Xdcr and the second output terminal LVout. The switching circuit 30 is in particular used as switching circuit between a reception mode and a transmission mode of this transmission channel 1 and transfers, when on, a low voltage signal being at the output of the antinoise block 6 of the transmission - - channel 1 towards the second output terminal LVout.

In particular, in the example of the figure, the first switching transistor MSWl is a high voltage P-channel MOS transistor (HV Pmos) while the second switching transistor MSW2 is a high voltage N-channel MOS transistor (HV Nmos). In Figure 7 A also the parasite or body diodes of these transistors are indicated, respectively DSW1 and DSW2, being connected in antiseries in correspondence with a first inner circuit node XW1.

According to an embodiment of the invention, the switching circuit 30 comprises at least one bootstrap circuit 31 connected to a first control or gate terminal XGW1 and to a second control or gate terminal XGW2 of the first switching transistor MSWl and of the second switching transistor MSW2, respectively.

The bootstrap circuit 31 is also connected, in correspondence with a first bootstrap node XBW1 and with a second bootstrap node XBW2, to a first voltage reference VDD_M and to a second voltage reference VDD_P, in particular a supply one.

The bootstrap circuit 31 comprises at least one first biasing generator Gl being inserted between the first control terminal XGW1 and the first bootstrap node XBW1, as well as a second biasing generator G2 inserted between the second bootstrap node XBW2 and the second control terminal XGW2. These first and second biasing generators, Gl and G2, supply respective first and second biasing currents, Ibl and Ib2 and have respective first and second parasite capacities, Cgenl and Cgen2, that are the parasite capacities of the bootstrap circuit 31 , respectively inserted between the first control terminal XGW1 and the first bootstrap node XBW1 and between the second control terminal XGW2 and the second bootstrap node XBW2.

Further preferably, these first and second parasite capacities, Cgenl and Cgen2, have much lower capacitive value than respective first and second gate- source capacities, Cswl and Csw2, of the first and second switching transistor, MSWl and MSW2. In particular, these first and second parasite capacities, Cgenl and Cgen2, have a capacitive value of at least one order of magnitude, preferably some orders of magnitude, in particular three orders of magnitude, lower than the first and second gate-source capacities, Cswl and Csw2.

More in particular, the first parasite capacity Cgenl has capacitive value of at least one order of magnitude lower than the first gate-source capacity Cswl of the first switching transistor MSWl and the second parasite capacity Cgen2 has capacitive value of at least one order of magnitude lower that the second gate- source capacity Csw2 of the second switching transistor MSW2.

The bootstrap circuit 31 also comprises a first bootstrap transistor MBW1 - - being inserted, in series to a first bootstrap resistive element RBW1 , between the first control terminal XGW1 of the first switching transistor MSW1 and the second bootstrap node XBW2. The first bootstrap transistor MBWl also has a control or gate terminal connected to the first inner circuit node XW1 of the switching circuit 30, corresponding to a source terminal of the first switching transistor MSW1.

Similarly, the bootstrap circuit 31 comprises a second bootstrap transistor MBW2 being inserted, in series to a second bootstrap resistive element RBW2, between the second control terminal XGW2 of the second switching transistor MSW2 and the first bootstrap node XBW1. The second bootstrap transistor MBW2 also has a control or gate terminal connected to a second inner circuit node XW2 of the switching circuit 30, corresponding to a source terminal of the second switching transistor MSW2.

In particular, in the example of the figure, the first bootstrap transistor MBWl is a low voltage N-channel MOS transistor (LV Nmos) while the second bootstrap transistor MBW2 is a low voltage P-channel MOS transistor (LV Pmos).

The first biasing generator Gl is a current generator suitable for supplying such a current Ibl that the voltage developed by this current Ibl flowing through the first bootstrap transistor MBWl and the first bootstrap resistive element RBW1 is able to turn on the first switching transistor MSW1. The same way, the second biasing generator G2 is a current generator suitable for supplying such a current Ib2 that the voltage developed by this current Ib2 flowing through the second bootstrap transistor MBW2 and the second bootstrap resistive element RBW2 is able to turn on the second switching transistor MSW2.

It is thus evident that, according to working or turn-on conditions of the switching circuit 30, the same behaves like its equivalent circuit shown in Figure 7B.

In particular, the gate terminals of the switching transistors MSW1 and MSW2 are both connected to a fix node in voltage, schematised in the Figure as connected to the ground GND and these transistors behave as respective resistances RSW1 and RSW2, that are inserted between the connection terminal Xdcr and the output terminal LVout of the transmission channel 1 (the output terminal LVout coinciding with the second inner circuit node XW2) and interconnected in correspondence with the first inner circuit node XW 1.

According to these conditions, thanks to the presence of the bootstrap circuit

31 and of its biasing generators Gl and G2, the first gate-source capacity Cswl of the first switching transistor MSW1 is inserted, in series to the first parasite capacity Cgenl of the first biasing generator Gl between the first inner circuit node XW1 and ground GND, while the second gate-source capacity Csw2 of the - - second switching transistor MSW2 is inserted, in series to the second parasite capacity Cgen2 of the second biasing generator G2 between the second inner circuit node XW2 and ground GND.

In this way, the total parasite capacity (enclosed by a dotted circle in Figure 7B) is reduced with respect to the known circuits, decreasing in consequence the undesired mitigation of the signal at the input of the switching circuit 30 itself, in particular applied to the connection terminal Xdcr and transmitted towards the second output terminal LVout.

According to an embodiment of the invention, the transmission channel 1 is in particular used for the driving of a piezoelectric transducer for ultrasound applications.

In substance, the transmission channel 1, thanks to the presence of the clamping circuit as above indicated ensures a correct clamping of the same to a voltage reference, in particular to a ground GND, also when a load of high value is present, eliminating malfunctions connected to the load of the junction capacities of the diodes of the known circuits.

In particular, any time the clamping circuit is turned on, the value of the voltage being on the connection terminal Xdcr reaches a value equal to the ground value GND plus or minus a diode voltage, improving the performances of second harmonic especially at low supply voltages.

Furthermore, a leakage current during a receiving step of the transmission channel according to the invention that comprises the clamping circuit is conveyed towards the ground reference terminal GND preventing the first output terminal HVout from charging itself and overcoming in this way the drawbacks of the circuits described in relation to the prior art.

Moreover, the reset circuit, after any clamping step realised by the clamping circuit, forces the voltage value of drain terminal of the buffer transistors, which are high power MOS transistors, comprised within the high voltage buffer block to voltage values next to a ground reference value, so that all the successive pulse cycles applied to the transmission channel restart from a same initial condition .

In particular, in case of ultrasound applications, this limits the differences between ultrasound pulse and successive ultrasound pulse.

Finally, thanks to the presence of the switching circuit a correct transmission of a signal applied to the connection terminal Xdcr of the transmission channel is ensured, this switching circuit having a reduced total parasite capacity when in turn-on conditions.

Obviously, a technician of the field, with the aim of meeting incidental and specific needs, will be allowed to introduce several modifications and variations to the above described circuit, all within the scope of protection of the invention as defined by the following claims.

Claims

1. Transmission channel (1) of the type comprising at least:

a high voltage buffer block (4) comprising buffer transistors (MB1, MB2, MB3, MB4) and respective buffer diodes (DB1, DB2, DB3, DB4), being inserted between respective voltage references (HVPO, HVP1 , HVMO, HVM 1), said high voltage buffer block (4) having at least one first and one second output terminal (OUTB1, OUTB2), as well as a buffer central node (XB);

a clamping circuit (10) being connected to a first output terminal (HVout) of said transmission channel (1) and having at least one first and one second input terminal (INC1, INC2) connected to said first and second output terminals (OUTB1 , OUTB2) of said high voltage buffer block (4), a first and a second clamp circuit node (XC l, XC2), as well as a clamp central node (XC) connected to said buffer central node (XB);

an antinoise block (6) being connected between said first output terminal (HVout) and a connection terminal (Xdcr) of said transmission channel (1); as well as

a switching circuit (30) being inserted between said connection terminal (Xdcr) and a second output terminal (LVout) of said transmission channel (1)

characterised in that

said clamping circuit (10) comprises a clamping core (1 1) in turn including at least one first and one second clamp transistor (MCI , MC2), being connected to said central node (XC) and to said first and second clamp circuit nodes (XC 1 , XC2), respectively, through diodes (DC l, DC2) connected to prevent the body diodes of said clamping transistors (MCI, MC2) from conducting and having respective control terminals (XGl, XG2), as well as at least one first switching off transistor (MSI) being connected to said first output terminal (HVout) and to said first clamp transistor (MCI) and a second switching off transistor (MS2) being connected to said first output terminal (HVout) and to said second clamp transistor (MC2), said first and second clamp transistors (MCI , MC2) being high voltage MOS transistors of complementary type and said first and second switching off transistor (MS I , MS2) being high voltage MOS transistors of complementary type connected to said first and second clamp transistors (MC I, MC2) by having the respective equivalent or body diodes in anti-series so as to close themselves when said clamping circuit (10) is active and to sustain positive and negative high voltages when said clamping circuit (10) is not active;

said reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4) and being inserted between circuit nodes (XMEl , XME2, XME3, XME4, XC l , XC2) of said high voltage buffer block (4) and of said clamping circuit (10), said circuit nodes (XMEl , XME2, XME3, XME4, XCl, XC2) being in correspondence with conduction terminals of said transistors (MB 1, MB2, MB3, MB4; MC I , MC2) comprised into said high voltage buffer block (4) and into said clamping circuit (10), and

said switching circuit (30) comprising at least one first and one second switching transistor (MSWl, MSW2) which are high voltage MOS transistors of complementary type being inserted, in series to each other and by having respective equivalent or body diodes (DSW1 , DSW2) in anti-series, between said connection terminal (Xdcr) and said second output terminal (LVout), as well as at least one bootstrap circuit (31) being connected to respective first and second control terminals (XGW1 , XGW2) of said at least one first and one second switching transistor (MSWl, MSW2), as well as to respective first and second voltage references (VDD_P, VDD_M) and having values of parasite capacities between said first and second control terminals (XGW1 , XGW2) and at least one first and one second bootstrap node (XBW1, XBW2) of at least one order of magnitude lower with respect to the gate-source capacities (Cswl, Csw2) of said at least one first and one second switching transistor (MSWl, MSW2).

2. Transmission channel (1) according to claim 1 , characterised in that said first switching off transistor (MSI) is a high voltage P-channel MOS transistor and said second switching off transistor (MS2) is a high voltage N- channel MOS transistor.

3. Transmission channel (1) according to claim 1 , characterised in that it further comprises a driving circuit (14) connected to respective control terminals of said first and second clamp transistors (MCI , MC2) and of said first and second switching off transistors (MSI, MS2) and suitable for closing said first and second switching off transistors (MS I, MS2) when said clamping circuit is on.

4. Transmission channel (1) according to claim 3, characterised in that said driving circuit (14) comprises a first and a second driving transistor (M l , M2), being inserted, in a crossed way, between said control terminals of said first and second clamp transistors (MCI , MC2), and respective control terminals of said first and second switching off transistors (MS I , MS2).

5. Transmission channel (1) according to claim 4, characterised in that said first driving transistor (M l) is inserted between said control terminal (XGl) of said first clamp transistor (MCI) and a control terminal (XS2) of said second switching off transistor (MS2) and in that said second driving transistor (M2) is inserted between a control terminal (XS 1) of said first switching off transistor (MS I) and said control terminal (XG2) of said second clamp transistor (MC2).

6. Transmission channel (l)according to claim 5, characterised in that said first and second driving transistors (M l, M2) have respective control terminals (XI , X2) connected to said central node (XC).

7. Transmission channel (1) according to claim 6, characterised in that said clamping core (1 1) is connected at the input to a low voltage input driver block (13) which comprises a first and a second driver (DRC 1 , DRC2) inserted between a first and a second supply voltage reference (VDD_P, VDD_M) and having respective output terminals connected to said control terminals (XG1, XG2) of said first and second clamp transistors (MC I , MC2).

8. Transmission channel (1) according to claim 1 , characterised in that said first clamp transistor (MCI) is a high voltage N-channel MOS transistor and said second clamp transistor (MC2) is a high voltage P-channel MOS transistor.

9. Transmission channel (1) according to claim 1 , characterised in that said first and second driving transistors (Ml, M2) are high voltage MOS transistors of the type similar with respect to said first and second switching off transistor (MS I , MS2).

10. Transmission channel (1) according to claim 1 , characterised in that said first switching off transistor (M l) is a high voltage N-channel MOS transistor and said second switching off transistor (M2) is a high voltage P-channel MOS transistor.

1 1. Transmission channel (1) according to claim 1 , wherein said high voltage buffer block (4) comprises at least one first branch in turn including a first buffer transistor (MB 1) and a first buffer diode (DB 1), being inserted, in series to each other, between a first higher voltage reference (HVP0) and a buffer central node (XB) and interconnected in correspondence with a first memory node (XME1), as well as a second buffer diode (DB2) and a second buffer transistor (MB2), being inserted, in series to each other, between said buffer central node (XB) and a first lower voltage reference (HVM0) and interconnected in correspondence with a second memory node (XME2), characterised in that said reset circuit (20) comprises:

a first memory diode (DME1), being inserted between said first memory node (XME1) and said first clamp circuit node (XC 1); and

- a second memory diode (DME2), being inserted between said second memory node (XME2) and said second clamp circuit node (XC2).

said first memory diode (DME1) having a cathode terminal connected to said first memory node (XME1) and an anode terminal connected to said first clamp circuit node (XC 1) and said second memory diode (DME2) having an anode terminal connected to said second memory node (XME2) and a cathode terminal connected to said second clamp circuit node (XC2);

said first memory node (XME1) being connected to an anode terminal of said first buffer diode (DB 1) and said first clamp circuit node (XC 1) is connected to an anode terminal of said first clamp diode (DC 1) and said second memory node (XME2) being connected a cathode terminal of said second buffer diode (DB2) and said second clamp circuit node (XC2) is connected to a cathode terminal of said second clamp diode (DC2); and

said first memory node (XME1) being in correspondence with a drain terminal of said first buffer transistor (MB 1) and said second memory node (XME2) being in correspondence with a drain terminal of said second buffer transistor (MB2).

12. Transmission channel (1) according to claim 1 1 , wherein said high voltage buffer block (4) also comprises, in parallel to said first branch, a second branch in turn including a third buffer transistor (MB3) and a third buffer diode (DB3), being inserted, in series to each other, between a second higher voltage reference (HVP1) and said buffer central node (XB) and interconnected in correspondence with a third memory node (XME3), as well as a fourth buffer diode (DB4) and a fourth buffer transistor (MB4), being inserted, in series to each other, between said buffer central node (XB) and a second lower voltage reference (HVM1) and interconnected in correspondence with a fourth memory node (XME4), characterised in that said reset circuit (20) further comprises:

a third memory node (DME3), being inserted between said third memory node (XME3) and said first clamp circuit node (XC1); and

a fourth memory diode (DME4), being inserted between said fourth memory node (XME4) and said second clamp circuit node (XC2);

said third memory diode (DME3) having a cathode terminal connected to said third memory node (XME3) and an anode terminal connected to said first clamp circuit node (XC1) and said fourth memory diode (DME4) having an anode terminal connected to said fourth memory node (XME4) and a cathode terminal connected to said second clamp circuit node (XC2);

said third memory node (XME3) being connected to an anode terminal of said third buffer diode (DB3) and said first clamp circuit node (XC 1) being connected to an anode terminal of said first clamp diode (DC1) and said fourth memory node (XME4) being connected to a cathode terminal of said fourth buffer diode (DB4) and said second clamp circuit node (XC2) being connected to a cathode terminal of said second clamp diode (DC2);

said third memory node (XME3) being in correspondence with a drain terminal of said third buffer transistor (MB3) and said fourth memory node (XME4) being in correspondence with a drain terminal of said fourth buffer transistor (MB4).

13. Transmission channel (1) according to claim 12, characterised in that said high voltage buffer block (4) comprises respective buffer drivers (DRB 1 , DRB2, DRB3, DRB4) connected to control terminals of said buffer transistors (MB 1, MB2, MB3, MB4).

14. Transmission channel (1) according to claim 1, characterised in that said bootstrap circuit (31) of said switching circuit (30) comprises at least one first biasing generator (Gl) inserted between said first control terminal (XGW1) and said first bootstrap node (XBW1), as well as a second biasing generator (G2) inserted between said second bootstrap node (XBW2) and said second control terminal (XGW2) as first and second parasite capacities (Cgenl, Cgen2) of said bootstrap circuit (31), said at least one first and one second biasing generator (Gl, G2) supplying respective first and second biasing currents (Ibl, Ib2).

15. Transmission channel (1) according to claim 14, characterised in that said bootstrap circuit (31) further comprises a first bootstrap transistor (MBW1) being inserted, in series to a first bootstrap resistive element (RBW1), between said first control terminal (XGW1) of said first switching transistor (MSW1) and said second bootstrap node (XBW2), as well as a second bootstrap transistor (MBW2) inserted, in series to a second bootstrap resistive element (RBW2), between said second control terminal (XGW2) of said second switching transistor (MSW2) and said first bootstrap node (XBW1);

said first bootstrap transistor (MBW1) having a control terminal connected to a first inner circuit node (XWl) of said switching circuit (30), corresponding to a source terminal of said first switching transistor (MSW1) and said second bootstrap transistor (MBW2) having a control terminal connected to a second inner circuit node (XW2) of said switching circuit (30), corresponding to a source terminal of said second switching transistor (MSW2).

16. Transmission channel (1) according to claim 1, characterised in that said values of parasite capacities of said bootstrap circuit (31) are of at least some orders of magnitude, preferably three, lower with respect to the gate-source capacities (Cswl, Csw2) of said at least one first and one second switching transistor (MSW1 , MSW2).