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WO2011083919A3 - Block and standard cell packing method for automated design area optimization - Google Patents

Block and standard cell packing method for automated design area optimization Download PDF

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Publication number
WO2011083919A3
WO2011083919A3 PCT/KR2010/008731 KR2010008731W WO2011083919A3 WO 2011083919 A3 WO2011083919 A3 WO 2011083919A3 KR 2010008731 W KR2010008731 W KR 2010008731W WO 2011083919 A3 WO2011083919 A3 WO 2011083919A3
Authority
WO
WIPO (PCT)
Prior art keywords
block
standard cell
packing
packing method
placement
Prior art date
Application number
PCT/KR2010/008731
Other languages
French (fr)
Korean (ko)
Other versions
WO2011083919A2 (en
Inventor
오성환
이은철
Original Assignee
주식회사 엔타시스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 엔타시스 filed Critical 주식회사 엔타시스
Publication of WO2011083919A2 publication Critical patent/WO2011083919A2/en
Publication of WO2011083919A3 publication Critical patent/WO2011083919A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present invention relates to a hard block and to a standard cell packing method used for optimizing a design area during the designing of a semiconductor integrated circuit. A typical hard block packing method involves packing each block separately and has the limitation of being unable to completely ensure a success rate of interconnections between blocks or between a block and a standard cell. However, the present invention relates to: 1) a method for packing neighbor block groups by automatically recognizing a placement pattern of hard blocks; and 2) a method for obtaining an exclusive area with respect to standard cells by expanding the outline of each group, thereby improving the interconnection possibility between blocks or between a block and a standard cell of a reduced chip. Moreover, a typical standard cell packing method uses an incremental placement technique and has the limitation of maintaining the relative position of each standard cell in an original layout placement. According to the present invention, however, the incremental placement is optimized by using an alignment technique to maximally maintain an original relative position.
PCT/KR2010/008731 2010-01-07 2010-12-08 Block and standard cell packing method for automated design area optimization WO2011083919A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020100001153A KR101044295B1 (en) 2010-01-07 2010-01-07 A method and apparatus to pack neighbor blocks and cells during the automatic chip level layout compaction
KR10-2010-0001153 2010-01-07

Publications (2)

Publication Number Publication Date
WO2011083919A2 WO2011083919A2 (en) 2011-07-14
WO2011083919A3 true WO2011083919A3 (en) 2011-11-03

Family

ID=44305908

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/008731 WO2011083919A2 (en) 2010-01-07 2010-12-08 Block and standard cell packing method for automated design area optimization

Country Status (2)

Country Link
KR (1) KR101044295B1 (en)
WO (1) WO2011083919A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112818625B (en) * 2021-02-05 2024-03-15 上海华虹宏力半导体制造有限公司 Layout and layout modification method
KR102597328B1 (en) 2023-01-25 2023-11-02 주식회사 마키나락스 Method for performing double clustering to evaluate placement of semiconductor devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000015456A (en) * 1998-08-29 2000-03-15 김영환 Internal unit block arrangement method of very large scale integration chip
US20020002697A1 (en) * 2000-06-30 2002-01-03 Kabushiki Kaisha Toshiba Semiconductor integrated circuit designing method and system
US20020110959A1 (en) * 2000-12-15 2002-08-15 Koninklijke Philips Electronics N. V. Semiconductor device layout

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000015456A (en) * 1998-08-29 2000-03-15 김영환 Internal unit block arrangement method of very large scale integration chip
US20020002697A1 (en) * 2000-06-30 2002-01-03 Kabushiki Kaisha Toshiba Semiconductor integrated circuit designing method and system
US20020110959A1 (en) * 2000-12-15 2002-08-15 Koninklijke Philips Electronics N. V. Semiconductor device layout

Also Published As

Publication number Publication date
WO2011083919A2 (en) 2011-07-14
KR101044295B1 (en) 2011-06-28

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