WO2011068493A1

WO2011068493A1 - Training data strategy for a mobile dtv system with diversity

Info

Publication number: WO2011068493A1
Application number: PCT/US2009/006351
Authority: WO
Inventors: Ivonete Markman
Original assignee: Thomson Licensing
Priority date: 2009-12-03
Filing date: 2009-12-03
Publication date: 2011-06-09

Abstract

A method for combining training data within groups of bytes in a digital data stream including a plurality of information blocks and a plurality of parity blocks provides for generating training data specific to the information blocks. The training data specific to the information blocks is inserted into a first reserved portion of at least one of the information blocks. Training data specific to the parity blocks is generated. The training data specific to the parity blocks is inserted into a first reserved portion of at least one of the parity blocks. Training data common to both the information blocks and the parity blocks is generated. The training data common to both the information blocks and the parity blocks is inserted into both a second reserved portion of at least one of the information blocks and a second reserved portion of at least one of the parity blocks.

Description

TRAINING DATA STRATEGY FOR A MOBILE DTV SYSTEM WITH DIVERSITY

FIELD

[0001] The present invention relates to mobile DTV systems and more specifically to a training data strategy for a mobile DTV system with diversity.

BACKGROUND

[0002] The Advanced Television Systems Committee (ATSC) standard for Digital Television (DTV) in the United States requires an 8-Vestigial Sideband (VSB) transmission system which includes Forward Error Correction (FEC) as a means of improving the system performance. The FEC system consists of a Reed-Solomon encoder, followed by a byte interleaver, and a trellis encoder on the transmitter side. At the receiver end, there is a corresponding trellis decoder, byte deinterleaver and Reed- Solomon decoder. The ATSC-DTV standard is document A53.doc, dated September 16, 1995 produced by the United States Advanced Television Systems Committee. Figure 1 shows a simplified block diagram of the DTV transmitter and receiver, emphasizing the FEC system.

[0003] The ATSC has started a study group to create a new M/H (mobile/handheld) DTV standard that is backwards compatible with the current DTV standard (A/53), more robust, more flexible, and provides expanded services to customers utilizing mobile and handheld devices. The new proposals have added a new layer of FEC coding and more powerful decoding algorithms to decrease the Threshold of Visibility (TOV).

[0004] The added layer of FEC coding requires decoding techniques such as turbo decoding discussed in an article by C. Berrou, A. Glavieux and P. Thitimajshima, entitled "Near Shannon Limit Error - Correcting Coding and Decoding: Turbo-Codes," found in Proceedings of the IEEE International Conference on Communications - ICC '93, May 23-26, 1993, Geneva, Switzerland, pp. 1064-1070. A discussion of turbo coding can be found in the article by M.R. Soleymani, Y. Gao and U. Vilaipornsawai, entitled "Turbo Coding for Satellite and Wireless Communications," Kluwer Academic Publishers, USA, 2002. [0005] Decoding of signals encoded for ATSC DTV with an added FEC layer can also involve trellis decoding algorithms like maximum a posteriori (MAP) decoders as described by L.R. Bahl, . Cocke, F. Jelinek and J. Rariv, in an article entitled "Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate," found in IEEE

Transactions on Information Theory, Vol. IT-20, No. 2, March 19 74, pp. 284-287.

Another discussion of trellis coders and a MAP decoder is found in an article written by A.J. Viterbi, entitled "An Intuitive Justification and a Simplified Implementation of the Map Decoder for Convolutional Codes," found in IEEE Journal on Selected Areas in Communications, Vol. 16, No. 2, February 1998, pp. 260-264.

[0006] In addition, the FEC system may allow for transmission with time diversity as described by International Patent Applications WO 2008/144004 and 2009/064468. Time diversity may advantageously be used in digital communication systems to minimize the effect of error bursts due to various transmission channel conditions. Error bursts are typically caused by fading from a moving receiver, an obstacle, or

electromagnetic interference. Although the proposed systems attempt to provide backwards compatibility with the current DTV standard, no other known system permit diversity within their coding structure.

[0007] This arrangement proposes a strategy for implementing training data within a mobile DTV system with diversity.

SUMMARY

[0008] A method for combining training data within groups of bytes in a digital data stream including a plurality of information blocks and a plurality of parity blocks provides for generating training data specific to the information blocks. The training data specific to the information blocks is inserted into a first reserved portion of at least one of the information blocks. Training data specific to the parity blocks is generated. The training data specific to the parity blocks is inserted into a first reserved portion of at least one of the parity blocks. Training data common to both the information blocks and the parity blocks is generated. The training data common to both the information blocks and the parity blocks is inserted into both a second reserved portion of at least one of the information blocks and a second reserved portion of at least one of the parity blocks. [0009] The training data specific to the information blocks may be inserted into a first reserved portion of each of the information blocks. The training data specific to the parity blocks may be inserted into a first reserved portion of each of the parity blocks. Training data common to both the information blocks and the parity blocks may be inserted into both a second reserved portion of each of the information blocks and a second reserved portion of each of the parity blocks.

[0010] Inserting the training data specific to the information blocks may be performed by selecting specific bytes corresponding to the first reserved portion of the information blocks and placing training data into the first reserved portion of the information blocks. Inserting the training data specific to the party blocks may be performed by selecting specific bytes corresponding to the first reserved portion of the parity blocks and placing training data into the first reserved portion of the parity blocks.

[0011] Each information block and each parity block includes S segments of B bytes and the reserved portion of each information block and each parity block includes RB bytes, wherein RB < B bytes in all S segments.

[0012] In a first embodiment, the first reserved portion of each information block includes RB bytes for RSI segments, wherein RSI < S segments and the second reserved portion of each information block includes RB bytes for RS2 segments, wherein RS2 = S - RS 1 segments. The first reserved portion of each parity block includes RB bytes for RSI segments, wherein RSI < S segments and the second reserved portion of each parity block includes RB bytes for RS2 segments, wherein RS2 = S - RSI segments.

[0013] In a second embodiment, the first reserved portion of each information block includes RBI bytes, wherein wherein RBI < RB bytes and the second reserved portion of each information block includes RB2 bytes, wherein RB2 = RB - RBI bytes. The first reserved portion of each parity block includes RBI bytes, wherein RBI < RB bytes and the second reserved portion of each parity block includes RB2 bytes, wherein RB2 = RB - RBI bytes.

[0014] The method further includes detecting whether a block is an information block or a parity block by analyzing a first reserved portion of each information block and parity block. [0015] An apparatus for combining training data within groups of byes in a digital data stream including a plurality of information blocks and a plurality of parity blocks includes a training data generator and a training data inserter. The training data generator generates: 1) training data specific to the information blocks, 2) training data specific to the parity blocks, and 3) training data common to both the information blocks and the parity blocks. The training data inserter inserts: 1) the training data specific to the information blocks into a first reserved portion of at least one of the information blocks, 2) the training data specific to the parity blocks into a first reserved portion of at least one of the parity blocks, and 3) the training data common to both the information blocks and the parity blocks into a second reserved portion of at least one of the information blocks and a second reserved portion of at least one of the parity blocks.

[0016] Training data specific to the information blocks is inserted into a first reserved portion of each of the information blocks. Training data specific to the parity blocks is inserted into a first reserved portion of each of the parity blocks. Training data common to both the information blocks and the parity blocks are inserted into both a second reserved portion of each of the information blocks and a second reserved portion of each of the parity blocks.

[0017] The training data inserter inserts the training data specific to the information blocks by selecting specific bytes corresponding to the first reserved portion of the information blocks and placing training data into the first reserved portion of the information blocks. The training data inserter also inserts the training data specific to the parity blocks by selecting specific bytes corresponding to the first reserved portion of the parity blocks and placing training data into the first reserved portion of the parity blocks.

[0018] Each information block and each parity block includes S segments of B bytes and the reserved portion of each information block and each parity block includes RB bytes, wherein RB < B bytes in all S segments.

[0019] In a first embodiment, the first reserved portion of each information block includes RB bytes for RSI segments, wherein RSI < S segments and the second reserved portion of each information block includes RB bytes for RS2 segments, wherein RS2 = S - RSI segments. The first reserved portion of each parity block includes RB bytes for RSI segments, wherein RSI < S segments and the second reserved portion of each parity block includes RB bytes for RS2 segments, wherein RS2 = S - RSI segments.

[0020] In a second embodiment, the first reserved portion of each information block includes RBI bytes, wherein wherein RBI < RB bytes and the second reserved portion of each information block includes RB2 bytes, wherein RB2 = RB - RB 1 bytes. The first reserved portion of each parity block includes RBI bytes, wherein RBI < RB bytes and the second reserved portion of each parity block includes RB2 bytes, wherein RB2 = RB - RBI bytes.

[0021] The apparatus may further include a receiver including a training data detector that receives the information blocks and parity blocks and detects whether a block is an information block or a parity block by analyzing a first reserved portion of each information block and each parity block.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 depicts an example block diagram of a digital television transmitter and receiver system;

Figure 2 depicts an example digital television data frame;

Figure 3 depicts an example of a DTV M/H system in accordance with the principles of the current arrangement;

Figure 4 depicts an example packet structure of a packet block code of code rate

R = K/N in accordance with the principles of the current arrangement;

Figure 5 depicts an example of a second FEC encoder;

Figure 6A depicts an example of a Packet Interleaver taking bytes from a fixed number of consecutive packets in a row-by-row order;

Figure 6B depicts an example of the Packet Interleaver outputting the bytes column-by-column;

Figure 7A depicts an example of a Packet Deinterleaver taking bytes from resulting block code codewords for the original group of packets in a column-by-column order;

Figure 7B depicts an example of the Packet Deinterleaver outputting the bytes in a row-by-row order; Figure 8 depicts an example of a receiver implementation for a mobile DTV system according to the present arrangement;

Figure 9 depicts an example of the High Latency FEC (HL FEC) according to the present arrangement;

Figure 10 depicts an example of the Low Latency FEC (LL FEC) according to the present arrangement;

Figure 1 1 depicts a block diagram of an HL FEC core according to the present arrangement;

Figure 12 depicts a mobile DTV system supporting time diversity according to the present arrangement;

Figure 13 depicts an example of a receiver implementation for a mobile DTV system with time diversity according to the present arrangement;

Figure 14 depicts an HL FEC core supporting time diversity according to the present arrangement;

Figure 15 A depicts a data block containing embedded training data;

Figure 15B depicts how training data is embedded and interleaved into a data block according to the present arrangement;

Figure 16 depicts an implementation according to the present arrangement showing how training data is differentiated between AA and BB blocks; and

Figure 17 depicts an implementation according to the present arrangement showing how training data is differentiated between AA and BB blocks.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] Figure 1 shows an example of a DTV system that incorporates forward error correction. Input digital data, which may be considered any of video, audio, textual, or other information data, is encoded using a DTV standard and transmitted to a receiver which decodes the digital data.

[0024] Figure 2 shows an exemplary DTV data frame organized for transmission. Each data frame may include two data fields, each containing 313 data segments. The first data segment of each data field may be a unique synchronizing segment (Data Field Sync). The remaining 312 data segments may each carry the equivalent of one 188-byte MPEG-compatible transport packet and its associated FEC data.

[0025] Each data segment may consist of 832 8-VSB symbols. The first four symbols of each data segment, including the Data Field Sync segments, form a binary pattern and provide segment synchronization. The first four 8-VSB symbols of each data segment have values of +5, -5, -5, and +5. This four-symbol data segment sync signal also represents the sync byte of each 188-byte MPEG-compatible transport packet conveyed by each of the 312 data segments in each data field. The remaining 828 symbols of each data segment carry data equivalent to the remaining 187 bytes of a transport packet and its associated FEC data.

[0026] Figure 3 shows a simplified block diagram of an exemplary transmitter and receiver for an M/H DTV system, hereby called DTV-M/H, wherein the added layer of FEC encoding, exemplified by FEC Encoder 2, may includes a packet block code and FEC Encoder 1 is compatible with the ATSC FEC encoder shown in Figure 1. At the receiver, the Iterative FEC Decoder performs turbo decoding of the various FEC encoders. The Iterative FEC decoder in question may includes MAP decoding of the ATSC trellis decoder and the added FEC codes within FEC Encoder 2 which will iteratively interact, resulting in each decoder sending extrinsic information to the other. In addition, the Iterative FEC Decoder will perform a number of iterations M deemed necessary to achieve a desired system performance.

[0027] Figure 4 shows a packet structure of a Packet Block Code having a rate R = K/N in accordance with the principles of the current arrangement. The block code is such that for each K packets of data, having 187 information bytes (assuming MPEG packets without the sync byte, 0x47 or 47 Hex, as in the ATSC standard), the block code adds N- K parity packets. This block code may be a Serial Concatenated Block Code (SCBC) over a Galois Field GF(256) similar to that described in International Patent Application WO 2008/144004 mentioned above, wherein each column in FIG. 3 would be a separate code word of N bytes associated with the first K information bytes.

[0028] Figure 5 shows an FEC Encoder according to the present arrangement. FEC block encoder 514 may be preceded by a packet interleaver 512 and followed by a packet deinterleaver 516. The operation of packet interleaver 512 and packet deinterleaver 516 are set forth more specifically hereinafter with reference to Figures 6 and 7, respectively.

[0029] The Packet Interleaver 512 may take bytes from a fixed number of consecutive packets in a row-by-row order as shown in Figure 6A, and outputs the bytes column-by- column, as shown in Figure 6B, for the case of R = 12/26. In this manner, all first bytes of the packets will be grouped together, all second bytes of the packets will be grouped together, and so on to the last bytes of the packets. Each source packet is an MPEG transport stream packet with the 0x47 sync byte removed, as in the A/53 ATSC DTV standard. As a result each packet has a length of 187 bytes. The number of packets in each code frame is the same as the number of source symbols required for the GF(256) Serial Concatenated Block Code. The Packet Interleaver is known in the art as a (K, 187) matrix interleaver.

[0030] The Packet Deinterleaver 516 may take bytes from the resulting SCBC codewords for the original group of packets in a column-by-column order as shown in Fig. 7A. The bytes are then output row-by-row, as shown in Fig. 7B, for the case of R=12/26. In this manner, the original packets are reconstituted and new packets are created from the parity bytes of the SCBC codewords. Each packet corresponds to a common GF(256) symbol location in all created SCBC codewords. The Packet Deinterleaver is specified as a (N, 187) matrix deinterleaver

[0031] An example of a burst repetitive data structure for transmission of the DTV-M/H data is given in Table 1. The DTV-M H receiver discards the Legacy ATSC data segments or packets, and works on the remaining data, which includes training data, also called a priori tracking (APT) packets, in addition to the synchronization data present in the ATSC-DTV data frame described above. Preamble training data is generated at a training data generator, which is a part of FEC encoder 2 shown in Figure 3. This preamble training data, however, is fully encoded by all levels of legacy ATSC FEC coding by the transmitter shown in Figure 1. The preamble training data is further interleaved and randomized as well. The preamble training data is a known data sequence added at FEC encoder 2 shown in Figure 3 and it may also be fully encoded by FEC encoder 2. At the receiver, the iterative FEC decoder takes advantage of the known data in order to improve performance, through correlation or any other method of performance enhancement. An example of a burst repetitive data structure for

transmission of the DTV-M/H data is given in Table 1.

TABLE 1

[0032] As shown in Table 1, a data burst comprising three data fields, F0, Fl and F2, is repetitively transmitted, each corresponding to 1.5 frame of the legacy ATSC-DTV standard.

[0033] When receiving a data burst such as set forth in Table 1 , a DTV-M H receiver will discard the 156 Legacy ATSC data segments in Data Field F0 and process the remaining data including the preamble training data segments. The preamble training data is to be utilized by the DTV-M H receiver in order to enhance performance.

[0034] Figure 8 shows a general block diagram of a receiver implementation for a mobile DTV receiver 810 used in the present arrangement. The receiver 810 is generally composed of a demodulator 812, equalizer 814, FEC decoding block 818 and transport function block 824, which includes video decoding. One skilled in the art will be familiar with the general functionality of these blocks in a DTV receiver. In this particular mobile system, the FEC decoder has two levels: High Latency (HL) 820, which has N iterations or cores and feeds the transport block, and Low Latency (LL) 822 with M<N iterations or cores, which feeds the equalizer to increase its performance. [0035] Figure 9 shows a more detailed diagram of HL FEC 820. Forward error correction in a system provides for error control for data transmissions. This is performed by sending redundant data to its messages, known as error correction codes that allow the receiver to detect and correct errors without the need to ask the sender for additional data or resending of data. HL FEC 820 has a plurality of HL Cores represented by HL Core 1 910, HL Core 2 912, and HL Core N 914, and as a last block, a legacy ATSC FEC block 916. Legacy ATSC FEC Block 916 includes a combination of the legacy FEC functions associated with the legacy ATSC decoder in Figure 1, including particularly, an RS decoder, derandomizer and data interface to the transport block.

[0036] Figure 10 shows a more detailed diagram of LL FEC 822. LL FEC 822 has as a last block, a trellis or MAP decoder 1016, since it is feeding 8-VSB symbols to the equalizer. LL FEC 722 also has a plurality of LL Cores represented by LL Core 1 1010, LL Core 2 1012, and LL Core M 1014. The main difference between the HL and LL cores is the latency of the core blocks. Since the LL FEC 822 feeds the equalizer 814 of Figure 8, its functionality must be designed for minimum latency, and therefore, it is not as robust as the HL FEC 820 in performance.

[0037] Figure 11 shows a block diagram of an HL FEC core 910. The input to each core consists of two streams: the first stream is the originally received stream (after demodulation and equalization), which is delayed and unaltered within each core to match the processing delay of the core and sent to the following core; and the second stream is a stream of extrinsic information associated with the received stream, as processed by the previous core. A noise estimator 918, metric generator 920 and MAP decoder 922 may be included in the HL FEC core, all of which are known in the art. Noise estimator 918 estimates the noise power in a received input stream to an HL FEC core. Metric generator 920 compares the symbols in the received input stream against the optimal 8-VSB values and calculates and stores the metrics needed by the MAP decoder, for the specific noise power. In addition, metric generator 920 calculates, stores and passes to the MAP decoder extrinsic information from the previous FEC core, also called a priori metrics. MAP decoder 922 decodes the ATSC trellis code with the metrics and the a priori metrics received from metric generator 920 and produces dual -bits. [0038] Symbol to byte converter (S2B) 924 groups dual-bit outputs of MAP decoder 922 associated with each 8-VSB symbol in bytes (4 dual-bits per byte). The output of the MAP decoder is a soft decision version of a dual-bit, instead of 2 bits. For example, each dual-bit could be represented by 20 bits and a soft byte would then be represented by 80 bits. S2B 924 also converts the stream from symbol based to byte based.

[0039] Convolutional deinterleaver 928 is connected between S2B 924 and derandomizer 930. The convolutional deinterleaver 928 and derandomizer 930 have the same functionality as in the legacy ATSC standard as well as having the additional ability to handle soft bytes of more than 8 bits. Convolutional deinterleaver 928 rearranges the received data from a previously interleaved sequence. Derandomizer 930 derandomizes the received data to prepare the data for processing by scale 0 936.

[0040] Scale 0 936 scales the soft bytes of the data stream received from derandomizer 930 by a chosen factor. This factor is microprocessor controlled. The scaling factor can be between 0.5 and 1.0, varying for each core. Properly chosen values optimize performance of the HL FEC.

[0041] Packet demultiplexer 940 discards legacy ATSC data and only passes mobile data to the remaining blocks.

[0042] Packet interleaver 942 receives the signals from packet demultiplexer 940 and performs block interleaving operations associated with the GF(256) SCBC block code.

[0043] SCBC decoder 946 receives data from packet interleaver 942 and performs the block decoding operation for the GF (256) SCBC blocks, as discussed previously. SCBC decoder 946 handles soft bytes, and is also a soft decision block decoder.

[0044] SCBC-to-SCBC interface 948 connects two SCBC decoders from two adjacent cores in order to pass extrinsic information and control signals from one FEC core to the next.

[0045] SRAM control 950 interfaces the packet interleaver 942, packet deinterleaver 944 and SCBC decoder 946 to an SRAM needed to perform their respective functionalities.

[0046] Packet deinterleaver 944 receives data from SCBC decoder 946 and performs the block deinterleaving operations associated with the GF(256) SCBC block code.

[0047] Packet multiplexer 952 receives data from packet deinterleaver 944 and recreates a full stream with both legacy and mobile data by obtaining the mobile data from the extrinsic information received from the SCBC decoder block 946 (through the packet deinterleaver 944) and zeroing the legacy data, since it is not of interest to the mobile DTV decoder. The SCBC extrinsic information is used to enhance the performance of the MAP decoder of the subsequent core or iteration.

[0048] Scale 1 938 scales the soft bytes of the data stream received from packet multiplexer 952 by a chosen factor. This factor is microprocessor controlled. The scaling factor can be between 0.5 and 1.0, varying for each core. Properly chosen values optimize performance of the HL FEC.

[0049] Rerandomizer 934 is connected between scale 1 938 and convolutional interleaver 932. The rerandomizer 934 has the same functionality as in the legacy ATSC standard as well as the additional ability to handle soft bytes of more than 8 bits. Rerandomizer 934 randomizes the received data. Convolutional interleaver 932 rearranges the received data into a sequence that is less prone to long sequences of errors.

[0050] Byte-to-symbol converter (B2S) block 926 performs the inverse functionality of the S2B block 924. It separates a soft byte into soft dual-bits and converts the data from byte based to symbol based.

[0051] B2S to metric generator interface 956 obtains extrinsic information from B2S 926 and the delayed received input signals (data and sync) from the core input, and

synchronizes these two sets of data with minimum latency and loss of data, outputting the two sets of data to the next core.

[0052] Equalizer to metric generator delay 954 delays the originally received data stream, field and segment sync, as well as other synchronization signals to match the overall latency of the current core blocks. In addition it passes a symbol enable from the input to the output of the core without delay.

[0053] The LL FEC core is a subset of the HL FEC core, where some of the blocks of the HL FEC core are replaced by a simpler functionality in order to decrease latency. As a result some portions of data are lost but the remaining extrinsic information must still be synchronized with the core input data and fed to the next core. The main differences between an LL FEC core and an HL FEC core are stated in the paragraph below.

[0054] The Metric generator and MAP decoder of the LL FEC core have a reduced latency, and therefore, lesser performance than in the HL FEC core. The convolutional deinterleaver, derandomizer, convolutional interleaver, (re)randomizer, packet demultiplexer, packet interleaver, packet deinterleaver, and packet multiplexer are not present in the LL FEC core and instead are replaced by different, simplified components that perform the operations of (de)randomizing and (re)randomizing as well as extracting the mobile data of interest, which is a subset of the entire mobile data. The SCBC decoder of the LL FEC core has a different code rate than the HL FEC code rate for the purpose of decreasing the latency of the core. In addition, the Equalizer to metric generator delay block of the LL FEC core has a smaller latency than in the HL FEC core.

[0055] Figure 12 shows a mobile DTV system with time diversity 1210. As discussed, the mobile DTV system may be flexible enough for transmission with time diversity. The main flexibility comes from the structure of the GF (256) block code and separation of blocks of segments (or packets) of data into information and parity packets at block coder 1212 which can produce a partially coded service broadcast. An information block contains all information packets and possibly some parity packets. A parity block only contains parity packets. In addition, a parity block can be used to derive information packets. Specifically, a parity block contains a linear combination of all the information packets. These information or parity blocks can then be delayed with respect to each other. The delays can be within a range of 8 to 10 seconds before transmission by delay buffer 1214, as shown in Figure 11, and regrouped in the receiver or physical layer combiner 1216 to obtain a robust system performance. The output of combiner 1216 is a robust time-diverse output. The information and parity blocks in the combiner 1216 output from the delayed and non-delayed paths can each be independently decoded for deep fades. Together, they provide maximum threshold performance.

[0056] The present arrangement provides a time diversity scheme associated with the data and parity blocks of packets of the GF (256) SCBC encoder. As an example, a code rate of R = 12/52 is used, according to Figure 4. Each codeword of 52 packets is split into two blocks of 26 packets: A and B blocks. The A block contains the 12 information packets (and 12 parity packets) and is hereby called an information block. The B block contains only parity packets and is hereby called a parity block. As a result, information (A) and parity (B) blocks in Figure 4 are 26 packets each and serially transmitted, where A and B jointly compose a 52 packet block out of the SCBC encoder or the packet deinterleaver. The code rate R is exemplary and may be defined as a different value, which would also result in different sized A and B blocks.

[0057] The original stream without diversity at the input to the legacy ATSC transmitter can be represented as Data Stream (1):

I A(0) I B(0) I A(l) I B(l) | ... | A(L) | B(L) | A(L+1) | B(L+1) ... (1) This is represented in Figure 12 as the input to block coder 1212.

[0058] In order to add time diversity capability to the stream, the A and B blocks are first grouped in accordance with the size of a mobile field F0 in Table 1. For a mobile data structure with 156 packets per mobile field F0, this grouping is represented by 6 A or B blocks per field, creating Data Stream (2):

I A(0) I A(l) I A(2) I A(3) | A(4) | A(5) | B(0) | B(l) | B(2) | B(3) | B(4) | B(5) | A(6) | A(7) I A(8) I A(9) I A(10) | A(l l) | B(6) | B(7) | B(8) | B(9) | B(10) | B(l l) | ... (2) or equivalently Data Stream (3):

I AA(0) I BB(0) I AA(1) | BB(1) | ... | AA(L) | BB(L) | AA(L+1) | BB(L+1) ... (3) where AA is a block of 6 As and BB is a block of 6 Bs. The BB blocks are delayed with respect to the AA blocks by feeding the BB blocks through delay buffer 1214 of Figure 12, in order to create the following separate streams entering physical layer combiner 1216, represented by Data Streams (4):

|AA(0)| AA(1) I AA(2) I AA(3) | ... | AA(L) |AA(L+1)|AA(L+2)|AA(L+3)| ...

(4)

-> Delay Buffer -> |BB(-L)|BB(-L+1)|BB(-L+2)|BB(-L+3)| ... I BB(0) I BB(1) | BB(2) | BB(3) | ... where, in this case, the delay buffer has a delay of L x 26 packets. [0059] The AA and BB delayed streams are then combined at physical layer combiner 1216 by alternately taking a block from each stream to create the time diversity stream, which feeds the legacy ATSC transmitter, represented by Data Stream (5): I AA(0) I BB(-L) I AA( 1 ) I BB(-L+ 1 ) | ... | AA(L) | BB(0) | AA(L+ 1 ) | BB(1 ) ... (5)

The legacy ATSC transmitter has the ability to transfer the time diversity stream of Data Stream (5) to a receiver.

[0060] Figure 13 shows a receiver implementation for the present arrangement. At the receiver, after demodulation at demodulator 1312 and equalization at equalizer 1314, delay buffer 1316 creates two versions of the transmitted stream, the first of which represents a delayed version of Data Stream (5), and the second which represents the original stream, Data Stream (5). These two versions are represented by Data Streams (6):

-> Delay Buffer -> |AA(0)| BB(-L) |AA(1) |BB(-L+1)| ... |AA(L)| BB(0) |AA(L+1 ) |...

(6)

|AA(0)|BB(-L)|AA(1)|BB(-L+1)| ... |BB(0)|AA(L+1)|BB(1 ) ||AA(L+2)| ... |BB(L)|AA(2L+1)|BB(L+1)|... where Delay Buffer 1316 has a length of (2xL) x 26 packets. These two streams are then fed into the FEC decoding block 1318. The paragraphs below describe operation of the HL FEC core for the present arrangement, which exists as part of HL FEC 1320. Similar concepts apply to LL FEC 1322 since it can be seen as a subset of the HL FEC 1320. Figure 14 shows the architecture for an HL FEC core that receives Data Streams (4) from Delay Buffer 1316 of Figure 13. Two separate FEC encoded inputs, (Path 0) 1412 and (Path 1) 1414, represented by the two streams of Data Streams (4), enter the dual- stream decoder. The data stream identified as Path 0 passing through the Delay Buffer is received in Subcore 0 while Path 1 identified by the other data stream of Data Streams (4) is received by Subcore 1. In addition, two separate a priori output streams (Path 0) 1416 and (Path 1) 1418 are delivered from one FEC core to the next, as part of the iterative FEC decoding process. [0061] Similar elements from Figure 11 are also present in the FEC Core of Figure 14 and only the blocks associated with the GF (256) SCBC code will see the recombined stream. All similar blocks are identified by the same reference numbers found in Figure 11. The similar blocks in Figures 11 and 14 are associated with most legacy ATSC FEC decoder functionalities, including trellis decoding, convolutional deinterleaving and derandomizing, as well as the reencoding counterparts. Figure 14 also includes decoding block 1428 which contains similar blocks to those discussed with respect to Figure 11.

[0062] The operation of stagger multiplexer 1430 and stagger demultiplexer 1432 is set forth below.

[0063] The streams of Data Streams (4) are fed into inputs 1412 and 1414. The streams are then processed by subcore 0 1420 and subcore 1 1422, respectively, before reaching packet demultiplexer 1426. Stagger multiplexer 1430 receives Data Streams (6), and creates one stream of alternating AA blocks and zeros and another stream of alternating BB blocks and zeros, represented by Data Streams (7):

| AA(0) | 0 | AA(1) | 0 | ... | AA(L) | 0 | AA(L+1) | 0 | ...

(7)

| BB(0) | 0 I BB(1) | 0 | ... | BB(L) | 0 | BB(L+1) | 0 | ... This step is performed by extracting AA and BB blocks from the streams of Data Streams (6) and zeroing the bolded blocks in Data Streams (6), which together do not form meaningful A&B SCBC codewords. For example, AA(0)&BB(0) form a meaningful block of SCBC codewords, but AA(L)&BB(-L) or BB(-L)&AA(L+1) do not. In addition, stagger multiplexer 1430 may also deconstruct the grouping of 6 As and 6 Bs from Data Streams (7) and Data Streams (2), in order to regenerate the stream

represented by Data Stream (8):

| A(0) | B(0) | A(1) | B(1 ) | ... | A(5) | B(5) | 0 | 0 | ... | A(L) | B(L) | A(L+1 ) | B(L+1) ... (8) [0064] The recreated stream is the same as the original stream represented by Data Stream (1), including embedded zeroes, ready to be delivered to decoding block 1424. Since zero is an SCBC codeword, it will pass unchanged through the remaining blocks in the chain.

[0065] Following decoding block 1424, stagger demultiplexer block 1432 receives the stream of Data Stream (8), and separates the A and B blocks of Data Stream (8). The blocks are regrouped to be representative of Data Stream (2) and used to generate data streams identical to Data Streams (7) in order to deliver the streams back to subcore 0 1420 and subcore 1 1422.

[0066] The grouping of A and B blocks dictates that the passing of extrinsic information from one FEC core to the next occurs as a continuous stream without interruption at the MAP decoder which results in a 0.8dB gain in AWGN (Additive White Gaussian Noise) performance over an implementation where A and B blocks are not grouped.. There is minimal loss in performance for the MAP decoder during that field of data. The loss in performance is only associated with the presence of legacy ATSC interspersed with the mobile ATSC data during the beginning and the end of the mobile data in field F0 of Table 1.

[0067] One skilled in the art may observe that increasing the grouping of As and Bs beyond 6 for this particular example does not increase the performance, but instead increases the latency of the receiver. This is because the mobile field F0 only contains 6 blocks of 26 packets. Thus, the size of the grouping of blocks is a function of the size of the mobile field.

[0068] The timing diversity scheme described above may be easily extended to include frequency diversity if, for example, the A blocks are transmitted in one frequency and the B blocks in another frequency. At the receiver, those two frequencies would be demodulated and the streams regrouped into Data Stream (3) prior to FEC decoding.

[0069] Figure 15A shows an example of how preamble training data may be embedded within the burst data in 156 segments of joint DTV M/H data and training data within field F0, shown in Table 1, for example, with a code rate of R = 12/52. This preamble training data is embedded by a training data inserter as described above as a part of FEC Encoder 2 of Figure 3. Training data exists in specific bytes of each segment for blocks of 52 segments. The same structure repeats 3 times throughout the 156 segments of data. Each 52 segment block constitutes an A & B block pair as described above. The A and B blocks are each 26 segments and serially transmitted out of the SCBC encoder or packet deinterleaver. In Figure 15 A, the top 26 segments represent block A and the bottom 26 segments represent block B. Thus, each vertical line of Figure 15A may contain one SCBC codeword. This implies that each vertical line of preamble training data in Figure 15 A (for example, vertical line 4) may also constitute an SCBC codeword, in which case, the top 26 segments are different than the bottom 26 segments for most good

performance codes, with good error correcting capability. If however, the preamble training data is not encoded by FEC encoder 2 shown in Figure 3 (which includes the SCBC encoder), then each preamble training data vertical line in Figure 15A may contain any chosen data. The 3 blocks of 52 segments may be repetitions of the same training codewords or new training codewords. As discussed above, the preamble training data is a known data sequence added by a training data generator at FEC encoder 2 shown in Figure 3 and may also be fully encoded by FEC encoder 2. At the receiver end, both equalizer 1314 shown in Figure 13 and the iterative FEC decoder may take advantage of known data in order to improve performance, through correlation or any other method. One skilled in the art will appreciate that there are known ways by which one may take advantage of training data to improve performance of equalizers or FEC decoders.

Figure 15A also depicts a 20 byte Reed Solomon (RS) addendum to the data block.

[0070] Figure 15B shows the training bytes after ATSC convolutional interleaving is performed by the interleaver shown in Figure 1 at the transmitter. In Figure 15B, the inputs to the convolutional interleaver are identified by the diagonal arrows and the outputs are identified by the horizontal lines. The training bytes, shown as vertical lines in Figure 15 A, are joined at the interleaver output to create serially continuous sets of bytes in a transmitted stream, as identified by the horizontal lines in Figure 1 B. For the 156 segments of the mobile burst, the structure of Figure 15B extends through the diamonds shown in Figure 15B to complete and add new horizontal lines of training. An important function of the preamble training data results from the serially continuous segments of the transmitted streams being utilized by equalizer 1314 shown in Figure 13 and the iterative FEC decoder shown in Figure 3 as training data since equalizer 1314 and the iterative FEC decoder receive the interleaved stream. In addition to its well known functionality of helping to improve the performance of the equalizer and iterative FEC decoder, the preamble training data may be designed to assist the receiver of Figure 13 in distinguishing between AA&BB and BB&AA blocks because only AA&BB blocks should be sent to the transport block receiver output of Figure 13. This is explained by the depiction of Data Streams 6 and 7 and the explanation of the processing of Data Streams 6 and 7 above, where all BB&AA blocks are discarded and replaced by all zero blocks since BB&AA blocks do not constitute SCBC codewords. This identification of AA&BB or BB&AA blocks can be performed by transmission of a flag embedded in the field sync of the mobile burst of interest However, due to strong impairments present in the mobile channels, it is desirable to complement this flag strategy with a more reliable detection mechanism, which takes advantage of the strong FEC decoding capabilities of the present arrangement shown in Figure 13. In particular, a preamble training data detector (by correlation or any other method) may be placed within the HL FEC core of Figures 13 and 14, after the MAP decoder or after the SCBC decoder to correlate against known preamble training data, thus taking advantage of HL FEC decoding over multiple iterations. In addition, a preamble training data detector may be placed within the LL FEC core, which feeds the equalizer shown in Figure 13, after the MAP decoder or after the SCBC decoder to correlate against known preamble training data, taking advantage of LL FEC decoding over multiple iterations. It is through the LL FEC feedback shown in Figure 13 that the equalizer may take advantage of the preamble training data for improved performance.

[0071] A training structure that jointly supports both functions of training data (improved equalization and FEC performance, as well as identification of AA&BB blocks) in this diversity system is desired. In this particular diversity system the A & B blocks are grouped in the manner represented by Data Stream (2), which results in the transmission of Data Stream (3). This means that one F0 field may contain six A blocks and a subsequent F0 field may contain six B blocks of mobile data. Specifically, the F0 fields will alternately include A and B blocks. Hence, it is desirable for the preamble training data of A blocks to differ from those of B blocks, therefore, distinguishing an AA type F0 field from a BB type F0 field. However, if the training data for A blocks differs from the training data for B blocks, the training algorithm in the equalizer would have to change for alternating F0 fields, separately storing training data for A or B blocks, instead of having one set for all fields. On the other hand, from the perspective of the equalizer, it is desirable for the training data to be the same in both the AA blocks and BB blocks of Data Stream (3), where a single AA or BB block each represents an F0 field. Thus, having the same training data for both A and B blocks would prevent the separation of AA&BB blocks and BB&AA blocks, since both blocks would contain the same training data, making them indistinguishable.

[0072] A mixed mode training data that supports the equalizer's need for similar training data in both AA and BB blocks, while retaining the differentiation necessary between AA and BB blocks to permit reliable detection of these blocks is proposed.

[0073] Figure 16 shows a first embodiment of mixed mode training data. A horizontal portion of the 156 segments denoted by block 1610 is reserved for separate training data between AA and BB blocks The remaining portion denoted by block 1612 contains training data that is common to both the AA and BB blocks. The portion of the 156 segments containing the separate training data in block 1610 is small enough to not considerably affect the convergence of the equalizer, yet still permits reliable detection of the AA and BB blocks at the FEC. For example, this portion may consist of 26 segments or less, but would not be restricted to this size. In addition, not all vertical lines depicted in block 1610 of Figure 16 need be chosen to contain distinct training data.

[0074] The particular vertical lines are chosen interfere minimally with equalizer training. For example, choosing vertical lines 17 or 43 of Figure 16 are preferable to vertical lines 56 or 108, since the latter pair of vertical lines creates a continuous segment of training data for the equalizer (as shown in the center horizontal line of Figure 15B), as opposed to the former. The advantage of this embodiment is that a preamble training detector within the FEC decoder placed after convolutional deinterleaver 928 in Figure 14 is restricted to a small subset of the serial data segments, thus facilitating quicker decision making. Figure 16 also depicts a 20 byte Reed Solomon (RS) addendum to the data block.

[0075] Figure 17 shows a second embodiment of mixed mode training data. A vertical portion of the 156 segments, shown as blocks 1710 and 1712, are reserved for separate training data between AA and BB blocks. The remaining portion denoted by block 1714 contains training data that is common to both the AA and BB blocks. The portions of 156 segments containing separate training data, shown by blocks 1710 and 1712, are small enough to not considerably affect the convergence of the equalizer, yet still permit reliable detection of the AA and BB blocks at the FEC. For example, this portion may consist of specific vertical lines constituting 156 bytes (or 3 SCBC codewords in the case of a R = 12/52 SCBC code rate). The entire line need not be chosen. For example, a 56 byte subset (equivalent to one SCBC codeword) is sufficient. In addition, the number of vertical lines chosen can be any subset of the training data. The advantage of this embodiment is that the particular portion of training data could be chosen to be an SCBC codeword and would be fully decoded by the SCBC decoder in each FEC iteration, thus enhancing decoder performance with respect to the first embodiment. The number of lines can also be any subset of the training data.

[0076] The particular vertical lines in the second embodiment are chosen to least interfere with equalizer training. For example, choosing vertical lines 17 or 43 of Figure

16 are preferable to vertical lines 56 or 108, since the latter pair of vertical lines create a continuous segment of training data for the equalizer, as opposed to the former. Figure

17 also depicts a 20 byte Reed Solomon (RS) addendum to the data block.

[0077] The concepts of both the first and second embodiments can be utilized together, in addition to offering a choice of horizontal and vertical portions of the 156 segments for holding separate training data between AA and BB blocks.

[0078] One skilled in the art will observe that the training structure schemes described above will operate similarly in a system with frequency diversity. For example, if the A blocks are transmitted in one frequency and the B blocks at another frequency. At the receiver, those two frequencies would be demodulated and regrouped into Data Stream (5) prior to FEC decoding.

[0079] Although the arrangement has been described in terms of exemplary

embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly to include other variants and embodiments of the arrangement which may be made by those skilled in the art without departing from the scope and range of equivalents of the arrangement. This disclosure is intended to cover any adaptations or variations of the embodiments discussed herein.

Claims

CLAIMS:

1. A method for combining training data within groups of bytes in a digital data stream comprising a plurality of information blocks and a plurality of parity blocks, the method comprising:

generating training data specific to the information blocks;

inserting the training data specific to the information blocks into a first reserved portion of at least one of the information blocks;

generating training data specific to the parity blocks;

inserting the training data specific to the parity blocks into a first reserved portion of at least one of the parity blocks;

generating training data common to both the information blocks and the parity blocks;

inserting the training data common to both the information blocks and the parity blocks into both a second reserved portion of at least one of the information blocks and a second reserved portion of at least one of the parity blocks.

2. The method of claim 1 , wherein training data specific to the information blocks is inserted into a first reserved portion of each of the information blocks.

3. The method of claim 1, wherein training data specific to the parity blocks is inserted into a first reserved portion of each of the parity blocks.

4. The method of claim 1 , wherein training data common to both the information blocks and the parity blocks are inserted into both a second reserved portion of each of the information blocks and a second reserved portion of each of the parity blocks.

5. The method of claim 1 , wherein inserting the training data specific to the information blocks is performed by selecting specific bytes corresponding to the first reserved portion of the information blocks and placing training data into the first reserved portion of the information blocks; and

inserting the training data specific to the parity blocks is performed by selecting specific bytes corresponding to the first reserved portion of the parity blocks and placing training data into the first reserved portion of the parity blocks.

6. The method of claim 1, wherein, each information block and each parity block includes S segments of B bytes and the reserved portion of each information block and each parity block includes RB bytes, wherein RB < B bytes in all S segments.

7. The method of claim 6, wherein the first reserved portion of each information block includes RB bytes for RSI segments, wherein RSI < S segments and the second reserved portion of each information block includes RB bytes for RS2 segments, wherein RS2 = S - RSI segments; and

the first reserved portion of each parity block includes RB bytes for RSI segments, wherein RSI < S segments and the second reserved portion of each parity block includes RB bytes for RS2 segments, wherein RS2 = S - RSI segments.

8. The method of claim 6, wherein the first reserved portion of each information block includes RBI bytes, wherein RBI < RB bytes and the second reserved portion of each information block includes RB2 bytes, wherein RB2 = RB - RBI bytes; and

the first reserved portion of each parity block includes RBI bytes, wherein RBI <

RB bytes and the second reserved portion of each parity block includes RB2 bytes, wherein RB2 = RB - RBI bytes.

9. The method of claim 1 , further comprising detecting whether a block is an information block or a parity block by analyzing a first reserved portion of each information block and parity block. O 2011/068493

10. An apparatus for combining training data within groups of bytes in a digital data stream comprising a plurality of information blocks and a plurality parity blocks, the apparatus comprising:

a training data generator that generates: 1) training data specific to the information blocks, 2) training data specific to the parity blocks, and 3) training data common to both the information blocks and the parity blocks;

the training data inserter that inserts: 1) the training data specific to the information blocks into a first reserved portion of at least one of the information blocks, 2) the training data specific to the parity blocks into a first reserved portion of at least one of the parity blocks, and 3) the training data common to both the information blocks and the parity blocks into a second reserved portion of at least one the information blocks and a second reserved portion of at least one of the parity blocks.

11. The apparatus of claim 10, wherein training data specific to the information blocks is inserted into a first reserved portion of each of the information blocks.

12. The apparatus of claim 10, wherein training data specific to the parity blocks is inserted into a first reserved portion of each of the parity blocks.

13. The apparatus of claim 10, wherein training data common to both the information blocks and the parity blocks are inserted into both a second reserved portion of each of the information blocks and a second reserved portion of each of the parity blocks.

14. The apparatus of claim 10, wherein the training data inserter inserts the training data specific to the information blocks by selecting specific bytes corresponding to the first reserved portion of the information blocks and placing training data into the first reserved portion of the information blocks; and

inserts the training data specific to the parity blocks by selecting specific bytes corresponding to the first reserved portion of the parity blocks and placing training data into the first reserved portion of the parity blocks.

15. The apparatus of claim 10, wherein, each information block and each parity block includes S segments of B bytes and the reserved portion of each information block and each parity block includes RB bytes, wherein RB < B bytes in all S segments.

16. The apparatus of claim 15, wherein the first reserved portion of each information block includes RB bytes for RS 1 segments, wherein RS 1 < S segments and the second reserved portion of each information block includes RB bytes for RS2 segments, wherein RS2 = S - RSI segments; and

the first reserved portion of each parity block includes RB bytes for RSI segments, wherein RS 1 < S segments and the second reserved portion of each parity block includes RB bytes for RS2 segments, wherein RS2 = S - RSI segments.

17. The apparatus of claim 15, wherein the first reserved portion of each information block includes RBI bytes, wherein RBI < RB bytes and the second reserved portion of each information block includes RB2 bytes, wherein RB2 = RB - RBI bytes; and the first reserved portion of each parity includes RBI bytes, wherein RBI < RB bytes and the second reserved portion of each parity block includes RB2 bytes, wherein RB2 = RB - RBI bytes.

18. The apparatus of claim 10, further comprising a receiver including a training data detector that receives the information blocks and parity blocks and detects whether a block is an information block or a parity block by analyzing a first reserved portion of each information block and each parity block.