WO2011064921A1

WO2011064921A1 - Solid-state image pickup device, method for driving same, and image pickup device

Info

Publication number: WO2011064921A1
Application number: PCT/JP2010/005075
Authority: WO
Inventors: 孝廣室島
Original assignee: パナソニック株式会社
Priority date: 2009-11-27
Filing date: 2010-08-17
Publication date: 2011-06-03
Also published as: JP2011114731A

Abstract

Disclosed is a solid-state image pickup device (100), which is provided with: a plurality of pixel circuits (111) which are disposed in matrix; a plurality of vertical signal lines (103); a plurality of switch transistors (114); and a plurality of column amplifying units (115) which are connected to the vertical signal lines (103) via the switch transistors (114). Each of the pixel circuits (111) is provided with: a photodiode (PD1) wherein signal charges are accumulated; a floating diffusion (FD1); a transfer transistor (NM1) connected between the photodiode (PD1) and the floating diffusion (FD1); and an amplifying transistor (NM3). Furthermore, the solid-state image pickup device (100) is provided with a control unit (110), which turns off the switch transistor (114) in a transfer period wherein the signal charges are transferred from the photodiode (PD1) to the floating diffusion (FD1).

Description

Solid-state imaging device, driving method thereof, and imaging device

The present invention relates to a solid-state imaging device, a driving method thereof, and an imaging device, and more particularly to a solid-state imaging device including a column amplification circuit.

In recent years, MOS (Metal-Oxide-Semiconductor) sensors are becoming mainstream as solid-state imaging devices replacing CCD (Charge-Coupled-Device) sensors.

A general CCD sensor includes PD (photodiode) as a light receiving element and a CCD transfer path in pixels arranged in a matrix. The PD generates and accumulates signal charges according to incident light. The CCD transfer path transfers this signal charge in the vertical and horizontal directions in response to a plurality of high voltage transfer pulses. The transferred charge Q is QV (charge-voltage) converted by an FDA (floating diffusion amplifier) provided at the sensor output terminal, and then output.

In contrast to this, in a general MOS sensor, pixels arranged in a matrix form each include a PD as a light receiving element and an FDA for charge-voltage conversion. Thereby, the MOS sensor QV converts the signal charge generated and accumulated by the PD in accordance with the incident light for each pixel. The converted signal is output through an output circuit configured with a single power source.

Here, the reason why MOS sensors have become mainstream in recent years is that a CCD sensor reads a signal using a plurality of high-voltage transfer pulses, whereas a MOS sensor reads a signal with a single power source in this way. Because it can. As a result, the MOS sensor can reduce power consumption compared to the CCD sensor.

Also, the MOS sensor does not require a special manufacturing process like the CCD sensor. Thus, in the MOS sensor, the analog circuit and the digital circuit can be arranged in the same chip, so that the video signal processing can be easily realized with one chip.

For example, a technique described in Patent Document 1 is known as such a MOS sensor.

FIG. 10 is a block diagram showing the configuration of the solid-state imaging device described in Patent Document 1.

A readout circuit 400 shown in FIG. 10 is arranged in each column, reads out a reset voltage and a signal voltage output from a pixel to a vertical signal line (pixel output line 430), and each amplified by a column amplifier circuit (column amplifier 401). The voltage is held in a column CDS (correlated-double-sampling) circuit composed of a switch transistor and a capacitor.

The pixel signal held by the readout circuit 400 is output via the differential amplifier 420.

JP 2008-42677 A

However, in the solid-state imaging device described in Patent Document 1, the voltage of the FD temporarily rises due to the parasitic capacitance between the gate and the FD (floating diffusion) during the rising period of the transfer transistor in the pixel. As a result, the voltage of the vertical signal line also rises, so that the output voltage of the column amplifier circuit also varies. Therefore, the solid-state imaging device described in Patent Document 1 has a problem that it takes time until the output voltage of the column amplifier circuit is stabilized.

Therefore, an object of the present invention is to provide a solid-state imaging device capable of shortening the time until the output voltage of the column amplifier circuit is stabilized.

In order to achieve the above object, a solid-state imaging device according to an aspect of the present invention is a solid-state imaging device, which is arranged in a matrix and includes a plurality of pixel circuits that output a signal voltage corresponding to the intensity of incident light. , One for each column, a plurality of vertical signal lines for outputting the signal voltage by a plurality of pixel circuits arranged in the corresponding column, and one for each column, provided for the corresponding column A plurality of switch units connected to the vertical signal line, one for each column, connected to the vertical signal line via the switch unit provided in the corresponding column, and output to the vertical signal line A plurality of column amplifiers that amplify the signal voltage, and each of the plurality of pixel circuits includes a light receiving unit that accumulates signal charges according to an intensity of incident light, a floating diffusion, the light receiving unit, and the light receiving unit. Floating diffusion And a transfer transistor connected to the vertical diffusion line, and an amplification transistor that outputs the signal voltage corresponding to the voltage of the floating diffusion to the vertical signal line. The solid-state imaging device further includes: A control unit that turns off the switch unit in a transfer period in which signal charges are transferred to the floating diffusion;

The control unit may turn off the transfer transistor and turn on the switch unit in a first output period after the transfer period.

Further, the control unit turns off the transfer transistor and turns off the switch unit in a second output period that is a period immediately after the transfer period, and the first output period is the same as that of the second output period. It may be a period immediately after.

The switch unit may be a MOS transistor.

The gate aspect ratio of the MOS transistor may be equal to or less than the gate aspect ratio of the amplification transistor.

The solid-state imaging device further includes a plurality of voltage supply circuits that are provided for each column and supply a constant voltage to the vertical signal lines provided in the corresponding column, and the control unit includes the transfer unit. In the period, the constant voltage may be supplied to the vertical signal line by the voltage supply circuit.

The voltage supply circuit may include a MOS transistor in which the constant voltage is applied to one of a source terminal and a drain terminal, and the other of the source terminal and the drain terminal is connected to the vertical signal line.

As described above, the present invention can provide a solid-state imaging device capable of shortening the time until the output voltage of the column amplifier circuit is stabilized.

FIG. 1 is a block diagram showing the configuration of the solid-state imaging device according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing the configuration of the pixel circuit and the column amplifier according to the first embodiment of the present invention. FIG. 3 is a timing chart showing the operation of the solid-state imaging device according to the first embodiment of the present invention. FIG. 4 is a timing chart showing the operation of the solid-state imaging device according to the comparative example of the first embodiment of the present invention. FIG. 5 is a circuit diagram showing a configuration of a pixel circuit and a column amplification unit according to the second embodiment of the present invention. FIG. 6 is a timing chart showing the operation of the solid-state imaging device according to the second embodiment of the present invention. FIG. 7 is a timing chart showing the operation of the solid-state imaging device according to the comparative example of the second embodiment of the present invention. FIG. 8 is a block diagram showing a configuration of a solid-state imaging device according to a modification of the embodiment of the present invention. FIG. 9 is a diagram illustrating a configuration of an imaging apparatus according to the third embodiment of the present invention. FIG. 10 is a diagram illustrating a conventional solid-state imaging device.

Hereinafter, embodiments of a solid-state imaging device according to the present invention will be described in detail with reference to the drawings.

(First embodiment)
The solid-state imaging device according to the first embodiment of the present invention includes a switch circuit connected between a vertical signal line and a column amplifier circuit. Furthermore, the solid-state imaging device according to the first embodiment of the present invention turns off the switch circuit during the transfer period in which the signal charge is transferred from the light receiving unit to the floating diffusion. Thereby, the solid-state imaging device according to the first embodiment of the present invention does not transmit the voltage fluctuation of the vertical signal line due to the voltage fluctuation of the floating diffusion generated in the transfer period to the column amplifier circuit. Thereby, the solid-state imaging device according to the first embodiment of the present invention can prevent the output voltage of the column amplifier circuit from changing in the opposite direction to the voltage obtained by amplifying the pixel signal. Therefore, the solid-state imaging device according to one embodiment of the present invention can shorten the time until the output voltage of the column amplifier circuit is stabilized.

First, the overall configuration of the solid-state imaging device according to the first embodiment of the present invention will be described.

FIG. 1 is a block diagram showing a configuration of a MOS type solid-state imaging device 100 according to the first embodiment of the present invention.

A solid-state imaging device 100 shown in FIG. 1 includes a pixel array 101, a vertical scanning circuit 102, a plurality of vertical signal lines 103, a switch circuit 104, a column amplification circuit 105, a column CDS circuit 106, and a horizontal scanning circuit 107. A horizontal common signal line 108, an output amplifier circuit 109, a control unit 110, and a plurality of column current sources 112.

The pixel array 101 includes a plurality of pixel circuits (pixel cells) 111 arranged in a matrix. Each pixel circuit 111 outputs a signal voltage corresponding to the intensity of incident light. Each pixel circuit 111 outputs a reset voltage in the reset state.

The vertical scanning circuit 102 selects the pixel circuit 111 in units of rows.

Each vertical signal line 103 is provided corresponding to a column of pixel circuits 111. The vertical signal line 103 is commonly connected to the pixel circuits 111 in each column, and transmits the signal voltage output by the pixel circuits 111 arranged in the corresponding column in the column direction.

The switch circuit 104 includes a plurality of switch transistors 114. Each switch transistor 114 is an n-type MOS transistor, for example, and is provided corresponding to each column. Each switch transistor 114 is connected to the vertical signal line 103 of the corresponding column.

The column amplifier circuit 105 includes a plurality of column amplifiers 115. Each column amplifier 115 is provided corresponding to each column. Each column amplifier 115 is connected to the vertical signal line 103 of the corresponding column via a switch transistor 114. The column amplification unit 115 inverts and amplifies the signal voltage output from the plurality of pixel circuits 111 arranged in the corresponding column. Note that the column amplifier 115 may non-invert amplify the signal voltage and the reset voltage.

The column CDS circuit 106 includes a plurality of column CDS units 116. Each column CDS unit 116 is provided corresponding to each column. Each column CDS unit 116 is connected to a column amplification unit 115 arranged in the corresponding column. This column CDS unit 116 performs correlation double sampling processing on the signal amplified by the column amplification unit 115 and holds it. Specifically, the column CDS unit 116 holds a voltage corresponding to the difference between the reset voltage amplified by the column amplifier 115 and the signal voltage as an output signal.

The horizontal scanning circuit 107 sequentially reads out the output signals held in the plurality of column CDS sections 116 to the horizontal common signal line 108 using the selection signal.

The horizontal common signal line 108 is connected to the output amplifier circuit 109.

The output amplifier circuit 109 amplifies the output signal read to the horizontal common signal line 108, and outputs the amplified signal to the outside of the solid-state imaging device 100.

Each column current source 112 is provided corresponding to each column. Further, each column current source 112 is connected to the vertical signal line 103 arranged in the corresponding column.

The control unit 110 controls operations of the vertical scanning circuit 102, the switch circuit 104, the column amplification circuit 105, the column CDS circuit 106, and the horizontal scanning circuit 107.

Next, a detailed configuration of the solid-state imaging device 100 according to the present embodiment will be described.

In the following, for simplification of description, a circuit configuration for one column will be described.

FIG. 2 is a circuit diagram showing a detailed configuration of the pixel circuit 111, the switch transistor 114, and the column amplifier 115 according to the present embodiment.

As shown in FIG. 2, the pixel circuit 111 includes a photodiode PD1, a floating diffusion FD1, a transfer transistor NM1, a reset transistor NM2, and an amplification transistor NM3.

The photodiode PD1 is a light receiving unit that generates signal charges corresponding to the intensity of incident light and accumulates the generated signal charges.

The floating diffusion FD1 accumulates the signal charge transferred from the photodiode PD1. Thereby, the floating diffusion FD1 converts the signal charge into a voltage.

The transfer transistor NM1 transfers the signal charge accumulated in the photodiode PD1 to the floating diffusion FD1. Specifically, the transfer transistor NM1 is connected between the photodiode PD1 and the floating diffusion FD1. The gate terminal of the transfer transistor NM1 is connected to the transfer signal line TR.

The reset transistor NM2 resets the voltage of the floating diffusion FD1 to the voltage of the power supply signal line VPIX. Specifically, the reset transistor NM2 is connected between the floating diffusion FD1 and the power supply signal line VPIX. The gate terminal of the reset transistor NM2 is connected to the reset signal line RS.

The amplification transistor NM3 outputs a signal voltage or a reset voltage corresponding to the voltage of the floating diffusion FD1 to the vertical signal line 103. Specifically, the amplification transistor NM3 is connected between the vertical signal line 103 and the power supply signal line VPIX. The gate terminal of the amplification transistor NM3 is connected to the floating diffusion FD1.

The column current source 112 includes a current source transistor NM4. The current source transistor NM4 is connected between the vertical signal line 103 and the ground potential line. The gate terminal of the current source transistor NM4 is connected to the control signal line LGCELL.

A source follower circuit is formed together with the current source transistor NM4 and the amplification transistor NM3. This source follower circuit outputs a signal voltage corresponding to the signal charge transferred from the photodiode PD1 to the floating diffusion FD1 to the vertical signal line 103.

Further, one end of a switch transistor 114 is connected to the vertical signal line 103. A column amplifier 115 is connected to the other end of the switch transistor 114.

The column amplifier 115 amplifies the signal input via the switch transistor 114 and outputs the amplified signal to the output terminal AMPOUT. The column amplifier 115 includes an input capacitor Cin1, a feedback capacitor Cfb1, a common-source amplifier transistor NM5, a current source transistor PM1, and a clamp transistor NM6.

The input capacitor Cin1 has one end connected to the other end of the switch transistor 114.

The feedback capacitor Cfb1 has one end connected to the other end of the input capacitor Cin1 and the other end connected to the output terminal AMPOUT.

The source grounded amplification transistor NM5 has a gate terminal connected to the other end of the input capacitor Cin1, a source terminal connected to the ground potential line, and a drain terminal connected to the output terminal AMPOUT.

The current source transistor PM1 has a gate terminal connected to the voltage line VLOAD, a source terminal connected to the power supply voltage line, and a drain terminal connected to the output terminal AMPOUT.

The clamp transistor NM6 is, for example, an n-type MOS transistor, and is connected between the other end of the input capacitor Cin1 and the output terminal AMPOUT. The clamp transistor NM6 has a gate terminal connected to the control signal line CL.

As described above, the solid-state imaging device 100 according to the present embodiment includes the column amplification unit 115 that amplifies the pixel signal between the vertical signal line 103 and the column CDS unit 116. As a result, the solid-state imaging device 100 has an FPN (fixed pattern) for each column caused by variations in Vth (threshold voltage) of the clamp transistor used in the column CDS unit 116 and variations in the parasitic capacitance between the gate and the source for each column. Noise) can be suppressed. Therefore, the solid-state imaging device 100 can prevent the occurrence of vertical line noise due to FPN.

Further, the solid-state imaging device 100 according to the present embodiment can increase the signal component with respect to the FPN generated in the column CDS unit 116 by providing the column amplification unit 115 for each column and amplifying the pixel signal. . Thereby, the solid-state imaging device 100 can realize high S / N.

1 and 2 exemplify a so-called one-pixel one-cell structure in which each unit cell (pixel circuit 111) has a light receiving portion, a transfer transistor, a floating diffusion, a reset transistor, and an amplification transistor. As described above, the unit cell includes a plurality of light receiving units and transfer transistors, and further has a structure in which any one or all of the floating diffusion, the reset transistor, and the amplification transistor are shared in the unit cell. It may be a cell structure.

In addition, the structure of the solid-state imaging device 100 may use a structure in which the light receiving portion is formed on the surface of the semiconductor substrate, that is, on the same side as the gate electrode and the wiring of the transistor. Further, in the configuration of the solid-state imaging device 100, a so-called back-illuminated image sensor (back surface) in which the light receiving portion is formed on the back surface side of the semiconductor substrate (the surface opposite to the surface on which the transistor gate electrode and wiring are formed). An irradiation type solid-state imaging device) structure may be used.

Next, operations of the pixel circuit 111 and the column amplifier 115 according to this embodiment will be described with reference to the timing chart of FIG. Note that RS, TR, CL, SH, FD, SFOUT, and AMPOUT shown in FIG. 3 are a reset signal line RS, a transfer signal line TR, a control signal line CL, a control signal line SH, a floating diffusion FD1, and a vertical signal line, respectively. 103 and the voltage of the output terminal AMPOUT. Further, the voltages of the reset signal line RS and the transfer signal line TR are controlled by the control unit 110 via the vertical scanning circuit 102. The voltages of the control signal line CL and the control signal line SH are controlled by the control unit 110.

First, in the period t1 to t2, the control unit 110 resets the floating diffusion FD1 in the pixel circuit 111 to the voltage of the power supply signal line VPIX by setting the reset signal line RS to a high level. Accordingly, the pixel circuit 111 outputs a reset voltage to the vertical signal line 103 in the periods t1 to t4.

Further, at the timing of time t1, the control unit 110 turns on the clamp transistor NM6 of the column amplification unit 115 by setting the control signal line CL to a high level. As a result, the column amplifier 115 is reset. In addition, at the timing of time t3, the control unit 110 releases the reset of the clamp transistor NM6 by setting the control signal line CL to the low level.

In the period t1 to t4, the control unit 110 turns on the switch transistor 114 by setting the control signal line SH to a high level. As a result, the reset voltage of the column amplifier is output to the output terminal AMPOUT during the period from time t3 to t4 after the reset is released.

Thereafter, in the period t4 to t5, the control unit 110 turns on the transfer transistor NM1 by setting the transfer signal line TR to the high level. Thereby, the signal charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD1. At the time t4, the voltage of the floating diffusion FD1 rises due to the parasitic capacitance between the gate and the FD of the transfer transistor NM1. As a result, the voltage of the vertical signal line 103 increases. At time t4, the control unit 110 turns off the switch transistor 114 by setting the voltage of the control signal line SH to a low level. As a result, the control unit 110 performs control so that fluctuations in the voltage of the vertical signal line 103 are not transmitted to the column amplification unit 115.

Thereafter, at time t5, the control unit 110 turns off the transfer transistor NM1 by setting the transfer signal line TR to the low level. As a result, a signal voltage corresponding to the intensity of incident light is output to the vertical signal line 103.

Next, at time t6, the control unit 110 turns on the switch transistor 114 by setting the voltage of the control signal line SH to a high level. As a result, the column amplifier 115 outputs an output voltage obtained by inverting and amplifying the signal voltage output to the vertical signal line 103 to the output terminal AMPOUT.

Here, for comparison, the operations of the source follower circuit (vertical signal line 103) and the column amplifier 115 when the switch transistor 114 is not provided will be described with reference to the timing chart of FIG.

As described above, in the period t4 to t5, the voltage of the floating diffusion FD1 rises due to the parasitic capacitance between the gate and the FD of the transfer transistor NM1. As a result, the voltage SFOUT of the vertical signal line 103 also increases. This rise in voltage SFOUT is transmitted to the column amplifier 115. As a result, the voltage at the output terminal AMPOUT decreases.

In this way, during the period t4 to t5, the voltage fluctuation of the vertical signal line 103 changes in the opposite direction to the actual pixel signal, and thus the voltage at the output terminal AMPOUT also changes in the opposite direction to the actual pixel signal. . As a result, a long time is required until the voltage of the output terminal AMPOUT is stabilized at the actual signal level.

On the other hand, when the switch transistor 114 is provided as in the present embodiment and the switch transistor 114 is turned off during the transfer period from t4 to t5, the voltage at the output terminal AMPOUT changes in the opposite direction to the actual pixel signal. Can be prevented.

Furthermore, in the example shown in FIG. 4, compared with the example shown in FIG. 3, it takes a long time until the voltage SFOUT of the vertical signal line 103 is stabilized at the actual signal level immediately after time t5. This is because when the switch transistor 114 is not provided, the input capacitance Cin1 of the column amplifier 115 is connected to the vertical signal line 103, and thus the load capacitance of the vertical signal line 103 is large. Thus, when there is no switch transistor 114, it takes a long time to stabilize the voltage SFOUT because it takes time to discharge the charge charged in the input capacitor Cin1.

On the other hand, by providing the switch transistor 114 and turning off the switch transistor 114 in the period t5 to t6, the influence of the input capacitance Cin1 can be reduced.

As described above, the solid-state imaging device 100 according to the first embodiment of the present invention can suppress the deterioration of the response speed of the column amplification unit 115 due to the voltage fluctuation of the vertical signal line 103. Thereby, the solid-state imaging device 100 can shorten the time until the voltage of the output terminal AMPOUT is stabilized.

As described above, the solid-state imaging device 100 according to the first embodiment of the present invention turns off the switch transistor 114 provided between the vertical signal line 103 and the column amplifier 115 during the signal transfer period. Thus, the solid-state imaging device 100 can shorten the time until the voltage of the vertical signal line 103 is stabilized, and can prevent the voltage fluctuation of the vertical signal line 103 from being transmitted to the column amplification unit 115 in the subsequent stage. Accordingly, the solid-state imaging device 100 can shorten the time until the voltage of the output terminal AMPOUT is stabilized. Thereby, the solid-state imaging device 100 can suppress vertical noise.

Also, the solid-state imaging device 100 can increase the output resistance of the pixel source follower circuit by the switch transistor 114. Thereby, since the solid-state imaging device 100 can narrow the frequency band of the pixel source follower circuit, it is possible to reduce random noise. Further, in this way, in order to narrow the frequency band of the pixel source follower circuit, the gate aspect ratio (gate width W / gate length L) of the switch transistor 114 should be less than or equal to the gate aspect ratio of the amplification transistor NM3. preferable.

Note that the pixel circuit 111 in this embodiment does not include a row selection transistor, but the same effect can be obtained even when the pixel circuit 111 includes a row selection transistor.

In addition, the column amplification unit 115 in the present embodiment is configured by a plurality of capacitors and a common source amplifier circuit. However, when the column amplification unit 115 is configured by only a common source amplifier circuit, or a plurality of capacitors and a differential circuit. The same effect can be obtained even when configured with an amplifier circuit.

(Second Embodiment)
The present invention is also effective for a circuit configuration including a circuit for pulling up the vertical signal line 103 to the power supply voltage in order to improve the characteristics of the pixel. In the second embodiment of the present invention, a case where the present invention is applied to a solid-state imaging device including such a pull-up circuit will be described.

In the following, differences from the above-described first embodiment will be mainly described, and redundant description will be omitted.

FIG. 5 is a circuit diagram showing a detailed configuration of the pixel circuit 111, the switch transistor 114, and the column amplifier 115 according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the element similar to FIG.

As shown in FIG. 5, the solid-state imaging device according to the second embodiment of the present invention further includes a voltage supply circuit 201 in addition to the configuration shown in FIG.

The voltage supply circuit 201 is provided for each column and is connected to the vertical signal line 103 of the corresponding column. The voltage supply circuit 201 supplies the voltage of the power supply signal line VPIX to the vertical signal line 103 in the corresponding column.

The voltage supply circuit 201 includes a pull-up transistor PM12.

The pull-up transistor PM12 is connected between the power signal line VPIX and the vertical signal line 103. The control signal line FDUP is connected to the gate terminal of the pull-up transistor PM12.

Hereinafter, the operations of the pixel circuit 111 and the column amplifier 115 according to the second embodiment of the present invention will be described with reference to the timing chart of FIG. Note that FDUP shown in FIG. 6 indicates the voltage of the control signal line FDUP. Further, the voltage of the control signal line FDUP is controlled by the control unit 110.

In addition to the operation shown in FIG. 3, the control unit 110 turns on the pull-up transistor PM12 by setting the control signal line FDUP to a low level during the transfer period from t4 to t5. As a result, the voltage of the vertical signal line 103 is pulled up to the voltage of the power supply signal line VPIX.

FIG. 7 is a diagram for comparison, and is a timing chart showing operations of the pixel circuit 111 and the column amplifier 115 when the switch transistor 114 is not provided.

As shown in FIGS. 6 and 7, similarly to the first embodiment described above, the solid-state imaging device according to the second embodiment has a response speed of the column amplification unit 115 caused by voltage fluctuations of the vertical signal line 103. Can be prevented.

Furthermore, in the example shown in FIG. 4, compared with the example shown in FIG. 3, it takes a long time until the voltage SFOUT of the vertical signal line 103 is stabilized at the actual signal level immediately after time t5. This is because when the switch transistor 114 is not provided, the input capacitance Cin1 of the column amplifier 115 is connected to the vertical signal line 103, and thus the load capacitance of the vertical signal line 103 is large. As described above, when the switch transistor 114 is not provided, it takes a long time for the voltage SFOUT to be stabilized because it is necessary to discharge the charge charged in the input capacitor Cin1 in the pull-up operation.

Further, when FIG. 4 is compared with FIG. 7, the voltage fluctuation of the vertical signal line 103 in the period t4 to t5 becomes larger by performing the pull-up operation in FIG. As a result, the voltage fluctuation of the output terminal AMPOUT also increases. Further, after time t5, since it is necessary to discharge the charge charged in the input capacitor Cin1 in the pull-up operation, it takes a longer time for the voltage SFOUT to stabilize.

Even in such a case, by providing the switch transistor 114 as in the present embodiment and turning off the switch transistor 114 in the period t4 to t5, the voltage at the output terminal AMPOUT changes in the opposite direction to the actual pixel signal. Can be prevented. Further, by turning off the switch transistor 114 in the period t5 to t6, the influence of the input capacitor Cin1 can be reduced. Accordingly, the solid-state imaging device 100 can shorten the time until the voltage of the output terminal AMPOUT is stabilized.

Further, the voltage supply circuit 201 in the present embodiment is configured to pull up the vertical signal line 103 to the power supply voltage, but the vertical signal line 103 is set to the ground (ground potential) or the bias voltage (arbitrary constant voltage). The same effect can be obtained with the reset configuration.

Also, some recent MOS sensors include a column ADC circuit (analog-digital converter) instead of the column CDS circuit. This has an advantage that the FPN generated in the pixel circuit 111 and the column amplifier 115 during AD conversion can be removed as compared with the conventional analog output configuration. In addition, since the MOS sensor including the column ADC circuit can convert the read pixel signal into a digital signal immediately after reading the pixel signal, noise generated in an output circuit such as a column CDS circuit and an output amplifier circuit can be suppressed. In addition, a MOS sensor including a column ADC circuit has an advantage that digital signal processing can be performed in a chip.

The present invention can obtain the same effect even if it is mounted on a chip having a built-in column ADC.

FIG. 8 is a block diagram illustrating a configuration of a solid-state imaging device 100A in which the present invention is applied to a solid-state imaging device including a column ADC. In addition, the same code | symbol is attached | subjected to the element similar to FIG.

8 differs from the solid-state imaging device 100 shown in FIG. 1 in place of the column CDS circuit 106, the horizontal scanning circuit 107, the horizontal common signal line 108, and the output amplifier circuit 109. A column ADC circuit 211, a digital memory 213, and a shift register 214 are provided.

The column ADC circuit 211 includes a plurality of column ADCs 212 provided for each column.

The column ADC 212 converts the signal amplified by the column amplifier 115 provided in the corresponding column into a digital signal.

The digital memory 213 holds digital signals converted by the plurality of column ADCs 212.

The shift register 214 transfers the digital signal held in the digital memory 213 in the horizontal direction and serially outputs it outside the solid-state imaging device 100A.

(Third embodiment)
In the third embodiment of the present invention, an imaging apparatus (camera system) including the solid-state imaging apparatus 100 described above will be described.

FIG. 9 is a diagram illustrating a configuration of an imaging apparatus 120 according to the third embodiment of the present invention.

An imaging device 120 shown in FIG. 9 includes an optical member (lens) 121 that collects external light, the MOS solid-state imaging device 100 according to the first or second embodiment of the present invention, and the interior of the solid-state imaging device 100. A timing control unit 123 that controls the operation timing of the circuit, and an image signal processing unit 124.

The solid-state imaging device 100 converts the light incident through the optical member 121 into an image signal and outputs the image signal.

The image signal processing unit 124 processes the image signal output from the solid-state imaging device 100 and outputs the processed image signal to an external device such as a display device.

For example, the solid-state imaging device 100 and the image signal processing unit 124 are formed on the same semiconductor chip. Note that the solid-state imaging device 100 and the image signal processing unit 124 may be formed on different semiconductor chips.

As described above, the solid-state imaging device 100 includes the pixel array 101 that converts incident light into a voltage signal, the signal processing unit 132 that processes the signal output from the pixel array 101, and the signal processing unit 132 that outputs the signal. And an output circuit 133 that outputs the signal as an image signal. The signal processing unit 132 corresponds to the switch circuit 104, the column amplifier circuit 105, and the column CDS circuit 106 described above. The output circuit 133 corresponds to the output amplifier circuit 109 described above.

The image signal processing unit 124 includes a correlated double sampling circuit (CDS circuit 134) that receives an image signal from the output circuit 133, an AGC (Auto Gain Control) 135, an ADC (Analog Digital Converter) 136, and a DSP (Digital Signal). Processor) 137.

That is, the imaging device 120 of the present embodiment can realize a high-speed imaging device by including the solid-state imaging device 100 that can suppress deterioration in response speed.

In other words, the present invention can provide an imaging device that can shorten the time until the output voltage of the column amplifier circuit is stabilized. Further, the imaging device 120 shortens the time until the voltage of the vertical signal line is stabilized by turning off the switch transistor provided in the vertical signal line during the signal transfer period, and the voltage fluctuation of the vertical signal line. Can not be transmitted to the column amplifier circuit in the subsequent stage. Thereby, the imaging device 120 can suppress deterioration of the response speed of the circuit, and can suppress vertical line noise.

In addition, since the imaging device 120 can increase the output resistance of the pixel source follower circuit by the switch transistor, the frequency band of the pixel source follower circuit can be narrowed and random noise can be reduced. .

(Summary)
As described above, the solid-state imaging devices according to the first to third embodiments of the present invention are arranged in a matrix and output a signal voltage corresponding to the intensity of incident light, and one for each column. Provided, and a plurality of vertical signal lines 103 from which signal voltages are output by a plurality of pixel circuits arranged in the corresponding column, and one vertical signal line provided for each column, connected to the corresponding vertical signal line. A plurality of switch sections (switch transistors 114), one for each column, connected to the vertical signal line via the switch section provided in the corresponding column, and the signal voltage output to the vertical signal line Each of the plurality of pixel circuits includes a light receiving unit (PD1) that accumulates signal charges corresponding to the intensity of incident light, a floating diffusion (FD1), a light receiving unit, and a floating unit. De The solid-state imaging device further includes a transfer transistor (NM1) connected to the fusion and an amplification transistor (NM3) that outputs a signal voltage corresponding to the voltage of the floating diffusion to the vertical signal line. A control unit 110 is provided to turn off the switch unit during a transfer period (t4 to t5) in which signal charges are transferred to the floating diffusion.

Thereby, the solid-state imaging device according to an aspect of the present invention does not transmit the voltage variation of the vertical signal line due to the voltage variation of the floating diffusion generated in the transfer period to the column amplification unit. Thereby, the solid-state imaging device according to an aspect of the present invention can prevent the output voltage of the column amplification unit from changing in the opposite direction to the voltage obtained by amplifying the pixel signal. Therefore, the solid-state imaging device according to one embodiment of the present invention can shorten the time until the output voltage of the column amplification unit is stabilized.

Further, the control unit turns off the transfer transistor and turns on the switch unit in the first output period (t6 and after) after the transfer period. Accordingly, the solid-state imaging device according to an aspect of the present invention can shorten the time until the column amplification unit stably outputs the output voltage obtained by amplifying the signal voltage in the first output period.

Further, the control unit turns off the transfer transistor and turns off the switch unit in the second output period (t5 to t6), which is a period immediately after the transfer period, and the first output period is immediately after the second output period. Is the period. As described above, the solid-state imaging device according to one embodiment of the present invention can reduce the load capacity of the vertical signal line in the second output period by turning off the switch unit in the second output period. Accordingly, the solid-state imaging device according to an aspect of the present invention can shorten the time until the voltage of the vertical signal line is stabilized, and as a result, the period until the output voltage of the column amplifier is stabilized can be shortened.

The switch unit is a MOS transistor, and the gate aspect ratio of the MOS transistor is equal to or less than the gate aspect ratio of the amplification transistor. Accordingly, the solid-state imaging device according to one embodiment of the present invention can increase the output resistance of the pixel source follower circuit. Therefore, the solid-state imaging device according to one embodiment of the present invention can narrow the frequency band of the pixel source follower circuit, and thus can reduce the occurrence of random noise.

The solid-state imaging device according to one embodiment of the present invention further includes a plurality of voltage supply circuits 201 that are provided for each column and supply a constant voltage to the vertical signal lines provided in the corresponding column, The unit causes the voltage supply circuit to supply a constant voltage to the vertical signal line in the transfer period. As a result, the solid-state imaging device according to one embodiment of the present invention can improve the output voltage of the column amplifier circuit even when it includes a voltage supply circuit (for example, a pull-up circuit) in order to improve pixel characteristics. You can save time.

The voltage supply circuit includes a MOS transistor (PM12) in which a constant voltage is applied to one of the source terminal and the drain terminal, and the other of the source terminal and the drain terminal is connected to the vertical signal line.

The present invention can be realized not only as such a solid-state imaging device, but also as a driving method or a control method of a solid-state imaging device using characteristic means included in the solid-state imaging device as a step. It can also be realized as a program that causes a computer to execute typical steps.

Furthermore, the present invention can be realized as a semiconductor integrated circuit (LSI) that realizes part or all of the functions of such a solid-state imaging device, or as an imaging device (camera) including such a solid-state imaging device. Or a camera system including such a solid-state imaging device.

Further, the solid-state imaging device according to the first to third embodiments and each processing unit included in the imaging device are typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.

Further, the integration of circuits is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI or a reconfigurable processor that can reconfigure the connection and setting of circuit cells inside the LSI may be used.

Also, some or all of the functions of the solid-state imaging device and the imaging device according to the first to third embodiments of the present invention may be realized by a processor such as a CPU executing a program.

Furthermore, the present invention may be the above program or a recording medium on which the above program is recorded. Needless to say, the program can be distributed via a transmission medium such as the Internet.

In addition, at least some of the functions of the solid-state imaging device, the imaging device, and the modifications according to the first to third embodiments may be combined.

Also, the numbers used above are all exemplified for specifically describing the present invention, and the present invention is not limited to the illustrated numbers. Furthermore, the logic levels represented by high / low or the switching states represented by on / off are illustrative for the purpose of illustrating the present invention, and different combinations of the illustrated logic levels or switching states. Therefore, it is possible to obtain an equivalent result. Further, the circuit configuration shown above is exemplified to specifically describe the present invention, and an equivalent input / output relationship can be realized by a circuit having a different configuration. In addition, n-type and p-type transistors and the like are illustrated to specifically describe the present invention, and it is possible to obtain equivalent results by inverting them. In addition, the connection relationship between the components is exemplified for specifically explaining the present invention, and the connection relationship for realizing the function of the present invention is not limited to this.

In the above description, an example using a MOS transistor is shown, but another transistor such as a bipolar transistor may be used.

Furthermore, various modifications in which the present embodiment is modified within the scope conceived by those skilled in the art are also included in the present invention without departing from the gist of the present invention.

The present invention can be applied to a solid-state imaging device. Further, the present invention can be applied to a digital still camera, a digital video camera, a mobile phone device, and the like provided with a solid-state imaging device.

DESCRIPTION OF SYMBOLS 100,100A Solid-state imaging device 101 Pixel array 102 Vertical scanning circuit 103 Vertical signal line 104 Switch circuit 105 Column amplification circuit 106 Column CDS circuit 107 Horizontal scanning circuit 108 Horizontal common signal line 109 Output amplifier circuit 110 Control part 111 Pixel circuit 112 Column current Source 114 Switch transistor 115 Column amplifying unit 116 Column CDS unit 120 Imaging device 121 Optical member 123 Timing control unit 124 Image signal processing unit 132 Signal processing unit 133 Output circuit 134 CDS circuit 135 AGC
136 ADC
137 DSP
201 Voltage supply circuit 211 Column ADC circuit 212 Column ADC
213 Digital memory 214 Shift register 400 Read circuit 401 Column amplifier 420 Differential amplifier 430 Pixel output line AMPOUT Output terminal Cfb1 Feedback capacitor Cin1 Input capacitor CL, FDUP, LGCELL, SH Control signal line FD1 Floating diffusion NM1 Transfer transistor NM2 Reset transistor NM3 Amplification Transistor NM4, PM1 Current source transistor NM5 Common source amplification transistor NM6 Clamp transistor PD1 Photo diode PM12 Pull-up transistor RS Reset signal line SFOUT voltage TR Transfer signal line VLOAD Voltage line VPIX Power supply signal line

Claims

A solid-state imaging device,
A plurality of pixel circuits arranged in a matrix and outputting a signal voltage corresponding to the intensity of incident light;
A plurality of vertical signal lines that are provided for each column and from which the signal voltage is output by a plurality of pixel circuits arranged in the corresponding column;
A plurality of switch units provided one for each column and connected to the vertical signal line provided in the corresponding column;
A plurality of column amplification units provided for each column, connected to the vertical signal line via the switch units provided in the corresponding column, and amplifying the signal voltage output to the vertical signal line; Prepared,
Each of the plurality of pixel circuits is
A light receiving unit that accumulates signal charges according to the intensity of incident light; and
Floating diffusion,
A transfer transistor connected between the light receiving unit and the floating diffusion;
An amplification transistor that outputs the signal voltage corresponding to the voltage of the floating diffusion to the vertical signal line;
The solid-state imaging device further includes:
A solid-state imaging device comprising: a control unit that turns off the switch unit during a transfer period in which signal charges are transferred from the light receiving unit to the floating diffusion.
The solid-state imaging device according to claim 1, wherein the control unit turns off the transfer transistor and turns on the switch unit in a first output period after the transfer period.
In the second output period that is a period immediately after the transfer period, the control unit turns off the transfer transistor and turns off the switch unit,
The solid-state imaging device according to claim 2, wherein the first output period is a period immediately after the second output period.
The solid-state imaging device according to claim 1, wherein the switch unit is a MOS transistor.
The solid-state imaging device according to claim 4, wherein a gate aspect ratio of the MOS transistor is equal to or less than a gate aspect ratio of the amplification transistor.
The solid-state imaging device further includes:
A plurality of voltage supply circuits, one for each column, for supplying a constant voltage to the vertical signal line provided in the corresponding column;
The solid-state imaging device according to claim 1, wherein the control unit causes the voltage supply circuit to supply the constant voltage to the vertical signal line in the transfer period.
The solid-state imaging according to claim 6, wherein the voltage supply circuit includes a MOS transistor in which the constant voltage is applied to one of a source terminal and a drain terminal, and the other of the source terminal and the drain terminal is connected to the vertical signal line. apparatus.
An imaging device comprising the solid-state imaging device according to claim 1.
A plurality of pixel circuits arranged in a matrix and outputting a signal voltage corresponding to the intensity of incident light;
A plurality of vertical signal lines that are provided for each column and from which the signal voltage is output by a plurality of pixel circuits arranged in the corresponding column;
A plurality of switch units provided one for each column and connected to the vertical signal line provided in the corresponding column;
A plurality of column amplification units provided for each column, connected to the vertical signal line via the switch units provided in the corresponding column, and amplifying the signal voltage output to the vertical signal line; A solid-state imaging device driving method comprising:
Each of the plurality of pixel circuits is
A light receiving unit that accumulates signal charges according to the intensity of incident light; and
Floating diffusion,
A transfer transistor connected between the light receiving unit and the floating diffusion;
An amplification transistor that outputs the signal voltage corresponding to the voltage of the floating diffusion to the vertical signal line;
The driving method of the solid-state imaging device is:
A method for driving a solid-state imaging device, wherein the switch unit is turned off during a transfer period in which signal charges are transferred from the light receiving unit to the floating diffusion.