WO2011047455A1

WO2011047455A1 - Controlled low temperature growth of epitaxial silicon films for photovoltaic applications

Info

Publication number: WO2011047455A1
Application number: PCT/CA2009/001512
Authority: WO
Inventors: Siva Sivoththaman; Mahdi Farrokh-Baroughi; Roohollah Samadzadeh-Tarightat
Original assignee: Arise Technologies Corporation
Priority date: 2009-10-23
Filing date: 2009-10-23
Publication date: 2011-04-28

Abstract

A low temperature method and system configuration for depositing a silicon layer on a silicon substrate of a selected grade. The method comprises the acts of: positioning the silicon substrate in a chamber suitable for chemical vapor deposition of the silicon layer on the silicon substrate, an external surface of the silicon substrate suitable for promoting crystalline film growth; using a plurality of process parameters for adjusting growth of the silicon layer, the plurality of process parameters including a first process parameter of a process temperature for inhibiting diffusion of dopant atoms into the external surface of the silicon substrate, and a second process parameter of a hydrogen dilution level for providing excess hydrogen atoms to affect a layer crystallinity and phase of the silicon layer; exposing the external surface of the silicon substrate in the chamber to a vapor at appropriate ambient chemical vapor deposition conditions, the vapor including silicon, dopant and the excess hydrogen precursors, the precursors for use in growing the silicon layer; and originating growth of the silicon layer on the external surface to form an interface between the doped silicon layer and the silicon substrate, such that the interface between the growing Si layer and the underlying Si substrate is extremely clean. The resultant silicon substrate and grown layers (or thin film) can be used in solar cell manufacturing.

Description

CONTROLLED LOW TEMPERATURE GROWTH OF EPITAXIAL SILICON FILMS FOR PHOTOVOLTAIC APPLICATIONS

FIELD OF THE INVENTION

The present invention relates processes for the production of silicon thin films and silicon wafer devices.

BACKGROUND

The need for the use of environment-friendly, sustainable energy technologies continues to grow by the day. Photovoltaics (PV) are an attractive form of energy conversion technology where sunlight is directly converted into electrical energy. While PV is considered one of the fastest growing industries in the renewable energy sector, there are still challenges in making PV affordable, i.e., in rendering it cost-competitive as opposed to conventional fossil-fuel-based electricity. Partly influenced by the diverse electricity tariff policies exercised by different countries, the current cost of PV electricity is approximately 2 - 4 times more expensive compared to conventional electricity. A vibrant market has so far helped to considerably reduce the cost of PV. An average market growth of over 30% translates into a 5% cost reduction per year on a system level. While the PV market continues to grow, the need to further reduce the cost of PV to achieve affordability persists. Wafer-based crystalline silicon (Si) solar cells dominate 90-95% of the PV market. In crystalline Si-based commercial PV modules, the material cost itself (poly-Si feedstock, ingot growth, and wafering) is responsible for 40%-50% of the cost, while the cell fabrication and module assembly are each responsible for 25%- 30% of the cost. The use of base Si materials produced by low-cost means, efficient device designs, and development of compatible device processing technologies hold the keys to meet the challenge of cost reduction.

In addition to affordability, another important challenge that is facing current PV manufacture is the expected shortage of Si feedstock in the near future. Until recently, the Si feedstock needs of the solar cell manufacturers have been sufficiently met by the off-spec silicon from the IC (integrated circuits) industry. However, due to the steady and continued growth of the PV industry, the Si supply for PV will now lag behind the demand. The PV Si supply in 2006 was about 20,000 tons. It is predicted that, already in 2007, the rapid growth of PV manufacture will be truncated by insufficient supply of Si. Several industries worldwide have started to respond to this problem in recent years through production initiatives for PV-specific Si. Various methods are being applied to produce Si wafers in less expensive ways. With the electronic quality of the low-cost Si somewhat inferior to that of traditional microelectronic grade Si, challenges arise in developing new fabrication technologies for solar cells that are suitable with low-cost (low-quality) silicon wafers/substrates (e.g. such as low grade IC silicon) in order not to compromise device performance of the produces silicon wafer solar cell devices.

Current conventional fabrication technologies for Si solar cells involve several high temperature (HT) steps, normally carried out at more than 900°C. Typical HT steps include; emitter diffusion, back surface field formation (BSF), and surface passivation. Depending on the complexity of the Si wafer device, there can also be multiple diffusions (selective emitters, localized BSF, point contacts) and oxidations (passivation oxide, anti- reflection coatings, masking oxides) at HT. The Si device performance largely depends on the minority carrier lifetime in the Si wafers, i.e. wafer/substrate grade. In order to maintain a high carrier lifetime in Si, the use of defect-free Si substrates/wafers of good quality, stringent wafer-cleaning requirements involving large quantities of chemicals, and clean process ambient are very critical in HT processes. High performance Si solar devices have been demonstrated at laboratory level using high-grade quality Float Zone (FZ) and Czochralski (CZ) Si wafers of both n-type and p-type. Generally, high efficiency PV systems can be too expensive for extensive use and application in solar cell markets. In the drive towards cutting the cost of PV, several methods have been introduced for producing PV-specific Si wafers by less expensive means compared to traditional microelectronic grade Si. Examples include multi-crystalline Si by direct casting, Si ribbon growth, and Si sheets from powder. Further, with the scarcity of Si for PV fast becoming an issue, manufacturers have started exploring new method Si production using Si substrate feedstock refined at different levels of purity. With the presence of impurities and crystal defects in considerable amounts in lower grade SI substrates, traditional HT device processing techniques may not be ideal for these materials since multiple thermal excursions at HT processing can further degrade the substrate material quality (rendering the resultant solar cell either substandard or otherwise insufficient for PV systems). Further, pre-process defect passivation techniques, such as hydrogenation, need to be applied to the wafers to improve the material quality. Again, HT process steps can remove the advantages brought about by the passivation techniques. Therefore, low temperature (LT) device processing technologies need to be resorted to in order to maintain the material cost advantage and device performance. A minimal thermal budget will also remove the stringent requirements for cleaning and chemical usage, as well as the thermal stress introduced to the substrate.

A current LT approach for Si solar cells is the hetero-junction technology. In this technology, amorphous Si (a-Si) films are deposited on crystalline Si substrates at LT. The junction (e.g. np) thus formed turns out to be a hetero-junction (i.e. amorphous- crystalline), as opposed to classical homo-junctions (i.e. crystalline-crystalline) created by HT diffusion processes, due to the difference in band gap between the a-Si emitter film and the crystalline Si (c-Si) substrate. A solar cell structure based on the LT technology is the so-called "hetero-junction with intrinsic layer" device. This device employs both intrinsic and extrinsic a-Si films. Since a-Si has low carrier mobility and electrical conductivity (due to lack of crystallinity), the devices always require additional transparent conductive oxide (TCO) films on top of a-Si to enable electrical conduction without resistive losses. The requirement of TCO films can add to process complexity and cost. Further, the interface quality between the a-Si film and the c-Si substrate is very critical for the hetero-junction structure. In order to achieve a better interface, the hetero- junction device processes employ an ultra-thin (5-10 nm), intrinsic (undoped) a-Si film deposited prior to the deposition of doped a-Si film. These requirements, in addition to increasing the number of process steps and complexity, can also add stringent condition complications for process control. Further, it is recognised that the use of amorphous Si in the emitter layers is disadvantageous, due to the low doping efficiencies of amorphous Si (a-Si) films.

As is generally known from industry, researchers have so far been unsuccessful in developing low temperature Si thin films that have desired levels of crystal quality, doping efficiency, and conductivity. The advantages of such low temperature Si thin films can be low temperature Si solar cell manufacturing technologies that are simpler, that inhibit process complexities like TCO layers and interface passivation, and that result in pn junctions that are of sufficient high quality providing desired high performance levels of the solar cells.

Further, it is recognized that deposition temperature can play an important role in determining the crystallinity quality of Si thin films. In the case of chemical vapor deposition (CVD) deposition of Si thin films on crystalline Si substrates, higher film crystallinity typically requires HT deposition conditions, which enhances surface migration of the dopant as well as Si atoms. In the case of low temperature techniques such as plasma enhanced chemical vapor deposition, LT depositions typically result in amorphous and some times micro or nano crystalline Si films. Further, the attempt of adding dopant atoms (e.g. boron and/or phosphorous) in the thin-film growth process can make it even more difficult to achieve sufficient crystallinity of the doped thin film at LT. Therefore, in Si solar cells, the LT requirement for processing and the requirement for depositing highly crystalline/conductive films have been difficult to achieve simultaneously.

Further high performance device design requires specific profiles in dopant concentrations. Achieving desired dopant profile in a controlled manner has been difficult in both high T and low temperature processes. In the case of low temperature deposition of films the added difficulty is due to the influence of crystallinity on dopant activation. Current low temperature Si cell fabrication processes have complexities associated with the need for transparent conductive oxides, the need for ultra-thin emitters, and the need for ultra-thin intrinsic buffer layers. Developing low temperature silicon solar cells without these complexities has not been possible since highly conductive Si emitters (e.g. with conductivities close to 1000 Ω 'αη^"1) with high crystallinity have not been possible to develop.

SUMMARY OF THE INVENTION It is an object of the present invention to provide fabrications systems and methodologies for producing silicon based thin films that obviate or mitigate at least some of the above-presented disadvantages.

Another objective of the present invention is to develop a silicon thin film at low temperature, that inhibits dopant diffusion into the substrate, with desired film conductivity and crystallinity and to develop new low-temperature silicon solar cell process sequences using this film.

Another objective of the present invention is to provide a process for depositing Si thin films in a low temperature CVD process with dopant precursor gases resulting in desired doping efficiencies comparable to those obtainable by high temperature fabrication processes.

Another objective of the present invention is to provide a process for growing Si thin films with controlled distribution in crystallinity and conductivity at low temperatures (approximately 150°C<300°C<600°C). Another objective of the present invention is to provide a process for depositing Si thin films in low temperature (approximately 150°C<300°C<600°C) PECVD process with dopant precursor gases to result in a controlled distribution in doping concentration.

Another objective of the present invention is to provide a process for depositing Si thin films in a low temperature (approximately 150°C<300°C<600°C) PECVD process with variable degrees of crystallinity.

Another objective of the present invention is to control the degree of film recrystallization in the deposited films due to rapid thermal treatments higher than film deposition temperatures.

Another objective of the present invention is to control the degree of dopant activation after rapid thermal treatments higher than film deposition temperatures.

Another objective of the present invention is to deposit a low temperature thin film of high crystal quality with desired doping density and conductivity on top of another low temperature thin film of high crystal quality of certain doping density and conductivity.

Another objective of the present invention is to deposit multi-layers of low temperature thin films of high crystallinity with iso-type high-low and hetero-type high- high (tunnel junction) profile structure.

Another objective of the present invention is to grow mixed phase of amorphous/epitaxial Si films in which epitaxial phase grows in a columnar form (vertical nanotubes) and the amorphous Si tissues surround and passivate the surface of Si nanotubes. The amorphous/epitaxial heterojunction forms within the bulk of the deposited film and in fact result in a bulk heterojunction film.

Another objective of the present invention is to grow mixed phase amorphous/epitaxial Si films in which epitaxial phase grows in a columnar form (vertical nanotubes) and the amorphous Si tissues surround the Si nanotubes.

Another objective of the present invention is to develop another set of new solar cells employing high-low, tunnel junctions, and mixed amorphous/epi bulk heterojunction devices created by the controlled growth of epitaxial and amorphous/epitaxial films.

Another objective of the present invention is to develop another set of new solar cells employing distinct highly and moderately doped regions in the device emitter.

BRIEF DESCRIPTION OF DRAWINGS These and other features of the present invention will become more apparent in the following detailed description in which reference is made to the appended drawings by way of example only, wherein:

Figure 1 is a schematic diagram of a silicon solar cell fabricated using high temperature processes; Figure 2a is a schematic diagram of a double-sided, low-temperature heterojunction solar cell employing an amorphous silicon/crystalline silicon hetero-junction;

Figure 2b is the single-sided version of the hetero-junction cell of Figure 2a; Figure 3 is the high-resolution transmission electron microscope (HRTEM) image of the atomic structure of a hydrogenated amorphous silicon film deposited on a crystalline silicon substrate of Figures 2a and 2b;

Figure 4 is a diagram of a low temperature silicon wafer device fabrication environment;

Figure 5 is a further HRTEM image closeup of the bulk of the doped layer of Figure 12b showing the atomic arrangement;

Figure 6 shows conductivity of the doped layers of the environment of Figure 4 evolving with different hydrogen dilution (HD) levels; Figure7a shows the UV Raman spectra of the as-deposited doped layer formed by the environment of Figure 4;

Figure 7b shows a further embodiment of the UV Raman spectra of Figure 7a;

Figure 8a shows current-voltage-temperature (I-V-T) diode characteristics of a diode employing the doped layer formed by the environment of Figure 4; Figure 8b shows the saturation currents (Ioi, I₀₂) and activation energies (E_A) extracted from Figure 8a;

Figure 9a shows the flow chart for an "LT Process I" of the system of Figure 4;

Figure 9b is the process sequence of an "LT Process II" of the system of Figure 4;

Figure 9c represents the process sequence for an "LT Process III" of the system of Figure 4;

Figure 9d represents the process sequence for an "LT Process IV" of the system of Figure 4;

Figure 9e represents the process sequence for an "LT Process V" of the system of Figure 4; Figure 9f represents the process sequence for an "LT Process VI" of the system of Figure 4;

Figures 10a, 10b, 10c, lOd, lOe, and 1 Of represent the schematic of the solar cell devices fabricated using the LT Process I, LT Process II, LT Process III, LT Process IV, LT Process V, and LT Process VI of Figures 9a,b,c,d,e, and f, respectively;

Figure 11 shows the current- voltage characteristic of a test solar cell device (1 cm ) fabricated using LT Process I to demonstrate the high fill factor (75%) of the device without using transparent conductive oxides;

Figure 12a is a TEM image of a low-temperature silicon based emitter layer deposited on a crystalline Si substrate using the fabrication environment of Figure 4;

Figure 12b is a close-up HRTEM image of the image of Figure 12a;

Figure 12c is a close-up HRTEM image of a further embodiment of the image of Figure 12b;

Figure 13 is a block diagram of a computing device of the fabrication environment of Figure 4;

Figure 14 is an example silicon wafer device fabricated using the environment of Figure 4; and

Figure 15 is an example fabrication process of the system of Figure 4.

Figure 16a shows the TEM picture of a film 23 deposited on a crystalline silicon substrate 22. The material has a mixed epitaxial/amorphous Si phase within the bulk of the film.

Figure 16b shows the HRTEM picture of section "aa" of Figure 16a where an epitaxial Si nanowire, surrounded by amorphous Si material, grows from an epitaxial Si seed layer. Figure 17 is a high resolution SRP of a film grown in a single deposition run by periodically controllingthe dopant (phosphine) gas flow rate from high to low and low to high values. Since the SRP gives carrier (electron) concentration, full dopant activation because of the perfect crystallinity is self-evident.

Figure 18 shows how abrupt changes (over 6 orders of magnitude) by properly controlling the parameters (from undoped to doped) in the low temperature epitaxial process can be achieved. The high electron concentration at the end of the film attests to crystallinity.

Figure 19 shows a near ideal interface 114 between an improved epitaxial Si layer 23 and a c-Si substrate.

Figure 20 shows a transmission electron microscopic image of a film grown with a crystallinity gradient along with Fast Fourier Transformation images showing the progressive crystallinity change brought about by changing the film deposition conditions.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A Low Temperature (LT) fabrication scheme 200 (see Figure 15) for silicon wafer devices 21 (see Figure 14) is described, with the resulting crystal structure of the devices 21 including a silicon substrate 22 attached to grown thin film(s) layer 23 (single or multiple layers of silicon films having uniform or mixed material phase), thereby defining an interface 114 with the underlying Si substrate. It is recognized that the fabrication scheme can be used for manufacturing a number of different silicon wafer devices 21 for differing technology applications, such as but not limited to photovoltaic cells used in manufacturing of solar systems for the conversion of sunlight into electrical energy. It is recognized that the fabrication scheme 200, and resultant silicon wafer device 21 structure, are different from other High Temperature (HT) and other LT fabrication schemes and their corresponding silicon wafer devices 1, 9, 17 (see Figures 1, 2a, 2b). Solar Cell Examples

Referring to Figure 1, shown is an example wafer structure of a HT processed conventional n⁺pp⁺ silicon solar cell 1. The conventional silicon solar cell 1 can comprise a high-temperature diffused crystalline silicon emitter 2, a crystalline silicon absorber 3, a high temperature diffused back surface field (BSF) structure 4, backside metal contact and reflector 5, a single or double layer anti-reflective coating 6, front metal grid 7, and a high temperature oxide passivation layer 8. This solar cell 1 owes its success largely to the quality of the junction between the n⁺ emitter 2 and the p-type silicon absorber substrate 3, for example. The n⁺ emitter 2 is formed by diffusion of normally phosphorous (it is recognized that an analogous p-type emitter 2 could be formed using boron in place of the phosphorous when using an n-type silicon substrate 3) in the silicon substrate 3 at high temperatures, normally more than 900 °C. Facilitated by the diffusion of dopant donor atoms inside the crystalline silicon substrate 3, the metallurgical junction can be formed inside (i.e. beneath the interface 0 between the substrate 3 and the emitter 2) the substrate 3 of the silicon wafer device 1, hence helping to provide a high quality pn junction diode (e.g. an example of the silicon wafer device 1). The emitter 2 layer is usually greater that 0.5 microns in thickness, and absorbs light in the short wavelength (blue) region. To reduce the recombination of minority holes at the emitter 2 surface, the oxide passivation film 8 is grown at temperatures greater than 900°C. In order to reduce the recombination of minority electrons on the rear surface of the silicon substrate 3, the p⁺ back surface field 4 is created at the rear surface by diffusing boron at high temperatures, usually more than 950°C. It is recognized that manufacturing of the silicon wafer device 1 involves multiple steps using process temperatures in excess of 900°C. Referring to Figures 2a and 2b, a low temperature (LT) alternative for the solar cell 1 of Figure 1 is based on a hetero-junction between hydrogenated amorphous silicon (a-Si:H) of an emitter layer 11 and crystalline silicon materials of a substrate 10. Figure 2a illustrates the schematic structure of a double-sided hetero-junction solar cell 9. This is referred to as the Sanyo's "HIT" solar cell structure. In this structure, the n-type crystalline silicon substrate 10 is used as the absorber and the very thin (5-10 nm), boron doped (p⁺), a-Si:H emitter layer 11 is used as the emitter. The emitter layer 11 is deposited using plasma enhanced chemical vapor deposition (PECVD) deposition at low temperature. Prior to this emitter layer 11 deposition, an intrinsic (undoped) a-Si:H layer 12 is employed to help improve the quality of the junction between the highly boron- doped a-Si:H emitter layer 11 and the n-type c-Si substrate 10. It should be noted that unlike the high temperature-diffused solar cell device 1 (see Figure 1), the metallurgical junction in the solar cell 9 is formed on the surface of the substrate 10 (between substrate 10 and layer 12), which initially was full of dangling bonds with density of more than 10¹⁵ cm^"2, for example. Therefore, an optimized surface treatment by the ultra-thin (< about 5 nm) intrinsic a-Si:H layer 12 has been shown to be effective in passivating the dangling bonds on the surface of silicon substrate 10. It is noted that the inclusion of the intrinsic layer 12 is a critical step to help the compatibility between the substrate 10 and the amorphous silicon (a-Si:H) emitter layer 11. Further, a back surface field structure is also implemented by using an ultra thin intrinsic a-Si:H 13 and a phosphorous-doped (n⁺) a-Si:H filml4. Since the conductivities of the doped a-Si:H film 14 and the doped emitter layer 11 are low, transparent conductive oxide (TCO) films 15 are employed on both sides of the solar cell 9 to collect photo-generated carriers in the absorber layer (i.e. silicon substrate 10). Further, top and bottom metal grid patterns 16 are employed on top of the TCO layers 15, hence it is recognized that the TCO layers 15 are interposed between the grid patterns 16 and the doped a-Si:H layers (e.g. emitter layer 11 and film 14). Referring to Figure 2b, shown is a single-sided version of the HIT solar cell 17 without using back surface field structure at the rear side of the device 17. The light absorber silicon substrate 10 can be an "n" or "p" type, with the emitter layer 11 being "p" or "n" type accordingly. It is recognized that all of the low temperature hetero- junction silicon solar cells (i.e. having a crystalline substrate 10 combined with amorphous silicon emitter layers 11, and/or films 14) rely on the high electrical conductivity of the TCO layers 15 for collection of the photo-generated carriers by the metal grid patterns 16.

Referring to Figure 3, shown is a high-resolution transmission electron microscope (HRTEM) image 30 of a low-temperature hydrogenated amorphous Si film 19 developed by using a standard RF PECVD system (e.g. plasmatherm 790). The atomic structure of a hydrogenated amorphous silicon film 19, deposited on a crystalline silicon substrate 18, shows the clear contrast in atomic structure between the film 19 (non-crystalline) and the substrate 18 (e.g. the lack of epitaxial growth in the film 19 inherited from the substrate 18 crystalline structure). It is recognized that epitaxial growth can be defined as thin film 19 atomic structure that has the same or similar crystalline orientation as the substrate 18 on which the thin film 19 is grown, of which the thin film 19 shown in Figure 3 has no discernable epitaxial growth.

For example, the HRTEM image 30 is of the fifteen nm, phosphorous-doped (n- type) a-Si:H filml9 that is deposited on the p-type crystalline-Si substrate 18. As shown in the picture, an interface 32 between the c-Si substrate 18 and the a-Si:H emitter 19 is very sharp and the material phases are completely different in the emitter 19 and in the substrate 18. For example, the conductivity of the (n-type) a-Si:H emitter 19 shown in Figure 3 is less than 0.01 Ω^'Όιη^"1., due to the lack of crystalline atomic structural quality of the amorphous Si material. The conductivity of this emitter 19 film is low because free carrier mobility, here electrons, in the a-Si:H emitter 19 film is low (in the order of lcm²/v/s), and also the doping efficiency of the emitter 19 film is very low (in the order of 1%). Such a low conductivity can result in a sheet resistance in the range of several tens of mega-ohms per square for the emitter 19 film of fifteen nm thickness. This is one reason why the solar cells of Figures 2a and 2b use the TCO layers 15 on top of their emitter layers.

Low Temperature Fabrication Environment 100

Referring to Figure 4, shown is a low temperature fabrication environment 100 for fabricating the silicon wafer devices 21, having a crystalline Si (including single crystal, multicrystalline, and multicrystalline ribbon) substrate 22 (doped or undoped) connected/attached directly to a grown thin film doped layer 23 (silicon based), thereby defining an interface 114 (e.g. pn junction). The fabrication environment 100 can be implemented using a deposition chamber 104 (e.g. PECVD or HWCVD) controlled by a computing system 101 (e.g. a plasmatherm 790 machine). The operation of the chamber 104 is done through specifying a number of process control parameters 102, in order to influence the growing conditions (e.g. growth rate, atomic composition, degree of doping, degree of crystallinity, thickness, etc.) of a growth surface 116 of the layer 23.

For example, the environment 100 can be a plasma enhanced chemical vapor deposition (PECVD) process applied with appropriate precursor gases (layer building materials 106) for supplying precursor gases including silicon atoms Si, dopant atoms P,B and the excess hydrogen atoms H, the atoms for use in growing the doped or undoped silicon layer 23. The process control parameters 102 are monitored in order to deposit the layer 23 (e.g. thin films) of sufficient epitaxial or bulk heterojunction quality on the Si substrates 22. The process is so designed that the desired material phase (epitaxial or Si bulk heterojunction) is obtained. In case of growth of epitaxial Si thin films, the process is so designed that high carrier mobility, electrical conductivity, and crystallinity can be obtained in the epitaxial phase of the grown epitaxial thin films, even when the deposition temperature is kept low, as further described below. The process is so designed that the desired level of electrically active dopant density in the film(s) is achieved.

More specifically, the environment 100 can be used to fabricate the silicon devices 21 in a low temperature (e.g. less than 350°C) PECVD process that inhibits dopant diffusion into the substrate 22. Referring to Figure 12b, the deposition process on the growth surface 116 (see Figure 4) allows the growth of the layer 23, which in this case is a single layer with high concentration of phosphorous dopants (n-type), starting off, or otherwise originating, on the external surface 114 to form a uniform atomic structural interface region 150 (see Figure 12b) (as compared to the interface 32 - see Figure 3) between the silicon layer 23 and the silicon substrate 22, such that silicon layer 23 includes first atomic structural regions 150 having a higher quality of the atomic crystallinity next to the represented external surface 114 with adjacent second atomic structural regions 152 having a lower quality of the layer crystallinity with increasing concentrations of crystal defects for increasing thickness T of the doped silicon layer 23.

The regions 150, 152 include a propagation of the substrate 22 crystal structure into the crystallinity of the deposited film 23. This layer crystallinity in the regions 150, 152 can include epitaxial growth inherited from the substrate 22 crystal structure. Further, the crystal orientation of the substrate 22 crystal structure can be similar to the crystal orientation of the doped layer 23 crystallinity.

Referring again to Figure 4, for an n-doped Si film process, precursor gases/vapours used can be such as but not limited to: silane (SiH4) as a silicon atomic source 108; phosphine (PH3) as a dopant atomic source 110; and hydrogen (H2) as a dilution gas source 112 for providing excess hydrogen atoms to modify growth reactions. For a p-doped Si film, diborane (B₂H₆) can be used instead of P¾ precursor gases. For growing an intrinsic Si film, only S1H4 and H₂ gases are used as precursors. The controlled amounts of hydrogen (H₂) (as one of the process parameters 102) as a hydrogen dilution level source 112 are used by the environment 100 to partially control the crystallinity of the deposited layer 23.

Referring again to Figure 12b, the doped layer 23 Si material exhibits desired high crystallinity and high conductivity. The higher crystallinity of the doped layer 23 (over that of amorphous layers 11 - see Figures 2a, 2b and Figure 3) serves the conductivity of the doped layer 23 in two ways: (i) it improves the carrier mobility, and (ii) it improves the doping efficiency of the dopant atoms in the crystalline-like atomic structure (the ratio of the electrically active phosphorous concentration to the total phosphorous concentration in the film). Figure 12b shows the HRTEM image 30 of the interface regions 150, 152 between a (n⁺) layer 23 and the p-type crystalline Si substrate 22. The doped emitter layer 23 was deposited using the PECVD chamber 104 (see Figure 4) at a process temperature of 300°C with silane and phosphine precursors diluted in hydrogen (the gas phase phosphine to silane ratio was 1%). As shown in Figure 12b in the regions 150, 152, the crystalline structure of the doped emitter layer 23 has followed the crystal order of the substrate 22. This results in a highly crystalline (n+) Si doped emitter layer 23. As a result and interestingly enough, there is not a well-defined interface 114 (other than shown representatively for the original growth surface 116 at growth time = 0) between the crystalline Si substrate 22 and the doped emitter layer 23. This shows that the crystal order of the substrate 22 has propagated into the doped emitter layer 23 and the atomic arrangement in the doped emitter layer 23 is very similar to the atomic arrangement of the substrate 22. Figure 5 shows the HRTEM image 30 taken within the bulk of the doped Si layer 23, such that the image 30 shows that the crystallinity of the film 23 is very high and that the material is expected to show high carrier mobility and electrical conductivity due to appropriate selection of the process control parameters 102 (see Figure 4). These facts have been verified experimentally, as further described below.

Figure 16a shows the TEM picture of a film 23 deposited on a crystalline silicon substrate 22. The figure shows a columnar epitaxial silicon phases 235 with few tens of nm in diameter. The columnar epitaxial silicon phase is surrounded by an amorphous silicon phase 236 which passivates the walls of the epitaxial silicon phase. Due to the difference in the bandgap of the epitaxial silicon phase 235 (about 1.1 eV) and the amorphous silicon phase 236 (about 1.7 eV) a heterojunction forms at the interface 237 of the 235 and 236. This is clearly shown in Figure 16b, which is the HRTEM picture of the region "aa" of Figure 16a. Due to the presence of the heterointerface in the bulk of the deposited film we categorize this material in the bulk heterojunction (BHJ) material category. The film shown in Figure 16 was deposited with the aim of controlling the crystalline portion of the film. In this case a change in crystallinity is forced by continuously and controllably varying the plasma power during the deposition.

Control Parameters 102

Referring again to Figure 4, the process control parameters 102 can be adjusted, such as but not limited to: flow rates of the precursor atoms with respect to the growth surface 116; hydrogen dilution (HD) of the precursor gases; plasma RF (radio frequency) power; chamber 104 process pressure; surface treatment (see Figure 9a) further described below; a soft plasma pre-treatment (see Figure 9a) further described below; and chamber 104 temperature, in order to achieve the doped silicon emitter layer 23 that starts to grow (e.g. epitaxially) from the external surface 114 of the silicon substrate 22, i.e. at low temperature. The kinetics of the silicon layer 23 formation, the gradual change in crystallinity of the layer 23 by increasing thickness of the layer, type of bonding of dopant atoms (e.g. P, B), dopant efficiency, and the mixed phase growth (BHJ) can all be affected and controlled using appropriate adjustment of the process control parameters 102. The desired high crystallinity, doping efficiency, and conductivity of the doped silicon layer 23, along with the ability to form electrically high quality pn junctions formed between layer 23 and the underlying substrate 22 are further discussed below.

The n-type doped layers 23 are grown on the substrates 22 using S1H4, PH₃, and H₂ precursors under proper process conditions specified by the process control parameters 102 (see Figure 4). A high hydrogen dilution (HD = [100H₂/(SiH₄+PH₃+H₂)]) technique with HD more than 90% was employed to get the crystalline character doped layers 23 with desired doping efficiency (represented by conductivity levels - see Figure 6). The RF power and the process pressure can be chosen, with a reasonably wide process window, such that the layer 23 starts to grow through crystal structure propagation of the crystal structure of the substrate 22. For growing 30 - 130 nm thick layer 23, the process parameters 102 can be specified in the following example process windows: chamber pressure [200 mTorr- 1 Torr], the RF power density [10 mW/cm - 70 mW/cm ], and temperature [200°C - 300°C]. It is recognized that the thickness of the doped silicon layer 23 can be such as but not limited to: equal to or less than 40 nm; equal to or less than 50 nm; equal to or less than 60 nm; equal to or less than 70 nm; equal to or less than 80 nm; equal to or less than 90 nm; equal to or less than 100 nm; equal to or less than 110 nm; equal to or less than 120 nm; or equal to or less than 130 nm, dependent upon the setting of the process parameters 102. It is recognized that the thickness of the BHJ silicon layer 23 can be such as but not limited to: equal to or less than 100 nm; equal to or less than 150 nm; equal to or less than 200 nm; equal to or less than 300 nm; equal to or less than 500 nm; equal to or less than 750 nm; equal to or less than 1000 nm; equal to or less than 1250 nm; equal to or less than 1500 nm, dependent upon the setting of the process parameters 102.

Further, it is recognised that the process temperature of the process parameters 102 for facilitating propagation of the crystal structure of the substrate 22 into the atomic structure of the doped layer 23 can be temperatures such as but not limited to: between 150 and 475 centigrade; between 150 and 450 centigrade; between 150 and 425 centigrade; between 150 and 400 centigrade; between 150 and 375 centigrade; between 150 and 350 centigrade; between 150 and 325 centigrade; between 150 and 300 centigrade; between 150 and 275 centigrade; between 150 and 250 centigrade; between 150 and 225 centigrade; or between 150 and 200 centigrade. Further, the process pressure can be specified in the range of 150 mTorr to 1.1 Torr, the plasma RF power can be specified in the range of 5 mW/cm² to 75 mW/cm², the hydrogen dilution level HD can be specified in the range of 80 percent to 99 percent or specified in the range of 85 percent to 95 percent. It is recognized that any combination (or single one thereof) of the control parameters 102 can be used to control the growth rate of the doped silicon layer 23, for example based on the hydrogen dilution level HD. Further, the gas flow rates and the RF power density can both be varied within the aforementioned process windows during the deposition of the layer 23.

In one embodiment, for a process temperature of 300 centigrade, the RF power density of 47 mW/cm² and the process pressure of 400 mTorr can be used with HD values of 80,85,90,95 percent to facilitate propagation of the crystal structure of the substrate 22 into the atomic structure of the highly doped silicon (doped emitter) layer 23. Figure 6 shows the measured conductivity 160 of Si thin films developed with different hydrogen dilution (HD) values 165. Two different regimes, an amorphous phase 170 and a high crystal quality epitaxial phase 175, can be identified. A transitional region 172 separates these two regimes 170, 175. The films deposited with HD<80% show low conductivity, about 0.008 Q 'cm^"1, comparable to the conductivity of n-type amorphous Si films. The films grown with HD>85% show very high film conductivities about 680 Q^cm^"1, comparable to the conductivity of the highly doped high temperature HT diffused crystalline Si emitters. A somewhat rapid change from low to high conductivity occurs in the HD window of 78%<HD<89% (e.g. transitional region 172). Along with other process parameters 102, HD can play a significant role in the growth mechanism of the doped Si layers 23. The conductivity of the doped layers 23 can be varied over 5 orders of magnitude with varying HD, where highest conductivity values were obtained for HD values larger than 90%. The doped layers 23 belong to the high HD regime. By varying the RF power density and process pressure and keeping the high HD constant it is possible to increase the conductivity of the as deposited doped layers 23 even further. It is possible to obtain very high conductivity exceeding 2000 Q 'cm^"1 by optimizing the RF power density and process pressure for a HD setting of approximately 90%. Also shown in Figure 6, the effect of a rapid thermal anneal 180 as one of the process control parameters 102 on the conductivity of the PECVD (n⁺) doped layers 23, deposited at low temperature. Based on this experiment all of the doped emitter layers 23, irrespective of HD, the majority of the doped emitter layers 23 show very high conductivities after a short time anneal time (e.g. less than 1 to 2 minutes) at a medium anneal temperature between 700 and 800°C (e.g. 750°C). This shows that solid phase (re)crystallization of the doped layers 23 has happened due to the anneal process. The conductivity of the as- deposited doped layers 23 that were initially amorphous improved by more than 5 orders of magnitude after the high temperature anneal 180, whereas only a small improvement (few times) in conductivity of the doped layers 23 which were initially epitaxial was brought about by the high temperature anneal 180. Computer Device 101 Referring to Figure 13, the computing device 101 of the environment 100 (see Figure 4) can include a connection interface 200 coupled via connection 218 to a device infrastructure 204. The connection interface 200 is connectable to the hardware systems of the chamber 104 as is known in the art, which enables the devices 101 to control the fabrication process 200 (see Figure 15), as appropriate.

Referring again to Figure 13, the device 101 can also have a user interface 202, coupled to the device infrastructure 204 by connection 222, to interact with a user (e.g. chamber 104 operator - not shown). The user interface 202 can include one or more user input devices such as but not limited to a QWERTY keyboard, a keypad, a stylus, a mouse, a microphone and the user output device such as an LCD screen display and/or a speaker. If the screen is touch sensitive, then the display can also be used as the user input device as controlled by the device infrastructure 204.

Referring again to Figure 13, operation of the device 101 is facilitated by the device infrastructure 204. The device infrastructure 204 includes one or more computer processors 208 and can include an associated memory 210 (e.g. a random access memory). The computer processor 208 facilitates performance of the device 101 configured for the intended task associated with fabrication of the layer 23 via the hardware of the chamber 104 (as is known in the art) through operation of the network interface 200, the user interface 202 and other application programs/hardware 207 of the device 101 by executing task related instructions. These task related instructions, including specification of the process control parameters 102 can be provided by an operating system, and/or software applications 207 located in the memory 102, and/or by operability that is configured into the electronic/digital circuitry of the processors) 208 designed to perform the specific task(s). Further, it is recognized that the device infrastructure 204 can include a computer readable storage medium 212 coupled to the processor 208 for providing instructions to the processor 208 and/or to load/update the instructions 207. The computer readable medium 212 can include hardware and/or software such as, by way of example only, magnetic disks, magnetic tape, optically readable medium such as CD/DVD ROMS, and memory cards. In each case, the computer readable medium 212 may take the form of a small disk, floppy diskette, cassette, hard disk drive, solid-state memory card, or RAM provided in the memory module 102. It should be noted that the above listed example computer readable mediums 212 can be used either alone or in combination.

Further, it is recognized that the computing device 101 can include the executable applications 207 comprising code or machine readable instructions for implementing predetermined functions/operations including those of an operating system and specification of the control process parameters 102, as well as any feedback sensors (not shown) for communicating (via the interface 202) the state of the fabrication process 200 performed through the chamber 104, for example. The processor 208 as used herein is a configured device and/or set of machine-readable instructions for performing operations as described by example above. As used herein, the processor 208 may comprise any one or combination of, hardware, firmware, and/or software. The processor 208 acts upon information by manipulating, analyzing, modifying, converting or transmitting information for use by an executable procedure or an information device, and/or by routing the information with respect to an output device. The processor 208 may use or comprise the capabilities of a controller or microprocessor, for example. Accordingly, any of the functionality of the chamber 104 and the associated process control parameters 102 may be implemented in hardware, software or a combination of both. Accordingly, the use of a processor 208 as a device and/or as a set of machine-readable instructions is hereafter referred to generically as a processor/module for sake of simplicity. Further, it is recognised that the environment 100 can include one or more of the computing devices 101 (comprising hardware and/or software) for implementing, as desired.

Differences between the Controlled Epitaxial or Mixed-phase BHJ layer 23 and Other Thin Films

The environment 100 described above leads to controllable growth of layer 23 with desired phase, crystallinity, and doping profile. In general, the layer 23 can be a single epitaxial layer 231 with certain doping density, multiple epitaxial layers with certain doping profile 232, a double highly doped epitaxial layers of opposite types 233, mixed epitaxial/amorphous phase in BHJ form 234, and multiple layers of epitaxial and amorphous layers 235 where epitaxial layers locate at the bottom and amorphous layers locate at the top of the stack. Growth of the single epitaxial layer 231 is somewhat different than that of the BHJ layer 23. Growing epitaxial layer 23 requires rather high HD values. Under such a condition a high quality epitaxial Si film start to grow on the surface of the substrate 22. As the layer 231 thickness increases, however, the crystal quality of the epitaxial phase starts to decrease gradually. Since the layers 231 growth was performed at low temperature (e.g. at around 200-350°C), it may not be feasible to maintain the crystal structure propagation (e.g. epitaxial growth) throughout, i.e. beyond hundreds of nm of layer 231 thickness using steady (time-invariant) process conditions. Observed and measured is a very gradual transition from the epitaxial phase (in the regions 150-see Figure 12b) tending towards a nano-crystalline phase (in the regions 152) with little to no defined boundaries between the material phases. It is recognised that for device 21 applications requiring smaller film thicknesses (e.g. less that lOOnm), the crystalline phase of the doped emitter layer 23 may never reach the tendency towards the nano- crystalline phase, and therefore can function as a device component with high crystallinity. However, to increase the propagation thickness of the crystal phase (epitaxy), the process conditions, e.g. HD and RF power, can be dynamically controlled during the film growth period to increase crystal phase content at higher thicknesses.

For growing multiple exiptaxial Si layers 232 having certain doping profile, an epitaxial Si layer with certain doping density is grown. Then the second and the third etc. epitaxial layers with certain doping density are grown on top of each other to achieve a highly crystalline Si layer of certain doping profile. In this method, every next epitaxial Si layers inherits its crystallinity from the previously grown epitaxial Si films. To achieve multiple layers of highly crystalline epitaxial Si films with certain doping density, the hydrogen dilution and possibly the RF power density must be gradually increased during growth of the films (as the process goes on).

To grow a double highly doped epitaxial layer of opposite types 233, a highly doped n⁺ or p⁺ epitaxial Si layer is grown first and then another highly doped p⁺ or n⁺ epitaxial Si layer using the previous layer as the seed layer. Such a junction can be used as a tunnel junction in the structure of tandem solar cells (see Figure 9e and Figure lOe). Similar to layers 232, higher HD ratio is required for growth of the top highly doped epitaxial Si layer because the crystallinity tend to degrade far from the crystalline Si substrate.

For growing BHJ layer 234, the HD values should be high at the beginning of the growth to form a seed epitaxial layer first, then should be lowered to form finite size amorphous islands at the surface of the film, and then should be increased to prevent amorphization outgrow the epitaxial phase. The amorphized parts of the surface impede the further growth of epitaxial Si layer on that portion of the film. Therefore, a mixed phase amorphous/epitaxial Si (bulk amorphous/crystalline heterojunction so called bulk heterojunction Si (BHJ)) film is obtained within the bulk of the growing material. It is recognized that the dynamic control of HD and RF power density during the growth is the key to achieve controllable BHJ layers 234 with different ratios of amorphous to crystalline phases. Controlled BHJ Si layers are used in the structure of Si based BHJ solar cells (see Figure 9f and Figure lOf).

For growing multiple layers of epitaxial and amorphous Si films layer 235 epitaxial Si films must be grown initially and then amorphous Si layer must be grown on top of the epitaxial Si films. Such combination of the layers can be used for making amorphous-crystalline Si tandem solar cells (see Figure 9e and Figure lOe).

In view of the below, layer 23 differs from both highly doped high temperature conventional films (obtained by diffusion, ion implantation, and LPCVD) and from prior art low temperature CVD films (amorphous silicon and micro/nano crystalline).

Process Temperature

High quality highly conductive c-Si thin films is obtained using high temperature processes (T>900°C) such as diffusion of dopants at high temperature, ion implantation and a subsequent thermal anneal and epitaxy of Si thin films by low pressure CVD technique at high temperature. On the contrary, layers 23 are obtained at much lower temperature (e.g. T<300°C) and result in quality of crystalline phase comparable to those grown at high temperatures.

The temperature window at which the layers 23 are obtained (e.g. 200°C<T<300°C) is comparable to the temperature window that traditional doped or undoped micro (or nano) crystalline Si thin films can be deposited (100°C<T<350°C). However, the electrical and structural properties of the layers 23 are completely different from the structural and electrical properties of micro(or nano) crystalline Si films due to help from specification of the process control parameters 102 as described above by example.

Doping Profile and Doping Mechanism:

The doping profile and the structure of the layers 23 material is different than the structure of materials obtained by diffusion, ion implantation, LPCVD techniques at high temperatures and micro(nano) crystalline Si and amorphous Si films at low temperatures, as the doping profile of the doped emitter layers 23 can potentially be almost uniform throughout the thickness of the film. This is compared to the doping profile obtained by both diffusion and ion implantation, which is non-uniform by nature (normally Gaussian distribution). A further difference is that extremely abrupt n⁺n, p⁺p, n⁺i, p⁺i, n⁺p, p⁺n, n⁺p⁺, np, and pn junctions can be achieved using layers 23. Although it is possible to grow highly doped high temperature LPCVD c-Si films having uniform doping distributions, it is not possible to obtain very abrupt junctions between the resultant substrate and thin film silicon materials because dopants of the high temperature process tend to diffuse at high temperature and the final distribution of the dopants is different than the grown distribution of dopants. Further, the doping mechanism and profile in the doped layers 23 is quite different than what is observed in doped amorphous Si and micro(nano) crystalline Si materials. For example, in doped amorphous Si films most of the dopant atoms (about 99%) form 3 fold covalent bonds rather than 4 fold covalent bonds and therefore the doping efficiency in doped amorphous Si films is always very low. The dopants in micro( or nano) crystalline Si films form mainly 3-fold covalent bonds in amorphous tissues and a combination of 3-fold and 4-fold covalent bonds in the crystallites. Therefore, the doping efficiency is not high in these micro( or nano)crystalline Si films. In the epitaxial phase of the doped layers 23, however, because of very high crystallinity, the major portion of dopants in the layer 23 form 4-fold covalent bonds and can result in close to 100% doping efficiency, similar to those obtained at high temperatures. The combination of highly abrupt junctions with close to 100% doping efficiency makes the layers 23, different than the layers obtained by conventional processing techniques.

Junction The junction obtained between the doped layer 23 and lowly doped Si substrate 22 is different than the junctions obtained between doped Si films obtained by diffusion and ion implantation. For example, in the high temperature diffusion and ion implantation processes, the dopants are forced into an existing perfect crystal substrate 22 due to diffusion as a function of the high temperatures. Therefore, the metallurgical junction formed in high temperature is located inside the crystalline substrate, well below the initial substrate surface. This is also partially true for doped LPCVD c-Si films grown on lowly doped Si substrate, because dopants tend to diffuse at high temperature and form the interface inside the existing crystalline substrate. On the contrary, in the doped layer 23, however, the doped interface (e.g. pn junction) between the doped emitter layer 23 and the substrate 22 is obtained right at the original external surface 114 of the Si substrate 22 (e.g. prior to growth of the doped emitter layer 23). Accordingly, it can be considered that there is almost no dopant diffusion into the substrate 22 during the growth of the doped emitter layer 23, due to the inhibition of diffusion as a result of the low process temperature (e.g. less that 300C). Accordingly, this results in a sudden or step change in the dopant distribution across the original external surface 114 location, what can be considered the border between the substrate 22 Si material and the doped layer 23 Si material.

The double highly doped epitaxial layer of opposite types layers 233 is a very low resistance tunnel junction which can be compared to those tunnel junctions obtained at high temperatures. The abruptness of the junction as well as the high doping efficiency in the epitaxial phase makes this junction a perfect candidate for tunnel junction application. Compared to tunnel junction made by conventional micro(nano) crystalline Si thin films, the the tunnel junction made by layer 235 can have significantly lower junction resistance at low applied bias regime. Further the junction between amorphous and crystalline phases in BHJ Si layer 235, has a bulk heterojunction structure which is a new phase of Si material. Such junctions can neither be obtained by high temperature diffusion, implantation, and LPCVD techniques nor they can be obtained by conventional low temperature growth processes for amorphous and micro(nano) crystalline Si thin films.

Crystal Structure

The crystal structure of the layer 231 is different than the crystal structure of Si films obtained at high temperature. Crystallinity of the films obtained by diffusion and ion implantation is extremely high, very close to 100%, because dopants are forced into the existing crystalline lattice. Crystallinity of the films obtained by LPCVD is also very high because at high temperatures (about 900C) pure epitaxy is possible and the crystallinity of the film can be as high as the crystallinity of the c-Si substrate. On the contrary, the crystal structure of the epitaxial phase of layer 231 is not exactly comparable to the crystallinity of the substrate 22. Because of the low temperature nature of the process the epitaxial layer 231 has the best crystallinity in the regions 150 (see Figure 12b) near the surface of the substrate 114 but the crystallinity of the layer gradually decreases with increasing thickness of the film. Nevertheless, the degree of inherited crystallinity of the layer 231 is high enough to result in desired degree of doping efficiency and desired degree of free carrier mobility. Further, the long range order and the crystallinity of the layer 231 is much better than long range order and the crystallinity of micro (or nano) crystalline Si films. As pictured in Figure 12a, 12b, and 12c, layers 231 have a very well defined crystal structure that is inherited from the crystalline substrate 22. The atomic arrangement is very similar to the atomic arrangement of the substrate 22 at the interface 114 and close to the interface regions 150 but far from the interface 114 the atomic arrangement is gradually distorted (i.e. in the regions 152). Rather than sharp grain boundaries observed in micro (or nano) crystalline Si films, we observe very slowly varying crystal planes. This can explain an order of magnitude difference in the mobility of the free carriers in micro (or nano) crystalline Si films and epitaxial layers 23. The mixed phase epitaxial/amorphous Si layer 234 has a unique characteristic where highly crystalline nanowires of Si, formed due to epitaxial phase growth, are surrounded by amorphous Si phase. Figure 16a shows this mixed epitaxial/amorphous structure. The nanowires formed within the film are vertically aligned and they connect the crystalline substrate to the top surface of the film. As a result, a very large surface area amorphous/crystalline heterojunction is formed within the bulk of the film. Figure 16b is a HRTEM picture of region "aa" marked in Figure 16a, where epiaxial and amorphous phases are clearly shown. This structure is totally different than known crystal phases reported for Si material. For example, high temperature processes yield to fully crystalline material where the formation of the amorphous phase is not possible. At low temperatures however, film growth using conventional PECVD techniques yield to formation of amorphous, micro (nano) crystalline or micromorph Si films. Crystal structure of none of the aforementioned conventional materials is similar to the crystal structure of layer 234.

Another aspect of the epitaxial layer 231 growth on a crystalline Si substrate 22 is its independence from the crystal orientation of the substrate. This means that layers 23 can be grown on multicrystalline Si substrate, which comprises large size crystallites with random crystal orientations. Therefore, the fabrication 200 process is applicable on mc-Si substrates, as well as CZ and FZ crystalline silicon substrates. Figure 12c shows the HRTEM picture of a doped layer 231 at the vicinity of a grain boundary (GB) region 42 of a (p) mc-Si substrate 22. The crystal orientations on different sides of the GB are different. The HRTEM picture 30 shows that the atomic arrangement in the doped emitter layer 23 follows the atomic arrangement of the mc-Si substrate 22 in both sides of the GB. This suggests that the epitaxial growth of the initial layer 23 is independent of the crystal orientation of the substrate 22. Further analyses showed that the developed doped layer 23 have very good crystallinity. Electrical Properties

The carrier mobility of the epitaxial phase of layer 23 (231) can be very high. This proves that despite the low temperature nature of the fabrication process 200 (see Figure 15) of the environment 100, the near-perfect long range order of the epitaxial phase of layer 231 leads to free carrier mobility close to those of single crystalline material. In case of doped epitaxial layer 231 , the conductivity of the film can be extremely high; as shown in Figure 6 and followup experiments, conductivity values of the as-deposited highly doped epitaxial layer 23 can reach close and even above 1000 Q^cm^"1. Again, the near- perfect crystal arrangement leads to both high free carrier mobility and very high doping efficiency, hence very high conductivity values for highly doped epitaxial Si layers 231. The conductivity of the doped silicon layer 231 is comparable to the conductivity of highly doped Si materials obtained by high temperature diffusion, ion implantation or LPCVD. But it must be noted that the doped silicon layer 23 are obtained by about 600 C less in temperature than its high temperature counterparts.

Let's compare the conductivity of the doped silicon layer 23 with the conductivity of highly doped amorphous silicon and micro (or nano) crystalline Si films that are obtained at low temperatures using PECVD or HWCVD techniques. The conductivity of the doped silicon layers 23 is about 5 orders of magnitude more than highly doped a-Si films and one to two orders of magnitude more than the conductivity of the doped micro (nano) crystalline Si thin films. Referring to Figure 7a, shown is the UV Raman spectra 190 of the as-deposited (low temperature 300°C) doped PECVD doped silicon layer 23 formed under various hydrogen dilutions (HD). Raman peaks corresponding to crystalline structure are obvious in the doped silicon layer 23 with high HD (>85%). Figure 7b shows the UV Raman spectra 190 of the doped silicon layers 23 that underwent a high temperature (750°C) annealing after the CVD deposition. After the high temperature annealing, the peaks correspond to crystalline Si appears irrespective of HD. Accordingly, Figures 7a and 7b show the UV Raman spectra 190 of the silicon doped silicon layers 23. The Raman measurements were performed at very short wavelengths (328nm). Because of the small penetration depth of the UV signal in silicon (<10 nm) the measured signal originates from the surface region of the doped silicon layers 23. The experiment showed that the doped silicon layers 23 deposited under low HD conditions did not show any Raman peak at 520 cm^"1 while the doped silicon layers 23 grown with HD values more than 85% showed a Raman peak at 520 cm^"1. This further conforms the epitaxial growth of the low-temperature doped silicon layers 23 using relatively high HD (>85%) and noncrystalline doped silicon layers 23 growth using low HD (<80%). This result is completely inline with the results obtained from the electrical conductivity measurements of Figure 6. Figure 7b shows the UV Raman spectra 190 of the doped silicon layers 23 after subjecting them to a high temperature (750°C) annealing following the PECVD deposition. The Raman peak at 520 cm^"' is observed for all of the samples irrespective of the HD during the PECVD deposition. This shows that the high temperature anneal caused a solid phase recrystallization in all the doped silicon layers 23. This result also supports the results of the conductivity measurement of Figure 6.

Accordingly, the high crystal quality of the doped silicon layers 23 makes their optical absorption properties close to that of crystalline silicon. Therefore while deploying the doped silicon layers 23 on c-Si substrates 22 for device applications, there could be much less restrictions on the maximum thickness of the doped silicon layers 23 from an optical point of view (whereas, amorphous and noncrystalline Si films need to be limited in thickness to reduce optical absorption in the emitter layer). This flexibility in doped silicon layers 23 thickness can enhance the chances of employing low-cost metallization techniques such as screenprinting in the case of doped silicon layers 23.

Referring to Figure 8a, a good quality junction between an n⁺ doped silicon layer 23 and the (p)c-Si substrate 22 is obtained. Such junctions can result in high efficiency solar cells (e.g. silicon device 21); which largely depend upon high quality of the n⁺p or p⁺n junctions to collect photogenerated carriers in the absorber layer (substrate in device 21). Figure 8a shows a dark current- voltage-temperature (I-V-T) characteristics 192 of a 16 mm² (n⁺)-Si/(p)c-Si diode having Al contacts on both sides of the diode. The I-V characteristic of the solar cell 21 can be modeled by double diode model where diode- 1 models the medium forward bias regime and diode-2 models the low forward bias regime. The first diode saturation current density at room temperature (300K) is 7.1 pA/cm² (extracted from Figure 8a). Saturation currents 194 of the first and the second diodes, Ioi and Io₂, are shown in Figure 8b in logarithmic scale versus 1000/T. The activation energies (EA) of the I₀i and ½ were calculated from the slope of the I₀ versus 1000/T curves of Figure 8b and E_A values of 1.16eV and 0.59eV were obtained respectively for the first and second diodes. The activation energy of 1.16eV, very close to the band gap of crystalline Si (1.12eV), in the medium forward bias region indicates that the diffusion in quasi-neutral region is the main current transport mechanism in this regime. However, the activation energy of 0.59eV, very close to the half of the c-Si band gap (0.56 eV), in the low forward bias regime indicates that the recombination in the space charge region and interface is the main current transport mechanism in this regime. Meanwhile, the average ideality factor of 1.84 in this regime shows that the energy levels of the active defects (in the space charge region and in the interface) are distributed inside the band gap of the c-Si substrate 22. The current-voltage-temperature measurement of the diode shows that the effect of the interface can be neglected for solar cell 21 applications because solar cells 21 work normally in medium forward bias (0.4<V<0.6) conditions. This means the interface between the n⁺ Si epitaxial layer 23 and the (p) mc-Si substrate 22 is photo voltaically clean and can be employed for fabrication of solar cells 21, without any additional interfacial passivation layers.

Controllability of the crystal structure and doping profile in the Si layer 23

The doping density, conductivity, and crystal structure of the Si layer 23 films can be controlled in a very wide range. Using Silane gas as the precursor for Si, phosphine (diborane) gas as the precursure for phosphorous (boron), and hydrogen as carrier gas in a PECVD chamber, described in Figure 4, and using appropriate process conditions it is possible to achieve a high level of control on doping density and hence the conductivity of the epitaxial Si layer 23. Figure 17 shows a high resolution Spreading Resistance Profile (SRP) of a film prepared in single deposition run, where the phosphin gas flow rate was switched between a high and low rates over time for multiple periods. Note that the y-axis shows the free carrier concentration (not the dopant concentration) in the film as function of depth of the film (x-axis). Several important conclusions can be made from this experiment: 1) free electron concentration in the Si film was varied in the range of 5xl0¹⁷ cm^"3 and 2xl0²⁰ cm^"3 by only varying PH₃ flow rate in the deposition chamber. Such a high dynamic range (about three orders of magnitude) achieved for free electron concentration pinpoints to the outstanding controllability of doping process in epitaxial Si layer 232 and the capability of the material processing method in this work. 2) Figure 17 shows that repeatable free carrier concentrations have been periodically achieved for a film by periodically varying PH₃ flow rate during deposition. This proves that the epitaxial nature of the film propagates throughout the deposition thickness (175 nm in this case) irrespective of the level of amount of PH₃ gas entered to the system. This means that significant change in the doping gas flow rate, change in dopant concentration, and change in free carrier concentration do not break the epitaxial nature of the growth. This makes this kind of films an excellent candidate for dopant tailoring and superlattice applications. 3) Figure 17 also shows that very sharp n⁺n junctions and ultra sharp n⁺p junctions have been obtained using with controlled level of active doping concentrations. This proves that Si layer 23 (231 and 232) can be utilized to make ultra sharp pn junctions as well as n⁺n junctions. It should be noted that Figure 17 shows the density of the free carrier concentration versus depth of the as grown epitaxial Si layer 23 not the density of the active dopant atoms. It is expected that the active dopant concentration profile in the film to be sharper than that shown in Figure 17 because the free carrier concentration cannot follow sharper changes than the Debye length of free carriers. This suggests that the junctions obtained in this work can be ultra sharp. 4) The sharp changes in active dopant and free carrier concentration, observed in Figure 17, result in strong local electric fields at the n⁺n interface. Such an electric field formed at the n⁺n epitaxial interfaces can be used for BSF application.

Figure 18 shows the concentration of the high resolution SRP measurement result on a stacked undoped/ n⁺ doped epitaxial Si film grown on top of a p-type crystalline Si substrate. An ultra sharp junction can be identified at the approximate depth of 100 nm. As discussed earlier, SRP shows free carrier density. This result also shows that the epitaxial Si growth has continued up to a thickness of 300 nm (rather far from the epitaxial/crystalline Si interface). This shows the potential of epitaxial layer 231 to grow rather thick, probably up to few micrometers.

Further, the process conditions can be optimized to achieve very high quality epitaxial Si layer 23 / crystalline Si substrate 22 interface. Figure 19 shows the interface 114 between an improved epitaxial Si layer 23 and a c-Si substrate. The figure shows that the crystallographic quality of the epitaxial Si film and its interface with the c-Si substrate is very high. Compared to the film shown in Figure 12(b), this film has a much better crystal quality and much less crystallographic defects at the interface 114. This suggest that the film growth can be controlled to achieve very high quality junctions between the layer 23 and underlying Si substrate 22.

In addition to the having high level of control on growth of epitaxial Si layer 23, the environment 100 provides a high level of control on the growth of mixed phase epitaxial/amorphous layer 23. Figure 16 shows a mixed phase epitaxial/amorphous growth of layer 23. Dynamic control of process conditions including gas flow rates and the RF power density can lead to such a mixed phase material growth. The ratio between the epitaxial and amorphous phases can be controlled by proper selection of process variables and proper variations of the process parameters during the growth. For example, to achieve the material of Figure 16, a high HD value was used to achieve an epitaxial see layer and then it was lowered to form islands of amorphous Si at the surface of the film and then it was increased to continue epitaxial growth on the exposed epitaxial regions. The amorphous islands, however, do not allow epitaxial growth on top of them and hence a mixed phase of epitaxial/amorphous phase is obtained.

Control over doping type, profile, and density and the crystal structure of the layer 23 and the number of deposited layers paves the road for development of variety of junctions n⁺n, p⁺p, n⁺i, p⁺i, n⁺p, p⁺n, n⁺p⁺, np, pn, and also multi-layers of these junction on top of each other. Such structures can be utilized for variety of Si based device applications, as partly described in Figure 9 and 10. For example, n⁺p⁺ junctions can be used as tunnel junctions for development of tandem solar cells which use Si substrate as the bottom cell absorber. Si based n⁺n and p⁺p junctions can be utilized as BSF for solar cells of Figure 10b, where the BSF consists of a bilayer of epitaxial Si based n⁺n or p⁺p junctions. Si BHJ films can be used as the absorber of solar cells made on metallurgical grade multicrystalline Si substrates.

Conclusions

It is recognized that the silicon layer 23 of Figure 4 and related Figures can be used in any electronic device 21 application where high quality pn junction(s) is to be formed under low temperature conditions (e.g. around and below 300C). Further, it is recognized that intrinsic, n-type, and p-type doping can be employed. Further, it is recognized that multiple layers of doped or intrinsic epitaxial Si films can be grown on top of each other inheriting the crystal order from the underlying epitaxial Si layer. Further, it is recognized that mixed phase epitaxial/amorphous Si layer 235 can be achived using the proper process variables. Further, it is an advantage of the silicon layer 23 that high quality junctions between highly doped silicon layers 231 and crystalline silicon substrates 22 can be obtained without use of ultra thin, intrinsic buffer layers as has been used in some hetero-junction cell processes. Further, the thickness of the doped silicon layer 23 can be in a wide range from a few nanometer up to few microns. The high crystallinity (close to crystalline silicon) of the doped silicon layer 23 may not impose an upper limit on the doped silicon layer 23 thickness on the basis of optical absorption. Further, it is recognized that thicker doped silicon layers 23 can also make the use of cost- effective metallization schemes such as screen-printing. A potential advantage of the doped silicon layer 23 is that a very simple solar cell device 21 can be fabricated at low temperature without use of the TCO layer. Further, the low temperature process used in the chamber 104 of a CVD apparatus, an example of which is PE. Furthermore, the low temperature nature of the fabrication process 200 can make it ideally suitable for defective (low cost) substrate 22 too. The crystal defects in the substrates 22 can require defect passivation by hydrogen for the low temperature environment 100, where it is recognised that high process temperatures lead to hydrogen out-diffusion thereby losing the passivation effect. In the solar cells fabricated by the fabrication method 200, the doped silicon layer 23 - Si substrate 22 interface can provide a high quality pn junction inhibiting the need for additional interfacial (intrinsic) passivation layers, while the highly conductive nature of the doped silicon layer 23 can inhibit the need for the use of any transparent conductive oxide films.

Further, the process of applying varying recipes Ri sequentially provides for desired quality thin films 23 and pn junctions in a low-temperature process in mind with yield. Ability to impose gradients (both degree as well as location) in film properties during the deposition and the possibility of the subsequent thermal treatment provides for further tailoring of the film 23 properties. High performance photovoltaic and other electronic devices may be possible using the application of varying recipes Ri sequentially, with an added potential benefit of higher throughput obtained in production line yielding high performance devices.

Further, the low temperature nature of the deposition process makes it suitable for defective (low cost) substrates 22 too. The crystal defects in the substrate 22 can require defect passivation by hydrogen (high process temperatures lead to hydrogen out-diffusion thereby loosing the passivation effect). As well, it is noted that the ability to control crystallinity during the deposition, while allowing a desired/predictable pn junction, helps reach higher film deposition rates through reducing the crystallinity in a predefined manner away from the junction region 150. As well, relatively thicker emitters using the deposited films 23 can help prevent shunting of the devices for solar cell metallization processes.

Time-Dependent Control of Process Parameters 102

Referring to Figure 4, there are a number of process control parameters 102 that can be controlled using various predefined recipes Rl, R2, R3, R4, etc. (representing a defined set of process parameters 102 to be imposed via the chamber 104 for a specified period of time), in order to influence in a time controlled fashion the growing conditions (e.g. the growth rate, atomic composition, degree of doping, degree of crystallinity, thickness, etc.) of a growth surface 116 of the emitter layer 23, thus resulting in the presence of predefined gradients in crystallinity, dopant concentration, and/or dopant efficiency, etc. in predefined regions (e.g. layers) of thin film layer 23. It is recognized that through the sequential use of various different recipes Ri for a respective film layer 23, the resulting silicon device 22 can feature a number of different layers 23a,b,c,d,e etc. within the film layer 23, each with their own identifiable film properties (see Figure 4) that are distinctive with respect to one another (e.g. crystallinity, doping concentration and profile, and crystal phase). It is also recognized that application of the different recipe Ri could be used to control optical properties of the surface of the layer 23, so as to optimize energy absorption characteristics of the film 23 material, e.g. provide for a desired optical window (e.g. band-gap engineered based on sequential recipe Ri application) for various wavelengths of incident radiation on the surface of the film 23. Further, the shape of the gradients for crystallinity, dopant concentration, and/or doping efficiency of the film 23 can be controlled by corresponding application of the recipes Ri, in order to provide for desired layer 23 property distributions other than Gaussian distributions that can be obtained by fixed low process temperature over time in the fabrication process.

Accordingly, the fabrication environment 100 can be used via the sequential application of different recipes Ri (each with their own predefined application temporal duration), via a computer device 101 controlled/assisted production process, to provide for low temperature processes for controlling electrical properties of thin films 23 and interfaces 114, obtained by PECVD technique, for example. Surface pretreatment of the substrate (e.g. Si) 22 by hydrogen/helium plasma, and process parameters (e.g. PECVD) such as gas flow rates, RF power density, process pressure can be employed for the growth of the films 23 with controlled (via the application of recipes Ri) gradient/distribution in crystallinity, dopant activation, electrical conductivity, and excess carrier lifetime. The ability to introduce gradients in the film 23 properties and parameters facilitates the realization of electronic/photo-electric devices 21 with different predefined doping profiles. Further, time-dependent control over the process variables such as gas flow rates and RF power density enables the fabrication environment 100 to grow mixed phase epitaxial/amorphous BHJ Si films.

Operation of the Deposition Environment 100 Referring to Figure 14, the silicon layers 23 of the silicon devices 21 can be prepared by CVD (e.g. PE, HW, hot wire) at low temperature (e.g. less than 350 °C). Referring to Figure 4, the substrates 22 can be of different grade qualities as measured using excess carrier lifetime (measured using microwave photoconductivity decay on a Semilab WT-2000 machine). For example, the selected Si material of the silicon substrate 22 can be material such as but not limited to: multi-crystalline silicon; single crystalline silicon; ribbon crystalline silicon; and powder formed silicon. Further, the excess carrier lifetime of the silicon substrate 22 for the respective Si material can be selected from such as but not limited to: less than 1 microsecond; 1 to 10 micro seconds; 10 to 20 micro seconds; 30 to 50 micro seconds; 50 to 70 micro seconds; 70 to 90 micro seconds; 90 to 110 micro seconds; and greater than 110 micro seconds.

Further below, discussed are six fabrication sequences; LT Process I, LT Process II, LT Process III, LT Process IV, LT Process V, and LT Process VI for low cost manufacture of solar cells 21, as a further embodiment of the fabrication process 200 of Figure 15. For example, process I, II, IV, and V could be a suitable fabrication technique for low quality silicon substrates 22 (with excess carrier lifetime in the range of 1 - 10 usee) with thickness of 150 - 200 m. Process III is similar to process 1,11 with only one major difference, a short medium temperature (e.g. about 750°C) rapid thermal annealing step is utilized to (i) form a back surface field structure, and to (ii) improve the conductivity of the doped silicon layer 23. Because of the formation of the back surface field structure, process III is suitable for medium and high quality silicon substrates, for example, (with excess carrier lifetime in the range of 50 - 100 usee. Process VI can be applied on very low quality (with excess carrier lifetime less than 1 microsecond) Si substrate such as multicrystalline metallurgical grade Si. LT Process I to VI, shown in Figure 9a to 9f, are the fabrication processes for fabrication of solar cells of Figure 10a to lOf. Fabrication Process 200

Referring to Figures 14 and 15, shown is the fabrication process 200 using the environment 100 of Figure 4. The fabrication process 200 is a low temperature process for depositing a silicon layer 23 on a silicon substrate 22 of a selected grade, the silicon substrate 22 for functioning either as a see layer and light absorber or only the seed layer and the silicon layer 23 for functioning as any or combination of the doped epitaxial Si layer, n⁺p⁺ tunnel junction, multiple layers of epitaxial and amorphous Si layer, and mixed epitaxial/amorphous Si bulk heteroj unction layer 23. The process 200 has the following steps, optionally a step 202 such that the substrate 22 surface is made suitable for promoting crystalline film growth. Cleaning the substrate 22 by wafer surface treatment by HF, for example can do this, and a fast pump down of the PECVD chamber 104 to high vacuum before deposition inhibits oxide formation on the cleaned substrate 22 surface. Further, pre-deposition of the surface treatment of the substrate 22 by a soft hydrogen plasma in the chamber 104 can be done. It is recognised that preparation of the substrate 22 surface prior to growth of the layer 23 layer can be done external to the environment 100 by a third party cleaner, not shown. A further embodiment of the surface preparation can be such that the crystalline Si substrates 22 are cleaned using a standard RCA cleaning technique and then go through a short (5 sec) HF dip (2% HF in DI water). The substrates 22 are then blow-dried by nitrogen gas before being loaded in the chamber 104. After getting proper base pressure (e.g. 1-2 x 10^"6 Torr) for film deposition, a very short (e.g. 2 min) and soft hydrogen (about 5mW/cm²) plasma treatment is performed on the substrate 22 surface.

Next, a step 204 the silicon substrate 22 is positioned in the chamber 104 suitable for chemical vapour deposition of the doped silicon layer 23 on the silicon substrate 22. Next, at step 206, a plurality of process parameters 102 are specified for adjusting growth of the doped silicon layer 23, such that the plurality of process parameters 102 includes at least a first process parameter of a process temperature between 190 and 360 centigrade and a second process parameter of a hydrogen dilution level for providing excess hydrogen atoms to affect a layer crystallinity of the atomic structure of the doped silicon layer 23. Other process parameters 102 can include plasma RF power, process pressure, and flow rates of the atoms with respect to the external surface of the substrate 22 in the chamber 104, depending upon the type of CVD process followed.

Next at step 208 the external surface 114 of the silicon substrate 22 is exposed in the chamber 104 to a vapour including silicon and dopant (e.g. P, B), and the hydrogen precursors (see Figure 4), the atoms for use in growing the silicon layer 23. At step 210, the growth of the doped silicon layer 23 is done on the external surface 114 to form an interface between the doped silicon layer 23 and the silicon substrate 22, such that doped silicon layer 23 includes first atomic structural regions having a propagated quality of layer crystallinity from the crystal structure of the substrate 22.

Subsequently, the produced silicon wafer 21 can be used to manufacture a number of different PV or other electronic silicon wafer based devices, examples of which are shown with respect to Figures 9a,b,c,d,e,f and 10a,b,c,d,e,f.

Using the new doped silicon layers 23 and the pn junctions formed with it, three solar cell fabrication process sequences, "LT Process I", "LT Process Π", and "LT Process III", are described. All the fabrication steps in LT-Process I, II, IV, V, and VI are carried out at low temperature (e.g. <300 °C). These sequences can be ideally suitable for low-quality silicon substrates 22 that would otherwise degrade if subjected to even moderately high temperatures (e.g. typical annealing temperatures), and also for defective Si substrates 22 that undergo pre-process hydrogenation for bulk defect passivation. "LT Process III" can be suited for those Si substrates 22 that can stand up to moderately high temperatures (e.g. around 700-800°C), but that would degrade if subjected to very high temperatures (e.g. greater than 900°C). All the process steps in LT Process III are carried out below a temperature of 750°C, for example.

It is recognized that all three processes I,II,III,IV,V, and VI can be suitable for low-cost (low-quality) Si substrates 22 whose material quality would degrade if subjected to multiple high temperature excursions (greater than 850-900°C). However, these processes can also be suited for high quality Si substrates 22 as well (e.g. electronics grade silicon wafers), and can yield high conversion efficiencies. The simplicity and the low-thermal budget nature of the processes can also contribute in cost-reduction. A selected grade of the silicon substrate can be: multi-crystalline silicon; single crystalline silicon; ribbon crystalline silicon; powder formed silicon, and in case of LT Process VI metallurgical grade Si. A quality of the substrate 22 crystal structure of a selected grade for excess carrier lifetime can be chosen such as but not limited to: less than 1 microseconds, 1 to 10 micro seconds; 10 to 20 micro seconds; 30 to 50 micro seconds; 50 to 70 micro seconds; 70 to 90 micro seconds; 90 to 110 micro seconds; and greater than 110 micro seconds, for example. Fabrication Process 300

Referring to Figures 9a and 10a, LT Process I is the basic process sequence 300, where doped silicon layer 23 is deposited onto a c-Si substrate 22 to form the pn junction device 21. This process 300 can be specifically suitable for silicon substrates 22 whose minority carrier diffusion length is small (compared to wafer thickness), for example low- cost Si materials that have high defect densities and the ones that would further degrade when subjected to multiple high temperature excursions. The low temperature nature (e.g. <360°C) of LT Process I also provides for an optional pre-process hydrogen defect passivation to be applied to the wafers 22. When the minority carrier diffusion length is low the back surface field won't be of much help, and hence the process is kept short and simple. The high conductivity of the doped silicon layer 23 helps to eliminate the need for TCO, and the highly crystalline nature of the doped silicon layer 23 provides a suitable abrupt pn junction.

Figure 9a illustrates the solar cell fabrication sequence 300 for LT Process I. The corresponding schematic of the solar cell device 21 is shown in Figure 10a. The solar cell 21 fabrication starts with standard cleaning 302 of the crystalline silicon substrate (p or n type), 22. The substrate 22 can be single crystalline silicon (CZ-Si or FZ-Si), multicrystalline silicon or silicon ribbon, for example. After standard cleaning 302 process the native oxide of the silicon substrate 22 is etched away by diluted hydrofluoric acid solution (2% HF in DI water). The doped silicon layer 23 (e.g. n+ or p+ type) is then formed 304 on the silicon substrate 22 using PECVD of silane and phosphine ( or diborane in the case of p-type films) in presence of sufficient amount of hydrogen. The process conditions of the parameters 102 (see Figure 4) is such that highly conductive doped silicon layer 23 is obtained. The thickness of the doped silicon layer 23 may vary between 10 nm - 40nm - 100 nm, for example. A front side grid metallization 25 is performed 306 using PVD techniques (sputtering or evaporation). It is noted that the front metallization 25 is formed directly on the doped silicon layer 23. Since the doped silicon layer 23 conductivity is high, there can be no need to employ any transparent conductive oxides (TCO). Antireflective coating layer (or layers) 24 with appropriate thickness is (are) deposited 310 using PECVD of silane, ammonia, and/or nitrous oxide as gas phase precursors at low temperature (about 250°C). Before deposition 308 of backside Al contact 26, a very short (1-2 sec) diluted HF (1%) dip process followed by a dip in 30 sec DI water can be conducted to remove native oxide in the backside of the wafer 22. The backside Al layer 26 with sufficient thickness (2-3 um) is deposited 308 on the backside of the solar cell 21 using a PVD technique, for example. To achieve highest level of simplicity, no back surface field structure has been utilized in LT Process I. Basically there can be no need for BSF structure if a low quality Si substrate is used. The minority carrier diffusion length for low quality materials is often less than 200 μιη, a typical value for the substrate thickness. This suggests that the use of BSF structure may not be necessary because the effective excess carrier lifetime is mainly dominated by the bulk of the Si substrate 22 rather than the back surface.

Fabrication Process 320

Referring to Figures 9b and 10b, with LT Process II, high quality Si substrates 22, thinner substrates 22 (diffusion length » wafer thickeness), or those substrates 22 with their carrier lifetimes increased by hydrogen passivation can yield to solar cells 21 with high conversion efficiencies. This fabrication process 320 uses the doped silicon layer 23 for the formation of both the emitter 23 (n⁺p or p⁺n) and BSF 27 (p+p or n+n). Both front 25 and rear 28 metallizations can be formed directly on top of the doped silicon layers 23, 27. The process 320 is entirely a at low temperature (e.g. <360°C).

Referring again to Figures 9b and 10b, when the low cost (or defective) substrate 22 quality can be improved by pre-process defect passivation techniques such as hydrogenation, or when thinner wafers (<150 um) are used, then the need for a BSF 28 can become useful while the stringent requirement for low-temperature process still holds. The LT Process II can be suited for such cases. Figure 9b illustrates the fabrication steps 320 involved in the LT Process II. The corresponding solar cell device 27 is schematically represented in Figure 10b. The only difference in LT Process II is that, following the deposition of the doped emitter 23 (n+ or p+ type) another qEPiDope Si film (p+ or n+ type) 27 is deposited 326 on the back side of the substrate 22 to function as BSF. A rear aluminum contact 28 is deposited 312 directly on the doped Si BSF layer 27. The LT Process II can provide high conversion efficiencies for either high lifetime wafers, or defect passivated wafers, or thinner wafers, while keeping all the process steps low temperature.

Fabrication Process 400

Referring to Figures 9c and 10c, the LT Process III 400 is shown where in addition to the doped Si emitter 23, a short time (e.g. < 1-2 minutes), medium temperature (e.g. 700-750-800°C) thermal anneal 408 is employed to cause a solid phase recrystallization of the emitter 23 and to form an aluminum alloyed BSF 31 simultaneously. In this process the low temperature formation of the thin film emitter 23 has a wider process window of variations, i.e., the film 23 growth rate can be increased at the expense of film 23 crystallinity. The subsequent thermal anneal step 408 can improve the crystallinity and electrical conductivity in the emitter 23. With the Al-alloyed BSF process 408, a separate boron doped p+ BSF film may not be necessary. Further, since the Al film 31 that is deposited on the rear surface of the device 29 prior to the short thermal anneal 408 is thick enough (3-5 um), there may be no need for another metal deposition process for rear contact. The LT Process III 400 is illustrated in Figure 9c, and, compared to LT Process I, it involves a very short (< 1-2 minute), medium temperature thermal anneal 408 in order to simultaneously (i) form the BSF, and (ii) to improve the crystal quality and conductivity of the emitter 23. The process 400 therefore is still a low thermal budget process. It provides a simple alternative for substrates that require a BSF and that do not degrade after medium temperature thermal anneal. The resulting device structure 29 from LT Process III is schematically represented in Figure 10c. In this process 400, the low temperature PECVD Si emitter (n+ type) 23 is deposited 304 on to the p-type c-Si substrate 22 followed by deposition 406 of a 3-5 um aluminum film 31 on the rear side of the wafer 22. The wafer 22 then undergoes 408 a short time (< 1 minute) rapid thermal anneal at 750°C. In this process, an Al-alloyed p+ BSF is formed, and, at the same time the crystallinity and conductivity of the emitter 23 are improved. As has been evidenced by the conductivity (Figure 6) and Raman (Figure 7b) measurements, the short-time, medium temperature anneal can improve the conductivity and crystal quality of the emitter 23, irrespective of the HD. It should be noted here that the doped silicon layers 23 that already have a high crystal quality and electrical conductivity may not need an improvement by the medium temperature anneal. However, in order to achieve as- deposited (unannealed) doped silicon layers 23, certain conditions such as HD and appropriate process parameters 102 should be followed. The LT Process III offers a wider window for process variations, so that even a sub-quality doped silicon layers 23 can be improved by the process 400. Further, the film growth rate is somewhat slowed down by increased HD. Therefore, in cases where having a high growth rate is useful, one can reduce the HD and still improve the film quality by using LT Process III for suitable substrates 22 of sufficient quality. Also, since the rear metal 31 is a relatively thick Al (3 - 5 um) film, after the thermal anneal part of the Al is consumed in the formation of alloyed p+ BSF, the remaining metal will act as rear metal contact 31, thereby helping to eliminate the need for metal contact formation for a second time. The aluminum BSF step replaces boron BSF, i.e. eliminate the (p+) Si BSF step compared to the LT Process II. The front metal 25, and the antireflection layer 24 can be employed similar to LT Process I.

Fabrication Process 500 Referring to Figures 9d and lOd, with LT Process IV, a bilayer of n⁺n or p⁺p epitaxial Si layers 23 is grown on a p- or n-type crystalline or multicrystalline Si substrate. In this kind of solar cell, Figure lOd, a very high quality PV junction forms between the doped n-type or p-type epitaxial Si layer and p-type or n-type underlying crystalline substrate, whereas in the Processes I to III , the PV junction forms between highly doped n⁺ or p⁺ epitaxial Si layer and underlying crystalline substrate. The use of np or pn junction instead of n⁺p or p⁺n junction can potentially improve the open circuit voltage of the solar cell because bandgap narrowing is not present in the active PV junction. This kind of solar cell is more suitable for moderate or rather high quality Si substrate therefore an epitaxial back surface field layer is used. The n⁺ or p⁺ top layer replaces the TCO layer in conventional low temperature Si solar cells. Fabrication Process 600

Figure lOe, with the fabrication process of Figure 9e, shows the structure of a Si based tandem solar cell utilizing a crystalline Si bottom cell and an amorphous Si based top cell, where the bottom cell absorbs part of red and near-infrared light and the top cell absorbs visible light and part of ultraviolet light. A p⁺ epitaxial Si layer forms the bottom PV junction with the underlying n-type crystalline Si substrate. The n⁺p⁺ junction, which is formed between the two epitaxially grown layers, form the tunnel junction between the bottom and the top solar cells. The top cell is a conventional amorphous Si pin diode comprising p, i, and n amorphous Si layers deposited on top of the n⁺ epitaxial Si emitter. Such a solar cell can be fabricated on rather low quality Si substrate, with excess carrier lifetime in the range of 5 to 20 microseconds, and can result in very high efficiencies, more than 20% in an ideal case.

Fabrication Process 700

Figure lOf, with the fabrication process of Figure 9f, shows the structure of a Si based bulk heterojunction solar cell. The solar cell has a pin structure, where an intrinsic amorphous Si/epitaxial Si heterojunction is used as the absorber layer. This kind of solar cell can be made on ultra-low quality Si substrate such as multicrystalline metallurgical grade Si substrate. The advantage of this solar cell over the conventional amorphous Si pin solar cell is that the bulk heterojunction absorber breaks the tradeoff between the absorber thickness (optical absorption) and photogenerated charge collection efficiency. The small diffusion length of photogenerated charge carriers in the absorber layer of amorphous Si solar cells often puts a limit on the thickness of absorber (intrinsic) layer and hence limits the short circuit current of the solar cell. This problem can be eliminated by using bulk heterojunction Si absorber where the photogenerated carriers in the amorphous phase inject into the epitaxial phase and get collected at the n and p layers. Since the mobility and diffusion coefficient of the free carriers in the epitaxial Si phase orders of magnitude larger than those in amorphous silicon phase, the absorber in the Si based BHJ solar cells can be much thicker compared to conventional pin junctions. Other advantage of this kind of solar cell over the conventional amorphous Si pin solar cells are better red and near-infrared absorption (because of the absorption in epitaxial Si phase) and better long term stability (due to reduced built-in electric field).

Claims

WE CLAIM:

1. A continuous deposition process for depositing a doped silicon layer on a silicon substrate of a selected grade; the method comprising the acts of: positioning the silicon substrate in a chamber suitable for chemical vapour deposition of the doped silicon layer on the silicon substrate, an external surface of the silicon substrate suitable for promoting crystalline film growth; accessing a plurality of recipes, each of the recipes having a defined combination of different control process parameters, the process parameters for adjusting deposition conditions of the doped silicon layer; exposing the external surface of the silicon substrate in the chamber to a vapor at appropriate ambient chemical vapor deposition conditions, the vapour including silicon atoms, dopant atoms and the excess hydrogen atoms, the atoms for use in growing the doped silicon layer; and sequentially applying each of the plurality of recipes for a respective predefined temporal duration in a temporal sequence of the deposition process, each of the plurality of recipes when applied providing a corresponding property gradient in the respective sub-layer of the doped silicon layer.

2. The process of claim 1, wherein the process parameters are selected from the group comprising: a process temperature for inhibiting diffusion of dopant atoms into the external surface of the silicon substrate; a hydrogen dilution level for providing excess hydrogen to affect a layer crystallinity of the atomic structure of the silicon layer; a (steady or time- variant) flow rate of a precursor gas adjacent to the external surface of the doped silicon layer; chamber pressure; and (steady or time-variant) plasma RF power; ; and other suitable process parameters.

3. The process of claim 2, wherein a single layer of doped or intrinsic epitaxial Si layer are grown on a crystalline or multicrystalline Si substrate. 4. The process of claim 3, wherein the single layer doped or intrinsic Si epitaxial Si layer inherits its crystallinity from the underlying crystalline or multicrystalline Si substrate.

5. The process of claim 2, wherein multiple layers of doped or intrinsic epitaxial Si layer are grown on a crystalline or multicrystalline Si substrate.

6. The process of claim 5, wherein the first epitaxial Si layer inherits its crystallinity from the underlying crystalline or multicrystalline Si substrate and any other epitaxial Si layer inherits its crystallinity from the underlying epitaxial Si layer.

7. The process of claim 5, wherein a bilayer of n⁺ /p⁺ or p⁺/n⁺ is formed by successive deposition of doped epitaxial Si films on a crystalline or multicrystalline Si substrate. 8. The process of claim 7, wherein a tunnel junction is formed between n⁺ and p⁺ epitaxial Si layers.

9. The process of claim 5, wherein multiple layers of amorphous Si layers are deposited on top of an epitaxial Si tunnel junction formed by n⁺p⁺ or p⁺n⁺ epitaxial Si junction.

10. The process of claim 9, wherein an amorphous pin tri-layer is deposited on a p⁺n⁺ epitaxial tunnel junction.

11. The process of claim 10, the amorphous Si pin structure forms a solar cell for absorbing visible light and the p⁺n junction formed between the epitaxial Si layer and the substrate form a solar cell for absorbing part of red and infrared light.

12. The process of claim 11, wherein the top amorphous Si cell and the bottom crystalline cell form a Si-based double junction tandem solar cell.

13. The process of claim 2, wherein a very high quality interface between the epitaxial Si film and the underlying crystalline Si substrate is obtained.

15. The process of claim 5, wherein an epitaxial n⁺n or p⁺p bilayer is grown on a p-type or n-type crystalline or multicrystalline Si substrate. 16. The process of claim 15, wherein a solar cell with a structure of n⁺np or p⁺pn is formed.

17. The process of claim 2, wherein a mixed phase epitaxial/amorphous Si film is grown on a crystalline or a multicrystalline Si substrate.

18. The process of claim 17, wherein the mixed epitaxial/amorphous phases in the bulk of the film form a large surface area bulk heterojunction material.

The process of claim 17, wherein the epitaxial Si phase forms vertically aligned silicon nanowires.

20. The process of claim 17, wherein the walls of epitaxial Si phase are passivated by the amorphous Si phase.

21. The process of claim 17 combined by process of claim 5, wherein a silicon based bulk-heterojunction solar cell is obtained.

22. The process of claim 2, wherein very sharp changes in active doping concentration and conductivity is obtained.

23. The process of claim 5, wherein periodic structure of epitaxial doped/intrinsic Si layers are obtained.