WO2010100685A1

WO2010100685A1 - Memory device and memory control device

Info

Publication number: WO2010100685A1
Application number: PCT/JP2009/004199
Authority: WO
Inventors: 村上大輔
Original assignee: パナソニック株式会社
Priority date: 2009-03-03
Filing date: 2009-08-28
Publication date: 2010-09-10
Also published as: JPWO2010100685A1

Abstract

Data transmission for adjusting timing for stable data transmission/reception may prevent data transmission required for an application operation. To cope with this, a register set (102) is arranged in a memory device (100) separately from a memory cell (101) and the register set (102) is accessed during an access-disabled period to the memory cell (101) so as to enable timing adjustment. Thus, it is possible to perform timing adjustment without affecting execution of an application.

Description

Memory device and memory control device

The present invention relates to a memory device and a memory control device capable of adjusting an access timing accompanying an increase in speed in a system using the memory device.

Memory devices such as SDRAM (Synchronous Dynamic Random Access Memory) and memory control devices that send and receive data to and from memory devices use technology that performs data transfer in a source-synchronous manner in response to requests for faster data transfer. ing. In the source synchronous method, a strobe signal is transmitted and received together with data.

In a system that performs data transfer by the source synchronous method, for example, when the memory control device receives data from the memory device, the strobe signal and the data timing are adjusted so that the valid period of the data can be received by the strobe signal.

In this timing adjustment, as the frequency of data transfer increases, the effective range of data for stably receiving data becomes smaller when receiving data with a strobe signal. Furthermore, since the relationship between the data and the strobe signal fluctuates due to factors such as process characteristics, temperature changes, and voltage changes, it is necessary to perform the above timing adjustment flexibly.

For this reason, in the conventional data receiving circuit, for example, the strobe signal is delayed by a delay element and the timing with the data is adjusted so that the delay amount at the delay element can be variably controlled. Generally, in order to search for a delay amount that allows stable data transfer, data is written to a memory device, the data is read, and whether the read data matches the written data, the corresponding delay amount is It is determined whether the amount of delay is enough for data transfer. By repeating this operation, a delay amount range (Window) in which data can be stably transferred is detected.

In the determination of the delay amount, the conventional system has adopted a method of determining uniquely for each system and a method of determining by searching for an optimum delay amount at the start of operation for each individual. However, since the range of the delay amount for stably transferring data varies even in time series due to the various factors described above, there is a case where the delay amount searched at the start of operation cannot stably transmit / receive data. It has become.

For this reason, it is necessary to search for a delay amount capable of stably transferring data by performing a search for the delay amount even during operation of the system. This is necessary and obstructs data transmission / reception that was originally necessary for the application operation of the system.

According to a certain prior art, a strobe signal delayed by a different delay amount is provided in addition to a strobe signal delayed by a delay amount at the time of normal data reception in a data receiving circuit in a memory control device. By comparing the data received by each strobe signal with each other, normal data reception and delay amount search can be performed simultaneously, and delay amount search is performed without interfering with data transmission / reception of system application operations. (See Patent Document 1).

Note that, here, the explanation has been given by taking the data transfer in the source synchronous method as an example, but the present invention is not limited to this, and can be applied to all systems that require adjustment of the delay amount.

JP 2001-350668 A

However, as described above, when the memory control device is configured to receive data by delaying one strobe signal by a plurality of delay amounts, it is difficult to match the delay characteristics in the respective data reception paths. Therefore, the accuracy of the delay value search with the increase in speed is reduced. In addition, since there are a plurality of data receiving circuits, there is a problem that the circuit scale increases.

An object of the present invention is to provide a highly accurate delay amount that enables stable data transfer without interfering with data transfer to a memory device required for application operation even during operation of an application that requires real-time performance. An object of the present invention is to provide a memory device and a memory control device capable of performing a search.

To achieve the above object, in the memory device of the present invention, at least one memory cell, at least one storage means (register set, SRAM), an input / output buffer, the storage means, and the memory cell, Detecting the detection by detecting a command indicating access to the storage means issued to the memory device, a selector for connecting the input / output buffer indicated by a predetermined selection signal, and the memory device A special command detection unit for outputting a signal, and a data path for outputting to the selector as a selection signal a signal indicating that the selector selects the storage means for a certain period of time in accordance with the detection signal from the special command detection unit And a management unit.

Here, the storage means is specifically a register set, for example. Further, the storage means may be SRAM (Static Random Access Memory).

That is, in addition to the memory cell, a storage means (register set) is provided. As a result, data transfer for searching for a delay amount can be performed during a period in which the data bus cannot be used due to a memory device control rule such as a refresh operation of the memory device. For this reason, a delay amount search can be performed during the operation of the application without hindering the data transfer necessary for the original application operation.

This memory device has the following configuration. In other words, in order to be able to use the unused period of the data bus resulting from memory control rules due to the inability to access internal memory cells such as refresh operations, storage means (register set) separate from the memory cells The structure with is taken. In this configuration, the data bus can be used by accessing the storage means (register set) during a period in which the data bus cannot be used according to the conventional memory control rules.

In addition, the memory control device of the present invention includes a command issuing unit that issues a read command that instructs a predetermined memory device to read data from a predetermined storage unit included in the memory device, and the memory A data transmission / reception unit for delaying a strobe signal output from the device and receiving storage data stored in a memory cell included in the memory device from the memory device using the delayed strobe signal; The data read from the storage means is compared with the expected value data held in advance, and when the stored data stored in the memory cell is received, the strobe is determined by the delay time specified by the comparison result. A delay control unit that delays the signal by the data transmission / reception unit.

That is, in the memory control device, in addition to the control rule of the conventional memory device, the control rule of access to the storage means (register set) is interpreted. A period during which the data bus cannot be used in the conventional control rule is used. A function for searching for a delay amount by transmitting / receiving data to / from the storage means (register set) is provided.

According to the present invention, timing adjustment for stably performing high-speed data transfer can be performed with high accuracy without affecting the execution of an application that requires real-time performance.

FIG. 1 is a block diagram illustrating a configuration example of a memory device and a memory control device. FIG. 2 is a flowchart showing an operation example in the configuration example of FIG. FIG. 3 is a timing chart showing a specific example of register read in the configuration example of FIG. FIG. 4 is a flowchart showing an operation example in the configuration example of FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In recent years, there are the following problems. That is, in a memory control device that performs high-speed data transfer with a memory device, it is necessary to perform timing adjustment for stable data transmission / reception during operation of the system application as data transfer speeds up. . However, when data transfer for timing adjustment is performed, data transfer necessary for original application operation is hindered, and for example, it is difficult to guarantee application operation that requires real-time performance.

Therefore, in the following embodiment, a register set 102 is provided in the memory device 100 (FIG. 1) separately from the memory cell 101. Then, the memory control device 110 (FIG. 1) accesses the register set 102 during a period in which the memory cell 101 cannot be accessed. As a result, the memory controller 110 can perform timing adjustment by data transfer with the register set 102. As a result, timing can be adjusted with high accuracy without affecting the execution of an application that requires real-time performance.

The details will be described below.

<First Embodiment>
FIG. 1 is a diagram illustrating the memory device 100 and the memory control device 110.

1, the memory device 100 includes a memory cell 101, a register set 102, a selector 103, an input / output buffer 104, a special command detection unit 105, and a data path management unit 106. Note that the memory device 100 may further include other components other than these components as appropriate.

The memory device 100 usually receives a command from the memory control device 110 through a command bus, and transmits / receives data mainly from the memory cell 101 to / from the memory control device 110 through the input / output buffer 104 according to the contents of the command. .

When the special command detection unit 105 detects a special command for accessing the register set 102 among the commands received by the memory device 100, the special command detection unit 105 sends a detection signal indicating the detection to the data path management unit 106. Output.

The data path management unit 106 notifies the selector 103 of a selection signal, which will be described in detail later, according to the command content of the detected special command. The selection signal is a signal for selecting one of the register set 102 and the memory cell 101.

The selector 103 causes the selected device to connect to the input / output buffer 104. Specifically, the selector 103 has a function of selecting either the register set 102 or the memory cell 101 and causing the selected device to connect to the input / output buffer 104. That is, the selector 103 selects one of the two paths of the register set 102 and the memory cell 101 based on the notification (previously described) from the data path management unit 106. Then, the data path management unit 106 selects one of the register set 102 and the memory cell 101 (selection side) indicated by the notified selection signal, and selects the input / output buffer 104 and the selection side as a selector. 103.

Note that the register set 102 can have a plurality of registers. Then, the special command detection unit 105 may notify the register set 102 of address information included in the detected command of the special command. Then, the special command detection unit 105 selects the register of the address indicated by the address information to be notified, that is, the corresponding register in the register set 102 by this notification, and the selected register and the input / output buffer 104 are selected. Connect. That is, when the former is selected from among the register set 102 and the memory cell 101, more specifically, a register is selected from a plurality of registers in the register set 102.

The input / output buffer 104 transmits / receives data and a strobe signal to / from the memory control device 110 in synchronization with the internal clock signal. For this reason, of the two paths, the path from the memory device 100 to the memory controller 110 passing through the memory cell 101 and the selector 103 and the path to the memory controller 110 passing through the register set 102 and the selector 103. The memory control device 110 cannot recognize the path difference.

Meanwhile, the memory control device 110 includes a data transmission / reception unit 111, a delay control unit 112, a memory state management unit 113, a command issue unit 114, and a command management unit 115. Here, the data transmission / reception unit 111 includes a delay unit 116 and a data reception circuit 117. The delay control unit 112 includes a data comparison unit 118, a delay value management unit 119, an expected value 120, and an address information addition unit 121.

The memory state management unit 113 manages the memory state of the memory device 100 according to the control rules of the memory device 100.

The command management unit 115 outputs a command to the memory device 100 to the command issuing unit 114 in accordance with the information from the memory state management unit 113. That is, the command management unit 115 issues a command to the memory device 100 by the command issuing unit 114 by outputting the command to the command issuing unit 114.

The command issuing unit 114 issues the command received from the command management unit 115 to the memory device 100.

When the data transmission / reception unit 111 receives data from the memory device 100, the data transmission / reception unit 111 delays the strobe signal by the delay unit 116 according to the delay value information from the delay value management unit 119. Then, the data transmitting / receiving unit 111 receives data from the memory device 100 by the data receiving circuit 117 using the delayed strobe signal.

The delay control unit 112 compares the data and notifies the delay value management unit 119 of the comparison result. Specifically, the delay control unit 112 includes predetermined data (register data) received by the data transmission / reception unit 111 from the memory device 100 by the data reception circuit 117 and an expected value 120 of the delay control unit 112. And compare. More specifically, the delay control unit 112 performs this comparison using the data comparison unit 118. Then, the delay control unit 112 notifies the delay value management unit 119 of the comparison result. Note that the delay control unit 112 includes, for example, an expected value storage unit that stores the expected value 120. Note that the symbol “120” may be understood to indicate the expected value storage unit.

The delay value management unit 119 determines, based on the notified comparison result, whether the currently output delay value is a delay value at which data transfer is possible. That is, if the notified comparison result is the same comparison result, the delay value management unit 119 determines that the current delay value is a delay value that allows data transfer. Then, the delay value management unit 119 outputs delay value information (described above) to the delay unit 116 based on the determination result of this determination.

That is, the delay control unit 112 determines whether the register data from the memory device 100 and the expected value 120 are the same by the data comparison unit 118. Then, the delay control unit 112 specifies the delay value information to be output based on the determination result of the determination by the delay value management unit 119, and the delay value information is specified by the delay value management unit 119. To output.

Note that the configuration example shown in FIG. 1 is an example, and does not limit the present invention. For example, the delay unit 116 of the data transmission / reception unit 111 may include two parts. That is, for example, the delay unit 116 may include not only the first delay unit for the strobe signal but also the second delay unit for the data signal, and the data receiving circuit 117 also has the configuration described above. Another configuration may be used.

FIG. 2 is a flowchart showing an operation example in the configuration example of FIG. 1, and the operation will be described below with reference to FIG.

In step Sa, after the operation of the system 1 is started and the initialization operation of the memory device 100 is completed, the delay control unit 112 starts searching for a range of delay values in which data can be received. Note that this search may be a search using the register set 102, but here, an example of a search using the memory cell 101 will be described.

The delay value management unit 119 issues a write command to the command management unit 115 in order to write the same value as the expected value 120 into the memory cell 101.

The command management unit 115 confirms whether or not a write command may be issued based on information from the memory state management unit 113, and issues a write command to the command issue unit 114.

The command issuing unit 114 issues the write command received from the command management unit 115 to the memory device 100.

In the following, detailed description of the operations of the memory state management unit 113, the command issue unit 114, and the command management unit 115 at the time of command issue will be omitted.

The memory device 100 interprets the write command received from the memory control device 110, and stores the expected value data received from the memory control device 110 via the input / output buffer 104 in the memory cell 101.

At this time, it is assumed that the data path management unit 106 issues a notification that the selector 103 normally selects the memory cell 101.

When the writing of the expected value data to the memory cell 101 is completed, the delay value management unit 119 sets the delay value to the minimum value, and the delay control unit 112 issues a read command to the command management unit 115.

The memory device 100 interprets the read command received from the memory control device 110, reads data from the memory cell 101, and outputs expected value data via the input / output buffer 104.

The data transmitting / receiving unit 111 delays the strobe signal by the delay unit 116 by the delay value which is the minimum value, and receives the data by the data receiving circuit 117.

The received data is compared with the expected value 120 by the data comparison unit 118, and the result of the comparison is notified to the delay value management unit 119.

When the comparison result is coincident, the delay value management unit 119 determines that the minimum delay value is a data receivable delay value. When the comparison result is disagreement, the minimum delay value is not data receivable. Judge that.

繰り返す By repeating this operation until the delay value reaches the maximum value from the minimum value, the delay value management unit 119 can know the range of the delay value in which data can be received.

Among the delay value ranges detected at the end, the intermediate value is determined as the delay value at which data can be received most stably, and the intermediate value is output to the delay unit 116 by the delay value management unit 119.

Note that the delay value search method in step Sa is not limited to this embodiment, and may be a statically set range or a search method using another algorithm. Further, in order to determine the delay value at which data can be received most stably, a value obtained by another calculation formula may be used instead of the intermediate value of the delay value range.

In step Sb, the system 1 performs normal system operation. Here, data transmission / reception from the memory control device 110 to the memory device 100 is also performed by the system 1.

In step Sc, the delay control unit 112 manages the timing at which the delay value search should be performed every certain period, and determines whether it is the timing. If it is not the timing, the system 1 continues the normal operation of step Sb (step Sc: No), and if it is the timing, the system 1 proceeds to step Sd (step Sc: Yes).

Note that, as a more specific content of step Sc, a case where it is determined here that the timing of the refresh operation of the memory device 100 is the timing of performing a delay value search will be described. That is, for example, in step Sc, the delay control unit 112 detects that the memory device 100 has started refreshing based on information from the memory state management unit 113, and determines that it is the timing of the delay value search (step Sc). : Yes).

In step Sd, for example, the delay control unit 112 determines whether there is time to process a read command for searching for a delay value. The determination here is performed in order to confirm whether or not there is an influence on data transmission / reception of a normal application by executing a read command for delay value search. Here, in this example, since the start of the refresh is detected and the process proceeds to step Sd (step Sc: Yes), it can be determined in advance that there is no data transmission / reception for the normal application for a certain period after the refresh. Therefore, it can be determined that the normal application is not affected (step Sd: Yes).

Note that if the delay value search timing other than refresh is detected in step Sc, there is a possibility that the normal application may be affected. In this case, the normal operation is continued in step Se until the influence disappears ( Step Sd: No). If it is confirmed that there is no influence, the process proceeds to step Sf (step Sd: Yes).

After step Sf, the delay value search is not performed for all delay values, but the reception of data in the vicinity of the minimum value and the vicinity of the maximum value only in the currently known delay value range (Window) is determined. A method of updating the value and the maximum value will be described. In addition, the method after step Sf is not limited to this description, You may search all the delay values, and you may use another algorithm.

In step Sf, the delay value management unit 119 outputs the maximum value of the window currently grasped to the delay unit 116.

In step Sg, in order to receive the expected value data from the register set 102, the command management unit 115 issues a special register read command different from the read command to the memory cell 101 by the command issuing unit 114. For example, the delay value management unit 119 may cause the command management unit 115 to issue it. Here, it is assumed that a data pattern suitable for delay value adjustment is stored in the expected value 120 and the register set 102, and a plurality of data patterns may be used. In this case, the address information adding unit 121 A data pattern can be selected by including address information in the register read command. Further, the memory state management unit 113 grasps a control rule for the read command to the register set 102 different from the control rule for the read command to the memory cell 101.

In step Sg, the memory device 100 that has received the register read command interprets the special command detection unit 105 as a read command to the register set 102. After the interpretation, the special command detection unit 105 notifies the register set 102 of address information and a read instruction, and notifies the data path management unit 106 to select the register set 102.

In step Sg, the data path management unit 106 instructs the selector 103 to select the register set 102 at the timing when the data is output from the register set 102. Select. Data output from the register set 102 is output to the memory control device 110 via the input / output buffer 104.

In step Sh, the delay unit 116 delays the strobe signal by the delay value set to the maximum value of the window, and the data receiving circuit 117 receives the data. The data comparison unit 118 compares the received data with the expected value 120 and notifies the delay value management unit 119 of the result.

If the comparison result is the same (step Sh: Yes), the delay value management unit 119 proceeds to step Si, determines that the maximum value of the window is still valid, and further increases the delay value by one. In order to confirm whether or not this is the next time, the maximum value information of the grasped window is increased by one and the maximum value information is updated. On the other hand, if the comparison results do not match (step Sh: No), the delay value management unit 119 proceeds to step Sj, determines that the maximum value of the window is invalid, and determines a smaller value as the maximum value of the window. Therefore, the maximum value information is reduced by one and the maximum value information is updated.

In step Sk, using the updated maximum value information and separately acquired minimum value information, the intermediate value is determined to be the delay value at which data can be received most stably at present, and the intermediate value is delayed. The delay value management unit 119 outputs to the unit 116.

From step S1 to step Ss, the operation from step Sd to step Sk is replaced by the minimum value instead of the maximum value of the window, and the detailed description is omitted. However, in Step Sq and Step Sr, since the minimum value of Window is updated, it is decreased by 1 when the comparison result is coincident, and is incremented by 1 when the comparison result is not coincident.

After step Ss, return to step Sb again.

Next, FIG. 3 shows an example of a timing diagram when the register read command is issued in FIG. 2 (see step Sg and step So).

At timing (A), the command issuing unit 114 issues a refresh command to the memory device 100. At this timing (A), the delay control unit 112 determines that it is the window detection timing of step Sc in FIG. 2 (step Sc: Yes), and at the same time, determines that it is the timing at which register read is possible at step Sd. (Step Sd: Yes).

At timing (B), the command issuing unit 114 issues a register read command (step Sg), and then the output signal from the data path management unit 106 selects the register set 102 from the signal for selecting the memory cell 101. Switch to signal.

Further, at timing (C), the delay value management unit 119 sets the delay value to the delay unit 116 to the maximum value of the window (step Sf).

Note that the switching timing of the output signal from the data path management unit 106 and the timing (C) are not limited to the present description, and may be in the reverse order or the same timing.

At timing (D), the comparison result of the comparison by the data comparison unit 118 with respect to the received data reaches the delay value management unit 119, and in this case, it is notified that they match. As a comparison result, a plurality of data are received, and when all these data match the expected value, a comparison result that matches is sent.

Here, the number of data is not limited to this description. Also, a register read command may be issued a plurality of times, and the result of comparing all the expected values may be used. At the timing when the output from the register set 102 ends, the data path management unit 106 returns the output signal to the output signal of the output value for selecting the memory cell 101.

At timing (E), the delay value management unit 119 receives the comparison result of coincidence, and increases the maximum value information of the window by one (step Si in FIG. 2). Here, since the numerical value 0x40 was first grasped as the maximum value, it is assumed that the value is updated to 0x41.

At timing (F), after this update, the delay value management unit 119 resets the intermediate value 0x30 to the delay unit 116 (step Sk). Here, the intermediate value is calculated by the round-down method, but it may be rounded up. Or, since it is not possible to determine here whether or not 0x41 is a valid delay value in the intermediate value calculation with the maximum value increased by one, even if it is determined that truncation is safer than rounding up Good.

Next, it is determined that there is still room for executing the register read command, and the register read command is issued at timing (G) (step So). The data path management unit 106 changes the output signal so as to select the register set 102.

At timing (H), the delay value management unit 119 next outputs the minimum value of the window to the delay unit 116 (step Sn). At timing (I), this time, a mismatch result is received, and at timing (J), the minimum value information is increased by one from 0x20 to 0x21 (step Sr). Thereafter, at timing (K), the delay value to the delay unit 116 is set to the intermediate value 0x31 (step Ss). Further, the data path management unit 106 changes the output signal so as to select the memory cell 101 at the timing when the data output from the register set 102 is completed.

In FIG. 3, the register read command is issued twice (step Sg and the like) during the refresh operation after the normal application read operation (step Sb) and the read operation thereafter. Since this register read command uses the data bus that was originally unavoidable for the refresh operation, it does not affect the read operation due to the normal application operation.

As described above, by searching for the delay value without interfering with normal application data transfer, it is possible to detect window fluctuations even while the application is running, and to adjust the timing accordingly. Explained that data can be sent and received.

Note that the timing described in FIG. 3 is an example, and the present invention is not limited to this. The register read command may be executed several times by changing the data pattern, may be executed only once, or the determination of the maximum value and the minimum value may be performed twice or more. In this example, a special register read command is used. However, the special command detection unit 105 interprets the refresh command as a read command to the register set 102 and converts the data from the register set 102 to the memory control device. 110 may be output. In that case, whether the special command detection unit 105 interprets the refresh command as a read command to the register set 102 may be set in a mode, or may be determined by an address signal or the like.

<Second Embodiment>
FIG. 4 shows an embodiment (second embodiment) of a memory device and a memory control device. In the present embodiment, an example of writing data to the register set 102 in the configuration of FIG. 1 will be described with reference to a timing chart of FIG.

The delay control unit 112 detects that there is a timing for transmitting data to the register set 102 based on information from the memory state management unit 113.

At timing (A), it is detected that the memory control device 110 has issued a refresh command to the memory device 100, and if there is no use of the data bus by a normal application for a certain period, the command management unit 115 (delay control unit 112). ) Can be determined (see step Sc in FIG. 2).

At timing (B), the command management unit 115 issues a special register write command to the register set 102 to the memory device 100 by the command issuing unit 114. For example, the delay control unit 112 causes the command management unit 115 to issue it. In addition, the data to be written by this issue is selected from the expected value 120. In the register write command, when the register set 102 includes a plurality of registers, the address information adding unit 121 can include address information for designating which register to write. After the special command detection unit 105 detects the register write command, the output of the data path management unit 106 is changed to select the register set 102. After the write data output from the memory control device 110 is stored in the register set 102, the output of the data path management unit 106 returns to select the memory cell 101 at timing (D).

Thereafter, at timing (E), the delay control unit 112 determines that a read command to the register set 102 can be issued (see step Sd), and issues a register read command. The description of the comparison of the expected value after that will be omitted, but when the output data from the register set 102 is output to the memory control device 110 via the input / output buffer 104, the output of the data path management unit 106 is the memory cell. 101 is selected. Thereafter, at timing (F), a read command by a normal application is issued to the memory device 100 by the memory control device 110, and data from the memory cell 101 of the memory device 100 is output to the memory control device 110 by the memory device 100. The

As described above, it has been explained that data can be stored in the register set 102 without interfering with normal application operation. In writing data to the register set 102, various data patterns are used when searching for a delay value, or an expected value comparison is performed using a data pattern other than the initial value of the register set 102. In this description, the case where the register set 102 is accessed within a range that does not interfere with the operation of the normal application has been described. On the other hand, the command management unit 115 may issue a command while viewing the information of the memory state management unit 113 so that the access between the memory cell 101 and the register set 102 does not collide. By performing such issuance, priority can be given to access to the register set 102 for searching for delay values over normal applications.

Thus, the memory device (memory device 100) which is an embodiment for carrying out the present invention is constituted by the first embodiment and the second embodiment, respectively.

The memory device according to this embodiment includes a memory cell (memory cell 101). The memory cell stores storage data that a predetermined application stores in the memory device by a predetermined memory control device (memory control device 110). Here, the stored data is received by the memory control device when a strobe signal output from the memory device to the memory control device is used in the memory control device. The stored data is stored when a predetermined transmission / reception is impossible (for example, when the memory device is in a mode in which data is not input / output from the memory cell, a refresh command is issued to the memory device). And when the memory device is in a refresh mode or when the data bus is not used due to a bank conflict), the memory device transmits to the memory control device and the memory control device to the memory device. And / or receiving data is impossible data.

Note that the time when the transmission / reception is disabled may be, for example, a time determined by a standard for the memory device. In addition, the memory cell may be, for example, a DRAM (Dynamic Random Access Memory) memory cell including a capacitor (capacitor) that stores charges representing information to be stored. Here, in such a DRAM memory cell, the charge of the capacitor is gradually lost due to the leakage current. Therefore, in such a DRAM memory cell, an operation (refresh) is necessary to replenish the charge lost due to the leakage current. During the refresh, the storage data of the memory cell to be refreshed cannot be received or transmitted.

The memory device further includes a register set (register set 102). The register set stores register data. The stored register data is data that can be transmitted by the memory device to the memory control device when the transmission / reception is impossible.

More specifically, the memory device includes a special command detection unit, a data path management unit, and a selector. Then, when a special command issued by the memory controller to the memory device is detected by the special command detection unit, and the detection is performed, the data path management unit and the selector perform appropriate operations, so that the register data is Communication is performed between the memory device and the memory control device (steps Sg and So).

In more detail, the memory device includes an input / output buffer. The input / output buffer performs buffering of data to be communicated so that data (memory cell data and register data) communicated between the memory device and the memory control device is appropriately communicated.

Also, in this way, the memory control device (memory control device 110), which is an embodiment when the present invention is implemented, is configured. This memory control device includes a delay unit (delay unit 116), a data reception unit (data transmission / reception unit 111), a determination unit (data comparison unit 118), a control unit (delay control unit 112, command management unit 115), Is provided.

The delay unit delays the strobe signal output from the predetermined memory device (memory device 100) to the memory control device by a predetermined delay time.

The data receiving unit receives storage data stored in the memory device by a predetermined application from the memory device using the strobe signal delayed by the delay unit.

Also, the data receiving unit receives register data (stored expected value 120) stored in a predetermined memory cell (memory cell 101) included in the memory device from the memory device. In more detail, the data receiving unit receives register data from the memory device when a predetermined transmission / reception is impossible, in which at least one of reception and transmission by the memory control device of the storage data of the memory device is impossible. Is received (steps Sg, So).

The determination unit determines whether or not the content (expected value 120) of the register data stored in the memory device is the same as the received register data. For example, the determination unit obtains the content of the stored register data from an expected value storage unit that stores the content of the register data, and performs a determination between the stored content and the received register data.

When the determination unit determines that the same is the same, the control unit uses the delay unit to output the strobe signal when the stored data of the application is received by the data reception unit. Delay by the delay time. Further, when it is determined that they are not the same, the control unit causes the delay unit to perform a delay for the second delay time when the stored data is received. Here, the first delay time is a predetermined time in the vicinity of the delay time (determination delay time) at the time of reception of the register data received at the time of determination. On the other hand, the second delay time is a time that is not included in the vicinity of the determination delay time. Here, the vicinity of the determination delay time is, for example, the determination delay time is one end (for example, the maximum time), the center value of the time range that is a predetermined other end (for example, the minimum time), This is a range between the determination delay time. The first delay time is the time of the center value, and the second delay time is a predetermined time closer to the other end than the center value. At this time, in the second delay time, the time difference from the first delay time to the determination delay time is larger than the time difference from the first delay time to the determination delay time.

Thus, a system (system 1) including the memory device and the memory control device is configured.

According to such an embodiment, the delay time when the stored data is received is appropriately selected by the control unit from the first delay time and the second delay time. As a result, an appropriate delay time is selected as the delay time when the stored data is received, for example, according to the ambient temperature of the memory system. The memory device includes the memory cell. Thus, by using this memory cell, communication necessary for determination is performed when the transmission / reception is impossible. Thus, while an appropriate delay time is selected as the delay time when the stored data is received, it is possible to avoid that the access of the memory device by the application is hindered. This makes it possible to both select an appropriate delay time and avoid an access hindrance by the application. As a result, the delay time can be adjusted with high accuracy without affecting the execution of an application that requires real-time performance.

Also, it is not necessary to communicate the data stored in the memory cell until the transmission / reception is disabled. For this reason, for example, the memory cell can be configured in accordance with the standard. As a result, the system configuration can be simplified.

As described above, in the first and second embodiments, at least one memory cell (memory cell 101), at least one register set (register set 102, storage unit), and input / output buffer (input / output buffer), respectively. 104), a selector (selector 103) that connects the register set and the memory cell indicated by a predetermined selection signal and the input / output buffer, and is issued to the memory device, A special command detection unit (special command detection unit 105) that detects a command for accessing the register set and outputs a detection signal indicating the detection, and according to the detection signal from the special command detection unit, A signal indicating that the selector selects the register set for a certain period is used as the selection signal. Memory device is formed comprising data path management unit for outputting a selector and a (data path management unit 106). For example, the data path management unit may continue outputting the signal for a certain period, and the selector may select the register set while the output continues.

This makes it possible to transmit register data when a register set is provided and transmission / reception is not possible. For this reason, by transmitting the register data when transmission / reception is impossible, the delay time of the strobe signal used for receiving the storage data stored in the memory cell can be adjusted. As a result, the delay time can be adjusted without hindering communication of stored data by the application.

Here, as described above, the memory cell is, for example, an SDRAM memory cell, and when the transmission / reception is disabled, communication of stored data stored in the memory cell is impossible. The data of the register set (register data) is data that can be communicated when such transmission / reception is impossible. Specifically, the command is detected by the special command detection unit, and the selector connects the register set to the input / output buffer, whereby the register data is communicated through the input / output buffer.

The special command detection unit detects a read command to the register set, and the special command detection unit outputs a detection signal indicating that the register set has detected the read command to the data path management unit. After that, the register value stored in the register set is output, and after the register value is output from the register set, the selector selects the one that is not the register set, that is, the memory cell. Is configured.

The special command detection unit detects a write command to the register set, and the special command detection unit outputs a detection signal indicating that the register set has detected the write command to the data path management unit. After the data is input from the outside of the memory device (the input expected value 120) is stored in the register set, the selector set stores the data input from the outside, The memory device is configured to select the one that is not the register set, that is, the memory cell.

The register set includes a plurality of registers, and the special command detection unit outputs address information (for example, a register number) included in the detected command to the register set, and the register set includes the register Based on the address information output by the set, a memory device is configured to select a register for reading from and writing to the register from the plurality of registers. That is, the register set selects a register specified by the address information as a register for reading and writing.

Then, a command issuing unit (command) that issues a read command that instructs the memory device (memory device 100) to read data from a predetermined register set (register set 102) of the memory device. Issuance unit 114) and a strobe signal output from the memory device is delayed by a delay unit 116, and storage data stored in a memory cell included in the memory device is transmitted from the memory device using the delayed strobe signal. Data transmitting / receiving unit to be received (data transmitting / receiving unit 111), data read from the register set of the memory device (read register data), and expected value data (expected value 120) held in advance Are compared by the data comparison unit 118 and stored in the memory cell. When receiving stored data, the strobe signal is sent to the delay of the data transmitting / receiving unit for a delay time specified by the comparison result (either the first delay time or the second delay time). A memory control device having a delay control unit (delay control unit 112) for delaying by the unit.

The delay control unit adds address information for selecting one register from a plurality of registers included in the register set to the read command, and further includes a plurality of sets of expected value data, A memory control device is configured to compare data read from a memory device and expected value data corresponding to a register selected by the address information among the plurality of sets of expected value data .

A data transmission / reception unit that transmits / receives data to / from a predetermined memory device; and a write that instructs the memory device to write data to a predetermined register set (register set 102) of the memory device A memory control device having a command issuing unit (command issuing unit 114) for issuing a command is configured. The command issuing unit acquires, from the command management unit 115, a command for accessing the register set issued by the command management unit 115 to the command issuing unit, and sends the acquired command to the memory device. Issue.

And a memory state management unit (memory state management unit 113) for detecting the mode of the memory device, and the memory device to the command issuing unit based on the mode of the memory device notified from the memory state management unit. A command management unit (command management unit 115) for instructing the issuance of a command to the memory unit, and the command management unit is configured to transfer the register set to the register set when the memory device does not input / output data from the memory cell. A memory control device is configured to instruct the command issuing unit to issue a command for instructing reading or writing of data.

The command management unit instructs the command issuing unit to issue a command for reading or writing data to the register set when the memory device is in a refresh mode. Composed.

The command management unit instructs the command issuing unit to issue a command to instruct reading or writing of data to the register set when the data bus is not used due to a bank conflict in the memory device. A memory control device is configured.

Note that the command management unit, for example, detects whether or not transmission / reception is disabled as described above, and sends a command to access the register set only when it is detected that transmission / reception is disabled. May be issued to the memory device.

The data transmitting / receiving unit includes a delay unit that delays the strobe signal based on delay value information from the delay control unit, and receives data from the memory device using the delayed strobe signal. A memory control device is configured.

The delay control unit is a value for delaying the strobe signal in a range where the data (register data) read from the memory device matches the expected value data (expected value 120) held in advance. (For example, holding range value specifying information for specifying the range), and executing the read command using a value larger than the upper limit value of the matching range as the value to be delayed. When the data read from the memory device matches the expected value data held in advance, the memory control device is configured to update the range of the held delay value. Here, updating the range means, for example, changing the held range from the range before the update to the range after the update. Here, the updated range is a range obtained by adding a predetermined neighborhood of the delay value when data (register data) is read to the range before the update.

The delay control unit holds a value for delaying the strobe signal in a range in which the data read from the memory device matches the expected value data held in advance, and the delay control unit The read command is executed using a value smaller than the upper limit value of the matching range, and the data read from the memory device by the execution does not match the expected value data held in advance. The memory control device is configured to update the range of the delay value. Here, the range after the update by the update is a range in which a predetermined neighborhood of the delay value when the data (register data) is read is excluded from the range before the update.

The delay control unit holds a value for delaying the strobe signal in a range in which the data read from the memory device matches the expected value data held in advance, and the delay control unit The read command is executed using a value smaller than the lower limit value of the matching range, and the data read from the memory device by the execution matches the expected value data held in advance. The memory control device is configured to update the range of the delay value. Here, the updated range is a range obtained by adding a predetermined neighborhood of the delay value when data (register data) is read to the range before the update.

The delay control unit holds a value for delaying the strobe signal in a range in which the data read from the memory device matches the expected value data held in advance, and the delay control unit , Execute the read command using a value larger than the lower limit value of the matching range, and hold when the data read from the memory device by the execution does not match the expected value data held in advance The memory control device is configured to update the range of the delay value. Here, the range after the update by the update is a range in which a predetermined neighborhood of the delay value when the data (register data) is read is excluded from the range before the update.

In addition, an integrated circuit including each part of the memory device may be configured. For example, the above memory device may be configured as an integrated circuit. Similarly, an integrated circuit including each part of the memory control device may be configured. In addition, the above description shows a control method for controlling the delay time of the strobe signal by including the steps performed by the memory device and the memory control device. Also, an operation method of the memory device including only a part performed by the memory device is shown in each process. Similarly, an operation method of the memory control device including only a part performed by the above-described memory control device in each process is shown.

In the above description, a form in which the technical matters are combined by the technical matters at a plurality of locations separated from each other is also shown.

As described above, the memory device and the memory control device according to the present invention can perform timing adjustment for data transfer with high accuracy even during execution of an application that requires real-time performance. It can be suitably used.

DESCRIPTION OF SYMBOLS 100 Memory device 101 Memory cell 102 Register set 103 Selector 104 Input / output buffer 105 Special command detection unit 106 Data path management unit 110 Memory control device 111 Data transmission / reception unit 112 Delay control unit 113 Memory state management unit 114 Command issue unit 115 Command management unit 116 Delay Unit 117 Data Receiving Circuit 118 Data Comparison Unit 119 Delay Value Management Unit 120 Expected Value

Claims

At least one memory cell;
At least one storage means;
An input / output buffer;
Of the storage means and the memory cell, a selector that connects a direction indicated by a predetermined selection signal and the input / output buffer;
A special command detection unit that detects a command issued to the memory device to access the storage unit and outputs a detection signal indicating detection;
A memory device comprising: a data path management unit that outputs a signal indicating that the selector selects the storage unit for a certain period of time according to the detection signal from the special command detection unit as the selection signal to the selector.
The memory device according to claim 1,
The special command detection unit detects a read command to the storage means,
The storage means outputs a register value stored in the storage means after a detection signal indicating that the read command has been detected is output to the data path management section by the special command detection section,
The selector is a memory device that selects the memory cell after the register value is output from the storage means.
The memory device according to claim 1,
The special command detection unit detects a write command to the storage means,
The storage unit stores data input from the outside of the memory device in the storage unit after a detection signal indicating that the write command is detected is output to the data path management unit by the special command detection unit. And
The selector is a memory device that selects the memory cell after the storage unit stores the data input from the outside.
The memory device according to claim 2, wherein
The storage means is a register set including a plurality of registers,
The special command detection unit outputs address information included in the detected read command to the storage unit,
The memory unit is a memory device that selects a register to be read out of the plurality of registers based on the address information output to the memory unit.
The memory device according to claim 3.
The storage means is a register set including a plurality of registers,
The special command detection unit outputs address information included in the detected write command to the storage means,
The memory unit is a memory device that selects a register to be written from among the plurality of registers based on the address information output to the memory unit.
A command issuing unit that issues a read command for instructing data reading from a predetermined storage unit included in the memory device to a predetermined memory device;
A data transmission / reception unit that delays a strobe signal output from the memory device and receives storage data stored in a memory cell included in the memory device from the memory device using the delayed strobe signal;
The data read from the storage means of the memory device is compared with the expected value data held in advance, and is specified from the result of the comparison when the stored data stored in the memory cell is received A memory control device comprising: a delay control unit that delays the strobe signal by the data transmitting / receiving unit by a delay time.
The memory control device according to claim 6, comprising:
The delay control unit
Adding address information for selecting one of the plurality of registers of the storage means to the read command;
Further, a plurality of sets of the expected value data are provided, and the data read from the memory device is compared with the expected value data corresponding to the register selected by the address information among the plurality of sets of expected value data. Memory control device.
The memory control device according to claim 6, comprising:
A data transmitter / receiver for transmitting / receiving data to / from a predetermined memory device;
A memory control device comprising: a command issuing unit that issues a write command for instructing the memory device to write data to a predetermined storage means included in the memory device.
The memory control device according to claim 6, comprising:
A memory state management unit for detecting a mode of the memory device;
A command management unit for instructing the command issuing unit to issue a command to the memory device based on the mode of the memory device notified from the memory state management unit;
The command management unit instructs the command issuing unit to issue a command for instructing reading or writing of data to the storage unit when the memory device is in a mode in which no data is input / output from the memory cell. apparatus.
The memory control device according to claim 9, comprising:
The command management unit is a memory control device that instructs the command issuing unit to issue a command instructing reading or writing of data to the storage unit when the memory device is in a refresh mode.
The memory control device according to claim 9, comprising:
The command management unit instructs the command issuing unit to issue a command for instructing reading or writing of data to the storage unit when the data bus is not used due to a bank conflict in the memory device. .
The memory control device according to claim 6, comprising:
The data transmission / reception unit includes a delay unit that delays the strobe signal based on delay value information from the delay control unit, and receives data from the memory device using the delayed strobe signal. .
The memory control device according to claim 12, comprising:
The delay control unit
Holds a value for delaying the strobe signal in a range where the data read from the memory device matches the expected value data held in advance,
As the value to be delayed, the read command is executed using a value larger than the upper limit value of the matching range, and the data read from the memory device by the execution and the expected value data held in advance are A memory control device that updates a range of held delay values when they match.
The memory control device according to claim 12, comprising:
The delay control unit
Holds a value for delaying the strobe signal in a range where the data read from the memory device matches the expected value data held in advance,
As the value to be delayed, the read command is executed using a value smaller than the upper limit value of the matching range, and the data read from the memory device by the execution and the expected value data held in advance are: A memory control device that updates a range of held delay values if they do not match.
The memory control device according to claim 12, comprising:
The delay control unit
Holds a value for delaying the strobe signal in a range where the data read from the memory device matches the expected value data held in advance,
As the value to be delayed, the read command is executed using a value smaller than the lower limit value of the matching range, and the data read from the memory device by the execution and the expected value data held in advance are A memory control device that updates a range of held delay values when they match.
The memory control device according to claim 12, comprising:
The delay control unit
Holds a value for delaying the strobe signal in a range where the data read from the memory device matches the expected value data held in advance,
As the value to be delayed, the read command is executed using a value larger than the lower limit value of the matching range, and the data read from the memory device by the execution and the expected value data held in advance are A memory control device that updates a range of held delay values if they do not match.