WO2010032861A1

WO2010032861A1 - Semiconductor programmable device and control method therefor

Info

Publication number: WO2010032861A1
Application number: PCT/JP2009/066570
Authority: WO
Inventors: 斎藤英彰
Original assignee: 日本電気株式会社
Priority date: 2008-09-16
Filing date: 2009-09-15
Publication date: 2010-03-25
Also published as: JPWO2010032861A1; JP5365637B2

Abstract

Disclosed is a low-cost, high-performance semiconductor programmable device comprising: multiple circuit blocks that input/output signals; a switch fabric that reciprocally transmits the signals input/output by the circuit blocks; and a conversion unit that parallel-serial converts the multiple signals output by the multiple circuit blocks into one signal to be used by the switch fabric and serial-parallel converts the signal output by the switch fabric into multiple signals to be used by the circuit blocks.

Description

Semiconductor programmable device and control method thereof

The present invention relates to a semiconductor programmable device in which a plurality of circuit blocks including processors and memories are integrated.

In order to reduce the cost and shorten the turnaround time (TAT) of semiconductor integrated circuit devices, programmable devices that can change the circuit configuration after device fabrication have been developed. As an example of this programmable device, there is an FPGA (Field Programmable Gate Array) that reconfigures by combining circuits at the gate level. Various programmable devices have been realized or proposed, such as devices that are reconfigured by combining processors and memories that are larger circuit units arranged in an array.
As a programmable device that reconfigures by combining circuit blocks, for example, a device that arranges circuit blocks in a two-dimensional array on a chip and connects the circuit blocks with a two-dimensional mesh coupling network is disclosed in Non-Patent Document 1. ing.
FIG. 29 shows an example of a related two-dimensional array programmable device described in Non-Patent Document 1. As shown in the figure, in a related programmable memory device 600, memory macros 610 as circuit blocks are arranged in a two-dimensional array. The circuit block is not limited to a memory, but includes a processor and a custom hardware circuit. The memory macro 610 is connected to the corresponding switch fabric 630. These switch fabrics 630 are coupled to each other in the form of a two-dimensional mesh in order to transfer data from the memory macro to another memory macro or the outside of the two-dimensional array.
As the switch fabric 630, for example, one having the configuration shown in FIG. 18 can be used. Referring to the figure, the switch fabric 230 is connected to

other switch fabrics

230U, 230D, 230L, and 230R adjacent in the vertical and horizontal directions of the switch fabric 230 by wiring, and one circuit block corresponding to the switch fabric 230 (for example, It is also coupled to the memory block 110). Input / output of signals between the switch fabrics or between the switch fabric and the circuit block is realized by five 4: 1 selectors SE1c to SE5c. Each selector selects and outputs one of the four input signals. Selection of the input signal of each selector is controlled by selection logic circuits LG1c to LG5c. The selection logic circuit includes, for example, a decoding circuit for decoding a data transfer direction addressed.
"Proceedings of the IEEE Computer Society Annual Symposium on VLSI", 2002, p. 40, Proceedings of the IE Computer Society Annual Symposium on VLSI (Proceedings of the IEEE Computer Society Annual VLSI). 105-112

The programmable device disclosed in Non-Patent Document 1 realizes a desired circuit configuration by switching connections between circuit blocks. However, compared to a normal semiconductor integrated circuit device that cannot change the circuit, it is necessary to arrange a wiring for connecting circuit blocks and a switch fabric for switching the connection, resulting in chip area overhead. There was a problem.
For example, in FPGA, about half of the chip area, and in the case of a two-dimensional array of processors, about 1/4 of the chip area is occupied by wiring and switch fabric.
By increasing the number of wiring layers and transferring the above-described wiring to another wiring layer, the number of circuit blocks that can be mounted without increasing the chip area can be increased, and the device performance can be improved. However, when the wiring layer is increased, the mask cost increases.
An object of the present invention is to provide a semiconductor programmable device that solves the above-described problem that it is difficult to obtain a low-cost and high-performance semiconductor programmable device, and a control method thereof.

The semiconductor programmable device of the present invention includes a plurality of circuit blocks that input and output signals, a switch fabric that transfers signals input and output by the circuit blocks to each other, and a plurality of signals output from the plurality of circuit blocks as one signal. And a conversion unit that causes the circuit fabric to use a plurality of signals obtained by serial-parallel conversion of signals output from the switch fabric.
A method for controlling a semiconductor programmable device of the present invention is a method for controlling a semiconductor programmable device comprising a plurality of circuit blocks that input and output signals and a switch fabric that transfers signals input and output by the circuit blocks to and from each other. The switch fabric uses a signal obtained by parallel-serial conversion of a plurality of signals output from a plurality of circuit blocks into one signal, and a plurality of signals obtained by serial-parallel conversion of a signal output from the switch fabric are used for a circuit block. Let

According to the present invention, the area overhead due to the switch fabric and the wiring around the switch fabric can be reduced. As a result, a low-cost and high-performance semiconductor programmable device can be obtained.

FIG. 1 is a block diagram showing a configuration of a programmable memory device according to the first embodiment of the present invention.
FIG. 2 is a block diagram showing a circuit configuration of the SRAM macro according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of the conversion unit according to the first embodiment of the present invention.
FIG. 4 is a circuit diagram showing the configuration of the 2: 1 multiplexer according to the first embodiment of the present invention.
FIG. 5 is a truth table showing the operation of the 2: 1 multiplexer according to the first embodiment of the present invention.
FIG. 6 is a signal waveform diagram showing the operation of the 2: 1 multiplexer according to the first embodiment of the present invention.
FIG. 7A is a circuit diagram showing a configuration of a 1: 2 demultiplexer according to the first embodiment of the present invention.
FIG. 7B is a circuit diagram showing a general configuration of the high-through latch according to the first embodiment of the present invention.
FIG. 8 is a truth table showing the operation of the high-through latch according to the first embodiment of the present invention.
FIG. 9 is a truth table showing the operation of the flip-flop according to the first embodiment of the present invention.
FIG. 10 is a signal waveform diagram showing the operation of the 1: 2 demultiplexer according to the first embodiment of the present invention.
FIG. 11 is a block diagram showing the configuration of the switch fabric according to the first exemplary embodiment of the present invention.
FIG. 12 is a circuit diagram showing the configuration of the read data control circuit constituting the switch fabric according to the first embodiment of the present invention.
FIG. 13 is a flowchart showing the operation of the selection logic circuit according to the first embodiment of the present invention.
FIG. 14 is a circuit diagram showing a configuration of a write data control circuit constituting the switch fabric according to the first embodiment of the present invention.
FIG. 15 is a circuit diagram showing a configuration of the memory input / output unit according to the first embodiment of the present invention.
FIG. 16 is a circuit diagram showing a configuration of a 1: 2 demultiplexer according to the second embodiment of the present invention.
FIG. 17 is a circuit diagram showing a configuration of a conversion unit according to the third embodiment of the present invention.
FIG. 18 is a circuit diagram showing a configuration of a switch fabric according to the fourth exemplary embodiment of the present invention.
FIG. 19 is a block diagram showing a configuration of a programmable memory device according to the fifth embodiment of the present invention.
FIG. 20 is a circuit diagram showing a configuration of a 4: 1 multiplexer according to the fifth embodiment of the present invention.
FIG. 21 is a Carnot diagram illustrating the operation of the 4: 1 multiplexer according to the fifth embodiment of the present invention.
FIG. 22 is a signal waveform diagram showing the operation of the 4: 1 multiplexer according to the fifth embodiment of the present invention.
FIG. 23 is a circuit diagram showing a configuration of a 1: 4 demultiplexer according to the fifth embodiment of the present invention.
FIG. 24 is a signal waveform diagram showing the operation of the 1: 4 demultiplexer according to the fifth embodiment of the present invention.
FIG. 25 is a circuit diagram showing a configuration of a 1: 4 demultiplexer according to the sixth embodiment of the present invention.
FIG. 26 is a circuit diagram showing a configuration of a 1: 4 demultiplexer according to the seventh embodiment of the present invention.
FIG. 27 is a perspective view showing the configuration of the laminated device according to the eighth embodiment of the present invention.
FIG. 28 is a block diagram showing a configuration of a programmable processor device according to the ninth embodiment of the present invention.
FIG. 29 is a block diagram showing a configuration of a related programmable memory device.

100, 300 Programmable memory device 110, 310, 511, 610 Memory macro 110A Upper memory macro 110B Lower memory macro 111 SRAM macro 112 Memory cell array 113 Address decoder 114 Word line driver 115 Sense amplifier 116 Write buffer 117 Read buffer 118 Control unit 119A Upper clock synchronous memory macro 119B Lower clock synchronous memory macro 120, 220, 320, 520 Converter 121, 142 2: 1 multiplexer 122, 141, 222 1: 2 demultiplexer 130, 130U, 130D, 130L, 130R, 230, 230U, 230D, 230L, 230R, 330, 530, 630 Switch fabric 131 read Data control circuit 132 Write data control circuit 140, 340, 440 Memory input / output unit 150, 350 Logic device 151, 351 Logic macro 151A Upper logic macro 151B Lower logic macro 310A Upper left memory macro 310B Upper right memory macro 310C Lower left memory macro 310D Right Lower memory macro 311A Upper left clock synchronous memory macro 311B Upper right clock synchronous memory macro 311C Lower left clock synchronous memory macro 311D Lower right clock synchronous memory macro 321 4: 1 multiplexer 322, 323, 324 1: 4 demultiplexer 400 Stacked device 410 logic device substrate 420 programmable memory device substrate 430 logic input / output unit 500 program Mable processor device 510 Memory device 540 Processor input / output unit 551 Processor 600 Related programmable memory device B1, B2 Buffer N1, N2 NOT gate TR1-TR8 Transistor FF1-FF7 Flip-flop LH1-LH3 High-through latch SE1-SE9, SE1c- SE5c selector LG1 to LG9, LG1c to LG5c selection logic circuit AD1 to AD4 AND gate

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a programmable memory device 100 as a semiconductor programmable device according to the first embodiment of the present invention. A plurality of memory macros 110 as circuit blocks are connected to the switch fabric 130 via a conversion unit 120 as conversion means. The switch fabrics 130 are arranged in a two-dimensional array, and some of the switch fabrics 130 are connected to the logic macro 151 that constitutes the logic device 150 via the memory input / output unit 140. In the present embodiment, as shown in FIG. 1, 16 memory macros 110 are arranged in a 4 × 4 two-dimensional array.
A read data signal from the memory macro 110 is serially converted by the conversion unit 120 and input to the switch fabric 130. Here, serial conversion is, for example, serializing after halving the time widths of parallel data signals output from two

memory macros

110A and 110B, and the same throughput as when transferring in parallel. Is obtained. Transfer between the switch fabrics 130 and transfer from the switch fabric 130 to the memory input / output unit 140 are performed by serialized signals.
By sharing one switch fabric 130 among a plurality of memory macros 110, the number of switch fabrics 130 required in the programmable memory device 100 can be reduced. For example, as shown in FIG. 1, when two

memory macros

110A and 110B share one switch fabric 130, the number of necessary switch fabrics 130 can be halved. Therefore, it is possible to reduce the chip area overhead caused by the wiring connecting the switch fabric. In addition, the placement overhead of the switch fabric and the like can be reduced by reducing the area overhead, and more wiring can be secured with a limited chip area, so that the performance can be improved. As described above, according to this embodiment, a low-cost and high-performance semiconductor programmable device can be obtained.
FIG. 2 shows a circuit configuration of the SRAM macro 111 as the memory macro 110. The SRAM macro 111 includes a memory cell array 112, an address decoder 113, a word line driver 114, a sense amplifier 115, a write buffer 116, a read buffer 117, and a control unit 118.
The address decoder 113 designates the address of data to be accessed when reading / writing data from / to the memory cells in the memory cell array 112. The word line driver 114 drives word lines (not shown) in the memory cell array 112 at a predetermined timing. The configuration of the memory cell array 112 will be described later.
The sense amplifier 115 amplifies and transmits a signal input to the memory cell array 112 or a signal output from the memory cell array 112. The write buffer 116 and the read buffer 117 adjust the difference in processing speed between the memory cell array 112 and other devices. The control unit 118 controls the operation of the SRAM macro 111.
In the memory cell array 112, for example, SRAM memory cells are arranged in a 1k word 16-bit configuration. At this time, the signal (address signal) for designating the address of the memory cell array 112 is 4 bits (memory macro address) for specifying the memory macro 110 to be accessed and the word address in each memory macro. A total of 14 bits of 10 bits. When the 4-bit memory macro address in the address signal to be read / written matches the memory macro address preset in the control unit 118, all circuits in the subsequent stage of the control unit 118 are activated. Then, a write or read operation is performed on the memory cell array 112.
As shown in FIG. 1, the programmable memory device 100 of this embodiment is connected to a logic device 150 arranged in the periphery thereof. The logic device 150 has a plurality of logic macros 151. These logic macros 151 are macrocells composed of logic circuits. These logic macros 151 execute predetermined processing defined in the circuit. Each logic macro 151 and the programmable memory device 100 perform data transfer via the memory input / output unit 140.
The programmable memory device 100 according to the present embodiment includes a plurality of (for example, 4 × 4 16) memory macros 110 as circuit blocks, a plurality of (for example, eight) conversion units 120 as conversion means, and a plurality of (for example, eight). For example, eight switch fabrics 130 are provided. Furthermore, it has a plurality (for example, four) of memory input / output units 140 and wirings connecting them.
The memory macro 110 is, for example, an SRAM (Static Random Access Memory) macro that can store 1k words in a unit of 16 bits. The two memory macros 110 share one conversion unit 120 and one switch fabric 130. The memory macro 110 inputs the signal serial-parallel converted by the converter 120 or outputs a signal for parallel-serial conversion.
As shown in FIG. 1, one of the two memory macros 110 sharing one switch fabric 130 is an upper memory macro 110A and the other is a lower memory macro 110B.
The conversion unit 120 performs parallel-serial conversion of the parallel signals output from the two memory macros 110 A and 110 B into serial signals, and inputs the converted serial signals to the switch fabric 130. The conversion unit 120 serial-parallel converts the serial signal output from the switch fabric 130 into a parallel signal, and inputs the converted parallel signal to the two

memory macros

110A and 110B, respectively.
The switch fabrics 130 are connected to each other by a two-dimensional mesh wiring, and the conversion unit 120 controls the transfer direction of the serial signal that has been subjected to parallel-serial conversion. A part of the switch fabric 130 is connected to the memory input / output unit 140 and inputs / outputs serial signals to / from the memory input / output unit 140.
The memory input / output unit 140 serial-parallel converts the serial signal output from the switch fabric 130 into a parallel signal, and inputs the converted parallel signal to each logic macro 151. Further, the memory input / output unit 140 performs parallel-serial conversion on the parallel signals output from the two logic macros 151 into serial signals, and inputs the converted serial signals to the switch fabric 130.
FIG. 3 is an example of a circuit diagram illustrating a configuration of the conversion unit 120 according to the present embodiment. Referring to the figure, the conversion unit 120 has one 2: 1 multiplexer 121 and three 1: 2 demultiplexers 122. The 2: 1 multiplexer 121 and the 1: 2 demultiplexer 122 receive a clock signal having a predetermined period.
The 2: 1 multiplexer 121 converts the 16-bit read data signal output from the upper memory macro 110 A and the 16-bit read data signal output from the lower memory macro 110 B into a serial signal and supplies the serial signal to the switch fabric 130. input.
The 1: 2 demultiplexer 122 converts the serial signal output from the switch fabric 130 into a parallel consisting of a 16-bit write data signal to the upper memory macro 110A and a 16-bit write data signal to the lower memory macro 110B. Convert to signal. Then, the 1: 2 demultiplexer 122 inputs the parallel signal to the upper memory macro 110A and the lower memory macro 110B.
The 1: 2 demultiplexer 122 converts the 2-bit command signal and the 14-bit address signal output from the switch fabric 130 in a serial manner into parallel signals, respectively. Then, the 1: 2 demultiplexer 122 inputs the converted parallel signal to the upper memory macro 110A and the lower memory macro 110B.
Next, the configuration and operation of the 2: 1 multiplexer 121 will be described with reference to FIGS.
FIG. 4 is a circuit diagram showing a configuration of the 2: 1 multiplexer 121. Referring to the figure, the 2: 1 multiplexer 121 includes a NOT gate N1, transistors TR1, TR2, TR3, and TR4, and a buffer B1.
Then, clock signals having the same phase are input to the NOT gate N1 and the gate electrode of the transistor TR1. A signal obtained by inverting the clock signal is input to the gate electrode of the transistor TR2.
The read data signal output from the upper memory macro 110A is input to the source electrodes of the transistors TR1 and TR2. The read data signal output from the lower memory macro 110B is input to the source electrodes of the transistors TR3 and TR4. NOT gate N1 inverts the clock signal and outputs the inverted signal to transistors TR2 and TR3. Here, the transistors TR1, TR2, TR3, and TR4 are, for example, FETs (Field Effect Transistors).
Signals output from the transistors TR1, TR2, TR3, and TR4 are input to the buffer B1. The buffer B1 adjusts the voltage level of the input signal and outputs it to the switch fabric 130.
By configuring the circuit in this way, when the clock signal is at a high level, the transistors TR1 and TR2 are turned on and the transistors TR3 and TR4 are turned off. As a result, the 2: 1 multiplexer 121 reads data from the upper memory macro 110A. Output only signals. When the clock signal is at a low level, the transistors TR1 and TR2 are turned off and the transistors TR3 and TR4 are turned on. As a result, the 2: 1 multiplexer 121 outputs only the read data signal from the lower memory macro 110B. As a result, read data signals from the

memory macros

110A and 110B are serially converted. At this time, since the transfer rate of the serial signal converted by the 2: 1 multiplexer 121 is twice the transfer rate of the parallel signal from the memory macro 110, the throughput is not reduced by the parallel-serial conversion.
FIG. 5 is a truth table showing the operation of the 2: 1 multiplexer 121. Referring to the figure, when the clock signal Clk is at a low level (0), the read data D2 from the lower memory macro is output as the signal Q as it is regardless of the value of the read data D1 from the upper memory macro. When the clock signal Clk is at a high level (1), the read data D1 from the upper memory macro is output as it is regardless of the value of the read data D2 from the lower memory macro.
FIG. 6 is a signal waveform diagram showing the operation of the 2: 1 multiplexer 121. Referring to the figure, while the clock signal Clk is at the high level, the 2: 1 multiplexer 121 outputs the read data signal D1 from the upper memory macro 110A as the signal Q to the switch fabric 130. While the clock signal Clk is at the low level, the 2: 1 multiplexer 121 outputs the read data signal D2 from the lower memory macro 110B to the switch fabric 130 as the signal Q.
As apparent from the signal waveform of FIG. 6, the input parallel read data signal has the same time width as the clock cycle, whereas the data signal serially converted by the 2: 1 multiplexer 121 is clocked. The time width is half of the cycle. This provides the same throughput as when transferring in parallel format.
Next, the configuration and operation of the 1: 2 demultiplexer will be described with reference to FIGS.
FIG. 7A is a circuit diagram showing a configuration of the 1: 2 demultiplexer 122. Referring to the figure, the 1: 2 demultiplexer 122 includes a high-through latch LH1 and flip-flops FF1 and FF2. Clock signals having the same phase are input to the high-through latch LH1 and the flip-flops FF1 and FF2. Here, the high-through latch is a latch that outputs the data D as a signal Q as it is when the clock Clk is at a high level (1) and holds a value when it is at a low level (0). As shown in FIG. 7B, a general high-through latch is composed of a gate of an input section that is opened and closed by a clock Clk and a loop using an inverter that follows the gate.
A signal from the switch fabric 130, for example, a write data signal is input to the high-through latch LH1. The signal output from the high through latch LH1 is input to the flip-flop FF1. The write data signal output from the flip-flop FF1 is input to the upper memory macro 110A. On the other hand, the write data signal from the switch fabric 130 is directly input to the flip-flop FF2. The signal output from the flip-flop FF2 is input to the lower memory macro 110B.
FIG. 8 is a truth table showing the operation of the high-through latch LH1. Referring to the figure, when the clock signal Clk is at the high level (1), the high through latch LH1 outputs the input signal D as it is as the signal Q and holds the output value. When the clock signal Clk is at low level (0), the high-through latch LH1 holds the value Q ₀ Is output.
FIG. 9 is a truth table showing the operations of the flip-flops FF1 and FF2. Referring to the figure, the flip-flops FF1 and FF2 output the input signal D as it is as the signal Q at the rising edge of the clock signal Clk, and the output value Q ₀ Hold. The flip-flops FF1 and FF2 hold the value Q at the falling edge of the clock signal Clk. ₀ Is output.
By configuring the circuit in this manner, when the clock signal Clk is at a high level, the flip-flop FF1 transparently outputs the output value from the high-through latch LH1, and holds the hold value while the clock signal Clk is at a low level. Output. When the clock signal Clk reaches the rising edge, the flip-flops FF1 and FF2 transparently output the input signal and hold the output value.
Since the write data in the serial format is latched by the high-through latch LH1, each memory macro 110 can capture only the data to be written. Further, since the 1: 2 demultiplexer 122 holds the value of the output signal in the flip-flops FF1 and FF2, the parallel signal transfer speed returns to the speed before the serial-parallel conversion and the parallel-serial conversion, and the memory macro 110A, There is no inconvenience in signal processing at 110B.
FIG. 10 is a signal waveform diagram showing the operation of the 1: 2 demultiplexer 122. The high-through latch LH1 takes in the serial-format write data signal from the switch fabric 130 input during the period when the clock is at the high level. The data signal captured at this time is the data signal in the first half of the clock cycle of the write data signal D. The high-through latch LH1 outputs the data signal taken as it is while the clock is at the high level, and holds and outputs the data signal while the clock is at the low level (high-through latch output LQ). The flip-flop FF1 takes in the high-through latch output LQ at the rising edge of the clock and outputs it as a parallel signal AQ to the upper memory macro 110A. On the other hand, the flip-flop FF2 takes in the write data signal D input during the low level of the clock at the rising edge of the clock and outputs it as a parallel signal BQ to the lower memory macro 110B. As can be seen from FIG. 10, in the parallel conversion by the 1: 2 demultiplexer 122, the write data signal is returned to the time width before the parallel-serial conversion and the serial-parallel conversion.
The configuration of the switch fabric 130 will be described with reference to FIGS.
FIG. 11 is a block diagram illustrating a configuration of the switch fabric 130. Referring to the figure, the switch fabric 130 includes a read data control circuit 131 and a write data control circuit 132.
FIG. 12 is a circuit diagram showing a configuration of the read data control circuit 131. Referring to the figure, the read data control circuit 131 has four selectors SE1, SE2, SE3, and SE4 and four selection logic circuits LG1, LG2, LG3, and LG4.
The selectors SE1, SE2, SE3, and SE4 respectively read from three switch fabrics of the adjacent upper, lower, left, and

right switch fabrics

130U, 130D, 130L, and 130R other than the one that is in the output direction. Data signal is input. A total of four data signals obtained by adding the data signals read from the memory macro 110 via the converter 120 are input to the selector SE. The selector SE1 selects one of the four input data signals according to the control of the selection logic circuit LG1, and outputs it to the upper switch fabric 130U. The selectors SE2, SE3, and SE4 select one of the input data signals according to the control of the selection logic circuits LG2, LG3, and LG4. Each selector outputs the selected data signal to the left switch fabric 130L, the lower switch fabric 130D, and the right switch fabric 130R.
For example, the selection logic circuits LG1 to LG4 select one of the input signals as follows. First, it is assumed that the upper bit of the address specifying the memory macro 110 to be read is the horizontal address MX in the two-dimensional array of memory macros, and the lower bit is the vertical address MY in the two-dimensional array of memory macros. These values are compared with the horizontal address SX and the vertical address SY of the switch fabric itself to select one of the input signals.
FIG. 13 is a flowchart showing the operation of the selection logic circuit. This operation starts when an address of a memory macro to be read is input to the read data control circuit 131 of the switch fabric 130. Referring to the figure, the selection logic circuit reads the address of the memory macro to be read, and sets the upper bit as the horizontal address MX of the memory macro and the lower bit as the vertical address MY of the memory macro (step S1).
The selection logic circuit compares MX and MY with the predefined horizontal address SX and vertical address SY of the switch fabric itself, and first determines whether MX is greater than SX (step S3). If MX is larger than SX (step S3: YES), the selection logic circuits LG1 to LG3 select and output the input signals from the right switch fabric 130R to the selectors SE1 to SE3 (step S5).
If MX is not larger than SX (step S3: NO), it is determined whether MX is smaller than SX (step S7). If MX is smaller than SX (step S7: YES), the selection logic circuit LG1, LG3, or LG4 selects and outputs the input signal from the left switch fabric 130L to the selector SE1, SE3, or SE4 (step S7). S9).
If MX is not smaller than SX (step S7: NO), it is determined whether MY is larger than SY (step S11). If MY is larger than SY (step S11: YES), the selection logic circuit LG2, LG3, or LG4 causes the selector SE2, SE3, or SE4 to select and output the input signal from the upper switch fabric 130U (step). S13).
If MY is not larger than SY (step S11: NO), it is determined whether MY is smaller than SY (step S15). If MY is smaller than SY (step S15: YES), the selection logic circuit LG1, LG2, or LG4 causes the selector SE1, SE2, or SE4 to select and output the input signal from the lower switch fabric 130D (step S15: YES). Step S17).
If MY is not smaller than SY (step S15: NO), the selection logic circuits LG1 to LG4 select and output the input signals from the memory macro 110 via the conversion unit 120 to the selectors SE1 to SE4 (step S19). ).
After steps S5, S9, S13, S17, or S19, the selection logic circuits LG1 to LG4 end their operations.
FIG. 14 is a circuit diagram showing a configuration of the write data control circuit 132. Referring to the figure, the write data control circuit 132 has five selectors SE5, SE6, SE7, SE8, and SE9 and five selection logic circuits LG5, LG6, LG7, LG8, and LG9.
The selectors SE5, SE6, SE7, and SE8 receive data signals from three switch fabrics other than the ones in the direction in which they are output among the adjacent upper, lower, left, and

right switch fabrics

130U, 130D, 130L, and 130R. Is done. The selector SE9 that outputs to the memory macro 110 receives data signals from the adjacent upper, lower, left, and

right switch fabrics

130U, 130D, 130L, and 130R.
The selectors SE5, SE6, SE7, and SE8 select one of the three input signals excluding the input signal from the output direction according to the control of the selection logic circuits LG5, LG6, LG7, and LG8, respectively. The selected signal is output to the upper, left, lower, and right switch fabrics 130. The selector SE9 selects one of four input data signals from the upper, lower, left, and right switch fabrics 130 according to the control of the selection logic circuit LG9, and outputs the selected data signal to the memory macro 110 via the conversion unit 120. .
FIG. 15 is a circuit diagram showing a configuration of the memory input / output unit 140. Referring to the figure, the memory input / output unit 140 has one 1: 2 demultiplexer 141 and three 2: 1 multiplexers 142. These 1: 2 demultiplexers 141 and 2: 1 multiplexers 142 receive clock signals having the same phase.
The 1: 2 demultiplexer 141 converts the read data signal, which is a serial signal output from the switch fabric 130, into parallel 16-bit read data signals for the upper logic macro 151 A and the lower logic macro 151 B. The 1: 2 demultiplexer 141 inputs the parallel-converted read data signal to the upper logic macro 151A and the lower logic macro 151B.
The 16-bit write data signal output from the upper logic macro 151A and the 16-bit write data signal output from the lower logic macro 151B are serially converted by the 2: 1 multiplexer 142. This serialized write data signal is input to the switch fabric 130 and transferred to the memory macro 110.
The 14-bit address signal output from the upper logic macro 151A and the 14-bit address signal output from the lower logic macro 151B are serially converted by the 2: 1 multiplexer 142 and input to the switch fabric 130. The
Similarly, the 2-bit command signal output from the upper logic macro 151A and the 2-bit command signal output from the lower logic macro 151B are serially converted by the 2: 1 multiplexer 142 and input to the switch fabric 130. Is done.
Here, the configuration of the 1: 2 demultiplexer 141 is the same as the configuration of the 1: 2 demultiplexer 122 shown in FIG. The configuration of the 2: 1 multiplexer 142 is the same as that of the 2: 1 multiplexer 121 shown in FIG.
In this embodiment, the memory macro 110 is a 1k word, 16-bit SRAM macro, but may be of any word and bit configuration.
In the present embodiment, the memory in the memory macro 110 is an SRAM macro, but it may be a DRAM (Dynamic Random Access Memory). In the case of a DRAM, since the circuit area of the DRAM is small, a larger capacity memory can be mounted. In addition, the memory of the memory macro may be a non-volatile memory such as a flash memory, an MRAM (Magnetic RAM), or a ReRAM (Resistance Random Access Memory). By using a non-volatile memory, it is possible to stop the power supply of a memory area that is not temporarily used and enter a power saving mode.
In this embodiment, the memory macros are arranged in a 4 × 4 two-dimensional array, but the array size may be other configurations.
In this embodiment, the memory input / output unit 140 is configured to perform parallel conversion of read data (serial signal) and serial conversion of write data (parallel signal). However, the logic macro 151 performs such conversion. Also good.
In the present embodiment, the 2: 1 multiplexer 121 is configured to perform serial conversion of parallel signals using transistors (TR1, TR2, TR3, and TR4) and logic gates (N1, B1). However, the 2: 1 multiplexer 121 is not limited to the configuration using these components or circuits. As shown in the timing chart of FIG. 6, if the function of multiplexing the signal output from the memory macro into the serial signal in a time division manner and transferring at a multiple speed can be realized so as not to reduce the throughput, other circuits can be realized. Alternatively, serial conversion may be performed using parts.
In the present embodiment, the 1: 2 demultiplexer 122 is configured to perform parallel conversion of serial signals using a high-through latch (LH1) and flip-flops (FF1, FF2). Is not limited to the configuration using these components or circuits. As shown in the timing chart of FIG. 10, in parallel conversion, if the period for outputting a parallel signal can be returned to the period before serial conversion, parallel conversion is performed using another component or circuit. Also good.
In this embodiment, the two

memory macros

110A and 110B share one switch fabric 130. However, more than two memory macros (circuit blocks) share one switch fabric. It is good also as a structure.
As described above, according to the present embodiment, signals input / output by a plurality of circuit blocks such as a memory macro are converted into serial signals, and the serial signals are transferred by the switch fabric. Can share one switch fabric. As a result, the area overhead due to the switch fabric and the wiring around the switch fabric can be reduced. In addition, the reduction in area overhead reduces the placement cost of the switch fabric and the like. Moreover, since many wirings can be ensured by the limited chip area, the performance of the programmable device can be improved.
For example, in the case of the programmable memory device 100 according to the present embodiment, two

memory macros

110A and 110B share one switch fabric 130. Therefore, the number of switch fabrics can be halved as compared with the case where a switch fabric is provided for each memory macro, and the number of horizontal and vertical two-dimensional mesh wirings between switch fabrics is also halved. Thus, these area overheads are very small.
In the parallel-serial conversion, the conversion unit 120 transfers signals output from the plurality of memory macros 110 to the switch fabric 130 at a speed twice the transfer speed. Therefore, the throughput of the programmable memory device 100 does not decrease even by parallel-serial conversion.
In the serial-parallel conversion, the conversion unit 120 returns the transfer speed of the serial signal output from the switch fabric 130 to the speed before conversion and inputs it to the plurality of memory macros 110, so that the signal processing in the memory macro is performed. There will be no hindrance.
The conversion unit 120 includes a 1: 2 demultiplexer 122. The 1: 2 demultiplexer 122 includes a high-through latch LH1 that holds a signal at a predetermined time output from the switch fabric 130, and flip-flops FF1 and FF2. . The flip-flops FF1 and FF2 store the signal output from the switch fabric 130 and the signal held by the high-through latch LH1 at the same time, and input the stored signals to the

memory macros

110A and 110B, respectively. Thus, serial-parallel conversion can be realized with an extremely simple configuration.
[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 16 is a circuit diagram illustrating a configuration of the 1: 2 demultiplexer 222 included in the conversion unit included in the programmable memory device of the present embodiment. Referring to the figure, the programmable memory device of the present embodiment is different from the programmable memory device of the first embodiment in that the configurations of the conversion unit and the memory macro are different.
The 1: 2 demultiplexer 222 according to the present embodiment is a circuit that converts a serial signal into a parallel signal, and does not include the flip-flops FF1 and FF2, but includes only the high-through latch LH1. The high-through latch LH1 latches a signal from the switch fabric while the clock signal is at a low level. The 1: 2 demultiplexer 222 according to the present embodiment includes a clock synchronous memory macro that is a memory macro having a clock input terminal. The upper clock synchronous memory macro 119A in FIG. 16 takes in the signal output from the high-through latch LH1 in synchronization with the clock signal. The lower clock synchronous memory macro 119B in FIG. 16 takes in the signal output from the switch fabric 130 in synchronization with the clock signal.
As described above, according to the present embodiment, the conversion unit holds the signal at a predetermined time output from the switch fabric by the high-through latch LH1. Then, the

synchronous memory macros

119A and 119B store the signal output from the switch fabric 130 or the signal held by the high-through latch LH1 at the same time. This eliminates the need for flip-flops, allows a serial signal to be converted into a parallel signal with a simpler configuration, and reduces manufacturing costs.
[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 17 is a circuit diagram showing a configuration of the conversion unit 220 included in the programmable memory device of the present embodiment. Referring to the figure, the programmable memory device of the present embodiment has the same configuration as that of the programmable memory device 100 of the first embodiment except that the configurations of the conversion unit and the memory macro are different.
The converter 220 of this embodiment is a circuit that converts a serial signal into a parallel signal, and includes a NOT gate N2 instead of the flip-flops FF1 and FF2 and the high-through latch LH1. The NOT gate N2 inverts the clock signal and outputs it to the lower clock synchronous memory macro 119B. The write data signal output from the switch fabric 130 is branched and input to the upper clock synchronous memory macro 119A and the lower clock synchronous memory macro 119B.
Since each of the clock

synchronous memory macros

119A and 119B captures the write data signal in synchronization with the clock signals having opposite phases, only the data signal to be written can be extracted.
As described above, according to the present embodiment, the conversion unit 220 outputs clock signals having opposite phases to the

memory macros

119A and 119B, and the

memory macros

119A and 119B are synchronized with these clock signals. Capture. Therefore, a flip-flop circuit and a high-through latch circuit are not necessary. As a result, serial signals can be converted into parallel signals with a simpler configuration, thereby reducing manufacturing costs.
[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 18 is a circuit diagram showing a configuration of the switch fabric 230 of the present embodiment. Referring to the figure, the switch fabric 230 of this embodiment is different from that of the first embodiment in that one circuit having both a function of controlling a read data signal and a function of controlling a write data signal is mounted. Different.
Referring to FIG. 18, the switch fabric 230 includes selectors SE1c, SE2c, SE3c, SE4c, and SE5c, and a selection logic circuit LG1c, instead of the read data control circuit 131 and the write data control circuit 132 in the first embodiment. LG2c, LG3c, LG4c, and LG5c.
That is, the input direction or the output direction differs between the write data and the read data in the switch fabric. Therefore, when the memory read operation and the memory write operation are not performed simultaneously in the same memory macro, the read data control circuit and the write data control circuit for controlling the connection direction can be shared by one circuit.
The selectors SE1c, SE2c, SE3c, and SE4c receive the read data signal and write data signal from the three adjacent switch fabrics and the data signal from the memory block 110, respectively, except for the output direction. The selectors SE1c, SE2c, SE3c, and SE4c select any one of the four input signals according to the control of the selection logic circuits LG1c, LG2c, LG3c, LG4c, and LG5c and output them to the switch fabric.
A read data signal or a write data signal from four

adjacent switch fabrics

230U, 230D, 230L, and 230R is input to the selector SE5c. The selector SE5c selects any one of the four input signals according to the control of the selection logic circuit LG5c and outputs the selected signal to the conversion unit 120.
As described above, according to the present embodiment, the write data signal control process and the read data signal control process can be used in a single circuit. Therefore, the number of parts of the switch fabric can be reduced, or the scale of the switch fabric circuit can be reduced.
[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 19 is a block diagram showing the configuration of the programmable memory device 300 of this embodiment. Referring to the figure, the programmable memory device 300 according to the present embodiment is different from the programmable memory device 100 according to the first embodiment in that four memory macros 310 share one switch fabric 330. Here, the four memory macros sharing one switch fabric 330 are an upper left memory macro 310A, an upper right memory macro 310B, a lower left memory macro 310C, and a lower right memory macro 310D, respectively.
Referring to FIG. 19, the programmable memory device 300 includes the conversion unit 320 instead of the conversion unit 120, and the programmable memory device 300 includes the memory input / output unit 340 instead of the memory input / output unit 140. The configuration is the same as that of the memory device 100. That is, the switch fabric 330 is arranged in a two-dimensional array, and a part of the switch fabric 330 is connected to the logic macro 351 constituting the logic device 350 via the memory input / output unit 340. In this embodiment, as shown in FIG. 19, 16 memory macros 310 are arranged in a 4 × 4 two-dimensional array.
The conversion unit 320 includes one 4: 1 multiplexer 321 and three 1: 4 demultiplexers 322 instead of the 2: 1 multiplexer and the 1: 2 demultiplexer used in the first embodiment.
FIG. 20 is a circuit diagram showing a configuration of the 4: 1 multiplexer 321 of the present embodiment. Referring to the figure, the 4: 1 multiplexer 321 includes AND gates AD1, AD2, AD3, and AD4, transistors TR5, TR6, TR7, and TR8, and a buffer B2.
The AND gate AD1 receives a clock signal and a signal obtained by inverting a clock signal obtained by advancing the phase of the clock signal by 90 degrees (hereinafter referred to as “90 ° shift clock signal”). A clock signal and a 90 ° shift clock signal are input to the AND gate AD2. A signal obtained by inverting the clock signal and a 90 ° shifted clock signal are input to the AND gate AD3. The AND gate AD4 receives a signal obtained by inverting the clock signal and a signal obtained by inverting the 90 ° shift clock signal.
AND gates AD1, AD2, AD3, and AD4 output the logical product of the input signals to the gate electrodes of transistors TR5, TR6, TR7, and TR8, respectively.
Read data from the upper left memory macro 310A is input to the source electrode of the transistor TR5. Read data from the upper right memory macro 310B is input to the source electrode of the transistor TR6. Read data from the lower left memory macro 310C is input to the source electrode of the transistor TR7. Read data from the lower right memory macro 310D is input to the source electrode of the transistor TR8.
The transistors TR5, TR6, TR7, and TR8 output the signal input to the source electrode to the buffer B1 when the signal input to the gate electrode is at a high level.
The buffer B2 adjusts the voltage level of the input signal and outputs it to the switch fabric 330.
FIG. 21 is a Carnot diagram illustrating the operation of the 4: 1 multiplexer 321. Referring to the figure, when the clock signal Clk1 is at the high level (1) and the 90 ° shift clock signal Clk2 is at the low level (0), only the transistor TR5 is turned on. Therefore, the 4: 1 multiplexer 321 outputs the read data (UL) from the upper left memory macro 310 A to the switch fabric 330.
When both the clock signal Clk1 and the 90 ° shift clock signal Clk2 are at the high level (1), only the transistor TR6 is turned on. Therefore, the 4: 1 multiplexer 321 outputs the read data (UR) from the upper right memory macro 310 B to the switch fabric 330.
When the clock signal Clk1 is at a low level (0) and the 90 ° shift clock signal Clk2 is at a high level (1), only the transistor TR7 is turned on. Therefore, the 4: 1 multiplexer 321 outputs the read data (LL) from the lower left memory macro 310C to the switch fabric 330.
When the clock signal Clk1 and the 90 ° shift clock signal Clk2 are both low level (0), only the transistor TR8 is turned on. Therefore, the 4: 1 multiplexer 321 outputs the read data (LR) from the lower right memory macro 310 D to the switch fabric 330.
FIG. 22 is a signal waveform diagram showing the operation of the 4: 1 multiplexer 321. Referring to the figure, when the clock signal Clk1 is at the high level and the 90 ° shift clock signal Clk2 is at the low level, the 4: 1 multiplexer 321 outputs the read data UL from the upper left memory macro 310A to the switch fabric 330 as the signal Q. To do.
When both the clock signal Clk1 and the 90 ° shift clock signal Clk2 are at the high level, the 4: 1 multiplexer 321 outputs the read data UR from the upper right memory macro 310B to the switch fabric 330 as the signal Q.
When the clock signal Clk1 is at the low level and the 90 ° shift clock signal Clk2 is at the high level, the 4: 1 multiplexer 321 outputs the read data LL from the lower left memory macro 310C to the switch fabric 330 as the signal Q.
When both the clock signal Clk1 and the 90 ° shift clock signal Clk2 are at the low level, the 4: 1 multiplexer 321 outputs the read data from the lower right memory macro 310D as the signal Q to the switch fabric 330.
As described above, when the 4: 1 multiplexer 321 serially converts the read data signal, the serial signal transfer speed is set to four times that before the conversion, so that the serial conversion does not reduce the throughput.
FIG. 23 is a circuit diagram showing a configuration of the 1: 4 demultiplexer 322 of the present embodiment. Referring to the figure, the 1: 4 demultiplexer 322 has high-through latches LH2 and LH3 and flip-flops FF3, FF4, FF5, FF6, and FF7.
The write data signal from the switch fabric 330 is input to the flip-flops FF3 and FF7 and the high through latches LH2 and LH3.
The flip-flop FF3 transparently outputs the input signal to the flip-flop FF4 when the 90 ° shift clock signal Clk2 is at the rising edge, and outputs a hold value when the 90 ° shift clock signal Clk2 is at the falling edge. When the clock signal Clk1 is at the rising edge, the flip-flop FF4 transparently outputs the write data signal to the upper left memory macro 310A and holds the output for a predetermined time.
The high through latch LH2 transparently outputs an input signal to the flip-flop FF5 when the clock signal Clk1 is at a high level, and outputs a hold value when the clock signal Clk1 is at a low level. When the clock signal Clk1 reaches the rising edge, the flip-flop FF5 transparently outputs the write data signal to the upper right memory macro 310B and holds the output for a predetermined time.
The high-through latch LH3 transparently outputs a write data signal to the flip-flop FF6 when the 90 ° shift clock signal Clk2 is high level, and outputs a hold value when the 90 ° shift clock signal Clk2 is low level. The flip-flop FF6 transparently outputs the write data signal to the lower left memory macro 310C when the clock signal Clk1 becomes the rising edge, and outputs the hold value when the clock signal Clk1 becomes the falling edge.
When the clock signal Clk1 becomes a rising edge, the flip-flop FF7 transparently outputs the write data signal to the lower right memory macro 310D and holds the output for a predetermined time.
As described above, since the input signals are latched by the high-through latches LH2 and LH3 synchronized with the clock signal Clk2 whose phase is shifted by 90 degrees, each memory macro 310 is a data signal to be written from the serial signal output from the switch fabric 330. Can only capture.
Since the 1: 4 demultiplexer 322 holds the output value with flip-flops (FF4, FF5, FF6, and FF7), the transfer rate of the serial signal from the switch fabric 330 can be returned to the pre-conversion rate.
FIG. 24 is a signal waveform diagram showing the operation of the 1: 4 demultiplexer 322. Referring to the figure, the 1: 4 demultiplexer 322 outputs the output FFQ by the 90 ° shift clock signal Clk2 of the flip-flop FF3 as the write data AQ to the upper left memory macro 310A in synchronization with the clock signal Clk1. Further, the output LHQ1 from the clock signal Clk1 of the high-through latch LH2 is output as write data BQ to the upper right memory macro 310B in synchronization with the clock signal Clk1. Further, the output LHQ2 by the 90 ° shift clock signal Clk2 of the high-through latch LH3 is output as write data CQ to the lower left memory macro 310C in synchronization with the clock signal Clk1. The write data D output from the switch fabric 330 is output as write data DQ to the lower right memory macro 310D in synchronization with the clock signal Clk1.
As described above, according to the present embodiment, since the four memory macros 310 can share one switch fabric 330, the area overhead of the switch fabric and wiring is further reduced.
[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. FIG. 25 is a circuit diagram illustrating a configuration of the 1: 4 demultiplexer 323 included in the conversion unit included in the programmable memory device of the present embodiment. Referring to the figure, the programmable memory device of the present embodiment is different from the programmable memory device of the fifth embodiment in that the configurations of the conversion unit and the memory macro are different.
The 1: 4 demultiplexer 323 of the present embodiment is a circuit that converts a serial signal into a parallel signal, does not have the flip-flops FF4, FF5, FF6, and FF7, and includes a flip-flop FF3, high-through latches LH2 and LH3, Have only. Further, the 1: 4 demultiplexer 323 of this embodiment has a clock synchronous memory macro that is a memory macro having a clock input terminal. The upper left clock synchronous memory macro 311A, upper right clock synchronous memory macro 311B, lower left clock synchronous memory macro 311C, and lower right clock synchronous memory macro 311D in FIG. 25 are 1: 4 demultiplexers in synchronization with the clock signal Clk1. The signal output from 323 is captured.
By configuring the circuit in this way, each memory macro can capture only data to be written.
As described above, according to the present embodiment, the conversion unit holds the signal at a predetermined time output from the switch fabric 330 by the high-through latches LH2 and LH3. The

memory macros

311A, 311B, 311C, and 311D store the data signals output from the switch fabric 330 and the data signals output from the flip-flop FF3 and the high-through latches LH2 and LH3 at the same time. Therefore, the flip-flops FF4 to FF7 for controlling the data output are not necessary, and the serial signal can be converted into the parallel signal with a simpler configuration, so that the manufacturing cost is reduced.
[Seventh Embodiment]
Next, a seventh embodiment of the present invention will be described. FIG. 26 is a circuit diagram illustrating a configuration of the 1: 4 demultiplexer 324 included in the conversion unit included in the programmable memory device of the present embodiment. Referring to the figure, the programmable memory device of the present embodiment has the same configuration as that of the programmable memory device of the sixth embodiment except that the configurations of the conversion unit and the memory macro are different.
The 1: 4 demultiplexer 324 of this embodiment does not have flip-flops (FF4, FF5, FF6, FF7, and FF8) and high-through latches (LH2, LH3), and branches write data from the switch fabric 330. Output to each clock synchronous memory macro. The 1: 4 demultiplexer 324 outputs a predetermined clock signal Clk1 to the upper left clock synchronous memory macro 311A. Further, the 1: 4 demultiplexer 324 converts the clock signal Clk1 and the clock signal having a phase difference of 90 degrees, 180 degrees, and 270 degrees into the upper right clock synchronized memory macro 311B, the lower left clock synchronized memory macro 311C, and the lower right clock synchronized. Output to the type memory macro 311D.
The upper left clock synchronous memory macro 311A of this embodiment takes in the signal input by the 1: 4 demultiplexer 324 in synchronization with the clock signal Clk1. The upper right clock synchronous memory macro 311B of the present embodiment takes in the signal input by the 1: 4 demultiplexer 324 in synchronization with the clock signal that is 90 degrees out of phase with the clock signal Clk1. Further, the lower left clock synchronous memory macro 311C and the lower right clock synchronous memory macro 311D are synchronized with clock signals that are 180 degrees and 270 degrees out of phase with the clock signal Clk1, respectively, by the 1: 4 demultiplexer 324. Capture the input signal.
Since each clock synchronous memory macro captures a signal in synchronization with clock signals having different phases, only the data to be written can be extracted.
As described above, according to this embodiment, the 1: 4 demultiplexer 324 configuring the conversion unit outputs clock signals having different phases to the clock

synchronous memory macros

311A, 311B, 311C, and 311D. Each clock synchronous memory macro captures a signal in synchronization with these clock signals. This eliminates the need for flip-flops and high-through latches, converts serial signals to parallel signals with a simpler configuration, and reduces manufacturing costs.
[Eighth Embodiment]
Next, an eighth embodiment of the present invention will be described. FIG. 27 is a perspective view showing a configuration of the laminated device 400 of the present embodiment. Referring to the figure, the second embodiment is different from the first embodiment in that a programmable memory device substrate 420 on which a programmable memory device is arranged is stacked on a logic device substrate 410 on which a logic device is arranged. The logic device substrate 410 has a logic input / output unit 430 overlapping the memory input / output unit 440, and data is transmitted and received between these input / output units.
As shown in the first embodiment, when the programmable memory device 100 and the logic device 150 are integrated on the same substrate, the memory input / output unit 140 is arranged around the programmable memory device 100. However, in this embodiment, the programmable memory device and the logic device are arranged on separate substrates, and these substrates are stacked, so that the memory input / output unit is arranged not only around the programmable memory device but also inside. It becomes possible.
As described above, according to the present embodiment, since the programmable memory device substrate 420 is stacked on the logic device substrate 410, the memory input / output unit 440 can also be disposed inside the programmable memory device substrate 420. Therefore, the amount of data transfer between the substrates can be increased.
[Ninth Embodiment]
Next, a ninth embodiment of the present invention will be described. FIG. 28 is a block diagram showing the configuration of the programmable processor device 500 of this embodiment. Referring to the figure, the programmable processor device 500 of the present embodiment is different from the first embodiment in that it has a processor 551 as a circuit block instead of a memory macro.
Referring to FIG. 28, the processor 551 of this embodiment includes a RISC (Reduced Induction Set Computer) type processor 551 arranged in a 4 × 4 two-dimensional array instead of the memory macro. Around the programmable processor device 500, a memory device 510 including a memory macro 511 is arranged.
A two-dimensional mesh wiring for transferring a data signal from the processor 551 to the processor input / output unit 540 or from the processor input / output unit 540 to the processor 551 is formed. A switch fabric 530 for controlling the signal transfer direction of the upper, lower, left, and right of the wiring is disposed at the intersection of the wiring. The switch fabric 530 is shared by the upper and lower processors 551, and the data signal from the processor 551 is serially converted by a 2: 1 multiplexer included in the conversion unit 520. In this embodiment, 8 switch fabrics 530 of 2 × 4 are arranged for 16 processors 551 of 4 × 4. That is, the number of switch fabrics 530 is halved compared to the case where switch fabrics are arranged for all processors. In addition, for the two-dimensional mesh wiring connecting the switch fabrics 530, the number of horizontal wirings is halved.
As described above, according to the present embodiment, the area overhead of the switch fabric and the wiring in the programmable processor device can be reduced.
The present invention is not limited to the above-described embodiment, and various modifications are possible within the scope of the invention described in the claims, and it is also included within the scope of the present invention. Not too long.
This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-236783 for which it applied on September 16, 2008, and takes in those the indications of all here.

The present invention can be applied to a semiconductor programmable device in which a plurality of circuit blocks including processors and memories are integrated.

Claims

A plurality of circuit blocks for inputting and outputting signals;
A switch fabric that mutually transfers signals input and output by the circuit block;
A signal obtained by parallel-serial conversion of a plurality of signals output from the plurality of circuit blocks into one signal is used in the switch fabric, and a plurality of signals obtained by serial-parallel conversion of the signals output from the switch fabric are A conversion unit used for the circuit block;
A semiconductor programmable device having:
The signal obtained by the parallel-serial conversion by the conversion unit is a multiple of the speed output from the circuit block, and the signal obtained by the serial-parallel conversion is a signal output from the switch fabric. 2. The semiconductor programmable device according to claim 1, wherein the semiconductor programmable device has a speed that is 1 / multiple.
The serial-parallel conversion of the conversion unit is
A holding circuit for holding a signal at a predetermined time output from the switch fabric;
A plurality of storage circuits for storing the signal output from the switch fabric and the signal held by the holding circuit at the same time, and inputting each stored signal to each of the circuit blocks;
The semiconductor programmable device of Claim 1 or 2 implement | achieved by the serial-parallel conversion circuit provided with.
The serial-parallel conversion of the conversion unit is
A signal at a predetermined time output from the switch fabric is held by the holding circuit, and the plurality of circuit blocks store signals output from the switch fabric or signals held by the holding circuit at the same time. The semiconductor programmable device according to claim 1, which is realized by:
The serial-parallel conversion of the conversion unit is
Using a clock signal synchronized with the operation of the circuit block and a shift clock signal having a phase different from that of the clock signal, a demultiplexer that extracts a plurality of signals multiplexed in a time division manner with the signal output from the switch fabric The semiconductor programmable device according to claim 1 or 2, which is realized by a circuit.
The serial / parallel conversion of the conversion unit is:
The conversion unit outputs a plurality of clock signals having different phases to the plurality of circuit blocks, and the plurality of circuit blocks capture the signals output from the switch fabric in synchronization with the plurality of clock signals. The semiconductor programmable device according to claim 1, wherein
7. The device according to claim 1, further comprising a device input / output unit that serial-parallel converts the signals transferred by the switch fabric into a plurality of signals and inputs / outputs the converted signals to / from another device. The semiconductor programmable device according to 1.
The semiconductor programmable device according to claim 7, wherein the semiconductor programmable device is stacked on the other device.
The semiconductor programmable device according to claim 1, wherein at least one of the plurality of circuit blocks is a memory macro.
The semiconductor programmable device according to claim 1, wherein at least one of the plurality of circuit blocks is a processor.
A method for controlling a semiconductor programmable device comprising: a plurality of circuit blocks that input and output signals; and a switch fabric that mutually transfers signals input and output by the circuit blocks,
A signal obtained by parallel-serial conversion of a plurality of signals output from the plurality of circuit blocks into one signal is used in the switch fabric,
A method for controlling a semiconductor programmable device, wherein the circuit block uses a plurality of signals obtained by serial-parallel conversion of signals output from the switch fabric.