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WO2010024674A1 - Solder interconnection - Google Patents

Solder interconnection Download PDF

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Publication number
WO2010024674A1
WO2010024674A1 PCT/NL2009/050515 NL2009050515W WO2010024674A1 WO 2010024674 A1 WO2010024674 A1 WO 2010024674A1 NL 2009050515 W NL2009050515 W NL 2009050515W WO 2010024674 A1 WO2010024674 A1 WO 2010024674A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip device
stacked chip
access terminals
substrate
providing
Prior art date
Application number
PCT/NL2009/050515
Other languages
French (fr)
Inventor
Jan Eite Bullema
Original Assignee
Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno filed Critical Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno
Publication of WO2010024674A1 publication Critical patent/WO2010024674A1/en

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Definitions

  • the invention relates to the field of stacking 3D electrically interconnected chip devices such as three-dimensional integrated circuits.
  • the present invention also relates to a method of providing electrical interconnections for such devices.
  • Full 3D design of electrically interconnected silicon layers is the current driver for stacking of ICs. Through this technology, the number of interconnect layers can be reduced, while speed is increased by shorter interconnect lengths and limited number of repeaters. In addition, less Si real-estate makes production cost effective.
  • To provide a 3D interconnected chip structure typically, multiple silicon substrates are provided in stacked arrangement so that at least two silicon substrates are interconnected. Examples of such arrangements are die-on-die, die-on-wafer or wafer-on- wafer arrangements. In such arrangement typically at least one of said substrates has integrated circuitry and access terminals to said integrated circuitry on at least a side facing the other substrate. Such multilayered stacks require bonding of various stacked substrates.
  • a 3D electrically interconnected, stacked chip device comprising: first and second silicon substrates at least one of said substrates having integrated circuitry and access terminals to said integrated circuitry on at least a side facing the other substrate; a mechanical connector for mechanically connecting said first and second silicon substrates in a stacked arrangement; electrical connectors for providing an electrical connection to said access terminals of at least one substrate to provide a 3D interconnected chip structure; wherein said electrical connectors are provided as metal connections that are permanently fluid.
  • a method of providing a 3D electrically interconnected, stacked chip device comprising: providing first and second silicon substrates at least one of said substrates having integrated circuitry and access terminals to said integrated circuitry on at least a side facing the other substrate; providing a fluid metal to said access terminals as a permanent fluid to provide electrical connectors for providing an electrical connection to said access terminals; and mechanically connecting said first and second silicon substrates in a stacked arrangement.
  • Advantages may include reduction of mechanical stress in the chip arrangement, reducing the number of process steps and providing less breakdown risk in the manufacturing process due to obviation of temperature process steps. Furthermore, due to the wetting property of the fluid metal, self alignment of the electrical connections may be promoted, that is, the fluid metal will solely adhere to the access terminals.
  • Figure 1 shows a schematic side view impression of typical production steps for a 3D electrically interconnected, stacked chip device according to an aspect of the invention
  • Figure 2 shows a typical arrangement of a 3D electrically interconnected, stacked chip device according to an aspect of the invention
  • Figure 3 shows an example of a process-flow for manufacture of a 3D electrically interconnected chip device according to an aspect of the invention.
  • Gallium is used in the semiconductor industry as a temporary interconnect in wafer probing and testing for its low melting temperature (circa 30 degrees Celsius).
  • liquid solders are described [Dag Ausen en Frodis Oderwald, Interconnections for Harsh Environments] that are liquid during their use at elevated temperatures, to overcome thermo mechanical stress issues.
  • An example is In52Sn48 as described by Mannan with a melting temperature of approximately 118 degrees Celsius.
  • Figure 1 shows an embodiment according an aspect of the invention showing a schematic side view impression of typical production steps for 3D electrically interconnected, stacked chip device 100 according to an aspect of the invention.
  • a flip chip 20 bonding to a base substrate 30 is shown, using the electrical interconnects 40 according to an aspect of the invention.
  • First substrate 30 is provided as a base substrate.
  • Substrate 30 has an isolating top layer 31.
  • cavities 32 may be formed to provide access to access terminals 33 of the substrate 30.
  • the access terminals 33 are provided distributed over a face of a silicon substrate 30.
  • a resin type sticky underfill coating 50 is applied to the substrate 30.
  • the underfill coating 50 has openings 51 aligned with the cavities 32 of the top layer 31.
  • the step is executed of providing a fluid metal 41 to said access terminals 33 as a permanent fluid to provide electrical connectors 40 for providing an electrical connection to said access terminals 33.
  • the term 'permanently fluid' refers to the permanency of the metal fluid phase during the manufacturing process and in normal operating temperatures in ambient temperature ranges, for example, temperatures ranging from 0 0 C to 80 0 C, or preferably, 0° C to 30 0 C.
  • One way to provide the fluid metal 41 is via a fine pitch wafer bumping process using a mold. Another way of providing the fluid metal 41 is to align a print head and administer the fluid via a jetting technique of fluid metal jets or droplets provided via the print head. A further way could be providing a cavity 51, 32, as shown in the present example, for example, in a resist layer 31 or a lithographic lacquer, wherein fluid metal 41 may be inserted via a blading technique. It is noted that by the wetting property of the fluid metal 41 and the terminals 33, the terminals 33 will have a terminal surface energy to bond to said fluid metal connections 40. This can be further enhanced by providing a wetting agent.
  • a top substrate 20 is provided, in this example a substrate of a flip chip type.
  • other types of silicon substrates may be provided, typically, substrates of a silicon through via type.
  • the top substrate 20 is provided with protrusions 21 that correspond to the cavities 32 of the first substrate.
  • FIG 2 shows a detailed side view of an exemplary embodiment of a 3D electrically interconnected chip device 200.
  • the device 200 has typically an overall thickness OT of 1 mm is embedded on a substrate 201 having a typical thickness ST of 160 um in a mold resin 202.
  • the device 200 can be packed on a printed circuit board using solder bumps 210, typically having a ball diameter of about 0.4 mm and a pitch of about 0.8 mm.
  • embedded circuitry 220 may be provided in the substrate 201.
  • one of the device parts 230 may comprise a flip chip type arrangement as illustrated in Figure 1, in another device part 240 a number of stacked through silicon via layers 270 is provided, typically having a thickness LT of 25 um provided in electrical connection to substrate terminals 260.
  • said electrical connectors are provided as vias 250 in said through silicon via layer 270 electrically connecting said access terminals by means of fluid metal connections.
  • Figure 3 is an example of process-flow for the manufacturing a 3D electrically interconnected chip devices according to an aspect of the invention.
  • the inventive electrical connection can be provided in a single process step 305.
  • the inventive method can be easily integrated in conventional manufacturing steps.
  • the invention provides a possibility for providing an alternative for the conventional electrical connection technology that provides a high bonding speed in an advantageous temperature range, wherein, as the material stays in the liquid phase thermo mechanical damage is reduced.
  • this technique enables the potential for repairing a stack with a defective chip since de-assembly can be done conveniently.
  • permanently fluid is not limited to a specified lower temperature range, but may encompass all kinds of typical operating for 3D electrically interconnected chip devices as commonly practical, that is, at least in ambient temperatures down to for example 10 0 C or even as low as 5 0 C.
  • permanently fluid is meant to indicate that for typical operation temperatures in the normal ambient temperature range, the electrical connection is and remains fluid.
  • mercury replacement alloys such as Gallium alloys or Indium alloys
  • an Gallium alloy including any of the group of Indium, Tin and Zinc such as 6lGa25Inl3SnlZn (by volume) which can be provided having a density of 6.5 g/cm3 and a melting range of 6-7 0 C.
  • 6lGa25Inl3SnlZn by volume
  • 62.5Ga/21.5In/16Sn by volume
  • 75.5Ga/24.5In can be used, having a melting range of 16 0 C.
  • Other low melting point Indium alloys as Sn Bi In or In Bi may be used having melting ranges of about 72 0 C.
  • the melting range can be a single melting point in the case of a eutectic alloy.
  • an oxide preventing agent can be administered, which prevents the forming of oxide skins in the fluid which may degrade the fluidity and electrical connectivity.
  • Such agent may include any of the group of Zn, Mg and Sb.
  • an anti-solidifying agent may be added such as, for example, including carbon nano tubes.
  • the metal terminals of the terminals may be optimized for wetting behavior of the metal fluid and which prevent degradation or corruption of the internal circuitry.
  • a barrier layer can be provided of Tantalum Nitride, Niobium or Nickel to prevent diffusion or dendrite forming.
  • a metallization of Au can be provided to optimize wetting behaviour; additionally, Ag and Nb can be used.
  • Under Bump Metallurgy may include a wetting agent that is formed by a layer stack of any one of: (a) Ni-Au (adhesion barrier wetting protection having Au as top layer interfacing with the fluid metal)
  • the manufacturing may be carried out in a reducing atmosphere, for example, after plasma treatment of for example hydrogen of the substrates, in particular, the access terminals.
  • the process may be carried out in an inert atmosphere or a reducing atmosphere (for example, hydrogen or HCOOH).
  • a reducing atmosphere for example, hydrogen or HCOOH.
  • the presence of oxygen may in some cases help to create an oxide skin that may have elastic deformation properties which can be useful for providing micro bumps typically having a pitch less than 100 micron.
  • eutectic Gallium Indium (eGaln) bumps having a skin of Ga2O3 may be formed with a typical pitch of 60 micron.
  • the liquid solder bonding technology facilitates repair potential en eventual self repair, i.e. the liquid bond has self repairing properties -
  • the liquid solder bump has a high intrinsic reliability

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Abstract

According to an aspect of the invention, there is provided a 3D electrically interconnected, stacked chip device comprising: first and second silicon substrates at least one of said substrates having integrated circuitry and access terminals to said integrated circuitry on at least a side facing the other substrate; a mechanical connector for mechanically connecting said first and second silicon substrates in a stacked arrangement; electrical connectors for providing an electrical connection to said access terminals of at least one substrate to provide a 3D interconnected chip structure; wherein said electrical connectors are provided as metal connections that are permanently fluid. Advantages may include reduction of mechanical stress in the chip arrangement, reducing the number of process steps and providing less breakdown risk in the manufacturing process due to obviation of temperature process steps.

Description

Title: Solder interconnection
FIELD OF THE INVENTION
The invention relates to the field of stacking 3D electrically interconnected chip devices such as three-dimensional integrated circuits. The present invention also relates to a method of providing electrical interconnections for such devices.
BACKGROUND OF THE INVENTION
Full 3D design of electrically interconnected silicon layers is the current driver for stacking of ICs. Through this technology, the number of interconnect layers can be reduced, while speed is increased by shorter interconnect lengths and limited number of repeaters. In addition, less Si real-estate makes production cost effective. To provide a 3D interconnected chip structure, typically, multiple silicon substrates are provided in stacked arrangement so that at least two silicon substrates are interconnected. Examples of such arrangements are die-on-die, die-on-wafer or wafer-on- wafer arrangements. In such arrangement typically at least one of said substrates has integrated circuitry and access terminals to said integrated circuitry on at least a side facing the other substrate. Such multilayered stacks require bonding of various stacked substrates. Both mechanically and electrically, an interconnection between the substrates needs to be established to provide a stacked arrangement. Conventionally, to establish an electrical connection for such devices, metal bumps are provided that can be soldered to an underlying circuit for providing an electrical connection. Other types of bonding are feasible, typically implying specific process steps such thermo compression, oxide bonding and plasma bonding. A desire exists to reduce the number of process steps and to provide an alternative for the present known electrical connections. GB2403173 discusses the use of Indium based solders for electronic packages and flip-chip arrangements, having a lowered melting point. However, in use, still a temperature process step is needed for providing an electrical connection introducing a risk of therm o mechanical damage.
SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a 3D electrically interconnected, stacked chip device comprising: first and second silicon substrates at least one of said substrates having integrated circuitry and access terminals to said integrated circuitry on at least a side facing the other substrate; a mechanical connector for mechanically connecting said first and second silicon substrates in a stacked arrangement; electrical connectors for providing an electrical connection to said access terminals of at least one substrate to provide a 3D interconnected chip structure; wherein said electrical connectors are provided as metal connections that are permanently fluid. According to another aspect of the invention, there is provided a method of providing a 3D electrically interconnected, stacked chip device comprising: providing first and second silicon substrates at least one of said substrates having integrated circuitry and access terminals to said integrated circuitry on at least a side facing the other substrate; providing a fluid metal to said access terminals as a permanent fluid to provide electrical connectors for providing an electrical connection to said access terminals; and mechanically connecting said first and second silicon substrates in a stacked arrangement.
Advantages may include reduction of mechanical stress in the chip arrangement, reducing the number of process steps and providing less breakdown risk in the manufacturing process due to obviation of temperature process steps. Furthermore, due to the wetting property of the fluid metal, self alignment of the electrical connections may be promoted, that is, the fluid metal will solely adhere to the access terminals.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a schematic side view impression of typical production steps for a 3D electrically interconnected, stacked chip device according to an aspect of the invention;
Figure 2 shows a typical arrangement of a 3D electrically interconnected, stacked chip device according to an aspect of the invention; and Figure 3 shows an example of a process-flow for manufacture of a 3D electrically interconnected chip device according to an aspect of the invention.
DETAILED DESCRIPTION OF EMBODIMENTS
It is known that Gallium is used in the semiconductor industry as a temporary interconnect in wafer probing and testing for its low melting temperature (circa 30 degrees Celsius). For high temperature sensors liquid solders are described [Dag Ausen en Frodis Oderwald, Interconnections for Harsh Environments] that are liquid during their use at elevated temperatures, to overcome thermo mechanical stress issues. An example is In52Sn48 as described by Mannan with a melting temperature of approximately 118 degrees Celsius.
Both applications of liquid metals/ alloys as an electrical interconnection differ from the current invention. Use of liquid metal/ alloys in a 3D stacked devices is not obvious for the interconnection expert.
(a) Interconnections for Harsh Environments only liquidify in the use of the product at elevated temperatures. (b) Probing of Wafers with Gallium as interconnect material is applied as a temporary bond.
(c) In these cases a stack of more than two layers is not used. Where in 3D stacking stack up to twenty layers have to be made possible.
Figure 1 shows an embodiment according an aspect of the invention showing a schematic side view impression of typical production steps for 3D electrically interconnected, stacked chip device 100 according to an aspect of the invention. As an example of such a device a flip chip 20 bonding to a base substrate 30 is shown, using the electrical interconnects 40 according to an aspect of the invention.
First substrate 30 is provided as a base substrate. Substrate 30 has an isolating top layer 31. In the isolating top layer 31, cavities 32 may be formed to provide access to access terminals 33 of the substrate 30. The access terminals 33 are provided distributed over a face of a silicon substrate 30.
In a next step, a resin type sticky underfill coating 50 is applied to the substrate 30. Such can be done by stencil printing or any other process step known in the art. The underfill coating 50 has openings 51 aligned with the cavities 32 of the top layer 31. Next, the step is executed of providing a fluid metal 41 to said access terminals 33 as a permanent fluid to provide electrical connectors 40 for providing an electrical connection to said access terminals 33. In this context, the term 'permanently fluid' refers to the permanency of the metal fluid phase during the manufacturing process and in normal operating temperatures in ambient temperature ranges, for example, temperatures ranging from 0 0C to 80 0C, or preferably, 0° C to 30 0C.
One way to provide the fluid metal 41 is via a fine pitch wafer bumping process using a mold. Another way of providing the fluid metal 41 is to align a print head and administer the fluid via a jetting technique of fluid metal jets or droplets provided via the print head. A further way could be providing a cavity 51, 32, as shown in the present example, for example, in a resist layer 31 or a lithographic lacquer, wherein fluid metal 41 may be inserted via a blading technique. It is noted that by the wetting property of the fluid metal 41 and the terminals 33, the terminals 33 will have a terminal surface energy to bond to said fluid metal connections 40. This can be further enhanced by providing a wetting agent.
Additionally, a top substrate 20 is provided, in this example a substrate of a flip chip type. However, other types of silicon substrates may be provided, typically, substrates of a silicon through via type. The top substrate 20 is provided with protrusions 21 that correspond to the cavities 32 of the first substrate. By mechanically connecting said first and second silicon substrates 20, 30 in a stacked arrangement 100 an electrical connection is provided via the fluid metal connections 30.
In summary, following process steps are disclosed:
1. Providing a substrate 30;
2. providing an underfill 50
3. providing cavities 51 in the underfill 50; for example by stencil printing 4. providing a fluid metal 41, for example Galn24.5;
5. filling the cavities 51 with fluid metal 41,
6. probing the cavities;
7. providing a flip chip 20 a second substrate;
8. mechanically attaching the flip chip 20, for example, by thermal curing.
Figure 2 shows a detailed side view of an exemplary embodiment of a 3D electrically interconnected chip device 200. The device 200 has typically an overall thickness OT of 1 mm is embedded on a substrate 201 having a typical thickness ST of 160 um in a mold resin 202. The device 200 can be packed on a printed circuit board using solder bumps 210, typically having a ball diameter of about 0.4 mm and a pitch of about 0.8 mm. In the substrate 201, embedded circuitry 220 may be provided. While one of the device parts 230 may comprise a flip chip type arrangement as illustrated in Figure 1, in another device part 240 a number of stacked through silicon via layers 270 is provided, typically having a thickness LT of 25 um provided in electrical connection to substrate terminals 260. As shown, said electrical connectors are provided as vias 250 in said through silicon via layer 270 electrically connecting said access terminals by means of fluid metal connections.
Figure 3 is an example of process-flow for the manufacturing a 3D electrically interconnected chip devices according to an aspect of the invention. According to an aspect of the invention, the inventive electrical connection can be provided in a single process step 305. Thus the inventive method can be easily integrated in conventional manufacturing steps.
In particular, there are provided that steps of
301 carrier debonding;
302 Wafer thinning; 303 Patterning;
304 through Silicon Via creating;
305 through Silicon Via filling with a permanently fluid metal;
306 Chemical Mechanical Polishing;
307 providing bumps; 308 probing;
309 dicing;
310 inspecting and cleaning;
311 picking and placing - high speed (<0.05 s) without thermal step; 312 die bonding;
313 encapsulating;
314 singulating;
315 end-testing & inspecting; 316 marking; and
317 packing.
In one aspect, the invention provides a possibility for providing an alternative for the conventional electrical connection technology that provides a high bonding speed in an advantageous temperature range, wherein, as the material stays in the liquid phase thermo mechanical damage is reduced.
In addition, this technique enables the potential for repairing a stack with a defective chip since de-assembly can be done conveniently.
In addition, through the wetting properties of the liquid metal to the terminals, self-alignment can be provided reducing mechanical stress problems.
In addition, for reasons of speed of the interconnection process bonding costs are reduced.
Further advantages may include:
- Applicable for both Wafer to Wafer stacking as Die to Die as Die to Wafer Stacking
- Limited compliance of the wafer surface or bumps on the wafers
- High tolerance for uncleanliness of the wafer or die surface; and
- Suitable for Face to Face Stacking and Face to Back stacking.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Furthermore, the skilled person will appreciate that the term permanently fluid used herein is not limited to a specified lower temperature range, but may encompass all kinds of typical operating for 3D electrically interconnected chip devices as commonly practical, that is, at least in ambient temperatures down to for example 10 0C or even as low as 5 0C. Thus, permanently fluid is meant to indicate that for typical operation temperatures in the normal ambient temperature range, the electrical connection is and remains fluid.
Further exemplary embodiments using the liquid solder connection can be for instance mercury replacement alloys such as Gallium alloys or Indium alloys, for example, an Gallium alloy including any of the group of Indium, Tin and Zinc, such as 6lGa25Inl3SnlZn (by volume) which can be provided having a density of 6.5 g/cm3 and a melting range of 6-7 0C. Another example is 62.5Ga/21.5In/16Sn (by volume) having a melting range of 11 0C. Furthermore 75.5Ga/24.5In can be used, having a melting range of 16 0C. Other low melting point Indium alloys as Sn Bi In or In Bi may be used having melting ranges of about 72 0C. It is noted that the melting range can be a single melting point in the case of a eutectic alloy. To optimize the fluidity of the metal fluid, an oxide preventing agent can be administered, which prevents the forming of oxide skins in the fluid which may degrade the fluidity and electrical connectivity. Such agent may include any of the group of Zn, Mg and Sb. Additionally, an anti-solidifying agent may be added such as, for example, including carbon nano tubes.
The metal terminals of the terminals (in the art referenced as under bump metal) may be optimized for wetting behavior of the metal fluid and which prevent degradation or corruption of the internal circuitry. In particular, a barrier layer can be provided of Tantalum Nitride, Niobium or Nickel to prevent diffusion or dendrite forming. A metallization of Au can be provided to optimize wetting behaviour; additionally, Ag and Nb can be used.
Other Under Bump Metallurgy may include a wetting agent that is formed by a layer stack of any one of: (a) Ni-Au (adhesion barrier wetting protection having Au as top layer interfacing with the fluid metal)
(b) Al-Ni-V-Cu (adhesion barrier wetting protection having Cu as top layer interfacing with the fluid metal)
(c) Ag (wetting protection) (d) Nb (wetting protection)
(e) Ti-W (adhesion) - Cu (wetting) - Au (protection having Au as top layer interfacing with the metal fluid)
(f) W (wetting protection)
To further optimize wetting, the manufacturing may be carried out in a reducing atmosphere, for example, after plasma treatment of for example hydrogen of the substrates, in particular, the access terminals. Alternatively, the process may be carried out in an inert atmosphere or a reducing atmosphere (for example, hydrogen or HCOOH). Such atmosphere conditions additionally prevents the oxide skins forming of the metal fluid.
In the alternative the presence of oxygen may in some cases help to create an oxide skin that may have elastic deformation properties which can be useful for providing micro bumps typically having a pitch less than 100 micron. For example, in eutectic Gallium Indium (eGaln) bumps having a skin of Ga2O3 may be formed with a typical pitch of 60 micron.
As non limiting aspects, following advantages of the metal fluid connections may be achieved: - Liquid solder bonding has an advantageous thermal budget (low bonding temperature)
- The liquid solder bonding technology facilitates repair potential en eventual self repair, i.e. the liquid bond has self repairing properties - The liquid solder bump has a high intrinsic reliability
- Liquid solder bonding facilitates a fast (< 1 s) bonding process, necessary for economic viable 3D chip to chip stacking
Other variations to the disclosed embodiments can be understood and by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A 3D electrically interconnected, stacked chip device comprising: first and second silicon substrates at least one of said substrates having integrated circuitry and access terminals to said integrated circuitry on at least a side facing the other substrate; a mechanical connector for mechanically connecting said first and second silicon substrates in a stacked arrangement; electrical connectors for providing an electrical connection to said access terminals of at least one substrate to provide a 3D interconnected chip structure; wherein said electrical connectors are provided as metal connections that are permanently fluid.
2. A stacked chip device according to claim 1, wherein said metal connections comprises a Gallium alloy or an Indium alloy.
3. A stacked chip device according to claim 2, wherein said Gallium alloy further includes any of the group of Indium, Tin and Zinc.
4. A stacked chip device according to claim 1, wherein said access terminals are provided distributed over a face of a silicon substrate; and include a wetting agent having a terminal surface energy adapted to bond to said fluid metal connections.
5. A stacked chip device according to claim 4, wherein the wetting agent is formed by a layer stack of any one of the group of Ni-Au, Al-Ni-V-Cu, Ag, Nb, Ti- W-Cu-Au and W.
6. A stacked chip device according to claim 1, wherein at least one of the substrates comprises a through silicon via layer and said electrical electrical connectors are provided as vias in said through silicon via layer electrically connecting said access terminals.
7. A stacked chip device according to claim 1, wherein said a mechanical connector comprises a layer of underfill resin material attached to said at least one substrate.
8. A stacked chip device according to claim 1, wherein said metal connections include an oxide preventing agent.
9. A stacked chip device according to claim 8, wherein said oxide preventing agent includes any of the group of Zn, Mg and Sb.
10. A stacked chip device according to claim 1, wherein said metal connections comprise an anti-solidifying agent.
11. A stacked chip device according to claim 10, wherein said anti-solidifying agent includes carbon nano tubes.
12. A stacked chip device according to claim 1, wherein said stacked chip arrangement is any of a die-on-die, die-on-wafer or wafer-on-wafer arrangement.
13. A method of providing a 3D electrically interconnected, stacked chip device comprising: providing first and second silicon substrates at least one of said substrates having integrated circuitry and access terminals to said integrated circuitry on at least a side facing the other substrate; providing a fluid metal to said access terminals as a permanent fluid to provide electrical connectors for providing an electrical connection to said access terminals; and mechanically connecting said first and second silicon substrates in a stacked arrangement.
14. A method according to claim 13, wherein said connection is provided by an underfill resin layer; said method further comprising the steps of: coating the underfill resin layer to the first substrate; providing cavities in said underfill layer exposing said access terminals; and filling the cavities of said underfill resin layer with the fluid metal.
PCT/NL2009/050515 2008-09-01 2009-08-27 Solder interconnection WO2010024674A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109273357A (en) * 2018-09-28 2019-01-25 中科芯电半导体科技（北京）有限公司 Improve the method for low doping concentration material surface Ohmic contact and the low doping concentration material of surface growth Ga metal

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5328087A (en) * 1993-03-29 1994-07-12 Microelectronics And Computer Technology Corporation Thermally and electrically conductive adhesive material and method of bonding with same
US5920125A (en) * 1992-11-12 1999-07-06 International Business Machines Corporation Interconnection of a carrier substrate and a semiconductor device
US20060220198A1 (en) * 2005-03-30 2006-10-05 Rajashree Baskaran Semiconductor integrated circuit (IC) packaging with carbon nanotubes (CNT) to reduce IC/package stress
US20070284758A1 (en) * 2006-05-22 2007-12-13 General Electric Company Electronics package and associated method
US20080029850A1 (en) * 2006-08-01 2008-02-07 Qimonda Ag Electrical through contact

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920125A (en) * 1992-11-12 1999-07-06 International Business Machines Corporation Interconnection of a carrier substrate and a semiconductor device
US5328087A (en) * 1993-03-29 1994-07-12 Microelectronics And Computer Technology Corporation Thermally and electrically conductive adhesive material and method of bonding with same
US20060220198A1 (en) * 2005-03-30 2006-10-05 Rajashree Baskaran Semiconductor integrated circuit (IC) packaging with carbon nanotubes (CNT) to reduce IC/package stress
US20070284758A1 (en) * 2006-05-22 2007-12-13 General Electric Company Electronics package and associated method
US20080029850A1 (en) * 2006-08-01 2008-02-07 Qimonda Ag Electrical through contact

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109273357A (en) * 2018-09-28 2019-01-25 中科芯电半导体科技（北京）有限公司 Improve the method for low doping concentration material surface Ohmic contact and the low doping concentration material of surface growth Ga metal
CN109273357B (en) * 2018-09-28 2021-03-23 中科芯电半导体科技（北京）有限公司 Method and material for improving ohmic contact on surface of low-doping concentration material

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