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WO2010017763A1 - 一种终端设备基带处理系统中的匹配滤波电路装置及方法 - Google Patents

一种终端设备基带处理系统中的匹配滤波电路装置及方法 Download PDF

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Publication number
WO2010017763A1
WO2010017763A1 PCT/CN2009/073191 CN2009073191W WO2010017763A1 WO 2010017763 A1 WO2010017763 A1 WO 2010017763A1 CN 2009073191 W CN2009073191 W CN 2009073191W WO 2010017763 A1 WO2010017763 A1 WO 2010017763A1
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WO
WIPO (PCT)
Prior art keywords
unit
matched filter
filter circuit
circuit device
control signal
Prior art date
Application number
PCT/CN2009/073191
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English (en)
French (fr)
Inventor
古艳涛
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to EP09806366.2A priority Critical patent/EP2317823B1/en
Priority to US13/057,647 priority patent/US8526548B2/en
Publication of WO2010017763A1 publication Critical patent/WO2010017763A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/709—Correlator structure
    • H04B1/7093—Matched filter type
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation

Definitions

  • the present invention relates to the field of joint detection algorithm circuits of a baseband processing system of a mobile communication terminal device, and more particularly to a matching filter circuit in a baseband processing system of a terminal device. Improvements in devices and methods. Background technique
  • the conventional detection technology performs signal detection for a single user and treats other users as noise, but when the number of users increases, the signal-to-noise ratio is easily deteriorated, resulting in system performance and The capacity is not satisfactory.
  • the joint detection technology makes full use of all user signals causing multiple access interference and the prior information of related multipaths, and regards the separation of user signals as a unified interrelated joint detection process.
  • the completion has excellent anti-interference performance and reduces the system's requirements for power control accuracy. Therefore, the spectrum resources of the uplink and downlink can be utilized more effectively, and the performance and capacity of the system are significantly improved.
  • the baseband processing algorithm of joint detection is generally used, and an important algorithm circuit, that is, a matching filter circuit, is often included in the joint detection.
  • the serial interference cancellation module performs multi-round multi-cell serial interference cancellation by using the Midamble code sample data in one time slot to obtain a relatively accurate initial channel estimation result.
  • the composite spreading code The generating module scrambles, rotates and conjugates the local channelization code to generate a composite spreading code; and then performs activation detection on all candidate code channels according to the initial channel estimation result and the composite spreading code, and finally determines which code channels will be used as The active code channel is included in the joint detection; secondly, the initial channel estimation result is post-processed to obtain an accurate channel estimation post-processing result; and the convolution between the channel estimation post-processing result and the active code channel composite spreading code is performed.
  • Calculating the V vector on each active code channel then, using the V vector to match and filter the data in the data field in one time slot, and obtaining the symbol level data after descrambling, despreading, derotating and maximum ratio combining;
  • the filter circuit sends the symbol data to the matrix operation module for inter-symbol and inter-code channel interference cancellation;
  • the subsequent symbol data will be sent to the symbol level processing subsystem as the final output of the joint detection algorithm, completing the inverse mapping process of the physical channel to the transport channel; the mapping result will be sent to the software for subsequent task scheduling through the hardware and software interface channel. process.
  • TD-SCDMA joint detection algorithm is very complex, and the processing time is very demanding. Considering the cost and power consumption problem, it is impossible to use the base station side in the TD-SCDMA mobile terminal equipment. High-performance software platform, therefore, TD-SCDMA mobile phone terminals need to design a large number of hardware accelerators. The purpose is to reserve enough processing time for the terminal software platform, but it will inevitably increase the complicated cost and the practicality is not strong.
  • TD-SCDMA mobile phone terminals have to face the higher hardware accelerator computing speed requirements:
  • the joint detection algorithm of TD-SCDMA for the 12.2 kbps voice service has an uplink spreading factor of 8, occupying one code channel;
  • the downlink spreading factor is 16, occupying two code channels.
  • the matched filter of the mobile terminal needs to obtain the descrambled and despread 1 symbol in the joint detection, and it is necessary to perform matched filtering on 31 chip data.
  • the matching filter implementation circuit with high speed is very important for improving the operating efficiency of the TD-SCDMA baseband processing subsystem; however, the existing matched filters are often implemented based on the base station baseband algorithm circuit device,
  • the cost pressure on the base station side is much smaller than the cost pressure on the mobile terminal side.
  • the base station side can use a high-performance software processor; and the hardware accelerator on the base station side has far less time and power requirements than the hardware accelerator of the mobile terminal. Therefore, the matched filter device on the existing base station side is difficult to directly apply to the terminal device, and the versatility is poor.
  • the present invention provides a matching filter circuit device and method in a baseband processing system of a terminal device, which can shorten the processing time of the hardware accelerator of the terminal, and can improve the operating efficiency of the hardware system of the mobile communication terminal. Simple, practical and highly versatile.
  • a matched filter circuit device in a baseband processing system of a terminal device located in a joint detection algorithm circuit of the baseband processing system, the matched filter circuit device comprising a control unit, a V vector buffer unit, a shift integral selection unit, and a correlator a unit and a coherent integration unit, wherein the control unit is configured to control a process of descrambling, despreading, derotating, and maximizing ratio combining data; an output port of the control unit is simultaneously connected to the V vector buffer unit, And shifting the integral selecting unit and the coherent integrating unit, wherein the V vector buffer unit is configured to perform data buffering while performing a matching filtering operation.
  • a front end of the coherent integration unit is further connected to a correlator unit, and the V vector buffer unit and the shift integral selection unit are connected by the correlator unit,
  • the correlator unit is set to the associated processing of parallel data and to perform a summation operation between related results.
  • an input port of the correlator unit is simultaneously connected to an output port of the V vector buffer unit and an output port of the shift integration selection unit, where the V vector cache unit An output port provides a V vector required for a matching operation for the correlator unit, and an output port of the shift integration selecting unit provides correct antenna sample data required for a matching operation for the correlator unit, the V vector And the antenna sampling data completes the correlation operation in the correlator unit to complete the matching filtering operation.
  • control unit includes a control signal generation logic and a counter
  • control signal generation logic is located at an output end of the control unit
  • the counter is connected to the control signal to generate
  • the logic is set to count under the control of the matched filter start indication signal to transmit the count result as the time coordinate of the matched filter to the control signal generation logic.
  • control signal generation logic is located at a back end of the counter, and is configured to generate and output a V vector buffer unit control signal, a shift buffer enable and a selection control signal, and an integral, respectively. Unit control signal.
  • the V vector buffer unit includes a plurality of dual port serial buffers, and the plurality of dual port serial buffers are set to be cached under the control of the V vector buffer unit control signals. And read the V vector element.
  • the shift integration selection unit includes two sets of shift register register groups and a set of selector groups, and the selector group is located in two sets of shift buffer registers. Between the sets of devices, it is arranged that, under the control of the shift buffer enable and select control signals, the sample output is buffered in real time to the antenna data in the shift integral selection unit.
  • the correlator unit includes a plurality of correlators and an adder group, and an output port of the correlator is directly connected to an input port of the adder group, and the correlator Set to multiply the V vector element and the antenna data, the adder set being arranged to accumulate the result of multiplying a single of the correlators.
  • the coherent integration unit includes a selector, a coherent integration accumulator, and a coherent integration buffer, and an input port of the coherent integration accumulator is simultaneously connected to an output of the selector. a port and an output port of the correlator unit, an output port of the coherent integration accumulator is connected to an input port of the coherent integration buffer; the coherent integration accumulator is set to be completed under the control of the integration unit control signal The integration operation of all symbol data on the code track.
  • a matching filtering method in a baseband processing system of a terminal device comprising the steps of: providing a matched filtering circuit device, wherein the matched filtering circuit device comprises a control unit, a coherent integrating unit, and an associated integral buffer;
  • the coherent integration control signal is continuously in an active state during each operating period of the first calculation cycle of the demodulated data, and is demodulated in each group
  • the coherent integration control signal is continuously in an inactive state within an operating clock of the second calculation cycle of the data
  • a coherent integration unit of the matched filter circuit device When the coherent integration control signal is valid, a coherent integration unit of the matched filter circuit device directly accumulates the current input correlation sum result, and caches the accumulated result as the calculation result of the current cycle to the Matching a correlation integration buffer of the filter circuit device; when the coherent integration control signal is invalid, the coherent integration unit compares the current input correlation sum result with the first calculation cycle buffered in the coherent integration buffer The calculation results are cumulative and demodulate a complete set of symbol level data.
  • the matched filter circuit device and method in the baseband processing system of the terminal device provided by the present invention can utilize the data flow buffering and matching filtering process at the same time, effectively utilizing each processing clock, due to the use of a completely flowing water design structure.
  • the time consumption of the terminal hardware accelerator is greatly reduced, and the stable operation of the software platform is guaranteed in time, thereby effectively improving the mobile communication terminal.
  • the high-speed matching filter circuit is also very versatile, can adjust the size of the shift register group inside the shift buffer selection unit as needed, and adjust the number of correlators inside the correlator unit, thereby being compatible
  • FIG. 1 is a schematic block diagram of a prior art TD-SCDMA digital baseband processing subsystem
  • FIG. 2 is a schematic block diagram showing an implementation structure of a matched filter circuit device of the present invention
  • FIG. 3 is a schematic block diagram showing the hardware implementation structure of the control unit of the present invention.
  • V vector buffer unit 4 is a schematic block diagram showing the hardware implementation structure of the V vector buffer unit of the present invention.
  • Figure 5 is a schematic block diagram showing the hardware implementation structure of the shift integral selection unit of the present invention.
  • FIG. 6 is a schematic block diagram showing the hardware implementation structure of the correlator unit of the present invention.
  • Fig. 7 is a schematic block diagram showing the hardware implementation structure of the coherent integrating unit of the present invention.
  • BEST MODE FOR CARRYING OUT THE INVENTION hereinafter, specific embodiments and embodiments of a matched filter circuit device and method in a baseband processing system of a terminal device of the present invention will be described in detail with reference to the accompanying drawings.
  • the main core point of the matched filter circuit device and method in the baseband processing system of the terminal device of the present invention is that the design structure of the complete flow and the simultaneous data buffering and matching filtering process improve the operating efficiency of the hardware system of the mobile communication terminal;
  • the design and manufacturing techniques of terminal devices such as TD-SCDMA handsets and the like are well known to those skilled in the art and will not be described herein.
  • n working clocks are used as a processing cycle, where n can be the number of code channels matched for filtering, and the design structure of the complete pipeline is used, and the n code channel matching filtering operations are completed.
  • the antenna data of the next processing cycle is buffered, and the data cache process and the operation process are completely matched, and all the operation time of each processing clock is effectively utilized, thereby greatly saving the time consumption of the hardware accelerator.
  • the matched filtering circuit device includes five units: a control unit 210, a V vector buffer unit 220, and a shift integration selecting unit 230.
  • the correlator unit 240 and the coherent integration unit 250, the control unit 210 is the same
  • the V vector buffer unit 220, the shift integration selecting unit 230, and the coherent integrating unit 250 are connected, the correlator unit 240 is located at the front end of the coherent integrating unit 250, and the correlator unit 240 is simultaneously connected to the V vector buffer unit 220 and the shift An integral selection unit 230, wherein:
  • the main function of the control unit 210 is to control the operation of the matched filter operation circuit, coordinate the timing of the entire matched filter process, and the input port of the control unit 210 is connected to the external matched filter start indication signal and the matched filter code number n,
  • the V vector buffer unit control signal of the output port of the unit 210 is connected to the V vector buffer unit 220, and the shift integration enable and selection signal of the output port of the control unit 210 is connected to the shift integration selection unit 230, and the integration unit of the output unit of the control unit 210
  • the control signal is connected to the coherent integration unit 250.
  • the main function of the V vector buffer unit 220 is to cache the V vector output by the front end activation code channel detection module according to the format of the parallel and partition code channels, and then under the control of the V vector buffer unit control signal, Reading the V vector element of the corresponding code channel; the input port of the V vector buffer unit 220 is connected to the V vector element signal from the output of the active track detection module and the V vector buffer unit control signal output by the control unit 210; and the V vector buffer unit The output port of 220 transmits the V vector element of the corresponding code channel to correlator unit 240.
  • the main function of the shift integration selection unit 230 is to shift the data of the data field input by the external module to the two internal shift register register groups according to the shift integration enable and selection signals.
  • the selector group inside the shift integration selecting unit 230 selects a set of registered data outputs from the two sets of shift register register groups; the input ports of the shift integral selecting unit 230 are respectively connected to the output of the external module.
  • the data domain sample data and the shift integration enable and select signals of the control unit 210, the output port of the shift integration selection unit 230 outputs a selected data domain sample signal to the correlator unit 240.
  • the main function of the correlator unit 240 is to perform parallel processing of n data in parallel, and perform a summation operation between n correlation results.
  • the input ports thereof are respectively connected to the shift integration selection unit 230.
  • the selected data field sample data and the V element output by the V vector buffer unit 220 are output, and the output port connects the output correlation result to the coherent integration unit 250.
  • the main function of the coherent integration unit 250 is to complete the data integration in the symbol under the control of the integration unit control signal.
  • the input port is connected to the control unit 210 and the correlator unit control signal and the correlator unit.
  • the matrix operation module completes the demapping process of the physical channel to the transmission channel by the symbol level processing subsystem, and the final demapping result is reported to the digital signal through the hardware and software interface channel.
  • the processor DSP Digital Singnal Processor
  • a high-speed matching filter implementation circuit is proposed.
  • the working principle can complete multiple matching filtering operations simultaneously in each working clock.
  • the operating efficiency of the TD-SCDMA terminal hardware system is improved, the time consumption of the hardware accelerator is greatly reduced, and the stable operation of the software platform is guaranteed in time.
  • the control logic of the circuit is also very simple, easy to implement, and has a large Practical value.
  • SF is equal to 1
  • SF is equal to 16. Since the latter is most commonly used, the matching filtering operation with the spreading factor SF of 16 is still used as an example to describe
  • the specific implementation of the matched filter circuit device details the working principle of each unit:
  • the control unit 210 of the matched filter circuit device is configured to control the entire matched filtering operation process for controlling the processes of descrambling, despreading, derotating, and maximizing the combined symbol level matching data, which mainly includes two Functional sections: a counter 301 and a control signal generation logic 302, the control signal generation logic 302 is located at an output of the control unit 210, the counter 301 is coupled to the control signal generation logic 302, and the control signal generation logic 302 Located at the back end of the counter 301.
  • the main function of the counter 301 is to perform counting under the control of the matched filter start indication signal, the counting period of which is defined by the number 16 of currently matched filtered code channels, and the counting result of the counter 301 is sent to the control as the time coordinate of the matched filter.
  • control signal generation logic 302 The main function of the control signal generation logic 302 is to generate and output a V vector buffer unit control signal, a shift buffer enable and selection control signal, and an integration unit control signal according to the number of code channels 16 currently matched for filtering, wherein:
  • the V vector buffer unit control signal is composed of a V vector buffer unit read enable signal and a read address signal; the V vector buffer unit read enable signal can be obtained by comparing the current count value of the counter with a threshold 1408, if the count result is less than 1408, the read enable Can be valid, otherwise invalid; V vector buffer unit read address signal is defined according to the lowest 4-bit count value of the counter;
  • Shift buffer enable and select control signals including shift register register set enable signal Store_enl, shift register register set 2 enable signal store-en2 and select control signal sel_data three parts, if 16 is used as a count period of the counter, then in the first and second count periods, The two sets of shift register enable signals store-enl and store-en2 are valid at the same time; then store_enl is invalid in the third counting cycle, and store-en2 continues to be valid, sel_data is state 0; in the fourth The count period store-enl is valid, store-en2 is invalid, sel-data is state 1; the fifth count period store-enl is invalid, store-en2 is valid, sel-data is state 0, and so on;
  • the integral control signal is also defined by the counter. When the counter count result module is less than 16, the fifth bit state of the counter is 0, the coherent integration control signal is enabled. Otherwise, it is set to the inactive state.
  • the main function of the V-vector buffer unit 220 at this time is to receive the generated V vector of the front-end active code channel detecting module, and under the control of the V-vector buffer unit control signal, do not select the internal 4-block dual-port serial buffer Buffer.
  • the read V vector is sent to the correlator unit 240.
  • the A port write enable of the four Buffers can be enabled, and the data is buffered into four buffers according to the serial, as shown in FIG. B0,0, B0,1 ⁇ 15,30, ⁇ 15,31, and so on, Bm, n represents the nth V-direction two elements obtained on the mth code channel, and 2 V-vector elements are buffered on each address unit.
  • the V vector buffer unit control signal outputted by the matched filter control unit 210 is required to simultaneously read the V vector element by using the A port and the B port of the four buffer buffers, wherein the A port has 16
  • the clock sequentially cycles the SectionO space for the cycle, and the B port also sequentially cyclically addresses the sectionl space with a cycle of 16 clocks, and the two send the read data to the correlator unit 240.
  • the main function of the shift integration selection unit 230 at this time is to alternately buffer the read antenna data into two sets of shift buffer groups in real time, and then send the correct 16 sample data to the correlator unit according to the selection control signal. 240, as shown in FIG.
  • the second group of shift register registers buffers the antenna data under the control of store_en2, and the selector group outputs 16 antenna data from the two sets of shift registers according to the selection control signal sel_data, when sel—
  • the content output in the first group k to k+15 register sets is selected, and the output result is sent to the correlator unit 240; when sel_data is state 1, the second group k+16 is selected.
  • the correlator unit 240 is provided. The function of the correlator unit 240 at this time is to complete the correlation operation of 16 data in parallel, and accumulate 16 related results. As shown in FIG.
  • each correlator inputs one antenna data and one V vector element, and then multiplies the two, and the product result is performed in the adder group
  • the main function of the coherent integration unit 250 at this time is to accumulate the summation result output by the correlator unit 240 and the summation result belonging to the same symbol in the previous cycle under the control of the coherent unit control signal, and accumulate the result buffer to the inside.
  • a selector 701 a coherent integration accumulator 702 and a coherent integration buffer 703 are included, and the input port of the coherent integration accumulator 702 is simultaneously connected to the output of the selector 701.
  • a port and an output port of the correlator unit 240, an output port of the coherent integration accumulator 702 is coupled to an input port of the coherent integration buffer 703.
  • the coherent integration control signal is continuously active within 16 clocks of the first calculation cycle of each set of demodulated data, which indicates that the matching filtering process of starting a new set of symbols is started.
  • the selection 0 is output to the coherent integration accumulator 702.
  • the coherent integration accumulator 702 the current input correlation result is directly accumulated and 0, and the accumulated result is buffered into the correlation integration buffer 703 as the calculation result of the current cycle;
  • the coherent integration unit control signal is continuously in an inactive state, at which time the coherent integration accumulator 702 will coherently integrate the correlation result at the current input with the coherent integration.
  • the accumulation operation between the correlation sum results obtained in the first calculation cycle of the cache 703 is performed to obtain complete symbol level data; then the demodulation of the next set of symbol data is restarted, and the process is repeated until 16 codes are repeated. All 704 symbols are demodulated on the track.
  • the digital baseband processing system of the TD-SCDMA mobile phone terminal starts the matrix operation module behind the matched filter circuit to complete inter-symbol and inter-code channel interference cancellation; and the interference-eliminated result is completed by the symbol-level processing subsystem to complete the physical channel to the transmission.
  • the inverse mapping process of the channel; and the final mapping result is reported to the DSP through the hardware and software interface channel, and the task scheduling is performed by the DSP.
  • circuit device and method for matched filtering in the above specific embodiments may be applied according to practical applications.
  • Various possible solutions are available to those skilled in the art and will not be described herein.
  • the matched filter circuit device and method in the baseband processing system of the terminal device can utilize the completely pipelined design structure, can simultaneously perform data buffering and matching filtering processes, and effectively utilize each A processing clock greatly reduces the time consumption of the terminal hardware accelerator, which provides a guarantee for the stable operation of the software platform, thereby effectively improving the operating efficiency of the hardware system of the mobile communication terminal;
  • the high-speed matching filter circuit is also very versatile Strong, can adjust the size of the shift register group inside the shift buffer selection unit as needed, and adjust the number of correlators inside the correlator unit, thereby being compatible with the matched filtering algorithm in various application environments;
  • the control logic is simple, easy to implement, and has strong practicality and utilization value.
  • the invention adopts a completely flowing water design structure, can simultaneously perform data buffering and matching filtering process, effectively utilizes each processing clock, greatly reduces the time consumption of the terminal hardware accelerator, and effectively improves the hardware system of the mobile communication terminal.
  • the operating efficiency at the same time, the invention can adjust the size of the shift register group inside the shift buffer selection unit according to needs, and adjust the number of correlators inside the correlator unit, thereby being compatible with the matching filtering algorithm in various application environments;
  • the control logic of the circuit device in the invention is simple, easy to implement, and has strong practicability and utilization value.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Description

一种终端设备基带处理系统中的匹配滤波电路装置及方法 技术领域 本发明涉及移动通信终端设备基带处理系统的联合检测算法电路领域， 尤其涉及的是一种终端设备基带处理系统中的匹配滤波电路装置及方法的改 进。 背景技术
在移动通信终端设备的基带处理系统中， 传统检测技术是针对单一用户 进行信号检测而把其他用户作为噪声加以处理的， 但在用户数量增多时， 极 易导致信噪比恶化， 使得系统性能和容量都不尽如人意。 而联合检测技术是 在传统检测技术的基础上， 充分利用了造成多址干扰的所有用户信号以及相 关多径的先验信息， 把用户信号的分离当作一个统一的相互关联的联合检测 过程来完成， 从而具有优良的抗干扰性能， 也降低了系统对功率控制精度的 要求， 因此， 可以更加有效地利用上下行链路的频谱资源， 显著地提高了系 统的性能和容量。
在 TD-SCDMA终端设备的移动通信基带处理系统中， 普遍釆用了联合 检测的基带处理算法， 在该联合检测中往往都包含有一个重要的算法电路即 匹配滤波电路。
如图 1所示，首先， 串行干扰消除模块利用一个时隙内的 Midamble码釆 样数据进行多轮多小区串行干扰消除， 得到一个较为准确的初始信道估计结 果； 同时， 复合扩频码产生模块对本地信道化码进行加扰、 旋转及共轭生成 复合扩频码； 再根据初始信道估计结果和复合扩频码， 对所有候选码道进行 激活检测， 并最终确定哪些码道将作为激活码道被纳入到联合检测； 其次， 对初始信道估计结果进行后处理， 得到准确的信道估计后处理结果； 在信道 估计后处理结果和激活码道的复合扩频码之间， 进行卷积运算得到各个激活 码道上的 V向量； 然后， 利用 V向量对一个时隙内的数据域釆样数据进行匹 配滤波， 得到解扰、 解扩、 解旋转和最大比合并后的符号级数据； 匹配滤波 电路将符号数据送给矩阵运算模块进行符号间和码道间干扰消除； 消除干扰 后的符号数据将作为联合检测算法的最终输出结果， 发送给符号级处理子系 统， 完成物理信道到传输信道的反映射过程； 映射结果将通过软硬件接口通 道， 发送给软件进行后面的任务调度过程。
但基于 TD-SCDMA的联合检测算法的算法复杂度非常高， 对处理时间 的要求很苛刻， 考虑到成本和功耗问题， 在 TD-SCDMA手机终端设备中， 不 可能釆用类似于基站侧的高性能软件平台， 因此， TD-SCDMA手机终端就需 要设计大量的硬件加速器， 其目的是， 为了给终端软件平台预留出足够的处 理时间， 但是势必增加复杂的成本， 实用性不强。
不仅如此， TD-SCDMA手机终端还不得不面对所提出更高的硬件加速器 运算速度要求： 如 TD-SCDMA的联合检测算法对于 12.2kbps语音业务， 上 行扩频因子为 8, 占用一个码道； 下行扩频因子为 16, 占用两个码道。 以扩 频因子 SF为 16的匹配滤波运算为例， 手机终端的匹配滤波器在联合检测中 要得到解扰解扩后的 1个符号， 需要对 31个码片数据进行匹配滤波， 在每个 码道上要完成两个数据域共 44 个符号的匹配滤波过程； 这个过程需要反复 16次才能把 16个码道上的符号全部解出来， 从而完成一个时隙全码道的匹 配滤波过程， 总共需要做 31 X 44 X 16=21824次匹配运算。
可见， 具有高速度的匹配滤波实现电路对于提高 TD-SCDMA基带处理 子系统的运行效率是多么的重要； 然而， 目前现有的匹配滤波器， 往往都是 基于基站基带算法电路装置实现的， 鉴于基站侧的成本压力远比手机终端侧 的成本压力要小的多， 基站侧可选用高性能的软件处理器； 且基站侧的硬件 加速器对时间和功耗要求也远没有手机终端的硬件加速器严格； 因此， 现有 基站侧的匹配滤波器装置很难直接应用于终端设备中， 通用性很差。
因此， 现有技术尚有待于改进和发展。
发明内容 本发明为解决现有技术中存在的问题， 提供一种终端设备基带处理系统 中的匹配滤波电路装置及方法， 可缩短终端硬件加速器的处理时间， 可提高 移动通信终端硬件系统的运行效率， 且简单、 实用和具有高通用性。
本发明的技术方案如下： 一种终端设备基带处理系统中的匹配滤波电路装置， 位于所述基带处理 系统的联合检测算法电路内， 所述匹配滤波电路装置包括控制单元、 V向量 緩存单元、 移位积分选择单元、 相关器单元以及相干积分单元， 其中， 所述 控制单元设置成控制解扰、 解扩、 解旋转和最大比合并数据的处理过程； 所 述控制单元的输出端口同时连接所述 V向量緩存单元、 所述移位积分选择单 元和所述相干积分单元， 所述 V向量緩存单元设置成进行匹配滤波操作的同 时进行数据緩存。
进一步地， 所述的匹配滤波电路装置中， 所述相干积分单元的前端还连 接相关器单元， 并通过所述相关器单元连接所述 V向量緩存单元和所述移位 积分选择单元， 所述相关器单元设置成并行数据的相关处理过程以及在相关 结果之间进行求和运算。
进一步地， 所述的匹配滤波电路装置中， 所述相关器单元的输入端口同 时连接所述 V 向量緩存单元的输出端口和所述移位积分选择单元的输出端 口， 所述 V向量緩存单元的输出端口为所述相关器单元提供匹配运算所需的 V向量， 所述移位积分选择单元的输出端口为所述相关器单元提供匹配运算 所需的正确的天线釆样数据， 所述 V向量和天线釆样数据在所述相关器单元 内完成相关运算即完成匹配滤波运算。
进一步地， 所述的匹配滤波电路装置中， 所述控制单元包括一控制信号 发生逻辑和一计数器， 所述控制信号发生逻辑位于所述控制单元的输出端， 所述计数器连接所述控制信号发生逻辑， 设置成在匹配滤波开始指示信号的 控制下进行计数， 以将计数结果作为匹配滤波器的时间坐标发送给该控制信 号发生逻辑。
进一步地， 所述的匹配滤波电路装置中， 所述控制信号发生逻辑位于所 述计数器的后端， 设置成分别产生并输出 V向量緩存单元控制信号、 移位緩 存使能和选择控制信号以及积分单元控制信号。
进一步地， 所述的匹配滤波电路装置中， 所述 V向量緩存单元包括多个 双口串行緩存， 多个双口串行緩存设置成在所述 V向量緩存单元控制信号的 控制下， 緩存和读取 V向量元素。
进一步地， 所述的匹配滤波电路装置中， 所述移位积分选择单元包括两 组移位緩存寄存器组和一组选择器组， 所述选择器组位于两组移位緩存寄存 器组之间， 其设置成在所述移位緩存使能和选择控制信号的控制下， 釆样输 出被实时緩存到所述移位积分选择单元内的天线数据。
进一步地， 所述的匹配滤波电路装置中， 所述相关器单元包括多个相关 器和一加法器组，所述相关器的输出端口直接连接所述加法器组的输入端口， 所述相关器设置成相乘所述 V向量元素和所述天线数据， 所述加法器组设置 成累加单个所述相关器相乘的结果。
进一步地， 所述的匹配滤波电路装置中， 所述相干积分单元包括一选择 器、 一相干积分累加器和一相干积分緩存， 所述相干积分累加器的输入端口 同时连接所述选择器的输出端口和所述相关器单元的输出端口， 所述相干积 分累加器的输出端口连接所述相干积分緩存的输入端口； 所述相干积分累加 器设置成在所述积分单元控制信号的控制下， 完成码道上所有符号数据的积 分操作。
一种终端设备基带处理系统中的匹配滤波方法， 所述方法包括以下步骤： 提供匹配滤波电路装置， 所述匹配滤波电路装置包括控制单元、 相干积 分单元以及相关积分緩存；
由所述匹配滤波电路装置的控制单元产生并输出相干积分控制信号； 在每组解调数据第一个计算周期的工作时钟内所述相干积分控制信号连 续处于有效状态， 而在每组解调数据第二个计算周期的工作时钟内所述相干 积分控制信号连续处于无效状态；
当所述相干积分控制信号有效时， 由所述匹配滤波电路装置的一相干积 分单元直接将当前输入的相关求和结果进行累积操作， 并将累积的结果作为 当前周期的计算结果緩存到所述匹配滤波电路装置的一相关积分緩存中； 当所述相干积分控制信号无效时， 所述相干积分单元则将当前输入的相 关求和结果与緩存在所述相干积分緩存中第一个计算周期的计算结果进行累 积操作， 解调出一组完整的符号级数据。
本发明所提供的一种终端设备基带处理系统中的匹配滤波电路装置及方 法， 由于釆用了完全流水的设计结构， 能同时进行数据緩存和匹配滤波过程， 有效的利用了每一个处理时钟， 大大压缩了终端硬件加速器的时间消耗， 为 软件平台的稳定运行在时间上提供了保障， 从而有效地提高了移动通信终端 硬件系统的运行效率； 该高速匹配滤波电路通用性也很强， 能根据需要调整 移位緩存选择单元内部的移位寄存器组的大小， 以及调整相关器单元内部的 相关器个数， 从而能兼容多种应用环境下的匹配滤波算法； 另外， 该匹配滤 波电路装置的控制逻辑简单， 易于实现， 具有很强的实用性和利用价值。 附图概述
图 1是现有技术 TD-SCDMA数字基带处理子系统示意框图；
图 2是本发明的匹配滤波电路装置的实现结构示意框图；
图 3是本发明的控制单元的硬件实现结构示意框图；
图 4是本发明的 V向量緩存单元的硬件实现结构示意框图；
图 5是本发明的移位积分选择单元的硬件实现结构示意框图；
图 6是本发明的相关器单元的硬件实现结构示意框图；
图 7是本发明的相干积分单元的硬件实现结构示意框图。 本发明的较佳实施方式 以下将结合所示附图， 对本发明终端设备基带处理系统中匹配滤波电路 装置及方法的具体实施方式和实施例加以详细说明。
本发明终端设备基带处理系统中的匹配滤波电路装置及方法， 主要核心 点在于， 完全流水的设计结构以及同时进行数据緩存和匹配滤波过程， 提高 了移动通信终端硬件系统的运行效率； 至于移动通信终端设备如 TD-SCDMA 手机等的设计和制造技术为本领域技术人员所熟知， 在此不再赘述。
根据 TD-SCDMA终端基带算法的处理特点， 以 n个工作时钟为一个处理 周期， 其中 n可为匹配滤波的码道数， 釆用完全流水的设计结构， 在完成 n个 码道匹配滤波操作的同时緩存下个处理周期的天线数据， 实现数据緩存过程 与运算过程的完全匹配， 有效利用每一个处理时钟所有的运算时间， 大大节 省硬件加速器的时间消耗。
如图 2所示，要在一个处理周期内完成 n个码道上的 n次匹配滤波运算， 该 匹配滤波电路装置包括五个单元： 控制单元 210、 V向量緩存单元 220、 移位 积分选择单元 230、 相关器单元 240和相干积分单元 250, 所述控制单元 210同 时连接 V向量緩存单元 220、 移位积分选择单元 230和相干积分单元 250, 所述 相关器单元 240位于相干积分单元 250的前端， 所述相关器单元 240同时连接 V 向量緩存单元 220和移位积分选择单元 230 , 其中：
1 )控制单元 210的主要功能是， 控制匹配滤波运算电路的操作， 协调整 个匹配滤波过程的时序，控制单元 210的输入端口连接外部的匹配滤波开始指 示信号和匹配滤波码道个数 n, 控制单元 210输出端口的 V向量緩存单元控制 信号连接到 V向量緩存单元 220 , 控制单元 210输出端口的移位积分使能和选 择信号连接到移位积分选择单元 230, 控制单元 210输出端口的积分单元控制 信号连接到相干积分单元 250。
2 ) V向量緩存单元 220的主要功能是， 如图 4所示， 按照并列和分区码道 的格式緩存前端激活码道检测模块输出的 V向量，然后在 V向量緩存单元控制 信号的控制下， 读取对应码道的 V向量元素； V向量緩存单元 220的输入端口 连接来自于激活码道检测模块输出的 V向量元素信号和控制单元 210输出的 V 向量緩存单元控制信号； 而 V向量緩存单元 220的输出端口将对应码道的 V向 量元素发送给相关器单元 240。
3 )移位积分选择单元 230的主要功能是， 根据移位积分使能和选择信号， 将外部模块输入的数据域釆样数据， 移位緩存到其内部的两组移位緩存寄存 器组中， 如图 5所示， 同时， 移位积分选择单元 230内部的选择器组从两组移 位緩存寄存器组中选择一组寄存数据输出；移位积分选择单元 230的输入端口 分别连接外部模块输出的数据域釆样数据和控制单元 210的移位积分使能和 选择信号 ,移位积分选择单元 230的输出端口输出选中的数据域釆样信号连接 到相关器单元 240。
4 )相关器单元 240的主要功能是， 并行 n个数据的相关处理过程， 并在 n 个相关结果之间进行求和运算， 如图 6所示， 其输入端口分别连接移位积分选 择单元 230输出选中的数据域釆样数据和 V向量緩存单元 220输出的 V元素，输 出端口将输出的相关求和结果连接到相干积分单元 250。
5 )相干积分单元 250的主要功能是， 在积分单元控制信号的控制下， 完 成符号内的数据积分， 如图 7所示， 其输入端口连接控制单元 210输出的积分 单元控制信号和相关器单元 240输出的 n个相关结果之和， 其输出端口将输出 完整的数据符号发送给匹配滤波单元后端的矩阵运算模块。 所述矩阵运算模块完成符号间干扰消除和码道间干扰消除后， 通过符号 级处理子系统完成物理信道到传输信道的解映射过程， 最终的解映射结果将 通过软硬件接口通道上报至数字信号处理器 DSP(Digital Singnal Processor)做 进一步的业务调度处理。
以上根据 TD-SCDMA终端硬件加速器的性能要求， 结合终端基带算法的 特点， 提出了一种高速的匹配滤波实现电路， 其工作原理能够在每一个工作 时钟内同时完成多次匹配滤波运算， 有效地提高了 TD-SCDMA终端硬件系统 的运行效率， 大大压缩了硬件加速器的时间消耗， 为软件平台的稳定运行在 时间上提供了保障， 另外该电路的控制逻辑也非常简单， 易于实现， 有较大 的实用价值。按照 TD-SCDMA协议规定，在下行链路中只存在两种扩频因子： SF等于 1和 SF等于 16, 由于后者最为常用， 仍然以扩频因子 SF为 16的匹配滤 波运算为例来描述匹配滤波电路装置的具体实施方式， 详细说明各单元的工 作原理：
如图 3所示， 匹配滤波电路装置的控制单元 210用于控制整个匹配滤波运 算过程， 用于控制解扰、 解扩、 解旋转和最大比合并符号级匹配数据的处理 过程， 它主要包括两个功能部分： 计数器 301和控制信号发生逻辑 302, 所述 控制信号发生逻辑 302位于所述控制单元 210的输出端，所述计数器 301连接所 述控制信号发生逻辑 302,所述控制信号发生逻辑 302位于所述计数器 301的后 端。
计数器 301的主要功能是， 在匹配滤波开始指示信号的控制下进行计数， 其计数周期由当前匹配滤波的码道个数 16来定义，计数器 301的计数结果作为 匹配滤波器的时间坐标发送给控制信号发生逻辑 302;
控制信号发生逻辑 302的主要功能是， 根据当前匹配滤波的码道个数 16, 分别产生并输出 V向量緩存单元控制信号、 移位緩存使能和选择控制信号以 及积分单元控制信号， 其中：
V向量緩存单元控制信号由 V向量緩存单元读使能信号和读地址信号组 成； V向量緩存单元读使能信号可通过比较计数器的当前计数值和门限 1408 得到， 如果计数结果小于 1408, 读使能有效， 否则为无效； V向量緩存单元 读地址信号则根据计数器最低的 4比特计数值来定义；
移位緩存使能和选择控制信号包括移位緩存寄存器组 1使能信号 store— enl、移位緩存寄存器组 2使能信号 store— en2和选择控制信号 sel— data三个 部分， 如果以 16作为计数器的一个计数周期， 那么在第一个和第二个计数周 期内， 两组移位寄存器组使能信号 store— enl和 store— en2同时有效； 之后在第 三个计数周期内 store— enl无效， 而 store— en2继续有效， sel— data为状态 0; 在第 四个计数周期 store— enl有效， store— en2无效， sel— data为状态 1 ; 第五个计数周 期 store— enl无效， store— en2有效， sel— data为状态 0, 以此类推；
积分控制信号也是计数器定义的，每当计数器计数结果模块上 32小于 16, 计数器的第 5个比特状态为 0时， 便使能相干积分控制信号， 否则， 其置位为 无效状态。
此时的 V向量緩存单元 220的主要功能是接收前端激活码道检测模块的 生成的 V向量， 并在 V向量緩存单元控制信号的控制下， 别从其内部 4块双口 串行緩存 Buffer中读取 V向量发送给相关器单元 240 ,在緩存 V向量元素时可分 别使能四块 Buffer的 A口写使能， 将数据按照串行緩存到四块 buffer中， 在图 4 所示中， B0,0、 B0,1 Β 15,30、 Β 15,31 , 以此类推 Bm,n表示第 m个码道 上得到的第 n个 V向两元素， 每个地址单元上緩存 2个 V向量元素， 在读取 V向 量元素时， 需要根据匹配滤波控制单元 210输出的 V向量緩存单元控制信号， 利用四块緩存 buffer的 A口和 B口同时读取 V向量元素， 其中， A口以 16个时钟 为周期顺次循环寻址 SectionO空间， 同时 B口也以 16个时钟为周期顺次循环寻 址 sectionl空间， 二者将读取的数据发送给相关器单元 240。 此时的移位积分选择单元 230的主要功能是， 将读出的天线数据实时交 替緩存到两组移位緩存组中，然后根据选择控制信号将正确的 16个釆样数据 发送给相关器单元 240, 如图 5所示， 包括两组移位緩存寄存器组和一组选 择器组， 所述选择器组位于两组移位緩存寄存器组之间， 移位积分选择输出 单元根据 store— enl和 store— en2移位緩存釆样数据， 当 store— enl有效时， 天 线数据 Db— rddata向右移位緩存到第一组移位緩存寄存器组， 当 store— enl无 效时， 停止移位緩存过程； 同理， 第二组移位緩存寄存器组在 store— en2的控 制下緩存天线数据， 选择器组根据选择控制信号 sel— data从两组移位寄存器 组中将输出 16个天线数据， 当 sel— data为状态 0时， 选择第一组 k到 k+15 个寄存器组中的内容输出， 输出结果发送给相关器单元 240; 当 sel— data为状 态 1时， 选择第二组 k+16到 k+31个寄存器组中的内容输出， 输出结果发送 给相关器单元 240。 此时的相关器单元 240的功能是， 并行完成 16个数据的相关运算操作， 并把 16个相关结果累积起来， 如图 6所示， 它是由 16个相关器组成， 所述 相关器的输出端口直接连接加法器组的输入端口， 每个相关器输入一个天线 数据和一个 V向量元素， 然后将二者相乘， 乘积结果在所述加法器组中进行
此时的相干积分单元 250的主要功能是， 在相干单元控制信号的控制下 将相关器单元 240输出的求和结果与前一个周期属于同一个符号的求和结果 进行累加， 累加结果緩存到内部的相干积分 Buffer中， 如图 7所示， 包括一 个选择器 701、 一个相干积分累加器 702和一块相干积分緩存 703 , 所述相干 积分累加器 702的输入端口同时连接所述选择器 701的输出端口和所述相关 器单元 240的输出端口， 所述相干积分累加器 702的输出端口连接所述相干 积分緩存 703的输入端口。
当相干积分单元 250开始工作时， 相干积分控制信号会在每组解调数据 第一个计算周期的 16时钟内连续处于有效状态，这表示开始一组新符号的匹 配滤波过程， 这时选择器 701选择 0输出给相干积分累积器 702, 在相干积 分累加器 702中， 直接将当前输入的相关求和结果与 0进行累积操作， 累积 结果作为当前周期的计算结果緩存到相关积分緩存 703中； 在每组解调数据 的第二个计算周期的 16个时钟周期内，相干积分单元控制信号连续处于无效 状态， 这时相干积分累加器 702会在当前输入的相关求和结果与緩存在相干 积分緩存 703中第一个计算周期得到的相关求和结果之间进行累积操作， 得 到完整的符号级数据； 然后再重新开始下一组符号数据的解调， 不断重复这 个过程， 直到在 16个码道上把所有 704个符号全部解调出来。
此时的 TD-SCDMA手机终端数字基带处理系统启动匹配滤波电路后面 的矩阵运算模块， 完成符号间和码道间干扰消除； 而消除干扰后的结果通过 符号级处理子系统， 完成物理信道到传输信道的反映射过程； 而最终的映射 结果通过软硬件接口通道上报 DSP, 由 DSP进行任务调度。
以上具体实施方式中匹配滤波的电路装置及方法根据实际应用可以釆用 现有各种可能的方案， 为本领域技术人员所熟知， 在此也不再赘述。
本发明具体实施例中所提供的一种终端设备基带处理系统中的匹配滤波 电路装置及方法， 由于釆用了完全流水的设计结构， 能同时进行数据緩存和 匹配滤波过程， 有效的利用了每一个处理时钟， 大大压缩了终端硬件加速器 的时间消耗， 为软件平台的稳定运行在时间上提供了保障， 从而有效地提高 了移动通信终端硬件系统的运行效率； 该高速匹配滤波电路通用性也很强， 能根据需要调整移位緩存选择单元内部的移位寄存器组的大小， 以及调整相 关器单元内部的相关器个数， 从而能兼容多种应用环境下的匹配滤波算法； 另外， 该电路装置的控制逻辑简单， 易于实现， 具有很强的实用性和利用价 值。
应当理解的是， 对本领域普通技术人员来说， 可以根据上述方案的说明 加以改进或变换， 例如应用于通讯和电子的其他产品领域， 而所有这些改进 和变换都本应属于本发明所附权利要求的保护范围。
工业实用性
本发明釆用了完全流水的设计结构， 能同时进行数据緩存和匹配滤波过 程， 有效的利用了每一个处理时钟， 大大压缩了终端硬件加速器的时间消耗， 有效地提高了移动通信终端硬件系统的运行效率； 同时本发明能根据需要调 整移位緩存选择单元内部的移位寄存器组的大小， 以及调整相关器单元内部 的相关器个数， 从而能兼容多种应用环境下的匹配滤波算法； 本发明中电路 装置的控制逻辑简单， 易于实现， 具有很强的实用性和利用价值。

Claims

权 利 要 求 书
1、一种终端设备基带处理系统中的匹配滤波电路装置， 所述匹配滤波电 路装置位于所述基带处理系统的联合检测算法电路内， 且包括控制单元、 V 向量緩存单元、 移位积分选择单元、 相关器单元以及相干积分单元， 其中， 所述控制单元设置成控制解扰、 解扩、 解旋转和最大比合并数据的处理 过程， 其输出端口同时连接所述 V向量緩存单元、 所述移位积分选择单元以 及所述相干积分单元；
所述 V向量緩存单元设置成在所述匹配滤波电路装置进行匹配滤波操作 的同时进行数据緩存。
2、 根据权利要求 1所述的匹配滤波电路装置， 其中， 所述相干积分单元的前端连接所述相关器单元， 并通过所述相关器单元 连接所述 V向量緩存单元和所述移位积分选择单元； 所述相关器单元设置成并行数据的相关处理过程， 以及在相关处理结果 之间进行求和运算。
3、 根据权利要求 2所述的匹配滤波电路装置， 其中， 所述相关器单元的输入端口同时连接所述 V向量緩存单元的输出端口和 所述移位积分选择单元的输出端口， 所述 V向量緩存单元的输出端口为所述 相关器单元提供匹配运算所需的 V向量， 所述移位积分选择单元的输出端口 为所述相关器单元提供匹配运算所需的正确的天线釆样数据， 所述 V向量和 天线釆样数据在所述相关器单元内完成相关运算即完成匹配滤波运算。
4、 根据权利要求 3所述的匹配滤波电路装置， 其中， 所述控制单元包括控制信号发生逻辑单元和计数器， 其中， 所述控制信号发生逻辑单元位于所述控制单元的输出端； 所述计数器连接所述控制信号发生逻辑单元， 并设置成在匹配滤波开始 指示信号的控制下进行计数， 以将计数结果作为匹配滤波器的时间坐标发送 给所述控制信号发生逻辑单元。
5、 根据权利要求 4所述的匹配滤波电路装置， 其中， 所述控制信号发生逻辑单元位于所述计数器的后端， 其设置成产生并输 出 V向量緩存单元控制信号、 移位緩存使能和选择控制信号以及积分单元控 制信号。
6、 根据权利要求 5所述的匹配滤波电路装置， 其中， 所述 V向量緩存单元包括多个双口串行緩存， 所述多个双口串行緩存设 置成在所述 V向量緩存单元控制信号的控制下緩存和读取 V向量元素。
7、 根据权利要求 6所述的匹配滤波电路装置， 其中， 所述移位积分选择单元包括两组移位緩存寄存器组和一组选择器组， 其 中， 所述选择器组位于所述两组移位緩存寄存器组之间， 并设置成在所述移 位緩存使能和选择控制信号的控制下， 釆样并输出被实时緩存到所述移位积 分选择单元内的天线数据。
8、 根据权利要求 7所述的匹配滤波电路装置， 其中， 所述相关器单元包括多个相关器和一加法器组， 其中， 所述相关器设置成相乘所述 V向量元素和所述天线数据， 其输出端口直 接连接所述加法器组的输入端口； 所述加法器组设置成累加单个所述相关器相乘的结果。
9、 根据权利要求 8所述的匹配滤波电路装置， 其中， 所述相干积分单元包括一选择器、一相干积分累加器和一相干积分緩存， 其中， 所述相干积分累加器的输入端口同时连接所述选择器的输出端口和所述 相关器单元的输出端口； 所述相干积分累加器设置成在所述积分单元控制信号的控制下， 完成码 道上所有符号数据的积分操作， 其输出端口连接所述相干积分緩存的输入端 口„
10、 一种终端设备基带处理系统中的匹配滤波方法， 所述方法包括以下 步骤：
提供匹配滤波电路装置， 所述匹配滤波电路装置包括控制单元、 相干积 分单元以及相关积分緩存； 由所述匹配滤波电路装置的控制单元产生并输出相干积分控制信号； 在每组解调数据第一个计算周期的工作时钟内 , 所述相干积分控制信号 连续处于有效状态， 而在每组解调数据第二个计算周期的工作时钟内所述相 干积分控制信号连续处于无效状态； 当所述相干积分控制信号有效时， 由所述匹配滤波电路装置的相干积分 单元直接将当前输入的相关求和结果进行累积操作， 并将累积操作的结果作 为当前周期的计算结果緩存到所述匹配滤波电路装置的相关积分緩存中； 以 及 当所述相干积分控制信号无效时， 所述匹配滤波电路装置的相干积分单 元则将当前输入的相关求和结果与緩存在所述匹配滤波电路装置的相干积分 緩存中的第一个计算周期的计算结果进行累积操作， 解调出一组完整的符号 级数据。
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