WO2010007173A1

WO2010007173A1 - A new sense amplifier circuit

Info

Publication number: WO2010007173A1
Application number: PCT/EP2009/059261
Authority: WO
Inventors: Claude Raphaël CHAPPERT; Weisheng Zhao
Original assignee: Universite Paris Sud (Paris 11); Centre National De La Recherche Scientifique - Cnrs -
Priority date: 2008-07-17
Filing date: 2009-07-17
Publication date: 2010-01-21

Abstract

A sense amplifier circuit comprising: four PMOS transistors whose sources are at a voltage source Vdd, two NMOS transistors whose drains are respectively connected with the drains of the PMOS transistors, the sources of the NMOS transistors being connected to variable resistors, the variable resistors being connected to the drain of a third NMOS transistor (28), the source of the third NMOS transistor (28) being connected to a reference voltage Vref, the gates of the transistors (14, 20) being connected together the gates of the transistors (16, 22) being connected together, the gate of the third NMOS transistor (28) being connected to the gates of the PMOS transistors (12,18).

Description

A new sense amplifier circuit

The invention relates to a sense amplifier circuit and logic circuits comprising said sense amplifier circuit. This application claims the priority right of the application US 61/081,517 which is hereby incorporated by reference .

The elemental brick of the application of magnetic control of electronic transports in nano-electronics is the magnetic tunnel junction (MTJ) .

A magnetic tunnel junction, represented on figure 1, comprises at least a first and a second ferromagnetic layers Fl and F2 separated by a thin insulating layer I acting as tunnel barrier for electronic transport, and is patterned into nanopillar shape.

The resistance of the nanopillar depends on the relative orientations of the magnetizations of the first and second layer Fl and F2, represented by arrows on the figure 1. In standard applications the magnetization of one layer, for example F2 is fixed, usually by interfacial interaction with an antiferromagnetic layer, not represented on figure 1, while the magnetization of the other layer is free to rotate, for example for sensor applications, or can take two antiparallel orientations, for example for memory and logic applications such as discussed in this description. In the latter case the resistance of the tunnel junction can take one of two extreme values RMIN and RMAX.

The resistance of the nanopillar can be controlled by magnetic fields and/or current pulses (spin transfer torque writing with current density already below 3 106 A/cm2) with a relative amplitude or "tunnel magnetoresistance" TMR = (RMAX-RMIN) /RMIN greater than 100%, for example up to 630%. Such devices have a natural aptitude to work in the frequency range around IGHz .

The magnetic tunnel junction is thus a commutable resistor that exhibits usual assets of magnetic storage, such as non-volatility and radiation hardness, while having transport properties, resistivity, write currents and operation speed compatible with CMOS electronics.

Besides, the integration of magnetic tunnel junctions is made by an "above CMOS" technology, the magnetic "back- end" process can be done after the CMOS "front-end" process, and with the new spin transfer torque writing scheme, requiring only bipolar current pulses sent through the magnetic tunnel junction itself, it becomes possible to finely distribute such magnetic tunnel junction cells into CMOS circuits. Therefore the magnetic tunnel junction can also be used to bring wide data non-volatility in the CMOS electronics, and exhibits great potential for embedded memory and logic applications.

When used in logic circuit, the magnetic tunnel junctions should be spread on the entire chip surface, while the standard MRAM sense amplifiers cannot provide the high sensing speed required by CMOS logic circuit.

To ensure robustness and high reading speed, the SRAM based sense amplifier represented in figure 2, and the dynamic current-mode logic sense amplifier represented on figure 3, were proposed to sense one pair of magnetic tunnel junctions with opposite magnetic configurations, one is at RMIN when the other is at RMAX, coding one logic bit.

In the conventional SRAM based sense amplifier as represented on figure 2, the cell senses the magnetic information by briefly turning on the NMOS transistor MN2, "SEN" is the reading control signal. This structure has been demonstrated to read the states of magnetic tunnel junctions in very high speed, which allows the FPGA circuits to realize a real "instant-on" .

However this sense amplifier has numerous drawbacks.

One of the most critical issues is the high sensitivity to the mismatch variations of CMOS transistor properties: when the control signal "SEN" is set to ' 0 ' , this circuit is in a metastable state and the statistic distribution of threshold voltage for the five transistors may lead to the wrong output. In order to reduce this high sensitivity, the dimension of the transistors must be oversized compared to overall technology node dimensions, which increases greatly the sense amplifier area on the chip. And the issue is aggravated as the MOS technology scales down. A second drawback of this sense amplifier is its high power consumption during the data sensing, because permanent currents pass in the two branches from Vdd_Logic to Gnd.

The dynamic current-mode logic sense amplifier represented on figure 3 was proposed to sense the magnetic tunnel junction pair coding the logic signal. In this scheme, each magnetic tunnel junction in the two branches of the circuit is associated with one NMOS transistor TNMOS MNl and MNO, which gates are controlled by a "SELECT" logic signal: hence, several pairs of magnetic tunnel junction and NMOS transistors can be connected to the same sense amplifier and addressed individually. Let's assume that for the MNl and MNO transistors represented on figure 3 the "SELECT" signal is set to Vdd_logic and the transistors are thus open. As in the SRAM based sense amplifier, there are two operating phases. In the first one, "SEN" equals to

' 0 ' , the outputs signals Qm and Qm are charged to Vdd_Logic and the capacitor CO is reset to ' 0 ' . When the control signal "SEN" is set from ' 0 ' to ' 1 ' , the circuit senses the resistance difference between the two magnetic tunnel junctions while charging the capacitor CO: the imbalance in resistance produces different currents in the two branches, finally switching the output signal Qm to "1" or "0". One major advantage of this sense amplifier is that there are no permanent currents from Vdd_Logic to GND.

However this scheme has still two major drawbacks.

First, the circuit comprised ten transistors including MP0-MP3, MNO-3, plus the inverter necessary to generate the signal "SEN", and a capacitor CO. Comparing with the classical sense amplifier, there are too many transistors for a high density application.

Secondly, although the capacitor CO blocks the permanent currents from Vdd_Logic to GND, it also produces the voltage at Qm and Qm, through a chain of transistors and MAGNETIC TUNNEL JUNCTIONS. Therefore the outputs can not be exactly zero or Vdd_Logic and the margin between the two voltages should be well reduced, resulting in high sensitivity to mismatch variations and also numerous errors in the next stage of logic circuits.

One goal of the present invention is to provide a sense amplifier circuit that does not present the drawbacks of the sense amplifiers of the prior art. Such sense amplifier can then be used for sensing the configuration of any pair of variable resistors.

For this purpose, one subject of the invention is a sense amplifier circuit comprising:

^■ a first, second, third and fourth PMOS transistors whose sources are at a voltage source Vdd,

^■ a first and second NMOS transistors whose drains are respectively connected with the drains of the first and second PMOS transistors, and with the drains of the third and fourth PMOS transistors,

^■ the sources of the first and second NMOS transistors being connected respectively to a first and second variable resistors that can be reversibly switched between two extreme states,

^■ the first and second variable resistors being connected to the drain of a third NMOS transistor,

^■ the source of the third NMOS transistor being connected to a reference voltage Vref, ■ the gates of the second PMOS transistor and of the first NMOS transistor being connected together and to the drains of the second NMOS transistor and third PMOS transistors,

^■ the gates of the third PMOS transistor and of the second NMOS transistor being connected together and to the drains of the first NMOS transistor and second PMOS transistors,

^■ the gate of the third NMOS transistor being connected to the gates of the first and fourth PMOS transistors, wherein the sense amplifier circuit is configured so that when one of the variable resistors is at minimum resistance state the other is at maximum resistance state.

Advantageously, the sense amplifier circuit according to the invention can improve significantly the stability, as a result shrink the die area, and reduce the sensing power down to be nearly negligible. The sense amplifier according to the invention provides a similar sensing latency as for the conventional SRAM sense amplifier, while based on the operation mode all transistors could be taken to the lowest size of the given technology node.

According to further embodiments of the invention: - the sense amplifier circuit is configured so as:

^■ the gates of the second PMOS transistor and of the first NMOS transistor are connected to the drains of the fourth PMOS transistor, and

^■ the gates of the third PMOS transistor and of the second NMOS transistor are connected to the first PMOS transistor;

- the first and second variable resistors are connected to the same third NMOS transistor;

- the first and second impulse current variable resistors are connected respectively to the drain of a first third NMOS transistor and a second third NMOS transistor, the gates of the first and second thirds NMOS transistors being connected together;

- the gates of the first and second thirds NMOS transistors being connected to the gates of the first and fourth PMOS transistors;

- the variable resistors are resistive memory devices;

- the variable resistors are magnetic tunnel junctions;

- the current variable resistors are phase-change memory devices; - one of the current variable resistors is replaced by an invariable reference resistor of resistance comprised between the minimum and maximum values of the resistance of the variable resistor;

- the sense amplifier circuit further comprises a fourth and fifth NMOS transistors, the drain of the fourth NMOS transistor being connected to a heating voltage, the source of the fourth NMOS transistor being connected to the first variable resistor, the drain of the fifth NMOS transistor being connected to the second variable resistor, the source of the fifth NMOS transistor being connected to a reference voltage, and the gates of the fourth and fifth NMOS transistors being arranged so as to receive a enabling signal; - the sense amplifier circuit further comprises a fourth and fifth NMOS transistors, the drains of the fourth and fifth NMOS transistors being connected together to a heating voltage, the source of the fourth NMOS transistor being connected to the source of the first NMOS transistor, the source of the fifth NMOS transistor being connected to the source of the second NMOS transistor, and the gates of the fourth and fifth NMOS transistors being arranged so as to receive a enabling signal; - the sense amplifier circuit further comprises a sixth NMOS transistor, the drain of the sixth NMOS transistor being connected to the drain of the third NMOS transistor, the source of the sixth NMOS transistor being connected to a reference voltage, the gate of the sixth NMOS transistor being arranged so as to receive a enabling signal;

- the first and fourth PMOS transistors are replaced by any CMOS circuit either specially attached to the sense amplifier or shared between several sense amplifiers in a word or register, and wherein the CMOS circuit is configured so as upon a sense signal to connect the drains of the second and third PMOS transistors and of the first and second NMOS transistors to a voltage substantially equal to Vdd.

The invention also relates to a hybrid CMOS logic circuit including magnetic tunnel junction comprising a sense amplifier circuit according to the invention.

The invention further relates to a look-up table of a programmable logic circuit comprising a sense amplifier circuit according to the invention. According to further embodiments of the invention:

- the look-up table comprises at least two non-volatile bit comprising a switching circuit, two variable resistors and a sense amplifier circuit according to the invention; - at least two couples of magnetic tunnel junctions share fully or partly the same switching circuit and the same sense amplifier circuit according to the invention.

The invention also relates to a Latch circuit comprising a sense amplifier circuit according to the invention .

According to further embodiments of the invention:

- a writing circuit is arranged for memorizing information in magnetic tunnel junctions by switching them, and wherein the sensing circuit and the switching circuits are independent and the sensing circuit comprises a sense amplifier circuit according to the invention;

- the writing circuit is arranged to switch magnetic tunnel junctions by spin transfer torque mechanism; - the magnetic tunnel junctions are arranged to be switched by thermally assisted switching mechanism.

Other features and advantages of the present invention will become apparent in the description of non limiting exemplary embodiments, making references to the following drawings, in which:

- Figure 1 is a schematic representation of a magnetic tunnel junction;

- Figure 2 is a schematic representation of a conventional Five transistor SRAM based sense amplifier;

- Figure 3 a schematic representation of a dynamic current-mode logic sense amplifier;

- Figure 4 is a schematic representation of a sense amplifier circuit according to the invention;

- Figures 5 is a schematic representation of a circuit for Spin Transfer Torque and Thermally Assisted Switching writing mode; - Figures 6a to 6 d are schematic representations of different heating circuit for Thermally Assisted Switching writing mode;

- Figure 7 is a schematic representation of a non volatile Flip-Flop gate, or non volatile latch;

- Figures 8a to 8c are schematic representations of circuit for multi-context configuration for look-up table applications;

- Figure 9 is a schematic representation of a two contexts A and B in a single sense amplifier circuit; and

- Figure 10 is a schematic representation of a sense amplifier circuit according to an embodiment of the invention . For reasons of clarity, the elements shown on the figures are not necessarily to scale.

Figures 1 to 3 has been discussed in the prior art. According to an embodiment of the invention represented on figure 4, the sense amplifier circuit 10 may comprise:

^■ a first 12, second 14, third 16 and fourth 18 PMOS transistors whose sources are at a voltage source Vdd,

^■ a first 20 and second 22 NMOS transistors whose drains are respectively connected with the drains of the first 12 and second 14 PMOS transistors, and with the drains of the third 16 and fourth 18 PMOS transistors,

^■ the sources of the first 20 and second 22 NMOS transistors being connected respectively to a first 24 and second 26 variable resistors that can be reversibly switched, for example by proper action, between two extreme states, the sense amplifier is configured so that one resistor is always at minimum resistance state while the other is at maximum resistance state,

^■ the first 24 and second 26 variable resistors being connected to the drain of a third NMOS transistor 28,

^■ the source of the third NMOS transistor 28 being connected to a reference voltage Vref,

^■ the gate of the third NMOS transistor 28 being connected to the gates of the first 12 and fourth 18 PMOS transistors,

^■ the gates of the second PMOS transistor 14 and of the first NMOS transistor 20 being connected together and to the drains of the second NMOS transistor 22 and third 16 PMOS transistors,

^■ the gates of the third PMOS transistor 16 and of the second NMOS transistor 22 being connected together and to the drains of the first NMOS transistor 20 and second 14 PMOS transistors.

The sense amplifier circuit 10 represented on figure 4 comprises inverters 14, 20 and 16, 22, two PMOS transistors 12, 18 in parallel with respectively the second 14 and third 16 PMOS transistors. The third NMOS transistor 28 is connected to the reference voltage, for example the ground voltage. The first and second variable resistors of the sense amplifier represented on figure 4 are magnetic tunnel junctions.

As a classical sense amplifier, this sense amplifier represented on figure 4 comprises two operating phases depending on the control signal "SEN".

In the first phase the control signal "SEN" is set to ' 0 ' , the sense amplifier circuit 10 pre-charges the polarisation voltages VO and Vl of the two magnetic tunnel junctions 24, 26 to a value slightly below Vdd_logic, but there is no stationary current in the circuit. Indeed, as the control signal "SEN" is set to ^y0 ' , the first, fourth PMOS transistors 12, 18 and the first, second NMOS transistors 20, 22 are open while the third NMOS transistor 28 is closed, therefore no stationary current passes through the circuit after the charging of VO and Vl has been completed, hence nearly zero power consumption during this operation phase.

In the second phase when the control signal "SEN" is set from ^y0 ' to ' 1 ' , the first and fourth PMOS transistors 12, 18 close while the third NMOS transistor 28 opens. So low discharge currents pass through the branches to sense the two magnetic tunnel junctions 24, 26, the resistance of the magnetic tunnel junctions 24, 26 determines the discharge speed. Since the two magnetic tunnel junctions 24, 26 have different resistances, the discharge speeds are different .

For example, if the two ferromagnetic layers of the first magnetic tunnel junctions 24 are parallel and the two ferromagnetic layers of the second magnetic tunnel junctions 26 are antiparallel, then the resistance of the first magnetic tunnel junction 24 is lower than the resistance of the second magnetic tunnel junction 26 RMTJO>RMTJ1. Therefore the current Il through the first magnetic tunnel junction 24 is greater than the current IO through the second magnetic tunnel junction 26.

In rapid sequence of this discharge, V3 is reduced faster than V2, and when V3 becomes smaller than the threshold switching voltage of the inverter composed by the third PMOS 16 and second NMOS 22 transistors, V2 charges to Vdd_logic and V3 continues the discharge process down to '0' .

After the sensing phase, the third PMOS transistor 16 and the first NMOS transistor 20 are open, the value of the output signal Qm is ' 1 ' for this configuration wherein the first magnetic tunnel junction 24 is parallel and the second magnetic tunnel junction 26 is anti-parallel.

If the magnetic tunnel junctions configuration had been opposite, the value of the output signal Qm would be '0' .

The sense amplifier circuit according to the invention overcomes the drawbacks of the sense amplifier of the prior art. In particular, the complete scheme requires only 7 transistors. Because only very small transitory currents are used, energy consumption for the sense phase is very small .

Furthermore, the scheme is less sensitive to mismatch variation than the conventional SRAM based scheme represented on figure 2. Hence transistors at the smallest size of a given technology can be used.

The output signal Qm results from the normal operation of a SRAM with only some resistances in series: the first and second magnetic tunnel junctions and the third NMOS transistor open when the control signal "SEN" is equal to ' 1 ' , contrary to the case of the Dynamic current-mode logic sense amplifier represented on figure 2.

Furthermore, it is possible to understand where the sensitivity to transistor mismatch comes from in the sense amplifier circuit according to the invention.

When the control signal "SEN" is equal to ^y0 ' , the difference between voltages Vl and VO reflects only the mismatch between threshold voltages of the transistors couples first NMOS-second PMOS 14-20 and second NMOS-fourth PMOS 18-22, estimated to be of the order of 10-20%. As soon as the discharge process starts, the difference in discharge speeds, hence the reliability of the reading process, depends only on the difference in resistances of the two magnetic tunnel junctions. If this difference in resistance is greater than 20%, the transistor mismatch rapidly becomes negligible. According to an embodiment of the invention, the sense amplifier circuit according to the invention may be implemented associated with a writing circuit. The sense amplifier circuit according to the invention may be used for the conventional magnetic tunnel junction writing approach using "Field Induced Magnetic Switching" (FIMS), where the sensing circuit and switching circuits are substantially independent.

Examples of Field Induced Magnetic Switching schemes are described by W. J. Gallagher and S. S. P. Parkin in "Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip, " IBM J. of Res. and Dev., vol. 50, p. 5, 2006; and by B. N. Engel, J. Akerman, B. Butcher, R. W. Dave, M. DeHerrera, M. Durlam, G. Grynkewich, J. Janesky, S. V. Pietambaram, N. D. Rizzo, J. M. Slaughter, K. Smith, J. J. Sun, and S. Tehrani in "A 4-Mb toggle MRAM based on a novel bit and switching method," Magnetics, IEEE Transactions on, vol. 41, pp. 132- -136, 2005.

An example of how such Field Induced Magnetic Switching can be applied to a Flip-Flop gate is given in by N. Sakimura, T. Sugibayashi, T. Honda, S. Miura, H. Numata, H. Hada, and S. Tahara, in "A 512kb cross-point cell MRAM," in Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, 2003, pp. 278--279 vol.l.

Because writing circuit and sensing circuit are almost completely separated, the implantation of Field Induced Magnetic Switching writing scheme using a sense amplifier according to the invention does not influence said sense amplifier .

The sense amplifier circuit according to the invention may also be adapted to be used with writing schemes that require sending a current through the magnetic tunnel junction. Indeed, during the precharge phase, when the value of the control signal "SEN" is ^y0', the third NMOS transistor 28 is closed and the two magnetic tunnel junctions from the sensing circuit are just connected in series between VO and Vl, and somewhat electrically isolated if the first and second NMOS transistors 20, 22 are blocked.

The Spin Transfer Torque (STT) such as described in M.Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachino and C. Fukumoto. "A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching Spin-RAM" IEEE International Electron Devices Meeting (IEDM), USA, Dec. 5-7, 2005, pp 473-476 and Thermally Assisted Spin Transfer Torque switching (TAS-STT) such as described in US 7230844 modes only require bipolar current pulses injected through the magnetic tunnel junction to directly write a magnetic tunnel junction configuration.

As represented on fig 5 the Spin Transfer Torque and Thermally Assisted Spin Transfer Torque switching circuits may be connected directly to a sense amplifier circuit 10 according to the invention. The Spin Transfer Torque and Thermally Assisted Spin Transfer Torque switching circuits can be active during the precharge phase and write the new data in the magnetic tunnel junction pair, but will have no impact on the sensing phase, as when the enabling signal EN is set to ' 0 ' the fourth 30, fifth 32, sixth 34 and seventh 36 NMOS transistors are blocked, and they require no additional transistors in the sense amplifier circuit.

Writing data by a current pulse in the magnetic tunnel junction pair may be done by setting the enabling signal "EN" to ' 1 ' in the precharge phase, i.e. when the control signal of the sense amplifier circuit 10 "SEN" equals ' 0 ' . In this case, the third NMOS transistor 28 is closed, the gates voltages V2 and V3 of the first and second NMOS transistors 20, 22 are charged to Vdd_logic, and the writing current pass through the two magnetic tunnel junctions only.

Prior to the data sensing phase, hence before the control signal "SEN" is set from ' 0 ' to ' 1 ' , the switching current circuit may be closed by simply setting the enabling signal "EN" from ' 1 ' to ' 0 ' with enough time left for the precharge circuit to stabilize before sensing.

In the example of a writing current flowing from the second 26 to the first 24 tunnel junction, the inventors have observed concerning the expected current paths during a writing phase: - Vdda is higher than Vdd_logic, thereby VO can also be higher than Vdd_logic and the second NMOS transistor 22 is always closed,

- after the voltage drop through the first and second magnetic tunnel junctions 24, 26, Vl may be slightly lower than Vdd_logic and a low courant 13 from V3 to Gnda passing through the first NMOS transistor to the seventh NMOS transistor 36 may appear. As it does not pass through the first magnetic tunnel junction 24, 13 may have no influence on the switching, but may be considered when optimizing the circuit .

A similar observation can be done for a reverse current flowing from the first 24 to the second 26 tunnel junction, with in this case VO that can be slightly lower than Vdd_logic and a low current 14 from V2 to Gnda passing through the second NMOS transistor to the fourth NMOS transistor 30.

The circuit represented on figure 5 comprises 3 NOT and 2 NOR gates. Said logic gates are used to fix the current direction and control the activation of the writing circuit .

The circuit represented on figure 5 may be simplified to 2 NOT and 2 NOR, which corresponds to 12 transistors. As a whole the Spin Transfer Torque writing circuit thus requires 16 transistors per bit, to be added to the 7 transistors of the sensing circuit according to the invention. However, a part of the logic block can be shared between several sense amplifier circuits in a multi-bit word or register. Besides, depending on the exact writing current density that may be required, all transistors could be taken to the smallest size of a given technology node below 90nm.

The Thermally Assisted Switching (TAS) writing mode uses a unipolar current pulse sent through the magnetic tunnel junction to rise its temperature above a given threshold, together with a bipolar magnetic field created by a bipolar current pulse sent through an independent conducting line to define the bit direction during the cool down step.

The requirement for only unipolar current pulse through the magnetic tunnel junction allows to greatly simplify the writing circuit of figure 5, with only two transistors as magnetic tunnel junction current source and no logic block as only the enabling signal "EN" is required .

This reduces the close writing circuit to 2 transistors per bit, plus of course the field creation line and CMOS circuit that can be shared between several bits.

Figures 6a to 6d represent several heating circuits of the sense amplifier circuit for the Thermally Assisted Switching writing mode. On figure 6a, a first scheme for the application of Thermally Assisted Switching writing mode to the sense amplifier circuit, adapted from the scheme represented on figure 5 as described in the text above. Similar to the Spin Transfer Torque mode, writing is done by setting the enabling signal "EN" to ' 1 ' during the precharge phase, i.e. when the control signal "SEN" equals ' 0 ' : then a current passes through the magnetic tunnel junctions to heat them, and a magnetic field pulse can then be applied to fix the new magnetic configuration. Vdda may take a different value than Vdd_logic. This scheme adds only 2 transistors to a single bit sense amplifier circuit, and the logic block of Figure 5 is no more required.

Figure 6b represents a second scheme to implement the Thermally Assisted Switching writing mode to the sense amplifier circuit. As for the Spin Transfer Torque mode, writing is done by setting the enabling signal "EN" to ' 1 ' in the precharge phase, i.e. when the control signal "SEN" equals ' 0 ' . The logic block, an inverter, an OR gate and a AND gate, ensures that the first and fourth PMOS transistor 12, 18 and the first, second and third NMOS transistors 20, 22, 28 are conducting, so that a current passes through the magnetic tunnel junctions to heat them.

Unlike the scheme of figure 6a, this scheme requires no extra transistor in the sense amplifier circuit itself, which stays at 7 transistors per sense circuit in total, and the logic block can be shared between several sense amplifier circuits in a multi-bit word or register.

Figure 6c represents a third scheme to implement the Thermally Assisted Switching writing mode to the sense amplifier circuit, adapted from the scheme of Figure 6b to allow higher values of the heating currents. Two NMOS transistors 40, 42 are added to connect the magnetic tunnel junctions 24, 26 to Vdda when the enabling signal "EN" is set to ' 1 ' : the heating current then passes through only two transistors in series with the magnetic tunnel junctions 24, 26, and furthermore Vdda can take a higher value than Vdd_logic. The logic block of Figure 6b is kept to create the input signals "A" and "B" from the enabling signal "EN" and the control signal "SEN".

Figure 6d represents a fourth scheme to implement the Thermally Assisted Switching writing mode to the sense amplifier circuit, adapted from the scheme of figure 6c. A transistor 44 is added to the sense amplifier circuit, which allows to get rid of the logic block used in figure 6c to create the input signals "A" and "B" from the enabling signal "EN" and control signal "SEN".

According to an embodiment of the invention, the enabling signal "EN" may be taken equal to the inverse of the clock signal "CLK_bar" and the control signal "SEN" may be taken equal to the clock signal "CLK". The complete magnetic logic bit described above plays the role of a non volatile Flip-Flop gate or non volatile latch, written at every period of the CLK as illustrated on figure 7. For other applications, it could also play the role of a memory that is written only at specific moment, for instance to register status information before powering down a device, or to reprogram dynamically a logic function in a Look Up Table (LUT) .

Combining the switching circuits represented on figures 5 and 6 with the sense amplifier circuit according to the invention, one non-volatile logic bit can be made, comparable to a non volatile SRAM memory cell.

With words of N bits to be written simultaneously in parallel using the Spin Transfer Torque or thermally Assisted Spin Transfer Torque modes, the requirement of a bipolar current through each pair of magnetic tunnel junctions results in that only the generation of the write enable signal "EN" and of the control signal "SEN" commands can be shared on the N-bits word. So each bit requires a complete "23 transistors" reading and writing circuit represented on Figure 5.

This condition could be greatly amended if the bits were written sequentially, but at the expense of a much slower operation.

Figure 8a shows an example of 2-inputs Look up table based on multi-context principle. One non volatile bit is composed of one sense amplifier circuit according to the invention including two magnetic tunnel junctions, and one switching circuit. Such example illustrates how non volatile bits can be combined to form a non volatile, dynamically reprogrammable Look up Table.

The area occupied by the non volatile bits seems large in this straightforward arrangement because all non volatile bits require their complete writing circuit, however in such configuration the NMOS switch is shared by all bits, which can lead to global wafer area reduction when the number of inputs increases compared to standard SRAM based look up tables.

A huge wafer area reduction could be further gained by sharing at least partly the same switching circuit between the N bits of a word, as schematized on Figure 8b where four couples of magnetic tunnel junctions share the same switching current source and the same sense amplifier circuit . Figure 8c provides an example of partly shared writing circuit on a 2 bits word. Writing with the circuit represented on figure 8c when the SEN command is kept to "0" requires 2 sub-phases: a) with the writing signal "Write" set to ' 0 ' and the enabling signal "EN" set to ^y0 ' , the gates of the NMOS transistors MNOA, MNOB, MNlA, MNlB are set to Vdd_logic for all bits, so when the enabling signal "EN" is set from ' 0 ' to ' 1 ' a "0" state is written on all bits. The enabling signal "EN" may be then taken back to ' 0 ' while the writing signal "Write" is still at ' 0 ' : this closes all transistors MN03, MN04, MN05, MN06 in the writing circuit. b) if the writing signal "Write" is changed to '1' with the enabling signal "EN" still set to O', only bits with Input set to '1' are written to ' 1 ' state when setting the enabling signal "EN" from O' to '\'. For the other bits, the previously written ' 0 ' state is preserved.

In this scheme, the logic block is shared on the whole word, with a compact 6-transistors writing circuit to be kept for each bit. The total bit size is only 13 transistors and 2 magnetic tunnel junctions per bit.

In the case of Look up Table, an integrated sharing can be achieved using a multi-context configuration as shown on figure 9. A single sense amplifier circuit is connected to several magnetic tunnel junction pairs storing the outputs of the logic function; two pairs A and B are shown on figure 9. For reading or writing a specific pair, a coder may provide the commands A and B. The combined commands SEN. A (resp. .B) and EN. A (resp. .B) may be used to select the pair of magnetic tunnel junctions to read or write.

The sense amplifier circuit structure itself is modified as the third NMOS transistor attached to the two magnetic tunnel junctions is replaced by three NMOS transistors, two for connecting individually each magnetic tunnel junctions to Gnd_logic, and the transistor MNA2 (resp B2) connecting together the two magnetic tunnel junctions of a given pair.

To program the A pair for instance, the input signal "A" is set to ' 1 ' as the enabling signal "EN" is active and the input signal "B" is set to ' 0 ' , and the two magnetic tunnel junctions of the A pair can be switched by the Iw current provided by a single bipolar current source.

To read the data in the A pair configuration, the input signal "A" is set to ' 1 ' and the control signal "SEN" is changed from ' 0 ' to ' 1 ' while the input signal "B" is kept to "0", and the data of the A pair is transferred to the output .

The scheme represented on figure 9 presents the advantage of completely sharing the sense amplifier circuit and the bipolar current writing circuit between all non volatile bits, at the expense of the shared coder providing the commands A and B, and of the gates, at each bit, charged to provide the combined commands SEN. A (resp. .B) and EN. A (resp. .B) .

Several types of assistance to Spin Transfer Torque and Spin Transfer Torque with Thermally Assisted Switching writing, designed to enhance speed and switching reliability while reducing threshold current densities, can also be shared at least on a word of N bits and probably on whole blocks depending on the specific block architecture used. Examples are: - assistance by a pulse of unipolar transverse magnetic field as described for example in EP06118378: in that case, the unipolar current source and the conducting line for field creation can easily be shared on a word (or even on several words to be written in parallel, the limitation being here the voltage drop and Joule heating in the line) . assistance by electric field as described in EP07112497, either through direct voltage influence on magnetic anisotropy as described by M. Weisheit, S. Fahler, A. Marty et al . , "Electric Field-Induced Modification of Magnetism in Thin-Film Ferromagnets, " Science 315 (5810), 349--351 (2007), though coupling to a piezoelectric or multiferroic layer, or similar effects allowing to momentarily change the magnetic properties relevant to switching processes. This mode of switching assistance could also be easily shared on a whole word or more, as it requires no current passing through the magnetic tunnel junctions.

The N-bits register, LUT and multicontext architectures according to the invention may also be adapted for writing by the standard thermally assisted writing mode. As described, only a unipolar current pulse through the magnetic tunnel junction is needed, which simplifies a lot the standard writing circuit attached to the sense amplifier circuit, only two transistors.

In a LUT configuration such as the one of figure 8a, or a N-bit register, the conducting line and bipolar current source may be shared between all bits, provided that the writing step is done in two steps: first step to write all magnetic tunnel junctions requiring one field direction, and second step to write the magnetic tunnel junctions requiring the reverse field direction. As the magnetic field is unable to switch a magnetic tunnel junction that is not heated, the two steps writing just requires a supplemental logic to control which bits are heated at each step, which can be done in a similar way as used for the device of figure 8c.

According to an embodiment of the invention, the sense amplifier circuit may be implemented in Sharing writing circuit and assistance for Flip-Flop applications. Unlike the Look up table application, the non-volatile Flip-Flop application requires very high speed, normally of smaller or equal to a nanosecond.

The signals "SEN", "EN", "Write" may all be generated through the clock signal "CLK". The Flip-Flop application, and some others, also requires another mandatory circuit: a "Slave" logic block on the output of each bit, to save the output Qm during the writing phase when the control signal "SEN" I set to ' 0 ' .

According to an embodiment of the invention, the sense amplifier circuit may be configured so as to use only one magnetic tunnel junction device per logic bit, therefore avoiding the need to simultaneously switch a pair of magnetic tunnel junctions.

A convenient technique to achieve this goal may be to replace the pair of magnetic tunnel junctions 24, 26 of the sense amplifier circuit by a writeable magnetic tunnel junction 24 combined with a reference magnetic tunnel junction 25. The reference magnetic tunnel junction 25 has an initial orientation of the free layer uniform on the whole chip and is kept unchanged by normal operation. An example of such structure is illustrated on figure 10.

To get the largest margin and improve the sensing stability, in average during the sensing phase, second phase after the pre-charge phase, the resistance of the reference magnetic tunnel junction 25 takes a value somewhere in between the P and AP resistances of the written magnetic tunnel junction, taking into account the bias voltage effect due to non zero voltage across the magnetic tunnel junctions. In that case, the effective TMR ratio may be about half compared to that of the sense amplifier circuit with the pair of writing magnetic tunnel junctions . The exact value of the resistance of the reference magnetic tunnel junction 25 may easily be evaluated from model electrical simulations.

Since the reference and the writing magnetic tunnel junctions 24 may be implemented with the same magnetic stack to save on fabrication costs, their resistances may be obtained by giving different lateral dimensions to both magnetic tunnel junctions.

Since the writing process in Spin Transfer Torque and all Thermally Assisted Switching modes requires sending currents through only one magnetic tunnel junction instead of two in series, the writing power is reduced and so is Vdda . In the Field Induced Magnetic Switching writing mode the complexity of the field creation lines may also be much reduced. One very important gain is for the multi context architecture, where only one transistor and one magnetic tunnel junction are now required per context, compared to three transistors and two magnetic tunnel junctions for the conventional sense amplifier circuit. The invention has been described above using embodiments without limitation of the general inventive concept; in particular the variable resistors are not limited to the example disclosed.

Claims

CLAIMS :

1. A sense amplifier circuit comprising:

^■ a first (12), second (14), third (16) and fourth (18) PMOS transistors whose sources are at a voltage source

Vdd,

^■ a first (20) and second (22) NMOS transistors whose drains are respectively connected with the drains of the first (12) and second (14) PMOS transistors, and with the drains of the third (16) and fourth (18) PMOS transistors,

^■ the sources of the first (20) and second (22) NMOS transistors being connected respectively to a first (24) and second (26) variable resistors that can be reversibly switched between two extreme states,

^■ the first (24) and second (26) variable resistors being connected to the drain of a third NMOS transistor (28 ),

^■ the source of the third NMOS transistor (28) being connected to a reference voltage Vref,

^■ the gates of the second PMOS transistor (14) and of the first NMOS transistor (20) being connected together and to the drains of the second NMOS transistor (22) and third (16) PMOS transistors, ■ the gates of the third PMOS transistor (16) and of the second NMOS transistor (22) being connected together and to the drains of the first NMOS transistor (20) and second (14) PMOS transistors,

^■ the gate of the third NMOS transistor (28) being connected to the gates of the first (12) and fourth

(18) PMOS transistors, wherein the sense amplifier circuit is configured so that when one of the variable resistors (24, 26) is at minimum resistance state the other is at maximum resistance state.

2. The sense amplifier circuit according to claim 1, wherein : ■ the gates of the second PMOS transistor (14) and of the first NMOS transistor (20) are connected to the drains of the fourth (18) PMOS transistor, and ■ the gates of the third PMOS transistor (16) and of the second NMOS transistor (22) are connected to the first (12) PMOS transistor.

3. The sense amplifier circuit according to any of claims 1 or 2, wherein the first (24) and second (26) variable resistors are connected to the same third NMOS transistor (28) .

4. The sense amplifier circuit according to any of claims 1 or 2, wherein the first (24) and second (26) impulse current variable resistors are connected respectively to the drain of a first third NMOS transistor (28a) and a second third NMOS transistor (28b) , the gates of the first and second thirds NMOS transistors being connected together .

5. The sense amplifier circuit according to claim 4, wherein the gates of the first and second thirds NMOS transistors being connected to the gates of the first (12) and fourth (18) PMOS transistors.

6. The sense amplifier circuit according to any of the preceding claims, wherein the variable resistors are resistive memory devices.

7. The sense amplifier circuit according to any of the preceding claims, wherein the variable resistors are magnetic tunnel junctions.

8. The sense amplifier circuit according to any of claims 1 to 6, wherein the current variable resistors are phase- change memory devices.

9. The sense amplifier circuit according to any of the preceding claims, wherein one of the current variable resistors is replaced by an invariable reference resistor of resistance comprised between the minimum and maximum values of the resistance of the variable resistor.

10. The sense amplifier circuit according to any of the preceding claims, further comprising a fourth (38) and fifth (39) NMOS transistors, the drain of the fourth NMOS transistor (38) being connected to a heating voltage (Vdda) , the source of the fourth NMOS transistor (38) being connected to the first (24) variable resistor, the drain of the fifth (39) NMOS transistor (38) being connected to the second (28) variable resistor, the source of the fifth (39) NMOS transistor (38) being connected to a reference voltage (Gnd_Heat), and the gates of the fourth (38) and fifth (39) NMOS transistors being arranged so as to receive a enabling signal (EN) .

11. The sense amplifier circuit according to any of claims 1 to 9, further comprising a fourth (42) and fifth (42)

NMOS transistors, the drains of the fourth (40) and fifth (42) NMOS transistors being connected together to a heating voltage (Vdda), the source of the fourth (40) NMOS transistor being connected to the source of the first NMOS transistor (20), the source of the fifth (42) NMOS transistor being connected to the source of the second NMOS transistor (22), and the gates of the fourth (40) and fifth (42) NMOS transistors being arranged so as to receive a enabling signal (EN) .

12. The sense amplifier circuit according to claim 11, further comprising a sixth NMOS transistor (44), the drain of the sixth NMOS transistor (44) being connected to the drain of the third NMOS transistor (28), the source of the sixth NMOS transistor (44) being connected to a reference voltage (Gnd_Heat), the gate of the sixth (44) NMOS transistor being arranged so as to receive a enabling signal (EN) .

13. The sense amplifier circuit, according to any of the preceding claims, wherein the first (12) and fourth (18) PMOS transistors are replaced by any CMOS circuit either specially attached to the sense amplifier or shared between several sense amplifiers in a word or register, and wherein the CMOS circuit is configured so as upon a sense signal to connect the drains of the second (14) and third (16) PMOS transistors and of the first (20) and second (22) NMOS transistors to a voltage substantially equal to Vdd.

14. A hybrid CMOS logic circuit including magnetic tunnel junction comprising a sense amplifier circuit according to any of claims 1 to 13.

15. A Look-up table of a programmable logic circuit comprising a sense amplifier circuit according to any of claims 1 to 13.

16. The look-up table according to claim 15, wherein the look-up table comprises at least two non-volatile bit comprising a switching circuit, two variable resistors and a sense amplifier circuit according to any of claims 1 to 13.

17. The look-up table according to claim 15, wherein at least two couples of magnetic tunnel junctions share fully or partly the same switching circuit and the same sense amplifier circuit according to any of claims 1 to 13.

18. A Latch circuit comprising a sense amplifier circuit according to any of claims 1 to 13.

19. The Latch circuit according to claim 18, wherein a writing circuit is arranged for memorizing information in magnetic tunnel junctions by switching them, and wherein the sensing circuit and the switching circuits are independent and the sensing circuit comprises a sense amplifier circuit according to any of claims 1 to 13.

20. The Latch circuit according to claim 19, wherein the writing circuit is arranged to switch magnetic tunnel junctions by spin transfer torque mechanism.

21. The Latch circuit according to claim 19 or 20, wherein the magnetic tunnel junctions are arranged to be switched by thermally assisted switching mechanism.