WO2010081603A1

WO2010081603A1 - Semiconductor circuit having interlayer connections and method for producing vertically integrated circuits

Info

Publication number: WO2010081603A1
Application number: PCT/EP2009/067211
Authority: WO
Inventors: Franz Schrank; Martin Schrems; Jochen Kraft
Original assignee: Austriamicrosystems Ag
Priority date: 2009-01-15
Filing date: 2009-12-15
Publication date: 2010-07-22
Also published as: DE102009004725A1

Abstract

The invention relates to semiconductor components (S1, S2) connected to each other by means of a connecting layer (5). A connection contact layer (17) is connected to a connection metal layer (12) by means of a metallization (11) in contact hole (14). The connection contact layer and the connection metal layer can be connected to a wiring by means of a metal level (7), or to a contact surface for connecting to a further semiconductor component.

Description

description

Through-hole semiconductor circuit and method of manufacturing vertically integrated circuits

The present invention relates to arrangements of semiconductor devices in which at least one semiconductor device is provided with a through-hole through the substrate, and the production of vertically or cubically integrated circuits.

For producing complex semiconductor circuits, semiconductor chips can be stacked and connected to one another by electrical connection contacts on the upper sides and lower sides. For this purpose, electrically conductive connections must be made from the respective upper side of a chip to the lower side through the substrate. This is usually done by etching contact holes in the substrate and then filling them with metal or another electrically conductive material. If the electric

Conductor thus fabricated does not extend to the backside of the substrate, the substrate is thinned by abrasion from the backside until the electrically conductive material of the via fill is exposed. For connecting the via can be on the surfaces of the

Component metal layers applied and structured according to the intended connections. When stacking the chips, the mutually belonging terminal contact surfaces are arranged one above the other and permanently connected electrically, for example by means of a solder.

(J. Vardaman, "3-D Through-Silicon Vias Become a Reality", Semiconductor International, 6/1/2007) Conventional methods produce vias with diameters of 10 μm to 50 μm, with the vias being copper (T. Rowbotham et al., "Back side exposure of variable size through silicon vias", J. Vac., Techn. B24 (5)). , 2006) or polycrystalline silicon (EM Chow et al., "Process-compatible polysilicon-based electrical through-wafer interconnects in silicon substrates", J. of Micromechanical Systems, Vol. 11, No. 6, 2002; JH Wu et al. , "Through-wafer interconnect in Silicon for RFICs", IEEE Trans, on El. Dev. 51, No. 11, 2004) or covered with organic material (N. Lietaer et al., "Development of cost-effective high-density through-wafer interconnects for 3D microsystems ", J. of Micromechanics and Microengineering 16, S29-S34, 2006).

Larger sized vias in semiconductor wafers are made, for example, by etching larger recesses with sloped sidewalls, for example, using KOH. A metal layer applied in the recess is exposed from the opposite upper side of the wafer and provided there with a contact. Heretofore conventional methods are described in US 2005/156330, US 2005/090096, US 6,323,546, US 6,483,147, US 6,159,833, JP 2001 116768, US 6,352,923, US 6,252,300, US 6,110,825, US 5,511,428 and CA 1,057,411.

US 2008/0111213 A1 describes a plated through hole in which a contact hole is etched from one side of the wafer to the opposite side and then completely filled with an electrically conductive material.

In DE patent application 10 2008 033 395.6 are a semiconductor device with a via through the substrate and an associated manufacturing method. In this case, only the side walls and the bottom of a contact hole are coated with electrically conductive material and realized, for example, plated through holes with typical diameters of 100 .mu.m in a substrate with a typical thickness of about 250 microns. A substrate made of a semiconductor material, in particular an SOI substrate made of silicon, is provided with a connection pad of electrically conductive material arranged in a buried insulation layer. From an upper side of the substrate, an opening extending up to the insulating layer is produced above the connection pad. A dielectric layer is deposited, and then the dielectric layer and the insulating layer within the opening are removed to the extent that an upper surface of the terminal pad is exposed. A metallization is applied, which contacts the connection pad. From a rear side of the substrate opposite the opening, a through-connection extending to the connection pad is produced.

The object of the present invention is to provide a new integration technique that demonstrates ways to simplify the production of vertically integrated circuits.

This object is achieved with the semiconductor circuit with through-connection with the features of claim 1 or with the method for producing vertically integrated circuits with the features of claim 12. Embodiments emerge from the dependent claims.

In the semiconductor circuit, a first semiconductor device is provided with a first substrate provided with a device or an integrated circuit, and a second one Semiconductor device having a second substrate, which is also provided with a component or an integrated circuit, permanently connected to each other by means of a connecting layer. The semiconductor devices are preferably still in the composite of a respective semiconductor wafer in the manufacture of the semiconductor circuit, and the semiconductor wafers are connected to each other by a per se known process of wafer bonding. For this purpose, at least one of the semiconductor wafers to be connected to one another is provided on a top side with a connection layer or bonding layer. The bonding layer may be, for example, an oxide of the semiconductor material, in particular silicon dioxide. The other wafer is placed on the tie layer and permanently attached thereto. This arrangement of two semiconductor bodies and the connecting layer therebetween is suitable for an application of the manufacturing method described in the introduction, in which a via is produced by applying a metallization to a contact pad exposed in a contact hole and to the side walls of the contact hole. A terminal metal layer arranged on the upper side is electrically conductively connected to the metallization and completes the through-connection. Any connection contact layer is suitable as a connection pad, in particular a metal layer, for example a metal plane of a wiring. If the side of a semiconductor wafer or substrate provided with a component structure, a circuit and / or a wiring or otherwise processed is designated as the front side of the semiconductor component and the opposite side as its rear side, the first semiconductor component and the second semiconductor component with their front sides, with their backs or with a front and a back are joined together. This results in different embodiments of the semiconductor circuit. An upper side of a semiconductor device, which is remote from the other semiconductor device, may be provided in the semiconductor circuit for receiving further components.

The terminal contact layer may be a diffusion region in a substrate and made, for example, by introducing dopant into a region of the semiconductor material. Preferably, the diffusion region is located on a front side of a substrate over which metal layers of a wiring are arranged.

The via may be present in only one of the semiconductor devices or in both semiconductor devices. When the via is provided in both semiconductor devices, the connection layer and the connection contact layer may be disposed on different sides of one of the semiconductor wafers, and the contact hole for receiving the metallization of the via through both semiconductor wafers may be etched. Instead, the terminal contact layer may be disposed between the connected semiconductor wafers. In this case, contact holes are etched in each of the semiconductor wafers each up to the terminal contact layer, and the contact holes are provided with metallizations contacting the terminal contact layer on opposite sides.

The metallization of the plated through hole is preferably electrically insulated from the semiconductor material of the relevant substrate by a sidewall insulation provided on the side wall of the contact hole. The metallization of Via can contact two or more terminal contact layers simultaneously. Two or more via holes in the same semiconductor device may be routed to terminal pads of different metal levels of the same semiconductor device or both semiconductor devices.

In embodiments, a micromechanical sensor, such as a pressure sensor or an inertia force responsive acceleration sensor or yaw rate sensor, is incorporated in a semiconductor device. In such an embodiment, at least one electrically conductive element of a sensor can be arranged in the front side of the one semiconductor component provided with the connection layer, which is electrically conductively connected to the connection contact layer. The electrically conductive element is, for example, an electrode of a capacitance-measuring acceleration sensor with inertia element. Such sensors are known per se and can be used in conjunction with the semiconductor circuit. In the case of a pressure sensor, the electrically conductive element may be an at least partially electrically conductive membrane which is arranged above a recess in the front side of a semiconductor component provided with the connection layer on the rear side and is electrically conductively connected to the connection contact layer.

On the terminal metal layer of the via, a contact surface for applying a solder ball may be provided. Instead, the terminal metal layer may belong to a metal level of the wiring of the respective semiconductor device or be electrically connected to a metal level of the wiring. Embodiments of the Circuitry provide that the terminal metal layer is provided with a terminal conductor of a surface sensor and a conductor pattern, for example, for a biological sensor, on the relevant upper side of the semiconductor circuit is present.

The following is a more detailed description of examples of the semiconductor circuit and the manufacturing method with reference to the attached figures.

FIG. 1 shows a cross section through an exemplary embodiment with a connection of the front side of a first substrate to the rear side of a second substrate provided with a through-through, wherein the through-connection is connected to a metal plane of the first substrate.

Figure 2 shows a cross section through an embodiment with a connection of the front side of a first substrate with the front one with a

Through-connection provided second substrate.

Figure 3 shows a cross section through an embodiment with a connection of the front of a first substrate with the front of one with two

Via contacts provided second substrate.

Figure 4 shows a cross section through an embodiment with a connection of the front side of a first substrate with the front one with a

Via provided second substrate, wherein the via is connected directly to metal layers of both substrates. FIG. 5 shows a cross section through an exemplary embodiment with a connection of the rear side of a first substrate to the rear side of a second substrate, wherein a through-connection through both substrates is present.

FIG. 6 shows a cross section through an exemplary embodiment with a connection of the rear side of a first substrate to the front side of a second substrate, wherein a through-connection through both substrates is present.

Figure 7 shows a cross section through an embodiment with a connection of the back of a first

Substrate with the front side of a second substrate, wherein in each case a via is present in both substrates.

FIG. 8 shows a cross section through an exemplary embodiment according to FIG. 1, wherein the through-connection is connected to a diffusion region of the first substrate.

FIG. 9 shows a cross section through an exemplary embodiment according to FIG. 1, in which the first substrate has an integrated micromechanical sensor.

FIG. 10 shows a cross section through a further exemplary embodiment according to FIG. 1, in which the first

Substrate has an integrated micromechanical sensor. FIG. 11 shows a cross section through an exemplary embodiment according to FIG. 2, in which the second substrate has a surface sensor.

FIG. 12 shows a cross section through an embodiment according to FIG. 5, in which the first substrate has an integrated pressure sensor.

FIG. 13 shows a cross section through a variant of the exemplary embodiment according to FIG. 7, in which two terminal contact layers are present.

FIG. 14 shows a cross section through a variant of the exemplary embodiment according to FIG. 13.

1 shows an embodiment of the semiconductor circuit in cross section. The semiconductor circuit comprises a first semiconductor substrate S1 having a first substrate 1 and a second semiconductor substrate S2 having a second substrate 2. The substrates 1, 2 are each semiconductor material, in particular silicon, and in the production of the semiconductor circuit, preferably in the composite of a semiconductor wafer a plurality of similar semiconductor devices or integrated circuits is produced. In the substrates 1, 2 semiconductor device or integrated circuits are formed, for each of which a wiring is provided on an upper side of the substrate. The wiring may, as usual, comprise one or more structured metal layers 7, as required with intermetal dielectric 4 and vertical conductive connections (vias) 8. In the exemplary embodiments described below, the semiconductor components are usually illustrated with a plurality of metal levels, which in this form are multi-layered wiring form, as is customary in particular in integrated circuits. Instead, only one metal level with terminal contacts may be present, in particular if the relevant component is a single component, such as a power semiconductor component (in particular, for example, a power MOS field-effect transistor, power MOSFET) or an IGBT (insulated-gate bipolar transistor). , The design of the semiconductor circuit with at least one individual component corresponds to the illustration in the figures, except for the number of metal levels, and results directly from deletion of the surplus metal levels. An insulating layer 3 may be present between the semiconductor material and the first or single metal level. The insulating layer 3 may instead be omitted. Under the name semiconductor device is intended in this

Description and in the claims in each case the substrate, including formed therein component structures and the connection contacts or wiring are understood.

The provided with at least one metal level 7 side of

Semiconductor component is hereinafter referred to as the front side Fl, F2, the opposite side of the semiconductor device as the rear side Bl, B2. There is a connection layer 5, which is the front side Fl or the back side Bl of the first semiconductor device Sl with the

Front F2 or the back B2 of the second semiconductor device S2 connects. In the exemplary embodiment of FIG. 1, the front side F1 of the first semiconductor component S1 is connected to the rear side B2 of the second semiconductor component S2. The bonding layer 5 may be a bonding layer commonly used in bonding of semiconductor wafers, and is particularly an oxide of the semiconductor material of the substrates 1, 2. The bonding layer 5 is not intermeshed with each other Connected tops of the semiconductor devices may be covered with a passivation 6.

On the front side Fl of the first semiconductor component S1 is a terminal contact layer 17, which is arranged in this embodiment in the uppermost metal level 7 of the first semiconductor device Sl. However, the terminal contact layer 17 can also be formed in a metal plane 7 which lies at a lower level, that is to say at a smaller distance from the first substrate 1. Above the terminal contact layer 17 is a contact hole 14 in the second semiconductor device S2. The contact hole 14 is etched into the second substrate 2 during manufacture. DRIE (deep reactive ion etching) is an etch process suitable for this purpose. The contact hole 14 is provided with a metallization 11 which contacts the terminal contact layer 17 and is electrically insulated from the semiconductor material of the second substrate 2 by a sidewall insulation 10. The metallization 11 can be applied by means of CVD (chemical vapor deposition) in conformity with the surface, ie with a uniform thickness. By means of a spacer etch, which removes the metal more quickly from the top than from the bottom of the contact hole 14, it is achieved that the remaining metallization 11 according to FIG. 1 is present at the bottom of the contact hole and on its side walls. The metallization

11 is preferably covered by the passivation 6.

On the side facing away from the connecting layer 5 side of the second semiconductor device S2, which is in this embodiment, the front side F2, there is a

Terminal metal layer 12, which is electrically connected to the metallization 11. The connection metal layer

12 is preferably made by sputtering, wherein the Inner sides of the contact hole 14 remain free. The connection metal layer 12 can be applied separately as the uppermost metal layer or, if the front side F2 of the second semiconductor component S2 is located on this upper side of the semiconductor circuit as in the exemplary embodiment of FIG. 1, forms a portion of an uppermost metal level of the second semiconductor component S2. A portion of the terminal metal layer 12a not directly connected to the metallization 11 in the contact hole 14 and forming part of a metal plane 7 is shown as an example.

The exemplary embodiment of FIG. 1 shows how a connection between metal planes of two stacked semiconductor components is possible by means of a through-connection through a substrate that reaches up to a connection contact layer 17, and thus a vertically integrated semiconductor circuit can be realized in an improved manner. The possibilities lying in this integration technology are shown below with reference to further embodiments.

FIG. 2 shows a further exemplary embodiment of the semiconductor circuit with a first semiconductor substrate S1 having a first substrate 1 and a second semiconductor substrate S2 having a second substrate 2 in cross-section. In the exemplary embodiment of FIG. 2, the front side F1 of the first semiconductor component S1 is connected to the front side F2 of the second semiconductor component S2. The components corresponding to the embodiment of FIG. 1 are provided with the same reference numerals in FIG. Preferably, both front sides Fl, F2 of the semiconductor components are provided with a bonding layer 5 before bonding, so that the uppermost metal layers 7 are each covered planarizing. This is in the figure 2 with the double Connection layer 5 indicated. The through-contact with contact hole 14 and metallization 11 is present here not only in the second substrate 2 but also between the conductors of the wiring on the front side F 2 of the second semiconductor component S 2. The terminal contact layer 17 is located, as in the previously described embodiment, in a metal plane 7 on the front side F1 of the first semiconductor component S1

The connection metal layer 12 is arranged in the embodiment of Figure 2 on the back side B2 of the second semiconductor device S2, which is provided with an insulating layer 15, for example, from the material of the Zwischenmetalldielektri- kums. The connection metal layer 12 is not provided here for a connection to a wiring of the second semiconductor component S2, but for an external connection, for example to a connection contact of a further semiconductor component. For this purpose, there is an opening in the passivation 6 in which a contact surface 9 of the connection metal layer 12 can be contacted by a solder ball 13.

FIG. 3 shows a further exemplary embodiment of the semiconductor circuit with a first semiconductor substrate S1 having a first substrate 1 and a second semiconductor substrate S2 having a second substrate 2 in cross-section. In the embodiment of FIG. 3, the front side F1 of the first semiconductor component S1 is connected to the front side F2 of the second semiconductor component S2. The arrangement of the semiconductor devices Sl, S2 with the double connection layer 5 and the configuration of the through-hole correspond to the exemplary embodiment according to FIG. 2, and the corresponding components are shown in FIG the same reference numerals as in Figure 2 provided. In the exemplary embodiment of FIG. 3, there is a further plated-through hole in the second substrate 2, which extends from the rear side B2 of the second semiconductor component S2 to a metal plane 7 on the front side F2 of the second semiconductor component S2. The further via has a further contact hole 14a with a further metallization IIa. The further metallization IIa is in contact with a further connection contact layer 18, which is formed in a metal plane 7 of the second semiconductor component S2. The plated-through holes of the second semiconductor component S2 are electrically conductively connected to one another via the common terminal metal layer 12, so that a connection between the wirings of the two semiconductor components S1, S2 is produced via the plated-through holes.

FIG. 4 shows a further exemplary embodiment of the semiconductor circuit having a first semiconductor substrate S1 with a first substrate 1 and a second semiconductor substrate S2 with a second substrate 2 in cross section. In the exemplary embodiment of FIG. 4, the front side F1 of the first semiconductor component S1 is connected to the front side F2 of the second semiconductor component S2. The components corresponding to the exemplary embodiments of FIGS. 1 to 3 are given the same reference numerals in FIG. The arrangement of the semiconductor components Sl, S2 with the double connection layer 5 and the embodiment of the via correspond to the exemplary embodiment according to FIG. 2. In the exemplary embodiment of FIG. 4, a further terminal contact layer 18a is located in a metal plane 7 on the front side F2 of the second semiconductor component S2 , which like the terminal contact layer 17 at the Front side Fl of the first semiconductor device Sl is contacted by the metallization 11 of the via. The illustrated arrangement of the further connection contact layer 18a within a metal plane 7 of the second semiconductor device S2 has the advantage that in the

Producing the contact hole 14, a portion of the surface of the further terminal contact layer 18 a is exposed and this area occupies only a small portion of the bottom surface of the contact hole 14. It is therefore possible to etch deeper the contact hole 14 adjacent to the further terminal contact layer 18a until the terminal contact layer 17 is also exposed. The then applied metallization 11 then contacted without further process effort already both terminal contact layers 17, 18 a. In this way, a direct electrically conductive connection between the wirings of the two semiconductor components Sl, S2 is produced by means of the plated-through hole.

FIG. 5 shows a further exemplary embodiment of the semiconductor circuit with a first semiconductor substrate S1 having a first substrate 1 and a second semiconductor substrate S2 having a second substrate 2 in cross-section. In the exemplary embodiment of FIG. 5, the rear side Bl of the first semiconductor component S1 is connected to the rear side B2 of the second semiconductor component S2. The components corresponding to the exemplary embodiments of FIGS. 1 to 4 are provided with the same reference numerals in FIG. In the exemplary embodiment of FIG. 5, the contact hole 14 passes through the first substrate 1 and the second substrate 2, and the terminal contact layer 17 is located in a metal plane 7 on the front side F1 of the first semiconductor component S1. In this embodiment, the feedthrough thus connects conductors on the opposite upper sides the semiconductor circuit, namely the terminal contact layer 17 on the front side Fl of the first semiconductor device Sl and the terminal metal layer 12 on the front side F2 of the second semiconductor device S2.

In the fabrication of the via of the embodiment of FIG. 5, the contact hole may be etched in two steps after bonding the semiconductor wafers of the substrates 1, 2. In a first step, starting from the front side F2 of the second semiconductor component S2

Contact hole etched to the connection layer 5, wherein the connection layer 5, which is for example silicon dioxide acts as an etch stop layer. Then, the material of the insulating layer is applied, which later forms the drawn in Figure 5 further sidewall insulation 10a. With a subsequent spacer etching, the material of the insulating layer is removed at the bottom of the contact hole, so that the further side wall insulation 10a stops. In the case of the spacer etching, etching is carried out at the bottom of the contact hole through the connection layer 5 as far as the first substrate 1, the semiconductor material of the first substrate 1, for example silicon, acting as an etching stop layer. The contact hole 14 is then further etched into the first substrate 1 until the insulating layer 3 is reached on the front side Fl of the first semiconductor device Sl, wherein the further sidewall insulation 10a is used as a hard mask. Then, the material of the insulating layer is applied, which later forms the drawn in Figure 5 side wall insulation 10, preferably the same material that is also used for the further side wall insulation 10 a, for

Example silicon dioxide. With a renewed spacer etching, the material is also removed from this insulating layer at the bottom of the contact hole, so that the side wall insulation 10 stop. At the bottom of the contact hole is etched through the present on the first substrate 1 insulating layer 3 until the terminal contact layer 17 is reached. Then, the metallization 11 is produced, which contacts the terminal contact layer 17. In the exemplary embodiment of FIG. 5, the plated-through hole can be configured on the front side F2 of the second semiconductor component S2 as in the exemplary embodiment of FIG. 1. In one variant of the production method, the material for the further side wall insulation 10a is only applied after the connection layer 5 has reached the bottom the contact hole has been removed.

Instead of initially etching the contact hole 14 only through the second substrate 2 and etching it through the first substrate 1 only after the first spacer etching with which the further sidewall insulation 10a is produced, it is also possible for the contact hole 14 to be a further variant of the production method the same through both substrates 1, 2 etched down to the terminal contact layer 17 down and then apply the material for the side wall insulation 10. In this variant, the further sidewall insulation 10a is eliminated.

FIG. 6 shows a further exemplary embodiment, in which the through-connection passes through both substrates 1, 2, as in the exemplary embodiment of FIG. In contrast to the exemplary embodiment of FIG. 5, in the exemplary embodiment of FIG. 6 the rear side Bl of the first semiconductor component S1 is connected to the front side F2 of the second semiconductor component S2. The connection metal layer 12 on the rear side B2 of the second semiconductor component S2 can, as in the exemplary embodiments of FIGS and 4 may be provided with a contact surface 9 for applying a solder ball 13.

If the contact hole is only etched by the second substrate 2 in a first etching step until the insulation layer 3 on the front side F2 of the second semiconductor component S2 is reached, and subsequently the material for the sidewall insulation is already applied, this is produced by a subsequent spacer etching further side wall insulation 10a only up to the insulating layer 3, as shown in Figure 6. Instead, at the bottom of the contact hole, first the insulating layer 3 and the intermetal dielectric 4 at the front side F2 of the second semiconductor component S2 and the connection layer 5 can be removed, before the material for the further sidewall insulation 10a is applied. The further sidewall insulation 10a extends in this case except for the first substrate 1. In this embodiment too, the contact hole 14 can first be etched through both substrates 1, 2 before the material of the sidewall insulation 10 is applied; In this case, the further side wall insulation 10a is omitted.

The further exemplary embodiment according to FIG. 7 is similar to the exemplary embodiment of FIG. 6, and the through-connection also passes through both substrates 1, 2 here. However, the terminal contact layer 17 is arranged on the connection layer 5, in the illustrated example in a metal plane 7 on the front side F2 of the second semiconductor component S2. For the via, a contact hole 24 in the first substrate 1 and a separate contact hole 14 in the second substrate 2 are provided. Accordingly, there are two separate sidewall insulations 10, 20, two separate metallizations 11, 21 and two terminal metal layers 12, 22nd

The further exemplary embodiment according to FIG. 8 is similar to the exemplary embodiment of FIG. In the embodiment of FIG. 8, in contrast to the exemplary embodiment of FIG. 1, the terminal contact layer 17a is not a metal layer, but rather a diffusion region in the first substrate 1. The diffusion region can be formed, for example, by implantation in a manner known per se and conventional in semiconductor technology Dopant and subsequent healing of the implants are produced. The through-connection thus extends between the conductors of the wiring on the front side F1 of the first semiconductor component S1.

The further exemplary embodiment according to FIG. 9 is a special embodiment of the exemplary embodiment of FIG. 1. A micromechanical sensor S, which can be, for example, an acceleration sensor, is integrated on the front side F1 of the first semiconductor component S1. As an embodiment, an embodiment of the acceleration sensor will be described in more detail below; However, possible embodiments of the integrated micromechanical sensor are not limited thereto. As a moment of inertia, a bending beam 25 is made

Metal or polysilicon provided which projects into a cavity 23. The bending beam 25 is at least partially electrically conductive and connected via a vertical conductive connection 8 with a metal level 7 of the wiring of the first semiconductor device Sl. The electrically conductive portion of the bending beam 25 acts as an electrode for a capacitive measurement of the position of the bending beam 25 and its deflection due to an inertial force occurring. A counterpart Electrode 26 is arranged at a small distance to the bending beam 25, so that the bending beam 25 can be deflected and a capacitive measurement with sufficient sensitivity can be performed. The counterelectrode 26 is connected via a vertical conductive connection 28 to a metal level 7 of the wiring on the front side Fl of the first semiconductor component S1. The plated-through hole can be provided for a connection of the micromechanical sensor to the wiring on the front side F2 of the second semiconductor component S2 or else for a connection to a further semiconductor component.

FIG. 10 shows a further exemplary embodiment with a micromechanical sensor S integrated in the front side F1 of the first semiconductor component S1. In the exemplary embodiment of FIG. 10, the front side F1 of the first semiconductor component S1 is connected to the front side F2 of the second semiconductor component S2. The components corresponding to the other exemplary embodiments are provided with the same reference symbols in FIG. In the exemplary embodiment of FIG. 10, the counter electrode 26a is arranged on the connection layer 5 in the same plane as the connection contact layer 17 and forms a metal plane with the connection contact layer 17. The plated-through hole is intended to connect the counterelectrode 26a in an electrically conductive manner to the terminal metal layer 12 on the rear side B2 of the second semiconductor component S2. The connection of the micromechanical sensor can be connected in this way via a solder ball 13 to a terminal of a further semiconductor component. The bending beam 25 is at least partially electrically conductive and connected via a vertical conductive connection 8 with a conductor 27 of the wiring of the first semiconductor device Sl. The conductor track 27 may, for example, be led to a further connection contact layer of a further through-connection of the semiconductor circuit.

The further embodiment according to the figure 11 is the

Embodiment of Figure 2 similar, and the corresponding components are provided in Figures 2 and 11 with the same reference numerals. In the embodiment of FIG. 11, in contrast to the exemplary embodiment of FIG. 2, no solder ball is applied to the terminal metal layer 12, but rather a connection conductor 29 for a surface sensor, which may in particular be a biological sensor. For this sensor, a conductor structure 30 is provided on the relevant upper side of the semiconductor circuit, which may be connected to the connecting conductor 29 electrically conductive.

The further exemplary embodiment according to FIG. 12 is a special embodiment of the exemplary embodiment of FIG. 5, and the corresponding components are provided with the same reference numerals in FIG. In the exemplary embodiment of FIG. 12, a pressure sensor P, which has a cavity 23 in the first substrate 1 and a membrane 31 terminating the cavity 23 to the outside, is integrated on the front side F1 of the first semiconductor component S1. The membrane 31 is at least partially electrically conductive and connected to the terminal contact layer 17. The measurement can be carried out, for example, capacitively by means of a counterelectrode not shown or piezoelectrically in a conventional manner known from micromechanical sensors. So that an external pressure can act on the membrane 31, a recess 32 is provided. The preferably provided passivation 6 may be applied to the membrane 31 as a thin protective layer 16. The exemplary embodiment according to FIG. 13 is similar to the exemplary embodiment of FIG. 7. In the exemplary embodiment according to FIG. 13, a terminal contact layer 17 for the contact hole 14 in the second substrate 2 and a further terminal contact layer 18b for the contact hole 24 in the first substrate 1 are present. This has the advantage that the layer sequence remaining between the contact holes 14, 24 comprises more layers than in the exemplary embodiment of FIG. 7, in which between the contact holes 14, 24 only a thin membrane, consisting of the terminal contact layer 17, the metallizations 11, 21 and the passivation 6, is present. In the variant of FIG. 13, there is additionally a layer portion of the wiring of the second semiconductor component S2. The connection contact layer 17 and the further connection contact layer 18b can, as shown in FIG. 13, be arranged in two different metal levels 7 of the wiring of the second semiconductor component S2. According to the exemplary embodiment of FIG. 2, if the front side F1 of the first semiconductor component S1 is connected to the front side F2 of the second semiconductor component S2, the terminal contact layer 17 can, for example, be in a metal level of the wiring of the second semiconductor component S2 and the further terminal contact layer 18b in a metal level the wiring of the first

Semiconductor device Sl be arranged. To complete the through-connection, the terminal contact layer 17 and the further terminal contact layer 18b are electrically conductively connected to one another via a vertical conductive connection 28a.

The embodiment of FIG. 14 is similar to the embodiment of FIG. 13. In the embodiment According to FIG. 14, a terminal contact layer 17 for the contact hole 14 in the second substrate 2 and a further terminal contact layer 18c for the contact hole 24 are present in the first substrate 1 and arranged laterally offset from each other, and the contact holes 14, 24 are correspondingly laterally opposite one another staggered. The other components corresponding to the exemplary embodiments of FIGS. 7 and 13 are provided with the same reference numerals. The exemplary embodiments, in particular FIGS. 3 and 14, show the multitude of possibilities of arranging two or more plated-through holes of the described type at different positions in the first and / or in the second semiconductor component and thus in an extremely diverse arrangement of plated-through holes in the stack of semiconductor components realize.

The possibilities of this integration technique are not limited to the embodiments described. The features of the various embodiments can be combined in a variety of ways, so that a variety of vertically integrated semiconductor circuits in a simple manner with the vias described can be realized. The terminal contact layer may be arranged in different layer layers and formed by a metal layer or a diffusion region. The terminal metal layer may be provided for internal connection to the wiring of the semiconductor circuit, for external connection to another semiconductor device, or for both an internal and an external terminal. The via may be configured to include only one substrate or both substrates. The metallization of the via can be designed so that it only one terminal contact layer or that they contacted two or more terminal contact layers. There can be any number of plated-through holes in both substrates which can each contact terminal contact layers in different layer layers. These and other features described can be largely independently selected and combined with each other.

Reference sign list

1 first substrate

2 second substrate 3 insulation layer

4 intermetal dielectric

5 bonding layer

6 passivation

7 metal level 8 vertical conductive connection

9 contact surface

10 sidewall insulation

10a further sidewall insulation

11 metallization IIa further metallization

12 terminal metal layer 12a terminal metal layer

13 solder ball

14 contact hole 14a further contact hole

15 insulation layer

16 protective layer

17 terminal contact layer 17a terminal contact layer 18 further terminal contact layer

18a further connection contact layer

18b further connection contact layer

18c further connection contact layer

19 contact surface 20 sidewall insulation

21 metallization

22 terminal metal layer

23 cavity 24 contact hole

25 bending beams

26 counter electrode 26a counter electrode 27 trace

28 vertical conductive connection 28a vertical conductive connection

29 connection conductor

30 Conductor structure 31 Membrane

32 recess

Bl rear side of the first semiconductor device

B2 back of the second semiconductor device

Fl front of the first semiconductor device F2 front of the second semiconductor device

P pressure sensor

S micromechanical sensor

51 first semiconductor device

52 second semiconductor device

Claims

claims

1. semiconductor circuit with via, in the

- A first semiconductor device (Sl) with a first substrate (1) made of semiconductor material, a front side

(Fl) and a front side opposite the rear side (Bl) is present, wherein at least one metal level (7) is present at the front,

- A second semiconductor device (S2) with a second substrate (2) made of semiconductor material, a front side

(F2) and a front side opposite the rear side (B2) is present, wherein at least one metal level (7) is present at the front,

a connection layer (5) is present, which connects the front side or the rear side of the first semiconductor component to the front side or the rear side of the second semiconductor component,

A terminal contact layer (17, 17a) is present on the front side of the first semiconductor component, in the first substrate or on the connection layer,

- In the second substrate, a contact hole (14) having a metallization (11) is present, wherein the metallization contacts the terminal contact layer and forms a via of the second semiconductor device, and

- A terminal metal layer (12) on the second semiconductor device and is electrically connected to the metallization.

2. A semiconductor circuit according to claim 1, wherein the terminal contact layer (17) in a metal plane (7) on the front side (Fl) of the first semiconductor device (Sl) is formed.

The semiconductor circuit according to claim 1, wherein the terminal contact layer (17a) is a diffusion region of the first substrate (1).

4. A semiconductor circuit according to any one of claims 1 to 3, wherein

the connection layer (5) connects the front side (Fl) or the back side (Bl) of the first semiconductor component (S1) to the front side (F2) of the second semiconductor component (S2),

- The terminal metal layer (12) on the back (B2) of the second semiconductor device is present and

- A contact surface (9) for a solder ball (13) on the terminal metal layer (12) is provided.

5. A semiconductor circuit according to any one of claims 1 to 3, wherein

the connection layer (5) connects the rear side (Bl) of the first semiconductor component (S1) to the front side (F2) or the rear side (B2) of the second semiconductor component (S2),

- The terminal contact layer (17, 17 a) on the front

(Fl) of the first semiconductor device is present and - the contact hole (14) and the metallization (11) of

Through-hole in the first substrate (1) and in the second substrate (2) are present.

6. The semiconductor circuit of claim 1, wherein - the connection layer (5) connects the rear side (Bl) of the first semiconductor device (Sl) to the front side (F2) of the second semiconductor device (S2), The terminal contact layer (17) is present at the connection layer,

In the first substrate (1) there is a contact hole (24) with a metallization (21), wherein the metallization contacts the terminal contact layer (17) and forms a through-connection of the first semiconductor component (S1), and

- A terminal metal layer (22) on the first semiconductor device and is electrically connected to the metallization in the contact hole of the first substrate.

7. The semiconductor circuit according to claim 1, wherein: the connection layer connects the front side of the first semiconductor component to the front side or the back side of the second semiconductor component;

- A further terminal contact layer (18) in a metal level (7) of the first semiconductor device or the second semiconductor device is present and

- In the second substrate (1) a further contact hole (14a) with a further metallization (IIa) is present, wherein the further metallization contacts the further terminal contact layer (18) and forms a further via of the second semiconductor device.

8. A semiconductor circuit according to any one of claims 1 to 3, wherein - The connection layer (5) the front side (Fl) of the first semiconductor device (Sl) with the front side

(F2) of the second semiconductor device (S2) connects,

- The terminal contact layer (17, 17 a) on the front side of the first semiconductor device or in the first

Substrate (1) is present,

- Another terminal contact layer (18a) in a metal level (7) of the second semiconductor device is present and - the metallization (11) contacts both the terminal contact layer (17, 17a) and the further terminal contact layer (18a).

9. A semiconductor circuit according to any one of claims 1 to 3, wherein

- The connection layer (5) the front side (Fl) of the first semiconductor device (Sl) with the front side

(F2) or the back (B2) of the second semiconductor device (S2) connects, - in the front of the first semiconductor device, a micromechanical sensor (S) is integrated, which has at least one electrically conductive element (25, 26, 26a), and

- An electrically conductive element (26, 26 a) of the sensor with the terminal contact layer (17, 17 a) is electrically connected.

10. The semiconductor circuit according to one of claims 1 to 3, wherein - the connection layer (5) connects the rear side (Bl) of the first semiconductor device (Sl) to the back side (B2) of the second semiconductor device (S2), - In the front side (Fl) of the first semiconductor device, a pressure sensor (P) is integrated and

- The pressure sensor has an at least partially electrically conductive membrane (31) which is electrically conductively connected to the terminal contact layer (17, 17 a).

11. The semiconductor circuit according to one of claims 1 to 3, wherein - the connection layer (5) connects the front side (Fl) or the back side (Bl) of the first semiconductor device (Sl) to the front side (F2) of the second semiconductor device (S2) and

A connection conductor (29), which is electrically conductively connected to the connection metal layer (12), and a conductor structure (30), which is provided for a surface sensor, are present above the rear side (B2) of the second semiconductor component.

12. A method of manufacturing vertically integrated circuits, wherein

Two semiconductor wafers having a front side (Fl, F2) and a rear side (Bl, B2) opposite the front side, each being provided on the front side with at least one metal plane (7),

A terminal contact layer (17, 17a) is produced on the front side of one of the two semiconductor wafers in a metal plane or by forming a diffusion region, the front side or the back side of the first semiconductor wafer with the front side or the back side of the second one Semiconductor wafer is permanently connected by means of a connection layer (5),

a contact hole (14) is etched into one of the semiconductor wafers in which the terminal contact layer (17, 17a) is exposed,

- A side wall insulation (10) and a metallization

(11) are made in the contact hole so that the metallization contacts the terminal contact layer, and - a terminal metal layer (12) is applied in electrically conductive connection with the metallization.

13. The method of claim 12, wherein

the connection layer (5) and the terminal contact layer (17, 17a) on different sides of one of

Semiconductor wafers are arranged and

- The contact hole (14) is etched through both semiconductor wafer therethrough.

14. The method of claim 12, wherein

the connection layer (5) and the terminal contact layer (17, 17a) are arranged on the same side of one of the semiconductor wafers, contact holes (14, 24) are etched through both semiconductor wafers, in each of which the

Terminal contact layer (17, 17a) is exposed, and

- Side wall insulation (10, 20) and metallizations (11, 21) are made in both contact holes, so that the metallization contact the terminal contact layer.