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WO2010079581A1 - Thin film transistor and method for manufacturing same - Google Patents

Thin film transistor and method for manufacturing same Download PDF

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Publication number
WO2010079581A1
WO2010079581A1 PCT/JP2009/007330 JP2009007330W WO2010079581A1 WO 2010079581 A1 WO2010079581 A1 WO 2010079581A1 JP 2009007330 W JP2009007330 W JP 2009007330W WO 2010079581 A1 WO2010079581 A1 WO 2010079581A1
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Prior art keywords
oxide
thin film
film transistor
semiconductor film
amorphous
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PCT/JP2009/007330
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French (fr)
Japanese (ja)
Inventor
笠見雅司
井上一吉
矢野公規
笘井重和
川嶋浩和
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出光興産株式会社
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Publication of WO2010079581A1 publication Critical patent/WO2010079581A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to a thin film transistor. More particularly, the present invention relates to a thin film transistor including an oxide semiconductor film.
  • IGZO indium oxide-gallium oxide-zinc oxide
  • a thin film transistor containing IGZO as a component is made of a quaternary oxide whose components are In, Ga, Zn, and O.
  • the composition of the sputtering target and the composition of the obtained thin film are changed, or the center of the glass is formed when the film is formed with a large film forming apparatus
  • the composition of the portion and the peripheral portion may be different, and the transistor characteristics (mobility, threshold voltage Vth, S value) of the glass central portion and the peripheral portion may be different, and it may be difficult to increase the uniformity of these. there were.
  • Patent Document 1 There is also a report of a crystalline thin film transistor using indium oxide (Patent Document 1). In this case, only a normally-on thin film transistor characteristic is shown, and a normally-off amorphous thin film transistor has been desired.
  • An object of the present invention is to provide a thin film transistor including an oxide semiconductor film exhibiting normally-off thin film transistor characteristics, and a manufacturing method thereof.
  • “normally off” is defined as a case where the value of the threshold voltage is positive.
  • the threshold voltage is obtained from the X-intercept of the transfer curve (drain current-gate voltage) graph.
  • the present inventors have intensively studied, and an oxide thin film transistor including an oxide semiconductor including indium oxide and one or more oxides selected from oxides of specific elements.
  • an oxide thin film transistor including an oxide semiconductor including indium oxide and one or more oxides selected from oxides of specific elements have intensively studied, and an oxide thin film transistor including an oxide semiconductor including indium oxide and one or more oxides selected from oxides of specific elements.
  • normally-off thin film transistor characteristics are exhibited, and the present invention has been completed.
  • the following thin film transistor and method for manufacturing the same are provided.
  • an oxide thin film transistor exhibiting normally-off thin film transistor characteristics can be provided.
  • a method for manufacturing an oxide thin film transistor exhibiting normally-off thin film transistor characteristics can be provided.
  • the oxide thin film transistor of the present invention includes indium oxide, lanthanum oxide, neodymium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, and erbium oxide.
  • the value of the atomic ratio M / (In + M) is 0.1 or more and 0.4
  • An oxide semiconductor film including the following is included.
  • the oxide semiconductor film of the present invention includes indium oxide and an oxide represented by M 2 O 3, where M is lanthanum, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and It is one or more elements selected from the group consisting of ytterbium, and the value of atomic ratio M / (In + M) is 0.1 or more and 0.4 or less.
  • M is lanthanum, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and It is one or more elements selected from the group consisting of ytterbium, and the value of atomic ratio M / (In + M) is 0.1 or more and 0.4 or less.
  • the oxide semiconductor film is not limited to an amorphous film, but an amorphous semiconductor film is more preferable because it is less likely to react with oxygen at the time of film formation and can reduce the possibility that the characteristics of the transistor change.
  • the oxide semiconductor film used in the present invention can obtain an amorphous film by containing indium oxide and the specific positive trivalent lanthanoid metal oxide.
  • the “amorphous film” means a layer in which a crystal peak cannot be confirmed by X-ray diffraction.
  • the amorphous oxide semiconductor film in the present invention may be referred to as a semiconductor film (thin film), an amorphous oxide film (thin film), or an amorphous semiconductor film (thin film).
  • the carrier concentration of the semiconductor film can be reduced, and the carrier concentration of the semiconductor film is 2 ⁇ 10 +17 cm ⁇ 3 at a temperature near room temperature. Therefore, good thin film transistor characteristics are exhibited.
  • the carrier concentration at temperatures near room temperature is preferably less than 1 ⁇ 10 +17 cm ⁇ 3 .
  • the thin film transistor (hereinafter sometimes referred to as TFT) may not be driven. Even when the TFT is driven, it may be normally on, the threshold voltage may be greatly negative, or the On-Off value may be small.
  • the oxide of M 2 O 3 the value of the atomic ratio M / (In + M) needs to be 0.1 or more and 0.4 or less. By setting the atomic ratio in such a range, indium oxide becomes a main component of the oxide semiconductor, a normally-off characteristic, high mobility, a small S value (fast rise in the transfer curve) transistor. Can be achieved.
  • content of each metal element can be calculated
  • content of each metal element can be implemented by adjusting the abundance of each element of the sputtering target used when forming a semiconductor film, for example.
  • the composition of the semiconductor film substantially matches the composition of the sputtering target.
  • the semiconductor film may contain components other than indium oxide and the specific positive trivalent lanthanoid metal oxide.
  • gallium oxide, scandium oxide, or the like may be contained.
  • the semiconductor film used in the present invention may consist essentially of indium oxide and the specific positive trivalent lanthanoid metal oxide, or may consist only of these components. “Substantially” means that the semiconductor film can contain other components in addition to the indium oxide and the specific positive trivalent lanthanoid metal oxide.
  • the substrate can be used for the substrate, gate electrode, gate insulating film, source / drain electrode, and the like, and are not particularly limited.
  • a metal thin film such as Al, Cu, or Au can be used for each electrode, and an oxide thin film such as a silicon oxide film or a hafnium oxide film can be used for the gate insulating film.
  • FIG. 1 is a schematic cross-sectional view showing an embodiment of a thin film transistor of the present invention.
  • the thin film transistor 1 has a gate electrode 20 sandwiched between a substrate 10 and a gate insulating film 30, and a semiconductor film (channel layer) 40 is stacked on the gate insulating film 30 as an active layer. Further, a source electrode 50 and a drain electrode 52 are provided so as to cover the vicinity of the end of the semiconductor film 40. A channel portion 60 is formed in a portion surrounded by the semiconductor film 40, the source electrode 50 and the drain electrode 52. 1 is a so-called channel etch type thin film transistor.
  • the thin film transistor of the present invention is not limited to a channel etch type thin film transistor, and an element configuration known in this technical field can be adopted. For example, an etch stopper type thin film transistor may be used.
  • FIG. 2 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention.
  • the thin film transistor 2 is a so-called etch stopper type thin film transistor.
  • the thin film transistor 2 has the same configuration as the thin film transistor 1 described above except that an etch stopper 70 is formed so as to cover the channel portion 60.
  • a source electrode 50 and a drain electrode 52 are provided so as to cover the vicinity of the end of the semiconductor film 40 and the vicinity of the end of the etch stopper 70.
  • a semiconductor film containing indium oxide and the specific positive trivalent lanthanoid metal oxide is used for the semiconductor film 40. Note that when the semiconductor film is an amorphous film, the etching processability is excellent and the productivity of the thin film transistor can be increased.
  • the structure of the thin film transistor is preferably an etch stopper type thin film transistor.
  • the oxide thin film to be the thin film transistor of the present invention is easily dissolved in a metal etching solution.
  • an oxide thin film island can be formed simultaneously with the electrode formation, and the number of photomasks used can be reduced.
  • the oxide thin film cannot be dissolved by the etching solution for etching the source / drain wiring / source / drain electrode, it is necessary to change the etching solution and the photomask, and the process becomes complicated and not industrial.
  • the method for producing a thin film transistor of the present invention includes a step of forming an oxide semiconductor film constituting the oxide thin film transistor of the present invention by sputtering, and oxygen during the sputtering.
  • the concentration is 2 to 20% by volume, and the substrate temperature is from room temperature to 200 ° C. or less.
  • a thin film having the same composition as the sputtering target can be obtained even when the oxide semiconductor film is formed by a sputtering process, and the application to a large glass substrate is facilitated. Further, by setting the oxygen concentration during sputtering to 2 to 20% by volume, uniform transistor characteristics can be provided in the transistor stabilization treatment step performed in the next step.
  • the substrate temperature at that time is from room temperature to 200 ° C. or less.
  • a cooling device is required, which is not economical. If it exceeds 200 ° C., the heating cost may increase, and the oxide thin film may be easily crystallized. When the oxide thin film is crystallized, a residue may be generated in the etching process or etching may not be performed, and an island having a desired shape may not be formed.
  • the substrate temperature may be adjusted as appropriate depending on the type of substrate and heat resistance.
  • the oxide semiconductor film formed by sputtering it is preferable to heat-treat the oxide semiconductor film formed by sputtering as described above at 150 to 450 ° C. for 0.5 to 1200 minutes after forming the source / drain electrodes. If it is lower than 150 ° C., there is a possibility of being normally on, and a stable thin film transistor may not be obtained. In addition, when it exceeds 450 degreeC, there exists a possibility that it may become crystalline.
  • a lamp annealing device for heat treatment of the semiconductor film, a lamp annealing device, a laser annealing device, a hot air heating device, a contact heating device, or the like can be used in the air or a nitrogen atmosphere.
  • the heat treatment temperature is more preferably 180 ° C. to 350 ° C., and particularly preferably 200 ° C. to 300 ° C.
  • the heat treatment time is less than 0.5 minutes, the heat treatment time is too short and thermal stabilization of the film may be insufficient. If it exceeds 1200 minutes, it takes too much time and is not productive.
  • the heat treatment time is more preferably 1 minute to 600 minutes, and particularly preferably 5 minutes to 60 minutes.
  • the heat treatment is preferably performed after the formation of the source / drain wiring / source / drain electrodes.
  • the resistance value of the source / drain wiring / source / drain electrode can be reduced, and the characteristics of the oxide thin film transistor can be stabilized.
  • the oxide thin film is formed by sputtering, and is often thinned in a non-equilibrium state immediately after the film formation, so that the internal stress may not be uniform or the density in the thickness direction may be distributed. .
  • the oxide thin film is not in an equilibrium state, the state of the oxide thin film is not uniform depending on the location, and thus transistor characteristics (particularly, On / Off value, mobility, threshold voltage Vth, S value) may vary. is there.
  • transistor characteristics particularly, On / Off value, mobility, threshold voltage Vth, S value
  • the characteristics of the oxide thin film transistor can be stabilized. Further, there is an effect of reducing the contact resistance between the source / drain wiring / source / drain electrode and the oxide thin film transistor, and more stable transistor characteristics can be obtained.
  • FIG. 3 shows a mask pattern to be used, and the left side is a cross-sectional view of a layered structure formed by the mask at a dotted line portion shown in the mask pattern.
  • a metal thin film is formed on glass (substrate 10), and resist coating, exposure, development, etching, resist peeling, and washing are performed to form gate wiring / gate electrode 20.
  • a first photomask for forming a desired shape of the gate wiring / gate electrode 20 is used.
  • an oxide thin film (semiconductor film 40) of the present invention and an SiO 2 thin film to be an etch stopper 70 are formed, resist coating, exposure, Development, etching, resist stripping, and cleaning are performed to form a desired etch stopper shape.
  • the etching is preferably performed by a dry process.
  • SiO 2 can be etched by a dry process using CF 4 and oxygen as etching gases. At this time, a second photomask is used to form an etch stopper having a desired shape.
  • a metal thin film to be the source / drain electrodes 50, 52 is formed, and resist application, exposure, development, etching, resist stripping, and cleaning are performed to form desired source / drain wirings / source / drain electrodes 50, 52.
  • the portion of the metal thin film that becomes the channel portion 60 can be removed. Since the oxide thin film can be easily etched with a metal etching solution, an island (island structure) to be an oxide thin film transistor can be formed.
  • an island (island structure) to be an oxide thin film transistor can be formed simultaneously with the etching solution for forming the source / drain wiring / source / drain electrode using the third photomask.
  • Example 1 ⁇ Production of Thin Film Transistor>
  • the etch stopper type thin film transistor shown in FIG. 4 was manufactured by a photoresist method.
  • Amorphous oxide thin film) 40 was formed.
  • Sputtering was carried out at room temperature with a sputtering power of 100 W while evacuating until the back pressure reached 5 ⁇ 10 ⁇ 4 Pa, adjusting the pressure to 0.2 Pa while flowing argon 9.5 sccm and oxygen 0.5 sccm. It was.
  • etch stopper layer was formed by dry etching with CF 4 .
  • the resist was stripped with a resist stripper, washed with water, and dried by air blow.
  • a molybdenum metal film was formed to 300 nm on the semiconductor film 40 and the etch stopper 70.
  • a resist was applied to the molybdenum metal film, and prebaked at 80 ° C. for 15 minutes. Thereafter, the resist film was irradiated with UV light (light intensity: 300 mJ / cm 2 ) through a mask, and then developed with 3 wt% tetramethylammonium hydroxide (TMAH). After washing with pure water, the resist film was post-baked at 130 ° C. for 15 minutes to form a resist pattern in the shape of the source electrode 50 and the drain electrode 52.
  • UV light light intensity: 300 mJ / cm 2
  • TMAH 3 wt% tetramethylammonium hydroxide
  • the substrate with a resist pattern was treated with a mixed acid of phosphoric acid, acetic acid and nitric acid, so that the molybdenum metal film and the amorphous oxide thin film 40 were simultaneously etched.
  • the molybdenum metal film on the channel portion protected by the etch stopper is etched to form the channel portion 60.
  • the substrate was heat-treated. Specifically, the substrate was heat-treated at 300 ° C. for 30 minutes in the air in a hot air heating furnace.
  • the resistance value of the source / drain wiring / source / drain electrode can be reduced and the contact resistance with the amorphous oxide thin film transistor can be reduced. There is.
  • the performance of the thin film transistor manufactured by changing the position of the substrate was almost the same and stable.
  • the composition of the semiconductor film was measured with an ICP apparatus, it was the same as the composition of the target.
  • the film formation substrate had a uniform composition.
  • the internal stress was 5 ⁇ 10 ⁇ 10 dyn ⁇ cm ⁇ 2 or less, showed only a small internal stress, and was stable with almost no distribution in the substrate.
  • the on-off ratio was 10 6 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
  • X-ray diffraction (XRD) measurement of the obtained semiconductor film was carried out, the peak of the structure resulting from indium oxide and neodymium oxide was not observed, but a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous.
  • the carrier concentration determined by hole measurement was 2.9 ⁇ 10 +16 cm ⁇ 3 .
  • the on-off ratio was 10 6 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
  • the X-ray diffraction (XRD) measurement of the obtained semiconductor film was carried out, the peak of the structure resulting from an indium oxide and a terbium oxide was not observed, but the broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. Further, the carrier concentration determined by Hall measurement was 3.7 ⁇ 10 +16 cm ⁇ 3 .
  • X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, the peak of the structure due to indium oxide and lanthanum oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous.
  • the carrier concentration determined by hole measurement was 0.95 ⁇ 10 +16 cm ⁇ 3 .
  • the on-off ratio was 10 6 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
  • X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, the peak of the structure due to indium oxide and samarium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous.
  • the carrier concentration determined by hole measurement was 1.4 ⁇ 10 +16 cm ⁇ 3 .
  • X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, a peak of the structure due to indium oxide and europium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous.
  • the carrier concentration determined by hole measurement was 2.1 ⁇ 10 +16 cm ⁇ 3 .
  • the on-off ratio was 10 6 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
  • the X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, the peak of the structure due to indium oxide and holmium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. Further, the carrier concentration determined by Hall measurement was 5.1 ⁇ 10 +16 cm ⁇ 3 .
  • the on-off ratio was 10 6 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
  • X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, the peak of the structure due to indium oxide and thulium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous.
  • the carrier concentration determined by hole measurement was 2.7 ⁇ 10 +16 cm ⁇ 3 .
  • the on-off ratio was 10 8 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
  • X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, a peak of the structure due to indium oxide and ytterbium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. Further, the carrier concentration determined by Hall measurement was 3.6 ⁇ 10 +16 cm ⁇ 3 .
  • Comparative Example 1 A thin film transistor was fabricated in the same manner as in Example 1 except that a target made of indium oxide (purity: 99.9%) (total of Sn, Ti, Zr as impurities: 120 ppm included) was used as the sputtering target.
  • the field effect mobility of this thin film transistor 46cm 2 / V ⁇ sec, On / OFF ratio is 10 5
  • the threshold voltage Vth is -12V
  • S value is 2.4V / dec.
  • the thin film transistor exhibits normally-on characteristics.
  • the carrier concentration obtained from the hole measurement was 1.4 ⁇ 10 18 cm ⁇ 3 .
  • the carrier concentration obtained from the hole measurement was 10 14 cm ⁇ 3 or less.
  • the channel layer was a semiconductor, and the field effect mobility of this thin film transistor was 40.1 cm 2 / V ⁇ sec.
  • the On-Off ratio is as small as 10 3 and the S value is 4.2 V / dec. Met.
  • the thin film transistor exhibits normally-on characteristics. The output characteristics showed a clear pinch-off.
  • the shift voltage ( ⁇ Vth) after applying 20V voltage to the gate electrode for 100 minutes was 0.29V.
  • the carrier concentration determined from the hole measurement was 4.8 ⁇ 10 18 cm ⁇ 3 .
  • the carrier concentration obtained from the hole measurement was 1.4 ⁇ 10 20 cm ⁇ 3 .
  • Table 1 below collectively shows the structures and characteristics of the oxide semiconductor films used in Examples and Comparative Examples.
  • the amorphous oxide thin film transistor of the present invention can be suitably used for sensors such as display panels, RFID tags, X-ray detector panels, fingerprint sensors, and photosensors.
  • the method for producing a thin film transistor of the present invention is particularly suitable for a method for producing an etch stopper type thin film transistor.

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Abstract

A thin film transistor which comprises an oxide semiconductor film containing indium oxide and at least one oxide selected from a group consisting of lanthanum oxide, neodymium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide and ytterbium oxide, wherein the atomic ratio M/(In + M) is 0.1 to 0.4 inclusive when the at least one oxide is represented by M2O3.

Description

薄膜トランジスタ及びその製造方法Thin film transistor and manufacturing method thereof
　本発明は、薄膜トランジスタに関する。より詳細には、本発明は、酸化物半導体膜を含む薄膜トランジスタに関する。 The present invention relates to a thin film transistor. More particularly, the present invention relates to a thin film transistor including an oxide semiconductor film.
　公知のアモルファスＩＧＺＯ（酸化インジウム－酸化ガリウム－酸化亜鉛）は薄膜トランジスタとして良好な特性を示すことが知られている。しかしながら、ＩＧＺＯを成分とする薄膜トランジスタは、成分がＩｎ、Ｇａ、Ｚｎ、及びＯからなる４元系の酸化物からなる。この場合、それぞれの金属成分のスパッタ率や、基板への付着率が異なるためにスパッタリングターゲットの組成と得られる薄膜の組成が変化したり、大型成膜装置にて成膜した場合にガラスの中心部分と周辺部分の組成が異なる場合があり、ガラス中心部と周辺部のトランジスタ特性（移動度、閾値電圧Ｖｔｈ、Ｓ値）が異なる場合があり、これらの均一性を上げることが困難な場合があった。 Known amorphous IGZO (indium oxide-gallium oxide-zinc oxide) is known to exhibit good characteristics as a thin film transistor. However, a thin film transistor containing IGZO as a component is made of a quaternary oxide whose components are In, Ga, Zn, and O. In this case, since the sputtering rate of each metal component and the adhesion rate to the substrate are different, the composition of the sputtering target and the composition of the obtained thin film are changed, or the center of the glass is formed when the film is formed with a large film forming apparatus The composition of the portion and the peripheral portion may be different, and the transistor characteristics (mobility, threshold voltage Vth, S value) of the glass central portion and the peripheral portion may be different, and it may be difficult to increase the uniformity of these. there were.
　また、酸化インジウムを用いた結晶質薄膜トランジスタの報告もある（特許文献１）が、この場合は、ノーマリーオンの薄膜トランジスタ特性しか示さず、ノーマリーオフの非晶質薄膜トランジスタが望まれていた。 There is also a report of a crystalline thin film transistor using indium oxide (Patent Document 1). In this case, only a normally-on thin film transistor characteristic is shown, and a normally-off amorphous thin film transistor has been desired.
特開２００８－１３０８１４号公報JP 2008-130814 A
　本発明の目的は、ノーマリーオフの薄膜トランジスタ特性を示す酸化物半導体膜を含む薄膜トランジスタ、及びその製造方法を提供することである。本発明において「ノーマリーオフ」とは、閾値電圧の値が正である場合と定義する。閾値電圧は伝達曲線（ドレイン電流－ゲート電圧）のグラフのＸ切片から求める。 An object of the present invention is to provide a thin film transistor including an oxide semiconductor film exhibiting normally-off thin film transistor characteristics, and a manufacturing method thereof. In the present invention, “normally off” is defined as a case where the value of the threshold voltage is positive. The threshold voltage is obtained from the X-intercept of the transfer curve (drain current-gate voltage) graph.
　上記目的を達成するため、本発明者らは鋭意研究を行い、酸化インジウムと、特定元素の酸化物から選ばれた１種又は２種以上の酸化物とを含む酸化物半導体を含む酸化物薄膜トランジスタが、ノーマリーオフの薄膜トランジスタ特性を示すことを見出し、本発明を完成させた。 In order to achieve the above object, the present inventors have intensively studied, and an oxide thin film transistor including an oxide semiconductor including indium oxide and one or more oxides selected from oxides of specific elements. However, it has been found that normally-off thin film transistor characteristics are exhibited, and the present invention has been completed.
　本発明によれば、以下の薄膜トランジスタ及びその製造方法が提供される。
１．酸化インジウムと、酸化ランタン、酸化ネオジム、酸化サマリウム、酸化ユウロピウム、酸化ガドリニウム、酸化テルビウム、酸化ジスプロシウム、酸化ホルミウム、酸化エルビウム、酸化ツリウム及び酸化イッテリビウムからなる群から選ばれた１種又は２種以上の酸化物をＭ２Ｏ３としたときに、原子比Ｍ／（Ｉｎ＋Ｍ）の値が、０．１以上０．４以下で含む酸化物半導体膜を含む薄膜トランジスタ。
２．前記酸化物半導体膜が非晶質である上記１に記載の薄膜トランジスタ。
３．前記薄膜トランジスタの構造が、エッチストッパー型の薄膜トランジスタである上記１又は２に記載の薄膜トランジスタ。
４．前記酸化物半導体膜をスパッタリングで成膜する工程を含み、該スパッタリング中の酸素濃度を２～２０体積％とし、基板温度を室温から２００℃以下とする上記１～３のいずれかに記載の薄膜トランジスタの製造方法。
５．前記酸化物半導体膜を、ソース・ドレイン電極を形成後に、１５０～４５０℃で０．５～１２００分間熱処理する上記４に記載の薄膜トランジスタの製造方法。 According to the present invention, the following thin film transistor and method for manufacturing the same are provided.
1. One or more selected from the group consisting of indium oxide and lanthanum oxide, neodymium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide and ytterbium oxide A thin film transistor including an oxide semiconductor film including an oxide having an atomic ratio M / (In + M) of 0.1 to 0.4 when the oxide is M 2 O 3 .
2. 2. The thin film transistor according to 1 above, wherein the oxide semiconductor film is amorphous.
3. 3. The thin film transistor according to 1 or 2 above, wherein the structure of the thin film transistor is an etch stopper type thin film transistor.
4). 4. The thin film transistor according to any one of the above 1 to 3, comprising a step of forming the oxide semiconductor film by sputtering, wherein the oxygen concentration during the sputtering is 2 to 20% by volume, and the substrate temperature is from room temperature to 200 ° C. Manufacturing method.
5). 5. The method for producing a thin film transistor according to 4 above, wherein the oxide semiconductor film is heat-treated at 150 to 450 ° C. for 0.5 to 1200 minutes after forming the source / drain electrodes.
　本発明によれば、ノーマリーオフの薄膜トランジスタ特性を示す酸化物薄膜トランジスタが提供できる。
　本発明によれば、ノーマリーオフの薄膜トランジスタ特性を示す酸化物薄膜トランジスタの製造方法を提供することができる。 According to the present invention, an oxide thin film transistor exhibiting normally-off thin film transistor characteristics can be provided.
According to the present invention, a method for manufacturing an oxide thin film transistor exhibiting normally-off thin film transistor characteristics can be provided.
本発明の薄膜トランジスタの実施形態を示す概略断面図である。It is a schematic sectional drawing which shows embodiment of the thin-film transistor of this invention. 本発明の薄膜トランジスタの他の実施形態を示す概略断面図である。It is a schematic sectional drawing which shows other embodiment of the thin-film transistor of this invention. 本発明の薄膜トランジスタの製造工程及び用いるフォトマスクを示す模式図である。It is a schematic diagram which shows the manufacturing process of the thin-film transistor of this invention, and the photomask to be used. 実施例及び比較例における薄膜トランジスタの製造工程を示す模式図である。It is a schematic diagram which shows the manufacturing process of the thin-film transistor in an Example and a comparative example.
　以下、本発明を詳細に説明する。
　本発明の酸化物薄膜トランジスタ（以下、本発明の薄膜トランジスタということがある）は、酸化インジウムと、酸化ランタン、酸化ネオジム、酸化サマリウム、酸化ユウロピウム、酸化ガドリニウム、酸化テルビウム、酸化ジスプロシウム、酸化ホルミウム、酸化エルビウム、酸化ツリウム及び酸化イッテリビウムからなる群から選ばれた１種又は２種以上の酸化物をＭ２Ｏ３としたときに、原子比Ｍ／（Ｉｎ＋Ｍ）の値が、０．１以上０．４以下で含む酸化物半導体膜を含むことを特徴とする。 Hereinafter, the present invention will be described in detail.
The oxide thin film transistor of the present invention (hereinafter sometimes referred to as the thin film transistor of the present invention) includes indium oxide, lanthanum oxide, neodymium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, and erbium oxide. In addition, when one or more oxides selected from the group consisting of thulium oxide and ytterbium oxide are M 2 O 3 , the value of the atomic ratio M / (In + M) is 0.1 or more and 0.4 An oxide semiconductor film including the following is included.
　即ち、本発明の酸化物半導体膜は、酸化インジウム及びＭ２Ｏ３で表される酸化物含み、前記Ｍは、ランタン、ネオジム、サマリウム、ユウロピウム、ガドリニウム、テルビウム、ジスプロシウム、ホルミウム、エルビウム、ツリウム及びイッテリビウムからなる群から選ばれる１種又は２種以上の元素であり、原子比Ｍ／（Ｉｎ＋Ｍ）の値が、０．１以上０．４以下である。 That is, the oxide semiconductor film of the present invention includes indium oxide and an oxide represented by M 2 O 3, where M is lanthanum, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and It is one or more elements selected from the group consisting of ytterbium, and the value of atomic ratio M / (In + M) is 0.1 or more and 0.4 or less.
　本発明では、酸化物半導体膜は非晶質膜に限定されないが、非晶質であれば、成膜時に酸素と反応し難く、トランジスタの特性が変化するおそれを低減できるため、より好ましい。本発明で使用する酸化物半導体膜は、酸化インジウムと、上記特定の正３価のランタノイド系金属酸化物を含有させることで、非晶質膜を得ることができる。尚、「非晶質膜」とは、Ｘ線回折により、結晶ピークを確認できない層を意味する。
　本明細書中において、本発明における非晶質酸化物半導体膜を、半導体膜（薄膜）、非晶質酸化物膜（薄膜）又は非晶質半導体膜（薄膜）と呼ぶことがある。 In the present invention, the oxide semiconductor film is not limited to an amorphous film, but an amorphous semiconductor film is more preferable because it is less likely to react with oxygen at the time of film formation and can reduce the possibility that the characteristics of the transistor change. The oxide semiconductor film used in the present invention can obtain an amorphous film by containing indium oxide and the specific positive trivalent lanthanoid metal oxide. The “amorphous film” means a layer in which a crystal peak cannot be confirmed by X-ray diffraction.
In this specification, the amorphous oxide semiconductor film in the present invention may be referred to as a semiconductor film (thin film), an amorphous oxide film (thin film), or an amorphous semiconductor film (thin film).
　酸化インジウムに、酸化ランタン、酸化ネオジム、酸化サマリウム、酸化ユウロピウム、酸化ガドリニウム、酸化テルビウム、酸化ジスプロシウム、酸化ホルミウム、酸化エルビウム、酸化ツリウム及び酸化イッテリビウムからなる群から選ばれた１種又は２種以上の酸化物を含有させて、非晶質の酸化物半導体膜を形成させると、半導体膜のキャリヤー濃度を低減することができ、室温付近の温度において半導体膜のキャリヤー濃度を２×１０＋１７ｃｍ－３未満にすることが可能となり、良好な薄膜トランジスタ特性を示すようになる。室温付近の温度におけるキャリヤー濃度は、好ましくは１×１０＋１７ｃｍ－３未満である。キャリヤー濃度が２×１０＋１７ｃｍ－３以上では、薄膜トランジスタ（以下、ＴＦＴということがある）として駆動しないおそれがある。また、ＴＦＴとして駆動したとしてもノーマリーオンになったり、閾値電圧が大きくマイナスになったり、Ｏｎ－Ｏｆｆ値が小さくなったりする場合がある。 One or more selected from the group consisting of indium oxide, lanthanum oxide, neodymium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide, and ytterbium oxide When an amorphous oxide semiconductor film is formed by containing an oxide, the carrier concentration of the semiconductor film can be reduced, and the carrier concentration of the semiconductor film is 2 × 10 +17 cm −3 at a temperature near room temperature. Therefore, good thin film transistor characteristics are exhibited. The carrier concentration at temperatures near room temperature is preferably less than 1 × 10 +17 cm −3 . When the carrier concentration is 2 × 10 +17 cm −3 or more, the thin film transistor (hereinafter sometimes referred to as TFT) may not be driven. Even when the TFT is driven, it may be normally on, the threshold voltage may be greatly negative, or the On-Off value may be small.
　本発明においては、酸化ランタン、酸化ネオジム、酸化サマリウム、酸化ユウロピウム、酸化ガドリニウム、酸化テルビウム、酸化ジスプロシウム、酸化ホルミウム、酸化エルビウム、酸化ツリウム及び酸化イッテリビウムからなる群から選ばれた１種又は２種以上の酸化物をＭ２Ｏ３としたときに、原子比Ｍ／（Ｉｎ＋Ｍ）の値が、０．１以上０．４以下であることが必要である。このような原子比の範囲とすることにより、酸化インジウムが酸化物半導体の主成分となり、ノーマリーオフ特性で、高い移動度を保ち、Ｓ値が小さい（トランスファーカーブにおいて、立ち上がりが早い）トランジスタを達成することができる。 In the present invention, one or more selected from the group consisting of lanthanum oxide, neodymium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide and ytterbium oxide. When the oxide of M 2 O 3 is used, the value of the atomic ratio M / (In + M) needs to be 0.1 or more and 0.4 or less. By setting the atomic ratio in such a range, indium oxide becomes a main component of the oxide semiconductor, a normally-off characteristic, high mobility, a small S value (fast rise in the transfer curve) transistor. Can be achieved.
　尚、各金属元素の含有量は、ＩＣＰ（Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）測定により求めることができる。
　また、各金属元素の含有量は、例えば、半導体膜を形成する際に使用するスパッタリングターゲットの各元素の存在量を調整することで実施できる。半導体膜の組成は、スパッタリングターゲットの組成とほぼ一致する。 In addition, content of each metal element can be calculated | required by ICP (Inductively Coupled Plasma) measurement.
Moreover, content of each metal element can be implemented by adjusting the abundance of each element of the sputtering target used when forming a semiconductor film, for example. The composition of the semiconductor film substantially matches the composition of the sputtering target.
　尚、本発明の効果が得られる範囲において、半導体膜は、酸化インジウム及び前記特定の正３価のランタノイド系金属酸化物以外の成分を含有していてもよい。例えば、酸化ガリウム、酸化スカンジウム等を含有してもよい。
　また、本発明で使用する半導体膜は、酸化インジウム及び前記特定の正３価のランタノイド系金属酸化物から実質的になっていてもよく、また、これらの成分のみからなっていてもよい。「実質的になる」とは、半導体膜は、酸化インジウム及び上記特定の正３価のランタノイド系金属酸化物に加えて上記の他の成分を含みうることを意味する。 In the range where the effects of the present invention can be obtained, the semiconductor film may contain components other than indium oxide and the specific positive trivalent lanthanoid metal oxide. For example, gallium oxide, scandium oxide, or the like may be contained.
Further, the semiconductor film used in the present invention may consist essentially of indium oxide and the specific positive trivalent lanthanoid metal oxide, or may consist only of these components. “Substantially” means that the semiconductor film can contain other components in addition to the indium oxide and the specific positive trivalent lanthanoid metal oxide.
　本発明の薄膜トランジスタにおいて、基板、ゲート電極、ゲート絶縁膜、ソース・ドレイン電極等の構成部材は、公知のものが使用でき、特に限定されない。
　例えば、各電極にはＡｌ、Ｃｕ、Ａｕ等の金属薄膜が使用でき、ゲート絶縁膜には、酸化シリコン膜、酸化ハフニウム膜等の酸化物薄膜を使用できる。 In the thin film transistor of the present invention, known components can be used for the substrate, gate electrode, gate insulating film, source / drain electrode, and the like, and are not particularly limited.
For example, a metal thin film such as Al, Cu, or Au can be used for each electrode, and an oxide thin film such as a silicon oxide film or a hafnium oxide film can be used for the gate insulating film.
　図１は、本発明の薄膜トランジスタの実施形態を示す概略断面図である。
　薄膜トランジスタ１は、基板１０及びゲート絶縁膜３０の間にゲート電極２０を挟持しており、ゲート絶縁膜３０上には半導体膜（チャンネル層）４０が活性層として積層されている。さらに、半導体膜４０の端部付近を覆うようにしてソース電極５０及びドレイン電極５２がそれぞれ設けられている。半導体膜４０、ソース電極５０及びドレイン電極５２で囲まれた部分にチャンネル部６０を形成している。
　尚、図１の薄膜トランジスタ１はいわゆるチャンネルエッチ型薄膜トランジスタである。本発明の薄膜トランジスタは、チャンネルエッチ型薄膜トランジスタに限定されず、本技術分野で公知の素子構成を採用できる。例えば、エッチストッパー型の薄膜トランジスタでもよい。 FIG. 1 is a schematic cross-sectional view showing an embodiment of a thin film transistor of the present invention.
The thin film transistor 1 has a gate electrode 20 sandwiched between a substrate 10 and a gate insulating film 30, and a semiconductor film (channel layer) 40 is stacked on the gate insulating film 30 as an active layer. Further, a source electrode 50 and a drain electrode 52 are provided so as to cover the vicinity of the end of the semiconductor film 40. A channel portion 60 is formed in a portion surrounded by the semiconductor film 40, the source electrode 50 and the drain electrode 52.
1 is a so-called channel etch type thin film transistor. The thin film transistor of the present invention is not limited to a channel etch type thin film transistor, and an element configuration known in this technical field can be adopted. For example, an etch stopper type thin film transistor may be used.
　図２は、本発明の薄膜トランジスタの他の実施形態を示す概略断面図である。尚、上述した薄膜トランジスタ１と同じ構成部材には同じ番号を付し、その説明を省略する。
　薄膜トランジスタ２は、いわゆるエッチストッパー型の薄膜トランジスタである。薄膜トランジスタ２は、チャンネル部６０を覆うようにエッチストッパー７０が形成されている点を除き、上述した薄膜トランジスタ１と同じ構成である。半導体膜４０の端部付近及びエッチストッパー７０の端部付近を覆うようにしてソース電極５０及びドレイン電極５２がそれぞれ設けられている。 FIG. 2 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. In addition, the same number is attached | subjected to the same structural member as the thin-film transistor 1 mentioned above, and the description is abbreviate | omitted.
The thin film transistor 2 is a so-called etch stopper type thin film transistor. The thin film transistor 2 has the same configuration as the thin film transistor 1 described above except that an etch stopper 70 is formed so as to cover the channel portion 60. A source electrode 50 and a drain electrode 52 are provided so as to cover the vicinity of the end of the semiconductor film 40 and the vicinity of the end of the etch stopper 70.
　本発明では半導体膜４０に、酸化インジウムと、前記特定の正３価のランタノイド系金属酸化物を含む半導体膜を使用する。
　尚、半導体膜を非晶質膜とすることにより、エッチング加工性に優れ、薄膜トランジスタの生産性を高くできる。 In the present invention, a semiconductor film containing indium oxide and the specific positive trivalent lanthanoid metal oxide is used for the semiconductor film 40.
Note that when the semiconductor film is an amorphous film, the etching processability is excellent and the productivity of the thin film transistor can be increased.
　本発明の酸化物薄膜トランジスタは、薄膜トランジスタの構造が、エッチストッパー型の薄膜トランジスタであることが好ましい。 In the oxide thin film transistor of the present invention, the structure of the thin film transistor is preferably an etch stopper type thin film transistor.
　本発明の薄膜トランジスタとなる酸化物薄膜は、金属のエッチング液に容易に溶解する。これにより、電極形成と同時に酸化物薄膜のアイランドを形成することができるようになり、使用するフォトマスクの数を低減することができる。 The oxide thin film to be the thin film transistor of the present invention is easily dissolved in a metal etching solution. Thus, an oxide thin film island can be formed simultaneously with the electrode formation, and the number of photomasks used can be reduced.
　酸化物薄膜が、ソース・ドレイン配線・ソース・ドレイン電極をエッチングするエッチング液で溶解できないと、エッチング液及びフォトマスクを変更する手間が必要となり、工程が煩雑になり、工業的ではない。 If the oxide thin film cannot be dissolved by the etching solution for etching the source / drain wiring / source / drain electrode, it is necessary to change the etching solution and the photomask, and the process becomes complicated and not industrial.
　次に、本発明の薄膜トランジスタの製造方法について説明する。
　本発明の薄膜トランジスタの製造方法（以下、本発明の方法ということがある）は、本発明の酸化物薄膜トランジスタを構成する酸化物半導体膜を、スパッタリングで成膜する工程を含み、該スパッタリング中の酸素濃度を２～２０体積％とし、基板温度を室温から２００℃以下とすることを特徴とする。 Next, a method for manufacturing the thin film transistor of the present invention will be described.
The method for producing a thin film transistor of the present invention (hereinafter sometimes referred to as the method of the present invention) includes a step of forming an oxide semiconductor film constituting the oxide thin film transistor of the present invention by sputtering, and oxygen during the sputtering. The concentration is 2 to 20% by volume, and the substrate temperature is from room temperature to 200 ° C. or less.
　本発明によれば、酸化物半導体膜の成膜工程をスパッタリング工程で行っても、スパッタリングターゲットと同じ組成の薄膜が得られ、大型ガラス基板への適用が容易となる。また、スパッタリング中の酸素濃度を２～２０体積％とすることにより、次工程で行われる、トランジスタの安定化処理工程において均一なトランジスタ特性を与えるようになる。 According to the present invention, a thin film having the same composition as the sputtering target can be obtained even when the oxide semiconductor film is formed by a sputtering process, and the application to a large glass substrate is facilitated. Further, by setting the oxygen concentration during sputtering to 2 to 20% by volume, uniform transistor characteristics can be provided in the transistor stabilization treatment step performed in the next step.
　スパッタリング中の酸素濃度を２体積％未満や２０体積％超にすると、次工程のトランジスタの安定化処理工程（熱処理工程）において均一なトランジスタ特性が得られない場合がある。また、そのときの基板温度は、室温から２００℃以下とする。基板温度を室温より低くするには、冷却装置が必要となり経済的でなくなり、２００℃超では、加熱コストが増大することがあり、また、酸化物薄膜が結晶化しやすくなる場合がある。酸化物薄膜が結晶化した場合等には、エッチング工程で残渣が発生したり、エッチングできなくなったりすることがあり、所望の形状のアイランドを形成できない場合がある。基板温度は、基板の種類及び耐熱性により、適宜調整すればよい。 If the oxygen concentration during sputtering is less than 2% by volume or more than 20% by volume, uniform transistor characteristics may not be obtained in the subsequent transistor stabilization process (heat treatment process). In addition, the substrate temperature at that time is from room temperature to 200 ° C. or less. In order to lower the substrate temperature below room temperature, a cooling device is required, which is not economical. If it exceeds 200 ° C., the heating cost may increase, and the oxide thin film may be easily crystallized. When the oxide thin film is crystallized, a residue may be generated in the etching process or etching may not be performed, and an island having a desired shape may not be formed. The substrate temperature may be adjusted as appropriate depending on the type of substrate and heat resistance.
　本発明の方法においては、上記のようにしてスパッタリングで成膜された酸化物半導体膜を、ソース・ドレイン電極を形成後に、１５０～４５０℃で０．５～１２００分間熱処理することが好ましい。１５０℃より低いとノーマリーオンとなるおそれがあり、安定した薄膜トランジスタが得られない可能性がある。なお、４５０℃より高いと結晶質となるおそれがある。 In the method of the present invention, it is preferable to heat-treat the oxide semiconductor film formed by sputtering as described above at 150 to 450 ° C. for 0.5 to 1200 minutes after forming the source / drain electrodes. If it is lower than 150 ° C., there is a possibility of being normally on, and a stable thin film transistor may not be obtained. In addition, when it exceeds 450 degreeC, there exists a possibility that it may become crystalline.
　半導体膜の熱処理には、大気下や窒素雰囲気下にランプアニ―ル装置、レーザーアニール装置、熱風加熱装置、接触加熱装置等を用いることができる。 For heat treatment of the semiconductor film, a lamp annealing device, a laser annealing device, a hot air heating device, a contact heating device, or the like can be used in the air or a nitrogen atmosphere.
　半導体膜を大気下や窒素雰囲気下に、１５０～４５０℃、０．５～１２００分の条件で熱処理することが好ましい。１５０℃未満では、半導体膜が十分に安定化しない場合があり、４５０℃超では、基板や半導体膜にダメージを与える場合がある。熱処理温度は、１８０℃～３５０℃がさらに好ましく、２００℃～３００℃が特に好ましい。 It is preferable to heat-treat the semiconductor film in the air or in a nitrogen atmosphere under conditions of 150 to 450 ° C. and 0.5 to 1200 minutes. If it is less than 150 ° C., the semiconductor film may not be sufficiently stabilized, and if it exceeds 450 ° C., the substrate and the semiconductor film may be damaged. The heat treatment temperature is more preferably 180 ° C. to 350 ° C., and particularly preferably 200 ° C. to 300 ° C.
　また、熱処理時間が０．５分未満では、熱処理時間が短すぎて膜の熱安定化が不十分となる場合があり、１２００分超では時間が掛かりすぎ生産的ではない。熱処理時間は、１分～６００分がさらに好ましく、特に、５分～６０分が好ましい。 Also, if the heat treatment time is less than 0.5 minutes, the heat treatment time is too short and thermal stabilization of the film may be insufficient. If it exceeds 1200 minutes, it takes too much time and is not productive. The heat treatment time is more preferably 1 minute to 600 minutes, and particularly preferably 5 minutes to 60 minutes.
　熱処理は、ソース・ドレイン配線・ソース・ドレイン電極の形成後に行うのがよい。これら熱処理により、ソース・ドレイン配線・ソース・ドレイン電極の抵抗値を低減することができ、且つ、酸化物薄膜トランジスタの特性を安定化することができる。 The heat treatment is preferably performed after the formation of the source / drain wiring / source / drain electrodes. By these heat treatments, the resistance value of the source / drain wiring / source / drain electrode can be reduced, and the characteristics of the oxide thin film transistor can be stabilized.
　酸化物薄膜は、スパッタリングにより成膜されており、成膜直後は非平衡状態で薄膜化していることが多く、内部応力が均一でなかったり、厚み方向の密度に分布が生じたりする場合がある。この場合、酸化物薄膜は、平衡状態ではないので、場所によりその状態が均一でないため、トランジスタ特性（特に、Ｏｎ／Ｏｆｆ値、移動度、閾値電圧Ｖｔｈ、Ｓ値）にバラツキが発生する場合がある。熱処理することにより、酸化物薄膜トランジスタの特性を安定化することができる。また、ソース・ドレイン配線・ソース・ドレイン電極と酸化物薄膜トランジスタ間の接触抵抗を低減したりする効果があり、より安定化したトランジスタ特性が得られるようになる。 The oxide thin film is formed by sputtering, and is often thinned in a non-equilibrium state immediately after the film formation, so that the internal stress may not be uniform or the density in the thickness direction may be distributed. . In this case, since the oxide thin film is not in an equilibrium state, the state of the oxide thin film is not uniform depending on the location, and thus transistor characteristics (particularly, On / Off value, mobility, threshold voltage Vth, S value) may vary. is there. By the heat treatment, the characteristics of the oxide thin film transistor can be stabilized. Further, there is an effect of reducing the contact resistance between the source / drain wiring / source / drain electrode and the oxide thin film transistor, and more stable transistor characteristics can be obtained.
　以下、本発明の方法による、エッチストッパー型薄膜トランジスタの形成方法を、図３を参照しながら説明する。図３の右側の図は用いるマスクのパターンを示し、左側の図は、当該マスクによって形成される積層構造の、マスクパターン中に示す点線部分における断面図である。 Hereinafter, a method of forming an etch stopper type thin film transistor according to the method of the present invention will be described with reference to FIG. The right side of FIG. 3 shows a mask pattern to be used, and the left side is a cross-sectional view of a layered structure formed by the mask at a dotted line portion shown in the mask pattern.
　ガラス（基板１０）上に、金属薄膜を形成し、レジスト塗布、露光、現像、エッチング、レジスト剥離、洗浄を行い、ゲート配線・ゲート電極２０を形成する。このとき、所望するゲート配線・ゲート電極２０の形状を形成するための第一のフォトマスクを使用する。 A metal thin film is formed on glass (substrate 10), and resist coating, exposure, development, etching, resist peeling, and washing are performed to form gate wiring / gate electrode 20. At this time, a first photomask for forming a desired shape of the gate wiring / gate electrode 20 is used.
　次に、ゲート絶縁膜３０として、ＳｉＮｘをＣＶＤにて成膜したあとに、本発明の酸化物薄膜（半導体膜４０）及びエッチストッパー７０となるＳｉＯ２薄膜を形成し、レジスト塗布、露光、現像、エッチング、レジスト剥離、洗浄を行い、所望のエッチストッパー形状を形成する。このとき、エッチングはドライプロセスで行うのがよい。 Next, after depositing SiN x as a gate insulating film 30 by CVD, an oxide thin film (semiconductor film 40) of the present invention and an SiO 2 thin film to be an etch stopper 70 are formed, resist coating, exposure, Development, etching, resist stripping, and cleaning are performed to form a desired etch stopper shape. At this time, the etching is preferably performed by a dry process.
　例えば、ＣＦ４と酸素をエッチングガスとして用いて、ドライプロセスによりＳｉＯ２をエッチングすることができる。このとき、所望の形状のエッチストッパーを形成するために、第二のフォトマスクを使用する。 For example, SiO 2 can be etched by a dry process using CF 4 and oxygen as etching gases. At this time, a second photomask is used to form an etch stopper having a desired shape.
　次に、ソース・ドレイン電極５０，５２となる金属薄膜を形成し、レジスト塗布、露光、現像、エッチング、レジスト剥離、洗浄を行い、所望のソース・ドレイン配線・ソース・ドレイン電極５０，５２を形成すると同時に、チャンネル部６０となる部分の金属薄膜を除去することができる。前記酸化物薄膜は、金属のエッチング液にて、容易にエッチングできるので、酸化物薄膜トランジスタとなるべきアイランド（島構造）を形成することができる。これにより、第三のフォトマスクで、ソース・ドレイン配線・ソース・ドレイン電極を形成するエッチング液で同時に、酸化物薄膜トランジスタとなるべきアイランド（島構造）を形成することができる。 Next, a metal thin film to be the source / drain electrodes 50, 52 is formed, and resist application, exposure, development, etching, resist stripping, and cleaning are performed to form desired source / drain wirings / source / drain electrodes 50, 52. At the same time, the portion of the metal thin film that becomes the channel portion 60 can be removed. Since the oxide thin film can be easily etched with a metal etching solution, an island (island structure) to be an oxide thin film transistor can be formed. Thus, an island (island structure) to be an oxide thin film transistor can be formed simultaneously with the etching solution for forming the source / drain wiring / source / drain electrode using the third photomask.
　以下、実施例及び比較例を挙げて本発明をより具体的に説明するが、本発明はこれらの実施例によって何ら限定されるものではない。 Hereinafter, the present invention will be described more specifically with reference to Examples and Comparative Examples, but the present invention is not limited to these Examples.
実施例１
＜薄膜トランジスタの作製＞
　図４に示すエッチストッパー型の薄膜トランジスタを、フォトレジスト法にて作製した。
　熱酸化膜３０（ＳｉＯ２膜）付きの導電性シリコン基板１０上に、酸化インジウム及び酸化ガドリニウムからなるターゲット［Ｇｄ／（Ｉｎ＋Ｇｄ）＝０．１５］を用いて、スパッタリング法で４０ｎｍの半導体膜（非晶質酸化物薄膜）４０を成膜した。スパッタリングは、背圧が５×１０－４Ｐａとなるまで真空排気したあと、アルゴン９．５ｓｃｃｍ、酸素０．５ｓｃｃｍを流しながら、圧力を０．２Ｐａに調整し、スパッタパワー１００Ｗにて室温で行った。 Example 1
<Production of Thin Film Transistor>
The etch stopper type thin film transistor shown in FIG. 4 was manufactured by a photoresist method.
On a conductive silicon substrate 10 with a thermal oxide film 30 (SiO 2 film), a target [Gd / (In + Gd) = 0.15] made of indium oxide and gadolinium oxide is used to form a 40 nm semiconductor film (by sputtering). Amorphous oxide thin film) 40 was formed. Sputtering was carried out at room temperature with a sputtering power of 100 W while evacuating until the back pressure reached 5 × 10 −4 Pa, adjusting the pressure to 0.2 Pa while flowing argon 9.5 sccm and oxygen 0.5 sccm. It was.
　次に、Ｓｉをターゲットとして、アルゴン：７ｓｃｃｍ、酸素３ｓｃｃｍ流し、圧力０．５Ｐａにて１００ｎｍ成膜した。その後、レジストを塗布し、８０℃で１５分間プレベークした。その後、マスクを通してＵＶ光（光強度：３００ｍＪ／ｃｍ２）をレジスト膜に照射し、その後、３ｗｔ％のテトラメチルアンモニウムハイドロオキサイド（ＴＭＡＨ）にて現像した。純水で洗浄後、レジスト膜を１３０℃で１５分ポストベークし、チャンネル部６０の下部となる部分（エッチストッパー層）にパターンを形成した。ＣＦ４によるドライエッチングにより、エッチストッパー７０を形成した。レジスト剥離剤にて、レジストを剥離し、水洗し、エアーブローにより乾燥した。 Next, using Si as a target, argon was flowed at 7 sccm and oxygen at 3 sccm, and a film was formed to a thickness of 100 nm at a pressure of 0.5 Pa. Thereafter, a resist was applied and prebaked at 80 ° C. for 15 minutes. Thereafter, the resist film was irradiated with UV light (light intensity: 300 mJ / cm 2 ) through a mask, and then developed with 3 wt% tetramethylammonium hydroxide (TMAH). After washing with pure water, the resist film was post-baked at 130 ° C. for 15 minutes, and a pattern was formed in a portion (etch stopper layer) to be the lower portion of the channel portion 60. An etch stopper 70 was formed by dry etching with CF 4 . The resist was stripped with a resist stripper, washed with water, and dried by air blow.
　その後、半導体膜４０、エッチストッパー７０上に、モリブデン金属膜を３００ｎｍ成膜した。 Thereafter, a molybdenum metal film was formed to 300 nm on the semiconductor film 40 and the etch stopper 70.
　モリブデン金属膜にレジストを塗布し、８０℃で１５分間プレベークした。その後、マスクを通してＵＶ光（光強度：３００ｍＪ／ｃｍ２）をレジスト膜に照射し、その後、３ｗｔ％のテトラメチルアンモニウムハイドロオキサイド（ＴＭＡＨ）にて現像した。純水で洗浄後、レジスト膜を１３０℃で１５分ポストベークし、ソース電極５０及びドレイン電極５２の形状のレジストパターンを形成した。 A resist was applied to the molybdenum metal film, and prebaked at 80 ° C. for 15 minutes. Thereafter, the resist film was irradiated with UV light (light intensity: 300 mJ / cm 2 ) through a mask, and then developed with 3 wt% tetramethylammonium hydroxide (TMAH). After washing with pure water, the resist film was post-baked at 130 ° C. for 15 minutes to form a resist pattern in the shape of the source electrode 50 and the drain electrode 52.
　レジストパターン付き基板を、燐酸・酢酸・硝酸の混合酸で処理することで、モリブデン金属膜及び非晶質酸化物薄膜４０を同時にエッチングした。この場合、エッチストッパーで保護されたチャンネル部上のモリブデン金属膜は、エッチングされ、チャンネル部６０が形成される。 The substrate with a resist pattern was treated with a mixed acid of phosphoric acid, acetic acid and nitric acid, so that the molybdenum metal film and the amorphous oxide thin film 40 were simultaneously etched. In this case, the molybdenum metal film on the channel portion protected by the etch stopper is etched to form the channel portion 60.
　レジストを剥離後、純水で洗浄しエアーブローして乾燥させた。その後、基板を熱処理した。具体的には、基板を熱風加熱炉内で空気中、３００℃で３０分間熱処理した。以上の工程により、薄膜トランジスタ（チャンネル部６０のソース・ドレイン電極間間隙（Ｌ）が１００μｍ、幅（Ｗ）が１０００μｍ）を作製した。 After removing the resist, it was washed with pure water and dried by air blowing. Thereafter, the substrate was heat-treated. Specifically, the substrate was heat-treated at 300 ° C. for 30 minutes in the air in a hot air heating furnace. Through the above steps, a thin film transistor (the gap (L) between the source and drain electrodes of the channel portion 60 is 100 μm and the width (W) is 1000 μm) was produced.
　尚、上記の熱処理をモリブデン金属膜のエッチング後に実施すると、ソース・ドレイン配線／ソース・ドレイン電極の抵抗値を低減することができ、且つ、非晶質酸化物薄膜トランジスタとの接触抵抗を低減させる効果がある。 If the heat treatment is performed after the etching of the molybdenum metal film, the resistance value of the source / drain wiring / source / drain electrode can be reduced and the contact resistance with the amorphous oxide thin film transistor can be reduced. There is.
＜薄膜トランジスタの評価＞
　半導体パラメーターアナライザー（ケースレー４２００ＳＣＳ）を用い、室温、大気中、かつ遮光環境下で測定した。
　この薄膜トランジスタの電界効果移動度は３２．３ｃｍ２／Ｖ・ｓｅｃ、閾値電圧Ｖｔｈ＝１．６Ｖ、Ｓ値＝０．９８Ｖ／ｄｅｃ．、Ｏｎ－Ｏｆｆ比は１０６であり、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。ゲート電極に２０Ｖ電圧を１００分間印加した後のシフト電圧（ΔＶｔｈ）は、０．３Ｖであった。 <Evaluation of thin film transistor>
Using a semiconductor parameter analyzer (Keutley 4200SCS), the measurement was performed at room temperature, in the atmosphere, and in a light-shielded environment.
The field effect mobility of this thin film transistor is 32.3 cm 2 / V · sec, threshold voltage Vth = 1.6 V, S value = 0.98 V / dec. The on-off ratio was 10 6 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off. The shift voltage (ΔVth) after applying a 20V voltage to the gate electrode for 100 minutes was 0.3V.
　基板の位置を変えて製造した薄膜トランジスタの性能にほとんど差はなく、安定していた。 The performance of the thin film transistor manufactured by changing the position of the substrate was almost the same and stable.
＜半導体膜の評価＞
　石英ガラス基板上に、上記のスパッタリングと同じ条件にて半導体膜を形成した。その後、熱風加熱炉内で、空気中、３００℃で３０分間熱処理した。得られた半導体膜のＸ線回折（ＸＲＤ）測定をしたところ、酸化インジウム、酸化ガドリニウムに起因する構造のピークは観察されず、ブロードなＸ線回折パターンが得られた。これにより、半導体膜が非晶質であることが確認できた。また、ホール測定により求めたキャリヤー濃度は、６．３×１０＋１６ｃｍ－３であった。 <Evaluation of semiconductor film>
A semiconductor film was formed on a quartz glass substrate under the same conditions as the above sputtering. Thereafter, heat treatment was performed in air at 300 ° C. for 30 minutes in a hot air heating furnace. When the X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, the peak of the structure resulting from indium oxide and gadolinium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. The carrier concentration determined by hole measurement was 6.3 × 10 +16 cm −3 .
　半導体膜の組成をＩＣＰ装置で測定したところ、ターゲットの組成と同じであった。また、成膜基板内は均一な組成であった。 When the composition of the semiconductor film was measured with an ICP apparatus, it was the same as the composition of the target. In addition, the film formation substrate had a uniform composition.
　内部応力は、５×１０－１０ｄｙｎ・ｃｍ－２以下であり、小さな内部応力しか示さず、基板内での分布がほとんどない安定したものであった。 The internal stress was 5 × 10 −10 dyn · cm −2 or less, showed only a small internal stress, and was stable with almost no distribution in the substrate.
実施例２
　スパッタリングターゲットとして、酸化インジウム、酸化ネオジムからなるターゲット［Ｎｄ／（Ｉｎ＋Ｎｄ）＝０．１０］を用いた他は、実施例１と同様にして、薄膜トランジスタを作製した。 Example 2
A thin film transistor was manufactured in the same manner as in Example 1 except that a target [Nd / (In + Nd) = 0.10] made of indium oxide and neodymium oxide was used as the sputtering target.
　この薄膜トランジスタの電界効果移動度は３２ｃｍ２／Ｖ・ｓｅｃ、閾値電圧Ｖｔｈ＝１．２Ｖ、Ｓ値＝１．８Ｖ／ｄｅｃ．、Ｏｎ－Ｏｆｆ比は１０６であり、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。 The field effect mobility of this thin film transistor is 32 cm 2 / V · sec, threshold voltage Vth = 1.2 V, S value = 1.8 V / dec. The on-off ratio was 10 6 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
　また、得られた半導体膜のＸ線回折（ＸＲＤ）測定をしたところ、酸化インジウム、酸化ネオジムに起因する構造のピークは観察されず、ブロードなＸ線回折パターンが得られた。これにより、半導体膜が非晶質であることが確認できた。また、ホール測定により求めたキャリヤー濃度は、２．９×１０＋１６ｃｍ－３であった。 Moreover, when X-ray diffraction (XRD) measurement of the obtained semiconductor film was carried out, the peak of the structure resulting from indium oxide and neodymium oxide was not observed, but a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. The carrier concentration determined by hole measurement was 2.9 × 10 +16 cm −3 .
実施例３
　スパッタリングターゲットとして、酸化インジウム、酸化テルビウムからなるターゲット［Ｔｂ／（Ｉｎ＋Ｔｂ）＝０．１５］を用いた他は、実施例１と同様にして、薄膜トランジスタを作製した。 Example 3
A thin film transistor was manufactured in the same manner as in Example 1 except that a target [Tb / (In + Tb) = 0.15] made of indium oxide and terbium oxide was used as the sputtering target.
　この薄膜トランジスタの電界効果移動度は２７ｃｍ２／Ｖ・ｓｅｃ、閾値電圧Ｖｔｈ＝２．８Ｖ、Ｓ値＝１．１Ｖ／ｄｅｃ．、Ｏｎ－Ｏｆｆ比は１０６であり、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。 The field effect mobility of this thin film transistor is 27 cm 2 / V · sec, threshold voltage Vth = 2.8 V, S value = 1.1 V / dec. The on-off ratio was 10 6 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
　また、得られた半導体膜のＸ線回折（ＸＲＤ）測定をしたところ、酸化インジウム、酸化テルビウムに起因する構造のピークは観察されず、ブロードなＸ線回折パターンが得られた。これにより、半導体膜が非晶質であることが確認できた。また、ホール測定により求めたキャリヤー濃度は、３．７×１０＋１６ｃｍ－３であった。 Moreover, when the X-ray diffraction (XRD) measurement of the obtained semiconductor film was carried out, the peak of the structure resulting from an indium oxide and a terbium oxide was not observed, but the broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. Further, the carrier concentration determined by Hall measurement was 3.7 × 10 +16 cm −3 .
実施例４
　スパッタリングターゲットとして、酸化インジウム、酸化ランタンからなるターゲット［Ｌａ／（Ｉｎ＋Ｌａ）＝０．２］を用いた他は、実施例１と同様にして、薄膜トランジスタを作製した。 Example 4
A thin film transistor was fabricated in the same manner as in Example 1 except that a target [La / (In + La) = 0.2] made of indium oxide and lanthanum oxide was used as the sputtering target.
　この薄膜トランジスタの電界効果移動度は２４ｃｍ２／Ｖ・ｓｅｃ、閾値電圧Ｖｔｈ＝３．１Ｖ、Ｓ値＝１．５Ｖ／ｄｅｃ．、Ｏｎ－Ｏｆｆ比は１０５であり、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。 The field effect mobility of this thin film transistor is 24 cm 2 / V · sec, threshold voltage Vth = 3.1 V, S value = 1.5 V / dec. , On-Off ratio was 10 5, was a thin film transistor showing a normally-off characteristics. The output characteristics showed a clear pinch-off.
　また、得られた半導体膜のＸ線回折（ＸＲＤ）測定をしたところ、酸化インジウム、酸化ランタンに起因する構造のピークは観察されず、ブロードなＸ線回折パターンが得られた。これにより、半導体膜が非晶質であることが確認できた。また、ホール測定により求めたキャリヤー濃度は、０．９５×１０＋１６ｃｍ－３であった。 Further, when X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, the peak of the structure due to indium oxide and lanthanum oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. The carrier concentration determined by hole measurement was 0.95 × 10 +16 cm −3 .
実施例５
　スパッタリングターゲットとして、酸化インジウム、酸化サマリウムからなるターゲット［Ｓｍ／（Ｉｎ＋Ｓｍ）＝０．２５］を用いた他は、実施例１と同様にして、薄膜トランジスタを作製した。 Example 5
A thin film transistor was fabricated in the same manner as in Example 1 except that a target [Sm / (In + Sm) = 0.25] made of indium oxide and samarium oxide was used as the sputtering target.
　この薄膜トランジスタの電界効果移動度は１８ｃｍ２／Ｖ・ｓｅｃ、閾値電圧Ｖｔｈ＝５．４Ｖ、Ｓ値＝１．３Ｖ／ｄｅｃ．、Ｏｎ－Ｏｆｆ比は１０６であり、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。 The field effect mobility of this thin film transistor is 18 cm 2 / V · sec, threshold voltage Vth = 5.4 V, S value = 1.3 V / dec. The on-off ratio was 10 6 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
　また、得られた半導体膜のＸ線回折（ＸＲＤ）測定をしたところ、酸化インジウム、酸化サマリウムに起因する構造のピークは観察されず、ブロードなＸ線回折パターンが得られた。これにより、半導体膜が非晶質であることが確認できた。また、ホール測定により求めたキャリヤー濃度は、１．４×１０＋１６ｃｍ－３であった。 Further, when X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, the peak of the structure due to indium oxide and samarium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. The carrier concentration determined by hole measurement was 1.4 × 10 +16 cm −3 .
実施例６
　スパッタリングターゲットとして、酸化インジウム、酸化ユウロピウムからなるターゲット［Ｅｕ／（Ｉｎ＋Ｅｕ）＝０．１５］を用いた他は、実施例１と同様にして、薄膜トランジスタを作製した。 Example 6
A thin film transistor was fabricated in the same manner as in Example 1 except that a target [Eu / (In + Eu) = 0.15] made of indium oxide and europium oxide was used as a sputtering target.
　この薄膜トランジスタの電界効果移動度は１５ｃｍ２／Ｖ・ｓｅｃ、Ｖｔｈ＝１．５Ｖ、Ｓ値＝１．８Ｖ／ｄｅｃ．、Ｏｎ－Ｏｆｆ比は１０５であり、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。 The field effect mobility of this thin film transistor is 15 cm 2 / V · sec, Vth = 1.5 V, S value = 1.8 V / dec. , On-Off ratio was 10 5, was a thin film transistor showing a normally-off characteristics. The output characteristics showed a clear pinch-off.
　また、得られた半導体膜のＸ線回折（ＸＲＤ）測定をしたところ、酸化インジウム、酸化ユロピウムに起因する構造のピークは観察されず、ブロードなＸ線回折パターンが得られた。これにより、半導体膜が非晶質であることが確認できた。また、ホール測定により求めたキャリヤー濃度は、２．１×１０＋１６ｃｍ－３であった。 Further, when X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, a peak of the structure due to indium oxide and europium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. The carrier concentration determined by hole measurement was 2.1 × 10 +16 cm −3 .
実施例７
　スパッタリングターゲットとして、酸化インジウム、酸化ホルミウムからなるターゲット［Ｈｏ／（Ｉｎ＋Ｈｏ）＝０．１５］を用いた他は、実施例１と同様にして、薄膜トランジスタを作製した。 Example 7
A thin film transistor was manufactured in the same manner as in Example 1 except that a target [Ho / (In + Ho) = 0.15] made of indium oxide and holmium oxide was used as the sputtering target.
　この薄膜トランジスタの電界効果移動度は１３ｃｍ２／Ｖ・ｓｅｃ、閾値電圧Ｖｔｈ＝１．１Ｖ、Ｓ値＝２．２Ｖ／ｄｅｃ．、Ｏｎ－Ｏｆｆ比は１０６であり、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。 The field effect mobility of this thin film transistor is 13 cm 2 / V · sec, threshold voltage Vth = 1.1 V, S value = 2.2 V / dec. The on-off ratio was 10 6 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
　また、得られた半導体膜のＸ線回折（ＸＲＤ）測定をしたところ、酸化インジウム、酸化ホルミウムに起因する構造のピークは観察されず、ブロードなＸ線回折パターンが得られた。これにより、半導体膜が非晶質であることが確認できた。また、ホール測定により求めたキャリヤー濃度は、５．１×１０＋１６ｃｍ－３であった。 Further, when the X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, the peak of the structure due to indium oxide and holmium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. Further, the carrier concentration determined by Hall measurement was 5.1 × 10 +16 cm −3 .
実施例８
　スパッタリングターゲットとして、酸化インジウム、酸化エルビウムからなるターゲット［Ｅｒ／（Ｉｎ＋Ｅｒ）＝０．１５］を用いた他は、実施例１と同様にして、薄膜トランジスタを作製した。 Example 8
A thin film transistor was manufactured in the same manner as in Example 1 except that a target [Er / (In + Er) = 0.15] made of indium oxide and erbium oxide was used as the sputtering target.
　この薄膜トランジスタの電界効果移動度は３５ｃｍ２／Ｖ・ｓｅｃ、閾値電圧Ｖｔｈ＝４．５Ｖ、Ｓ値＝１．１Ｖ／ｄｅｃ．、Ｏｎ－Ｏｆｆ比は１０６であり、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。 The field effect mobility of this thin film transistor is 35 cm 2 / V · sec, threshold voltage Vth = 4.5 V, S value = 1.1 V / dec. The on-off ratio was 10 6 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
　また、得られた半導体膜のＸ線回折（ＸＲＤ）測定をしたところ、酸化インジウム、酸化エルビウムに起因する構造のピークは観察されず、ブロードなＸ線回折パターンが得られた。これにより、半導体膜が非晶質であることが確認できた。また、ホール測定により求めたキャリヤー濃度は、５．１×１０＋１６ｃｍ－３であった。 Further, when X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, the peak of the structure due to indium oxide and erbium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. Further, the carrier concentration determined by Hall measurement was 5.1 × 10 +16 cm −3 .
実施例９
　スパッタリングターゲットとして、酸化インジウム、酸化ツリウムからなるターゲット［Ｔｍ／（Ｉｎ＋Ｔｍ）＝０．１５］を用いた他は、実施例１と同様にして、薄膜トランジスタを作製した。 Example 9
A thin film transistor was manufactured in the same manner as in Example 1 except that a target [Tm / (In + Tm) = 0.15] made of indium oxide and thulium oxide was used as the sputtering target.
　この薄膜トランジスタの電界効果移動度は１１ｃｍ２／Ｖ・ｓｅｃ、閾値電圧Ｖｔｈ＝６．２Ｖ、Ｓ値＝２．６Ｖ／ｄｅｃ．、Ｏｎ－Ｏｆｆ比は１０７であり、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。 The field effect mobility of this thin film transistor is 11 cm 2 / V · sec, threshold voltage Vth = 6.2 V, S value = 2.6 V / dec. , On-Off ratio is 10 7, was a thin film transistor showing a normally-off characteristics. The output characteristics showed a clear pinch-off.
　また、得られた半導体膜のＸ線回折（ＸＲＤ）測定をしたところ、酸化インジウム、酸化ツリウムに起因する構造のピークは観察されず、ブロードなＸ線回折パターンが得られた。これにより、半導体膜が非晶質であることが確認できた。また、ホール測定により求めたキャリヤー濃度は、２．７×１０＋１６ｃｍ－３であった。 Further, when X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, the peak of the structure due to indium oxide and thulium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. The carrier concentration determined by hole measurement was 2.7 × 10 +16 cm −3 .
実施例１０
　スパッタリングターゲットとして、酸化インジウム、酸化イッテリビウムからなるターゲット［Ｙｂ／（Ｉｎ＋Ｙｂ）＝０．１５］を用いた他は、実施例１と同様にして、薄膜トランジスタを作製した。 Example 10
A thin film transistor was manufactured in the same manner as in Example 1 except that a target [Yb / (In + Yb) = 0.15] made of indium oxide and ytterbium oxide was used as a sputtering target.
　この薄膜トランジスタの電界効果移動度は１７ｃｍ２／Ｖ・ｓｅｃ、閾値電圧Ｖｔｈ＝２．７Ｖ、Ｓ値＝１．９Ｖ／ｄｅｃ．、Ｏｎ－Ｏｆｆ比は１０８であり、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。 The field effect mobility of this thin film transistor is 17 cm 2 / V · sec, threshold voltage Vth = 2.7 V, S value = 1.9 V / dec. The on-off ratio was 10 8 , and the thin film transistor exhibited normally-off characteristics. The output characteristics showed a clear pinch-off.
　また、得られた半導体膜のＸ線回折（ＸＲＤ）測定をしたところ、酸化インジウム、酸化イッテリビウムに起因する構造のピークは観察されず、ブロードなＸ線回折パターンが得られた。これにより、半導体膜が非晶質であることが確認できた。また、ホール測定により求めたキャリヤー濃度は、３．６×１０＋１６ｃｍ－３であった。 Further, when X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, a peak of the structure due to indium oxide and ytterbium oxide was not observed, and a broad X-ray diffraction pattern was obtained. This confirmed that the semiconductor film was amorphous. Further, the carrier concentration determined by Hall measurement was 3.6 × 10 +16 cm −3 .
比較例１
　スパッタリングターゲットに、酸化インジウム（純度９９．９％）からなるターゲット（不純物としてＳｎ，Ｔｉ，Ｚｒの総合計：１２０ｐｐｍを含む）を使用した他は、実施例１と同様にして薄膜トランジスタを作製した。 Comparative Example 1
A thin film transistor was fabricated in the same manner as in Example 1 except that a target made of indium oxide (purity: 99.9%) (total of Sn, Ti, Zr as impurities: 120 ppm included) was used as the sputtering target.
　その結果、この薄膜トランジスタの電界効果移動度は、４６ｃｍ２／Ｖ・ｓｅｃ、Ｏｎ／ＯＦＦ比は、１０５であり、閾値電圧Ｖｔｈは－１２Ｖ、Ｓ値は２．４Ｖ／ｄｅｃ．でノーマリーオンの特性を示す薄膜トランジスタであった。 As a result, the field effect mobility of this thin film transistor, 46cm 2 / V · sec, On / OFF ratio is 10 5, the threshold voltage Vth is -12V, S value is 2.4V / dec. The thin film transistor exhibits normally-on characteristics.
　得られた薄膜のＸ線回折結果より、結晶質膜であることが判明した。また、ホール測定より求めたキャリヤー濃度は、１．４×１０１８ｃｍ－３であった。 From the X-ray diffraction result of the obtained thin film, it was found to be a crystalline film. Further, the carrier concentration obtained from the hole measurement was 1.4 × 10 18 cm −3 .
比較例２
　スパッタリングターゲットに、酸化インジウム及び酸化サマリウムからなるターゲット［Ｓｍ／（Ｉｎ＋Ｓｍ）＝０．４５］を使用した他は、実施例１と同様にして薄膜トランジスタを作製した。 Comparative Example 2
A thin film transistor was manufactured in the same manner as in Example 1 except that a target [Sm / (In + Sm) = 0.45] made of indium oxide and samarium oxide was used as the sputtering target.
　その結果、チャンネル層（実施例では半導体膜）が絶縁体となったため、ＴＦＴ特性は観察されなかった。 As a result, since the channel layer (semiconductor film in the example) became an insulator, TFT characteristics were not observed.
　得られた薄膜のＸ線回折結果より、非晶質膜であることが判明した。また、ホール測定より求めたキャリヤー濃度は、１０１４ｃｍ－３以下であった。 From the X-ray diffraction result of the obtained thin film, it was found to be an amorphous film. Further, the carrier concentration obtained from the hole measurement was 10 14 cm −3 or less.
比較例３
　スパッタリングターゲットに、酸化インジウム及び酸化サマリウムからなるターゲット［Ｓｍ／（Ｉｎ＋Ｓｍ）＝０．０７］を使用し、また、熱処理（熱風加熱炉内で空気中、３００℃で３０分間熱処理）しなかった他は、実施例１と同様にして薄膜トランジスタを作製した。 Comparative Example 3
The sputtering target used was a target made of indium oxide and samarium oxide [Sm / (In + Sm) = 0.07] and was not heat-treated (heat-treated in air at 300 ° C. for 30 minutes). Were produced in the same manner as in Example 1.
　その結果、チャンネル層は半導体であり、この薄膜トランジスタの電界効果移動度は４０．１ｃｍ２／Ｖ・ｓｅｃであった。しかしながら、Ｏｎ－Ｏｆｆ比は１０３と小さく、Ｓ値は４．２Ｖ／ｄｅｃ．であった。また、ノーマリーオンの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。ゲート電極に２０Ｖ電圧を１００分間印加した後のシフト電圧（ΔＶｔｈ）は、０．２９Ｖであった。 As a result, the channel layer was a semiconductor, and the field effect mobility of this thin film transistor was 40.1 cm 2 / V · sec. However, the On-Off ratio is as small as 10 3 and the S value is 4.2 V / dec. Met. In addition, the thin film transistor exhibits normally-on characteristics. The output characteristics showed a clear pinch-off. The shift voltage (ΔVth) after applying 20V voltage to the gate electrode for 100 minutes was 0.29V.
　尚、得られた薄膜のＸ線回折結果より、非晶質膜であることが判明した。また、ホール測定より求めたキャリヤー濃度は、４．８×１０１８ｃｍ－３であった。 In addition, it turned out that it was an amorphous film from the X-ray-diffraction result of the obtained thin film. Further, the carrier concentration determined from the hole measurement was 4.8 × 10 18 cm −3 .
比較例４
　スパッタリングターゲットに、酸化インジウム、酸化スズ及び酸化サマリウムからなるターゲット［Ｉｎ／（Ｉｎ＋Ｓｎ＋Ｓｍ）＝０．９、Ｓｎ／（Ｉｎ＋Ｓｎ＋Ｓｍ）＝０．０７、Ｓｍ／（Ｉｎ＋Ｓｎ＋Ｓｍ）＝０．０３であり、Ｓｍ／（Ｉｎ＋Ｓｍ）＝０．０３］を使用した他は、実施例１と同様にして薄膜トランジスタを作製した。 Comparative Example 4
The target consisting of indium oxide, tin oxide, and samarium oxide [In / (In + Sn + Sm) = 0.9, Sn / (In + Sn + Sm) = 0.07, Sm / (In + Sn + Sm) = 0.03, and Sm / A thin film transistor was manufactured in the same manner as in Example 1 except that (In + Sm) = 0.03] was used.
　その結果、チャンネル層（実施例では半導体膜）が導電体となったため、ＴＦＴ特性は観察されなかった。 As a result, since the channel layer (semiconductor film in the examples) became a conductor, TFT characteristics were not observed.
　得られた薄膜のＸ線回折結果より、結晶質膜であることが判明した。また、ホール測定より求めたキャリヤー濃度は、１．４×１０２０ｃｍ－３であった。 From the X-ray diffraction result of the obtained thin film, it was found to be a crystalline film. Further, the carrier concentration obtained from the hole measurement was 1.4 × 10 20 cm −3 .
　下記表１に、実施例及び比較例で用いた酸化物半導体膜の構成及び特性をまとめて示す。 Table 1 below collectively shows the structures and characteristics of the oxide semiconductor films used in Examples and Comparative Examples.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　本発明の非晶質酸化物薄膜トランジスタは、ディスプレイ用パネル、ＲＦＩＤタグ、Ｘ線ディテクタパネル・指紋センサ・フォトセンサ等のセンサ等に好適に使用できる。 The amorphous oxide thin film transistor of the present invention can be suitably used for sensors such as display panels, RFID tags, X-ray detector panels, fingerprint sensors, and photosensors.
　本発明の薄膜トランジスタの製造方法は、特に、エッチストッパー型の薄膜トランジスタの製造方法に適している。 The method for producing a thin film transistor of the present invention is particularly suitable for a method for producing an etch stopper type thin film transistor.
　上記に本発明の実施形態及び／又は実施例を幾つか詳細に説明したが、当業者は、本発明の新規な教示及び効果から実質的に離れることなく、これら例示である実施形態及び／又は実施例に多くの変更を加えることが容易である。従って、これらの多くの変更は本発明の範囲に含まれる。
　この明細書に記載の文献の内容を全てここに援用する。 Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will appreciate that these exemplary embodiments and / or embodiments are substantially without departing from the novel teachings and advantages of the present invention. It is easy to make many changes to the embodiment. Accordingly, many of these modifications are within the scope of the present invention.
The entire contents of the documents described in this specification are incorporated herein by reference.

Claims (5)

  1. 　酸化インジウムと、酸化ランタン、酸化ネオジム、酸化サマリウム、酸化ユウロピウム、酸化ガドリニウム、酸化テルビウム、酸化ジスプロシウム、酸化ホルミウム、酸化エルビウム、酸化ツリウム及び酸化イッテリビウムからなる群から選ばれた１種又は２種以上の酸化物をＭ２Ｏ３としたときに、原子比Ｍ／（Ｉｎ＋Ｍ）の値が、０．１以上０．４以下で含む酸化物半導体膜を含む薄膜トランジスタ。 One or more selected from the group consisting of indium oxide and lanthanum oxide, neodymium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide and ytterbium oxide A thin film transistor including an oxide semiconductor film including an oxide having an atomic ratio M / (In + M) of 0.1 to 0.4 when the oxide is M 2 O 3 .
  2. 　前記酸化物半導体膜が非晶質である請求項１に記載の薄膜トランジスタ。 The thin film transistor according to claim 1, wherein the oxide semiconductor film is amorphous.
  3. 　前記薄膜トランジスタの構造が、エッチストッパー型の薄膜トランジスタである請求項１又は２に記載の薄膜トランジスタ。 3. The thin film transistor according to claim 1, wherein the structure of the thin film transistor is an etch stopper type thin film transistor.
  4. 　前記酸化物半導体膜をスパッタリングで成膜する工程を含み、該スパッタリング中の酸素濃度を２～２０体積％とし、基板温度を室温から２００℃以下とする請求項１～３のいずれか１項に記載の薄膜トランジスタの製造方法。 4. The method according to claim 1, further comprising a step of forming the oxide semiconductor film by sputtering, wherein an oxygen concentration during the sputtering is set to 2 to 20% by volume, and a substrate temperature is set to room temperature to 200 ° C. or less. The manufacturing method of the thin-film transistor of description.
  5. 　前記酸化物半導体膜を、ソース・ドレイン電極を形成後に、１５０～４５０℃で０．５～１２００分間熱処理する請求項４に記載の薄膜トランジスタの製造方法。 5. The method of manufacturing a thin film transistor according to claim 4, wherein the oxide semiconductor film is heat-treated at 150 to 450 ° C. for 0.5 to 1200 minutes after forming the source / drain electrodes.
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