[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2010049086A3 - Recessed drain and source areas in combination with advanced silicide formation in transistors - Google Patents

Recessed drain and source areas in combination with advanced silicide formation in transistors Download PDF

Info

Publication number
WO2010049086A3
WO2010049086A3 PCT/EP2009/007548 EP2009007548W WO2010049086A3 WO 2010049086 A3 WO2010049086 A3 WO 2010049086A3 EP 2009007548 W EP2009007548 W EP 2009007548W WO 2010049086 A3 WO2010049086 A3 WO 2010049086A3
Authority
WO
WIPO (PCT)
Prior art keywords
recessed drain
transistors
combination
reduced
silicide formation
Prior art date
Application number
PCT/EP2009/007548
Other languages
French (fr)
Other versions
WO2010049086A2 (en
Inventor
Uwe Griebenow
Andy Wei
Jan Hoentschel
Thilo Scheiper
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102008054075A external-priority patent/DE102008054075B4/en
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to CN200980143153.9A priority Critical patent/CN102203915B/en
Priority to JP2011533583A priority patent/JP5544367B2/en
Priority to KR1020117012510A priority patent/KR101482200B1/en
Publication of WO2010049086A2 publication Critical patent/WO2010049086A2/en
Publication of WO2010049086A3 publication Critical patent/WO2010049086A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H10D30/0213—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation providing different silicide thicknesses on gate electrodes and on source regions or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and also a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal suicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide for reduced overall series resistance and enhanced stress transfer efficiency.
PCT/EP2009/007548 2008-10-31 2009-10-21 Recessed drain and source areas in combination with advanced silicide formation in transistors WO2010049086A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN200980143153.9A CN102203915B (en) 2008-10-31 2009-10-21 The recessed drain be combined with advanced Formation of silicide in transistor and source area
JP2011533583A JP5544367B2 (en) 2008-10-31 2009-10-21 Recessed drain and source areas combined with advanced silicide formation in transistors
KR1020117012510A KR101482200B1 (en) 2008-10-31 2009-10-21 Recessed drain and source areas in combination with advanced silicide formation in transistor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102008054075.7 2008-10-31
DE102008054075A DE102008054075B4 (en) 2008-10-31 2008-10-31 Semiconductor device having a lowered drain and source region in conjunction with a method of complex silicide fabrication in transistors
US12/549,769 US8026134B2 (en) 2008-10-31 2009-08-28 Recessed drain and source areas in combination with advanced silicide formation in transistors
US12/549,769 2009-08-28

Publications (2)

Publication Number Publication Date
WO2010049086A2 WO2010049086A2 (en) 2010-05-06
WO2010049086A3 true WO2010049086A3 (en) 2010-08-19

Family

ID=42028170

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2009/007548 WO2010049086A2 (en) 2008-10-31 2009-10-21 Recessed drain and source areas in combination with advanced silicide formation in transistors

Country Status (1)

Country Link
WO (1) WO2010049086A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510886B2 (en) * 2017-10-26 2019-12-17 Samsung Electronics Co., Ltd. Method of providing reacted metal source-drain stressors for tensile channel stress

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020053711A1 (en) * 1997-06-30 2002-05-09 Chau Robert S. Device structure and method for reducing silicide encroachment
US20040227185A1 (en) * 2003-01-15 2004-11-18 Renesas Technology Corp. Semiconductor device
US6887762B1 (en) * 1998-11-12 2005-05-03 Intel Corporation Method of fabricating a field effect transistor structure with abrupt source/drain junctions
US20050110082A1 (en) * 2003-11-25 2005-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having high drive current and method of manufacture therefor
US20070238242A1 (en) * 2006-04-06 2007-10-11 Shyh-Fann Ting Semiconductor structure and fabrication thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020053711A1 (en) * 1997-06-30 2002-05-09 Chau Robert S. Device structure and method for reducing silicide encroachment
US6887762B1 (en) * 1998-11-12 2005-05-03 Intel Corporation Method of fabricating a field effect transistor structure with abrupt source/drain junctions
US20040227185A1 (en) * 2003-01-15 2004-11-18 Renesas Technology Corp. Semiconductor device
US20050110082A1 (en) * 2003-11-25 2005-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having high drive current and method of manufacture therefor
US20070238242A1 (en) * 2006-04-06 2007-10-11 Shyh-Fann Ting Semiconductor structure and fabrication thereof

Also Published As

Publication number Publication date
WO2010049086A2 (en) 2010-05-06

Similar Documents

Publication Publication Date Title
WO2007120324A3 (en) A dual metal silicide scheme using a dual spacer process
TW200703518A (en) Integration process for fabricating stressed transistor structure
WO2011087606A3 (en) Techniques for forming contacts to quantum well transistors
TW200731362A (en) Resolving pattern-loading issues of SiGe stressor
TW200731413A (en) Technique for forming a contact insulation layer with enhanced stress transfer efficiency
GB2487308A (en) Self-aligned graphene transistor
TW200603294A (en) Method of making transistor with strained source/drain
WO2008027473A3 (en) A transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor
TW200605234A (en) Silicided gate and method for forming the same
GB2459072A (en) An SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device
WO2007078590A3 (en) Silicide layers in contacts for high-k/metal gate transistors
TW200802732A (en) Nonvolatile semiconductor memory device and manufacturing method thereof
GB2473568A (en) CMOS device comprising MOS transistors with recessed drain and source areas and non-conformal silicide regions
TW200727409A (en) Methods of forming devices associated with semiconductor constructions
TW200633219A (en) Device with stepped source/drain region profile
WO2013101790A3 (en) Finfet with merged fins and vertical silicide
TW200802558A (en) Methods for contact resistance reduction of advanced CMOS devices
WO2009017997A9 (en) Method for forming a semiconductor device having abrupt ultra shallow epi-tip regions
TW200715467A (en) Self-aligned gate isolation
TW200744156A (en) Semiconductor structure, semiconductor device and the method for fabricating thereof
TW201614846A (en) Source/drain contacts for non-planar transistors
GB2454135A (en) A field effect transistor having a stressed contact etch stop layer with reduced conformality
SG156582A1 (en) Enhanced stress for transistors
TW200737356A (en) Methods of forming a semiconductor device
WO2007005999A3 (en) Early contact, high cell density process

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200980143153.9

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09736864

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 2011533583

Country of ref document: JP

Ref document number: 3117/DELNP/2011

Country of ref document: IN

ENP Entry into the national phase

Ref document number: 20117012510

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 09736864

Country of ref document: EP

Kind code of ref document: A2