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WO2010046881A2 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
WO2010046881A2
WO2010046881A2 PCT/IB2009/054696 IB2009054696W WO2010046881A2 WO 2010046881 A2 WO2010046881 A2 WO 2010046881A2 IB 2009054696 W IB2009054696 W IB 2009054696W WO 2010046881 A2 WO2010046881 A2 WO 2010046881A2
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WO
WIPO (PCT)
Prior art keywords
layer
oxide layer
over
depositing
silicon nitride
Prior art date
Application number
PCT/IB2009/054696
Other languages
French (fr)
Other versions
WO2010046881A3 (en
Inventor
Marnix Willemsen
Stephan Theeuwen
Guido Dormans
Annemarie Aarts
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2010046881A2 publication Critical patent/WO2010046881A2/en
Publication of WO2010046881A3 publication Critical patent/WO2010046881A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
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    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure

Definitions

  • the present i nvention relates to a method of manufacturi ng a semiconductor device, in particular a LDMOS transistor.
  • RF radio frequency
  • MOSFETs such as MOSFETs having a lateral drain extension region between the drain and channel.
  • MOSFETs are known as LDMOS transistors.
  • LDMOS transistors For a LDMOS transistor to be able to switch large voltages at high frequencies the transistor gate oxide is kept thin, e.g. 25 nm and the gate is kept low-ohmic. This may be achieved by using a heavily doped poly-Si gate material, or a salicide poly-Si gate. Further improvements of the device performance may be achieved by the inclusion of a metal shield over the drain extension region to reduce the detrimental gate-to-drain capacitance.
  • a poly-Si gate is formed over a gate oxide grown after the formation of the channel stop implants, p-well and the field insulation, e.g. shallow trench isolation.
  • the poly-Si gate is used to implant the source and drain junctions in a self-aligned fashion, which is followed by one or more high temperature steps to diffuse the junctions under the gate. Due to the fact that at least the drain implantation is performed at relatively high implant energy, the poly-Si gate must be kept relatively thick, e.g. at least 400 nm, to prevent ion-channeling through the poly-Si into the channel during this step.
  • the poly-Si may be partially salicided during a subsequent process step.
  • the high temperatures required for the junction diffusion step can cause the recrystallization of the poly-Si, which increases the roughness of the gate, which can lead to unreliable performance of the semiconductor device.
  • a polycide gate e.g. a stack of poly-Si and tungsten suicide.
  • Such a gate type is however not available in a standard CMOS production flow, and would therefore require additional investments in such a flow, such as the integration of a polycide deposition and etch step into the flow.
  • a metal gate may be considered to achieve a low-ohmic gate.
  • the metals that are most commonly used in a CMOS flow are incompatible with the high temperature steps required to perform the aforementioned junction diffusion step.
  • Japanese patent application JP 5 1 14 607 discloses a method of manufacturing a MOS transistor in which a tapered gate is formed by utilizing a difference in etching rate between doped and undoped poly-Si.
  • a silicon nitride (Si3lSI 4 ) film for positioning a gate region is formed on a gate oxide film formed on a semiconductor substrate.
  • a source- drain layer is formed by ion implanting followed by the formation of impurity- doped poly-Si regions doped over the source and drain region using the silicon nitride film as a mask.
  • Non-doped poly-Si is grown on the impurity-doped poly-Si, after which a doped region and a non-doped region are formed in the undoped poly-Si by a thermal diffusion from the doped poly-Si.
  • a gate electrode is formed by utilizing the different etching speeds of the doped region and the undoped region. This is followed by the formation of lightly doped regions using the gate electrode as a mask. This method is however unsuitable for the manufacture of a LDMOS transistor because the formation of the doped regions next to the gate, e.g.
  • a drain extension implant would require a significant thermal budget, which not only would mean that the poly-Si forming the gate should be relatively thick but would also introduce the risk of unwanted migration of the gate impurities into the channel. Hence, this process is unsuitable for manufacturing semiconductor devices for high voltage applications.
  • the present invention seeks to provide a method for manufacturing a semiconductor device suitable for use in high voltage applications.
  • a method of manufacturing a semiconductor device comprising growing a sacrificial oxide layer over a substrate; forming a silicon nitride portion covering an intended gate area on the sacrificial oxide layer; forming a source region, a drain region and a drain extension region in the substrate; depositing a further oxide layer and polishing said layer back to the silicon nitride portion; removing the silicon nitride portion, thereby exposing a portion of the sacrificial oxide layer; removing the sacrificial oxide layer portion, thereby exposing a substrate portion; growing a gate oxide layer on the exposed substrate portion; and depositing a gate material over the gate oxide layer.
  • the method of the present invention provides a semiconductor device such as a LDMOS transistor in which a silicon nitride portion temporarily takes the place of the intended gate material until after all the implants have been developed such that the semiconductor device manufactured in accordance with the method of the present invention does not suffer from the aforementioned problems, such as unreliable performance or increased manufacturing cost.
  • the method may further comprise the step of implanting an impurity into the exposed substrate prior to removing the sacrificial oxide layer portion.
  • Such an implant may be used to set the threshold voltage of the semiconductor device, - A -
  • Such engineering steps may include the insertion of a tilted implant, a homogeneous p-well or a box shape implant, to improve the linearity of the device.
  • the step of depositing a gate material comprises depositing a barrier layer; depositing a metal layer over the barrier layer; and polishing the barrier layer and the metal layer back to the further oxide layer.
  • the step of depositing a gate material comprises growing a polysilicon layer; and removing excess polysilicon from the further oxide layer, thereby defining a polysilicon gate.
  • a poly-Si gate may be formed that does not suffer from recrystallization problems caused by the exposure to the aforementioned high temperature steps.
  • the poly-Si gate may be salicided by depositing a metal layer; saliciding the polysilicon gate; and removing unreacted metal from the further oxide layer to lower the resistance of the gate.
  • the manufacture of the semiconductor device may comprise further processing steps, for instance to form contacts to the source and drain regions.
  • further processing steps include depositing an additional oxide layer; etching contact holes for the source and drain regions and forming contacts in said contact holes.
  • the further oxide layer may comprise an impurity such as a phosphor dopant, which allows the further oxide layer to act as a getter.
  • the contact forming step comprises depositing a barrier layer in said contact holes; performing a contact annealing step; and fill the annealed barrier layer-coated contact holes with a conductive material such as a metal.
  • the method of the present invention may be used to manufacture a
  • the method further comprises depositing a silicon nitride layer over the sacrificial oxide layer after said implant forming step and before said further oxide layer forming step.
  • a silicon nitride layer which may be deposited by a chemical vapor deposition step such as LP-CVD, may be used as a dielectric layer for further structures to be formed in the semiconductor device of the present invention.
  • said contact hole etching step may comprise the substeps of partially etching said contact holes up to the silicon nitride layer, said contact holes further including a further contact hole over the drain extension region; applying a mask that covers the further contact hole; and completing the etching of the drain and source contact holes by removing the silicon nitride layer and the sacrificial oxide layer in said holes; and wherein said contact hole filling step includes filling the further contact hole.
  • a shield may be formed over the drain extension region.
  • the substrate further comprises a field oxide region
  • the method further comprises forming a further silicon nitride portion over the field oxide region simultaneous with the formation of the silicon nitride portion; forming a conductive structure over the field oxide region simultaneous with the formation of the gate material; removing the further oxide layer after the formation of the conductive structure and the gate material, thereby exposing the silicon nitride layer; depositing a dielectric layer over the silicon nitride layer, the gate material and the conductive structure; forming a further layer over the dielectric layer; patterning the further layer for forming a shield over the drain extension region and a further conductive structure over the conductive structure, said conductive structure and further conductive structure being separated by the dielectric layer; and depositing an oxide layer over the patterned further layer followed by said contact hole etching step.
  • the further layer is a silicon layer, over which a metal layer such as a cobalt layer is deposited after patterning the silicon layer, followed by an thermal anneal step to form a salicide layer, after which unreacted metal is removed, e.g. by dipping.
  • a metal layer such as a cobalt layer
  • the silicon can be easily patterned using for instance the shield mask, whereas the patterning of a further layer being metal layer may be more difficult, especially when the gate is relatively high.
  • FIG 1A-F schematically depict respective steps of an embodiment of the method of the present invention
  • FIG 2A-C schematically depict respective steps of an aspect of another embodiment of the method of the present invention.
  • FIG 3A-C schematically depict respective steps of an aspect of yet another embodiment of the method of the present invention.
  • FIG. 1A depicts a first stage of an embodiment of the method of the present invention.
  • a substrate 10 is provided, into which channel stop implants 12 and field oxide regions 14 may be formed in any suitable way, if necessary.
  • a sacrificial oxide layer 18, e.g. a SiO2 layer, is formed over the substrate 10.
  • This layer may be formed in any suitable way, e.g. by means of thermal oxidation or a suitable deposition method such as chemical vapor deposition, which may be plasma- enhanced.
  • a silicon nitride layer is formed over the sacrificial oxide layer 18 and subsequently patterned to form a silicon nitride portion 20, which has the same height as the intended height of the gate to be formed in the location of the silicon nitride portion 20, as will be explained in more detail below.
  • the silicon nitride layer may be deposited and patterned in any suitable way. It will be appreciated that the formation of silicon nitride structures in semiconductor device manufacturing methods is known per se such that further details of the formation of the silicon nitride portion 20 have been omitted for reasons of brevity only.
  • the substrate 10 is implanted with the appropriate impurities, e.g. a shallow p-well impurity 22, which is subsequently diffused into the substrate region covered by the gate area, i.e. the silicon nitride portion 20, by a thermal diffusion step, a source impurity 24, a drain impurity 26, and first and second drain extension impurities 28 and 30, with the first drain extension impurity 28 may have a different impurity concentration than the second drain extension impurity to provide a lateral doping gradient between the drain region 26 and the channel underneath the gate to be formed.
  • the appropriate impurities e.g. a shallow p-well impurity 22
  • the first drain extension impurity 28 and 30 may have a different impurity concentration than the second drain extension impurity to provide a lateral doping gradient between the drain region 26 and the channel underneath the gate to be formed.
  • the impurities are implanted into the substrate 10 in a self-aligned fashion with the silicon nitride portion 20, such as the shallow p-well implant 22. It will be appreciated that the exact nature and number of the implants is not of crucial importance to the present invention.
  • the implants shown in Fig. 1 B are given by way of non-limiting example only, and alternatives will be apparent to the skilled person.
  • silicon nitride portion 20 has several advantages over the use of a poly-Si portion for the self- aligned implantation of these impurities.
  • Silicon nitride has a much better stopping power than silicon, such that much higher implant energies may be used. This can be advantageously used to increase the breakdown voltage of the semiconductor device. This further means that the height of the gate may be reduced, thus lowering the gate resistance.
  • the crystalline nature of poly-Si can cause the channeling of impurities along the ordered crystal grain boundaries of the poly-Si, which can pollute the channel region.
  • Silicon nitride is amorphous, hence does not suffer from this problem.
  • the amorphous nature of silicon nitride further means that the temperature drives required to migrate, i.e. diffuse, the impurities to their intended locations in the substrate 10 can be performed without the risk of causing recrystallization of the gate material.
  • a further oxide layer 32 is grown over the substrate 10 and polished back to expose the silicon nitride portion 20, as shown in FIG. 1C.
  • the further oxide layer 32 e.g. a Si ⁇ 2 layer, may be deposited in any suitable way and may be polished back for instance using a chemical mechanical polishing (CMP) step.
  • CMP chemical mechanical polishing
  • the silicon nitride portion 20 is removed, e.g. by means of a wet etching step, to form a cavity in which the sacrificial oxide layer 18 is exposed.
  • the channel region under the exposed sacrificial oxide may be implanted with an impurity to set the threshold voltage of the semiconductor device. More generally, the fact that the channel region is well-delimited and exposed at this stage enables the tailoring of the channel region doping profile, for instance to improve the linearity of the semiconductor device.
  • suitable implant shapes may include box shapes, tilted implants, homogeneous p-wells and other suitable shapes.
  • a gate dielectric 33 is grown over the exposed substrate 10, such as a gate oxide or another suitable dielectric material, after which the cavity is filled with a gate material 36.
  • the gate material 36 may be any suitable conductive material, such as poly-Si or a metal such as tungsten. In case of the deposition of a metal such as tungsten, this deposition step may be preceded by the growth of a barrier layer 34 in the cavity such as a Ti/TiN layer to prevent the deposited metal from forming parasitic conductive paths by migrating into the further oxide layer 32.
  • the deposition of the gate material 36 may be achieved in any suitable way. This will be apparent to the skilled person.
  • the gate material 36 being poly-Si
  • the gate material may be metalized, i.e. salicided, for instance by depositing a metal layer such as cobalt over the gate material 36 and the further oxide layer 32, exposing the substrate stack to a reactive thermal anneal (RTA) step and subsequent removal of the unreacted metal.
  • RTA reactive thermal anneal
  • the gate material 36 may be a metal that is commonly used in semiconductor manufacturing processes because the incompatibility of these metals with the elevated temperature steps is no longer of any relevance.
  • an additional oxide layer 38 is deposited over the gate material 36 and the further oxide layer 32.
  • the additional oxide layer 38 may comprise an impurity, e.g. phosphor, such that the additional oxide layer 38 can act as a getter layer.
  • contact holes to the source region 24 and the drain region 26 are etched, which may be lined with a barrier layer 40 such as a Ti/TiN layer, prior to filling the contact holes with a conductive material 42 such as tungsten.
  • a conductive material 42 such as tungsten.
  • Other suitable conductive materials may also be used.
  • the excess deposited conductive material, e.g. tungsten may be removed in any suitable way, e.g. by means of a CMP step.
  • a contact anneal step is performed after the deposition of the barrier layer 40 to improve, i.e. reduce, the contact resistance with the source and drain regions 24 and 26. These steps are followed by conventional back-end processing steps to complete the semiconductor device.
  • an example of such an alternative structure may be a semiconductor device in which a conductive shield is formed over the drain extension region to reduce the drain to gate capacitance. The reduction of this capacitance further improves the performance of the semiconductor device.
  • a shield- comprising semiconductor device may be formed by performing the steps of the method shown in FIG. 1A and 1 B up to and including the implanting of the various impurities into the substrate 10. Following these implanting steps, a silicon nitride layer is deposited over the implanted substrate 10 prior to the deposition of the further oxide layer 32.
  • the silicon nitride layer 50 may be deposited in any suitable way, e.g. by means of a low pressure CVD (LP-CVD) step.
  • LP-CVD low pressure CVD
  • the steps shown in FIG. 1 C-1 E may be performed, i.e. the removal of the silicon nitride portion 20 and the deposition of the gate material 36, as previously described, followed by the deposition of the additional oxide layer 38.
  • the contact mask for forming the contact holes 52 to the source and drain regions 24 and 26 is adapted to form a further contact hole 54 over the drain extension region 28.
  • an oxide etch is performed that stops at the silicon nitride layer 50. This may be any suitable etch step, such as a contact etch step.
  • a mask is applied that only exposes the contact holes 52, i.e. masks the further contact hole 54, after which the exposed silicon nitride 50 and the underlying sacrificial oxide 18 is removed from the contact holes 52. This may be done by means of any suitable etching step, which may comprise one or more sub-steps.
  • the contact holes 52 and 54 may be filled as described in the description of FIG. 1 F. This is shown in FIG. 2C, in which the contact holes 52 and the further contact hole 54 are lined with a barrier layer 56, e.g. a Ti/TiN layer and filled with a conductive material 58, e.g. tungsten.
  • a barrier layer 56 e.g. a Ti/TiN layer
  • a conductive material 58 e.g. tungsten.
  • FIG. 3A-C depict how such a shield may be formed in combination with a metal-insulator-metal (MIM) capacitor.
  • MIM metal-insulator-metal
  • FIG. 3A the method depicted in FIG. 2A-C and described in its detailed description is followed up to and including the step in which the gate material 36 has been deposited.
  • a further conductive structure 72 is simultaneously formed over one of the field oxide regions 14 by way of non- limiting example only. It should be understood that the exact location of this further conductive structure 72 is not essential to the present invention.
  • the further conductive structure 72 may have been formed by patterning the silicon nitride layer deposited over the sacrificial gate oxide 18 such that a further silicon nitride portion (not shown) is formed over the field oxide region 14, after which the steps of FIG. 1 B-1 E may have been performed such that the conductive structure 72 over the field oxide region 14 is formed together with the gate material 36.
  • a barrier layer 70 may have been formed together with the barrier layer 32 in case of the further conductive structure 72 being a metal, as previously explained for the gate material 36.
  • a dielectric layer 74 is formed over the substrate stack.
  • This dielectric layer 74 is to form the insulator between the two plates of the MIM capacitor to be formed, the further conductive structure 72 forming one of these plates.
  • the dielectric layer 74 may comprise a silicon oxide layer, a silicon nitride layer, a combination thereof, or any other suitable dielectric material.
  • the dielectric layer 74 may be formed in any suitable way.
  • a conductive layer 76 is subsequently deposited over the dielectric layer 74 and patterned, e.g. using a lithography step, to form the second plate 78 of the M I M capacitor and the shield 80 over the drain extension region. Subsequently, as shown in FIG. 3C, the additional oxide layer 38 is deposited after which the contact holes may be formed as for instance described with the aid of FIG. 2C.
  • the patterning step of the conductive layer 76 may require an anisotropic etching step to remove the conductive layer 76 over the source side of the gate material 36. This step may be difficult to control if the gate structure is relatively high.
  • a thin silicon layer may be deposited, e.g. 50 nm amorphous silicon layer, which may be patterned using a lithography step, thereby forming the shield region 80 and the second plate region 78.
  • This patterned silicon layer may subsequently be salicided by the deposition of a metal such as cobalt and exposing the substrate stack to a RTA step, after which the unreacted metal is removed e.g. by dipping. It will be appreciated that the flow shown in FIG.
  • 3A-C may be modified to form a semiconductor device with a shield 80 but not a MIM capacitor or vice versa.
  • Other modifications such as the formation of resistances in the semiconductor device by alteration of one or more of the described process steps will be apparent to the skilled person.
  • a method is provided in which the gate material is deposited after the implant development steps have been completed, which facilitates the use of gate metals that are incompatible with the evaluated temperatures applied during these development steps.

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Abstract

A method of manufacturing a semiconductor device is disclosed which comprises the steps of: growing a sacrificial oxide layer (18) over a substrate (10); forming a silicon nitride portion (20) covering an intended gate area on the sacrificial oxide layer (18); forming a source region (24), a drain region (26) and a drain extension region (28, 30) in the substrate; depositing a further oxide layer (32) and polishing said layer back to the silicon nitride portion (20); removing the silicon nitride portion (20), thereby exposing a portion of the sacrificial oxide layer (18); removing the sacrificial oxide layer portion, thereby exposing a substrate portion; growing a gate oxide layer (33) on the exposed substrate portion; and depositing a gate material (36) over the gate oxide layer (33). Consequently, a method is provided in which the gate material is deposited after the implant development steps have been completed, which facilitates the use of metals that are incompatible with the evaluated temperatures applied during these development steps.

Description

DESCRIPTION
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
FIELD OF THE INVENTION The present i nvention relates to a method of manufacturi ng a semiconductor device, in particular a LDMOS transistor.
BACKGROUND OF THE INVENTION
Many semiconductor devices are used in application domains in which the device is required to switch between high voltages. An example of such an application domain is radio frequency (RF) electronics, in which RF power transistors may be used in electronic devices such as base stations.
The application of such semiconductor devices in such application domains is a far from trivial exercise, because the semiconductor devices are required to perform at the limit of what may be achievable in a given semiconductor technology. This has led to semiconductor devices having been specially developed for such demanding application domains, e.g. power MOSFETs such as MOSFETs having a lateral drain extension region between the drain and channel. Such MOSFETs are known as LDMOS transistors. For a LDMOS transistor to be able to switch large voltages at high frequencies the transistor gate oxide is kept thin, e.g. 25 nm and the gate is kept low-ohmic. This may be achieved by using a heavily doped poly-Si gate material, or a salicide poly-Si gate. Further improvements of the device performance may be achieved by the inclusion of a metal shield over the drain extension region to reduce the detrimental gate-to-drain capacitance.
However, with technology scaling, the provision of a low-ohmic gate has become cumbersome. Traditionally, a poly-Si gate is formed over a gate oxide grown after the formation of the channel stop implants, p-well and the field insulation, e.g. shallow trench isolation. The poly-Si gate is used to implant the source and drain junctions in a self-aligned fashion, which is followed by one or more high temperature steps to diffuse the junctions under the gate. Due to the fact that at least the drain implantation is performed at relatively high implant energy, the poly-Si gate must be kept relatively thick, e.g. at least 400 nm, to prevent ion-channeling through the poly-Si into the channel during this step. In order to reduce the gate resistance the poly-Si may be partially salicided during a subsequent process step. However, the high temperatures required for the junction diffusion step can cause the recrystallization of the poly-Si, which increases the roughness of the gate, which can lead to unreliable performance of the semiconductor device. These problems may be overcome by the use of a polycide gate, e.g. a stack of poly-Si and tungsten suicide. Such a gate type is however not available in a standard CMOS production flow, and would therefore require additional investments in such a flow, such as the integration of a polycide deposition and etch step into the flow. Alternatively, a metal gate may be considered to achieve a low-ohmic gate. However, the metals that are most commonly used in a CMOS flow are incompatible with the high temperature steps required to perform the aforementioned junction diffusion step.
Japanese patent application JP 5 1 14 607 discloses a method of manufacturing a MOS transistor in which a tapered gate is formed by utilizing a difference in etching rate between doped and undoped poly-Si. A silicon nitride (Si3lSI4) film for positioning a gate region is formed on a gate oxide film formed on a semiconductor substrate. Using the silicon nitride film as a mask, a source- drain layer is formed by ion implanting followed by the formation of impurity- doped poly-Si regions doped over the source and drain region using the silicon nitride film as a mask. Non-doped poly-Si is grown on the impurity-doped poly-Si, after which a doped region and a non-doped region are formed in the undoped poly-Si by a thermal diffusion from the doped poly-Si. A gate electrode is formed by utilizing the different etching speeds of the doped region and the undoped region. This is followed by the formation of lightly doped regions using the gate electrode as a mask. This method is however unsuitable for the manufacture of a LDMOS transistor because the formation of the doped regions next to the gate, e.g. a drain extension implant, would require a significant thermal budget, which not only would mean that the poly-Si forming the gate should be relatively thick but would also introduce the risk of unwanted migration of the gate impurities into the channel. Hence, this process is unsuitable for manufacturing semiconductor devices for high voltage applications.
SUMMARY OF THE INVENTION The present invention seeks to provide a method for manufacturing a semiconductor device suitable for use in high voltage applications.
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising growing a sacrificial oxide layer over a substrate; forming a silicon nitride portion covering an intended gate area on the sacrificial oxide layer; forming a source region, a drain region and a drain extension region in the substrate; depositing a further oxide layer and polishing said layer back to the silicon nitride portion; removing the silicon nitride portion, thereby exposing a portion of the sacrificial oxide layer; removing the sacrificial oxide layer portion, thereby exposing a substrate portion; growing a gate oxide layer on the exposed substrate portion; and depositing a gate material over the gate oxide layer.
Hence, the method of the present invention provides a semiconductor device such as a LDMOS transistor in which a silicon nitride portion temporarily takes the place of the intended gate material until after all the implants have been developed such that the semiconductor device manufactured in accordance with the method of the present invention does not suffer from the aforementioned problems, such as unreliable performance or increased manufacturing cost.
The method may further comprise the step of implanting an impurity into the exposed substrate prior to removing the sacrificial oxide layer portion. Such an implant may be used to set the threshold voltage of the semiconductor device, - A -
or more generally, to engineer the channel profile. Such engineering steps may include the insertion of a tilted implant, a homogeneous p-well or a box shape implant, to improve the linearity of the device.
In an embodiment, the step of depositing a gate material comprises depositing a barrier layer; depositing a metal layer over the barrier layer; and polishing the barrier layer and the metal layer back to the further oxide layer. Hence, the method of the present invention allows for the manufacture of a semiconductor device having a metal gate using commonly used metals in the manufacturing process because the metal is not exposed to the high temperature steps required to diffuse the implants to under the gate.
In an alternative embodiment, the step of depositing a gate material comprises growing a polysilicon layer; and removing excess polysilicon from the further oxide layer, thereby defining a polysilicon gate. Hence, a poly-Si gate may be formed that does not suffer from recrystallization problems caused by the exposure to the aforementioned high temperature steps.
The poly-Si gate may be salicided by depositing a metal layer; saliciding the polysilicon gate; and removing unreacted metal from the further oxide layer to lower the resistance of the gate.
The manufacture of the semiconductor device may comprise further processing steps, for instance to form contacts to the source and drain regions. In an embodiment, such further processing steps include depositing an additional oxide layer; etching contact holes for the source and drain regions and forming contacts in said contact holes. The further oxide layer may comprise an impurity such as a phosphor dopant, which allows the further oxide layer to act as a getter.
In an embodiment, the contact forming step comprises depositing a barrier layer in said contact holes; performing a contact annealing step; and fill the annealed barrier layer-coated contact holes with a conductive material such as a metal. The method of the present invention may be used to manufacture a
LDMOS transistor or may be used to manufacture more complex devices by adjusting the aforementioned manufacturing steps. For instance, in an embodiment, the method further comprises depositing a silicon nitride layer over the sacrificial oxide layer after said implant forming step and before said further oxide layer forming step. Such a silicon nitride layer, which may be deposited by a chemical vapor deposition step such as LP-CVD, may be used as a dielectric layer for further structures to be formed in the semiconductor device of the present invention.
For instance, said contact hole etching step may comprise the substeps of partially etching said contact holes up to the silicon nitride layer, said contact holes further including a further contact hole over the drain extension region; applying a mask that covers the further contact hole; and completing the etching of the drain and source contact holes by removing the silicon nitride layer and the sacrificial oxide layer in said holes; and wherein said contact hole filling step includes filling the further contact hole. This way, a shield may be formed over the drain extension region.
In a further example, the substrate further comprises a field oxide region, and the method further comprises forming a further silicon nitride portion over the field oxide region simultaneous with the formation of the silicon nitride portion; forming a conductive structure over the field oxide region simultaneous with the formation of the gate material; removing the further oxide layer after the formation of the conductive structure and the gate material, thereby exposing the silicon nitride layer; depositing a dielectric layer over the silicon nitride layer, the gate material and the conductive structure; forming a further layer over the dielectric layer; patterning the further layer for forming a shield over the drain extension region and a further conductive structure over the conductive structure, said conductive structure and further conductive structure being separated by the dielectric layer; and depositing an oxide layer over the patterned further layer followed by said contact hole etching step. This way, both a shield and a metal- insulator-metal (MIM) capacitor may be formed in the semiconductor device. In a preferred embodiment, the further layer is a silicon layer, over which a metal layer such as a cobalt layer is deposited after patterning the silicon layer, followed by an thermal anneal step to form a salicide layer, after which unreacted metal is removed, e.g. by dipping. This variant is advantageous because the silicon can be easily patterned using for instance the shield mask, whereas the patterning of a further layer being metal layer may be more difficult, especially when the gate is relatively high.
BRIEF DESCRIPTION OF THE EMBODIMENTS
Embodiments of the invention are described in more detail and by way of non-limiting examples with reference to the accompanying drawings, wherein FIG 1A-F schematically depict respective steps of an embodiment of the method of the present invention;
FIG 2A-C schematically depict respective steps of an aspect of another embodiment of the method of the present invention; and
FIG 3A-C schematically depict respective steps of an aspect of yet another embodiment of the method of the present invention.
DETAILED DESCRIPTION OF THE DRAWINGS
It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts.
FIG. 1A depicts a first stage of an embodiment of the method of the present invention. A substrate 10 is provided, into which channel stop implants 12 and field oxide regions 14 may be formed in any suitable way, if necessary. The substrate 10, which for instance may be a low-ohmic p-type epi substrate, may be further provided with a deep p-well 16 using any suitable process step.
In accordance with an embodiment of the present invention, a sacrificial oxide layer 18, e.g. a SiO2 layer, is formed over the substrate 10. This layer may be formed in any suitable way, e.g. by means of thermal oxidation or a suitable deposition method such as chemical vapor deposition, which may be plasma- enhanced. A silicon nitride layer is formed over the sacrificial oxide layer 18 and subsequently patterned to form a silicon nitride portion 20, which has the same height as the intended height of the gate to be formed in the location of the silicon nitride portion 20, as will be explained in more detail below. The silicon nitride layer may be deposited and patterned in any suitable way. It will be appreciated that the formation of silicon nitride structures in semiconductor device manufacturing methods is known per se such that further details of the formation of the silicon nitride portion 20 have been omitted for reasons of brevity only.
As shown in FIG. 1 B, in a next step, the substrate 10 is implanted with the appropriate impurities, e.g. a shallow p-well impurity 22, which is subsequently diffused into the substrate region covered by the gate area, i.e. the silicon nitride portion 20, by a thermal diffusion step, a source impurity 24, a drain impurity 26, and first and second drain extension impurities 28 and 30, with the first drain extension impurity 28 may have a different impurity concentration than the second drain extension impurity to provide a lateral doping gradient between the drain region 26 and the channel underneath the gate to be formed. At least some of the impurities are implanted into the substrate 10 in a self-aligned fashion with the silicon nitride portion 20, such as the shallow p-well implant 22. It will be appreciated that the exact nature and number of the implants is not of crucial importance to the present invention. The implants shown in Fig. 1 B are given by way of non-limiting example only, and alternatives will be apparent to the skilled person.
At this stage, it is important to realize that the use of the silicon nitride portion 20 has several advantages over the use of a poly-Si portion for the self- aligned implantation of these impurities. Silicon nitride has a much better stopping power than silicon, such that much higher implant energies may be used. This can be advantageously used to increase the breakdown voltage of the semiconductor device. This further means that the height of the gate may be reduced, thus lowering the gate resistance.
Also, the crystalline nature of poly-Si can cause the channeling of impurities along the ordered crystal grain boundaries of the poly-Si, which can pollute the channel region. Silicon nitride is amorphous, hence does not suffer from this problem. The amorphous nature of silicon nitride further means that the temperature drives required to migrate, i.e. diffuse, the impurities to their intended locations in the substrate 10 can be performed without the risk of causing recrystallization of the gate material.
After the temperature drives, a further oxide layer 32 is grown over the substrate 10 and polished back to expose the silicon nitride portion 20, as shown in FIG. 1C. The further oxide layer 32, e.g. a Siθ2 layer, may be deposited in any suitable way and may be polished back for instance using a chemical mechanical polishing (CMP) step.
Subsequently, as shown in FIG. 1 D, the silicon nitride portion 20 is removed, e.g. by means of a wet etching step, to form a cavity in which the sacrificial oxide layer 18 is exposed. At this stage, the channel region under the exposed sacrificial oxide may be implanted with an impurity to set the threshold voltage of the semiconductor device. More generally, the fact that the channel region is well-delimited and exposed at this stage enables the tailoring of the channel region doping profile, for instance to improve the linearity of the semiconductor device. Depending on the required performance, suitable implant shapes may include box shapes, tilted implants, homogeneous p-wells and other suitable shapes. It will be appreciated that this is a significant advantage over the prior art where any channel-tailoring implants had to be diffused under the poly-Si gate, thus limiting the profile shapes that could be achieved this way. In addition, the exposure of the poly-Si to such diffusion steps increased the risk of degradation of the poly-Si, e.g. through recrystallization, as previously explained. Subsequently, the exposed portion of the sacrificial oxide layer 18 is removed, e.g. by dipping, such that the substrate 10 is exposed in the cavity. In a next step, as shown in FIG. 1 E, a gate dielectric 33 is grown over the exposed substrate 10, such as a gate oxide or another suitable dielectric material, after which the cavity is filled with a gate material 36. The gate material 36 may be any suitable conductive material, such as poly-Si or a metal such as tungsten. In case of the deposition of a metal such as tungsten, this deposition step may be preceded by the growth of a barrier layer 34 in the cavity such as a Ti/TiN layer to prevent the deposited metal from forming parasitic conductive paths by migrating into the further oxide layer 32. The deposition of the gate material 36 may be achieved in any suitable way. This will be apparent to the skilled person. In case of the gate material 36 being poly-Si, the gate material may be metalized, i.e. salicided, for instance by depositing a metal layer such as cobalt over the gate material 36 and the further oxide layer 32, exposing the substrate stack to a reactive thermal anneal (RTA) step and subsequent removal of the unreacted metal.
It is pointed out that because the elevated temperature step(s) required to diffuse the impurities that have been implanted in the substrate to their destinations, are performed before the deposition of the gate material 36, the gate material 36 may be a metal that is commonly used in semiconductor manufacturing processes because the incompatibility of these metals with the elevated temperature steps is no longer of any relevance.
The semiconductor device may now be completed using conventional processing steps. For instance, as shown in FIG. 1 F, an additional oxide layer 38 is deposited over the gate material 36 and the further oxide layer 32. The additional oxide layer 38 may comprise an impurity, e.g. phosphor, such that the additional oxide layer 38 can act as a getter layer. Next, contact holes to the source region 24 and the drain region 26 are etched, which may be lined with a barrier layer 40 such as a Ti/TiN layer, prior to filling the contact holes with a conductive material 42 such as tungsten. Other suitable conductive materials may also be used. The excess deposited conductive material, e.g. tungsten, may be removed in any suitable way, e.g. by means of a CMP step.
In an embodiment, a contact anneal step is performed after the deposition of the barrier layer 40 to improve, i.e. reduce, the contact resistance with the source and drain regions 24 and 26. These steps are followed by conventional back-end processing steps to complete the semiconductor device.
At this point, it is emphasized that the steps depicted in FIG. 1A-F may be modified to facilitate the manufacturing of alternative semiconductor devices. For instance, an example of such an alternative structure may be a semiconductor device in which a conductive shield is formed over the drain extension region to reduce the drain to gate capacitance. The reduction of this capacitance further improves the performance of the semiconductor device. Such a shield- comprising semiconductor device may be formed by performing the steps of the method shown in FIG. 1A and 1 B up to and including the implanting of the various impurities into the substrate 10. Following these implanting steps, a silicon nitride layer is deposited over the implanted substrate 10 prior to the deposition of the further oxide layer 32. The silicon nitride layer 50 may be deposited in any suitable way, e.g. by means of a low pressure CVD (LP-CVD) step. Next, the steps shown in FIG. 1 C-1 E may be performed, i.e. the removal of the silicon nitride portion 20 and the deposition of the gate material 36, as previously described, followed by the deposition of the additional oxide layer 38.
The contact mask for forming the contact holes 52 to the source and drain regions 24 and 26 is adapted to form a further contact hole 54 over the drain extension region 28. In a next step, shown in FIG. 2B, an oxide etch is performed that stops at the silicon nitride layer 50. This may be any suitable etch step, such as a contact etch step. In a next step (not shown), a mask is applied that only exposes the contact holes 52, i.e. masks the further contact hole 54, after which the exposed silicon nitride 50 and the underlying sacrificial oxide 18 is removed from the contact holes 52. This may be done by means of any suitable etching step, which may comprise one or more sub-steps.
The contact holes 52 and 54 may be filled as described in the description of FIG. 1 F. This is shown in FIG. 2C, in which the contact holes 52 and the further contact hole 54 are lined with a barrier layer 56, e.g. a Ti/TiN layer and filled with a conductive material 58, e.g. tungsten.
At this point, it is emphasized that the formation of the shield over the drain extension region is not explicitly depicted in FIG. 2A-2C. However, the formation of such a shield is known per se and not explicitly depicted for reasons of brevity only. FIG. 3A-C depict how such a shield may be formed in combination with a metal-insulator-metal (MIM) capacitor. In FIG. 3A, the method depicted in FIG. 2A-C and described in its detailed description is followed up to and including the step in which the gate material 36 has been deposited. In addition to the formation of the gate structure, a further conductive structure 72 is simultaneously formed over one of the field oxide regions 14 by way of non- limiting example only. It should be understood that the exact location of this further conductive structure 72 is not essential to the present invention.
The further conductive structure 72 may have been formed by patterning the silicon nitride layer deposited over the sacrificial gate oxide 18 such that a further silicon nitride portion (not shown) is formed over the field oxide region 14, after which the steps of FIG. 1 B-1 E may have been performed such that the conductive structure 72 over the field oxide region 14 is formed together with the gate material 36. A barrier layer 70 may have been formed together with the barrier layer 32 in case of the further conductive structure 72 being a metal, as previously explained for the gate material 36. In a next step, as shown in FIG. 3B, a dielectric layer 74 is formed over the substrate stack. This dielectric layer 74 is to form the insulator between the two plates of the MIM capacitor to be formed, the further conductive structure 72 forming one of these plates. The dielectric layer 74 may comprise a silicon oxide layer, a silicon nitride layer, a combination thereof, or any other suitable dielectric material. The dielectric layer 74 may be formed in any suitable way.
A conductive layer 76 is subsequently deposited over the dielectric layer 74 and patterned, e.g. using a lithography step, to form the second plate 78 of the M I M capacitor and the shield 80 over the drain extension region. Subsequently, as shown in FIG. 3C, the additional oxide layer 38 is deposited after which the contact holes may be formed as for instance described with the aid of FIG. 2C.
It is noted that the patterning step of the conductive layer 76 may require an anisotropic etching step to remove the conductive layer 76 over the source side of the gate material 36. This step may be difficult to control if the gate structure is relatively high. As an alternative, a thin silicon layer may be deposited, e.g. 50 nm amorphous silicon layer, which may be patterned using a lithography step, thereby forming the shield region 80 and the second plate region 78. This patterned silicon layer may subsequently be salicided by the deposition of a metal such as cobalt and exposing the substrate stack to a RTA step, after which the unreacted metal is removed e.g. by dipping. It will be appreciated that the flow shown in FIG. 3A-C may be modified to form a semiconductor device with a shield 80 but not a MIM capacitor or vice versa. Other modifications, such as the formation of resistances in the semiconductor device by alteration of one or more of the described process steps will be apparent to the skilled person. In summary, a method is provided in which the gate material is deposited after the implant development steps have been completed, which facilitates the use of gate metals that are incompatible with the evaluated temperatures applied during these development steps.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method of manufacturing a semiconductor device, comprising: growing a sacrificial oxide layer (18) over a substrate (10); forming a silicon nitride portion (20) covering an intended gate area on the sacrificial oxide layer (18); forming a source region (24), a drain region (26) and a drain extension region (28, 30) in the substrate; depositing a further oxide layer (32) and polishing said layer back to the silicon nitride portion (20); removing the silicon nitride portion (20), thereby exposing a portion of the sacrificial oxide layer (18); removing the sacrificial oxide layer portion, thereby exposing a substrate portion; growing a gate oxide layer (33) on the exposed substrate portion; and depositing a gate material (36) over the gate oxide layer (33).
2. The method of claim 1 , further comprising implanting an impurity into the exposed substrate (10) prior to removing the sacrificial oxide layer portion.
3. The method of claim 1 or 2, wherein the step of depositing a gate material (36) comprises: depositing a barrier layer (34); depositing a metal layer over the barrier layer (34); and polishing the barrier layer (34) and the metal layer back to the further oxide layer (32).
4. The method of claim 1 or 2, wherein the step of depositing a gate material (26) comprises: growing a polysilicon layer; and removing excess polysilicon from the further oxide layer (32), thereby defining a polysilicon gate.
5. The method of claim 4, further comprising: depositing a metal layer; saliciding the polysilicon gate; and removing unreacted metal from the further oxide layer (32).
6. The method of any of claims 1-5, further comprising: depositing an additional oxide layer (38); etching contact holes (52) for the source and drain regions (24, 26); and forming contacts (58) in said contact holes (52).
7. The method of claim 6, wherein said contact forming step comprises: depositing a barrier layer (56) in said contact holes (52); performing a contact annealing step; and filling the annealed barrier layer-coated contact holes with a conductive material (58).
8. The method of claim 6 or 7, wherein the additional oxide layer (38) comprises an impurity thereby allowing the additional oxide layer (38) to function as a getter.
9. The method of claims 6 or 7, further comprising: depositing a silicon nitride layer (50) over the sacrificial oxide layer (18) after said implant forming step.
10. The method of claim 9, wherein said contact hole etching step comprises the following substeps: partially etching said contact holes (52, 54) up to the silicon nitride layer (50), said contact holes further including a further contact hole (54) over the drain extension region; applying a mask that covers the further contact hole (54); and completing the etching of the drain and source contact holes (52) by removing the silicon nitride layer (50) and the sacrificial oxide layer (18) in said holes; and wherein said contact hole filling step includes filling the further contact hole (54).
11. The method of claim 9 or 10, wherein the silicon nitride layer (50) is deposited by a chemical vapor deposition step.
12. The method of claim 9, 10 or 11 , wherein the substrate further comprises a field oxide region (14), the method further comprising: forming a further silicon nitride portion over the field oxide region (14) simultaneous with the formation of the silicon nitride portion (20); forming a conductive structure (72) over the field oxide region (14) simultaneous with the formation of the gate material (34); removing the further oxide layer after the formation of the conductive structure (72) and the gate material (34), thereby exposing the silicon nitride layer (50); depositing a dielectric layer (74) over the silicon nitride layer (50), the gate material (34) and the conductive structure (72); forming a further layer (76) over the dielectric layer (74); patterning the further layer (76) for forming a shield (80) over the drain extension region and a further conductive structure (78) over the conductive structure (72), said conductive structure (72) and further conductive structure (78) being separated by the dielectric layer (74); and depositing the additional oxide layer (38) over the patterned further layer (76) followed by said contact hole etching step.
13. The method of claim 12, wherein forming said further layer (76) comprises depositing a silicon layer over the dielectric layer (74); depositing a metal layer over the patterned silicon layer; forming a salicide layer by reacting the patterned silicon layer with the metal layer; and removing unreacted metal after forming the salicide layer.
14. The method of claim 13, wherein the metal layer is a cobalt layer.
15. A semiconductor device manufactured by the method of any of claims 1- 14.
PCT/IB2009/054696 2008-10-23 2009-10-23 Semiconductor device manufacturing method WO2010046881A2 (en)

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CN104882409A (en) * 2014-02-27 2015-09-02 北大方正集团有限公司 Method of manufacturing radio frequency lateral double-diffusion power device with integrated capacitor
WO2022177971A1 (en) * 2021-02-16 2022-08-25 Efficient Power Conversion Corporation Gate metal-insulator-field plate metal integrated circuit capacitor and method of forming the same

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