WO2009122344A1

WO2009122344A1 - An electronic component, and a method of operating an electronic component

Info

Publication number: WO2009122344A1
Application number: PCT/IB2009/051323
Authority: WO
Inventors: Roger Cuppens
Original assignee: Nxp B.V.
Priority date: 2008-04-04
Filing date: 2009-03-30
Publication date: 2009-10-08

Abstract

An electronic component (100), the electronic component (100) comprising a convertible structure (102) being convertible between at least two states by heating and having different electrical properties in different ones of the at least two states, a signal source (104) adapted for triggering conversion of the convertible structure (102) between the at least two states by supplying an electric conversion signal to the convertible structure (102), a controllable selection resistance (106) electrically coupled to the convertible structure (102) and adapted for controlling an electric current value flowing through the convertible structure (102) upon application of the electric conversion signal, and a control unit (108) adapted for controlling an electric resistance value of the controllable selection resistance (106) to thereby define into which of the at least two states the convertible structure (102) is converted upon application of the electric conversion signal.

Description

An electronic component, and a method of operating an electronic component

FIELD OF THE INVENTION The invention relates to an electronic component.

Furthermore, the invention relates to an electronic array. Moreover, the invention relates to a method of operating an electronic component.

BACKGROUND OF THE INVENTION

In the field of non- volatile memories, scaling beyond a 45 nm node has become a real issue. Potential technologies that face this challenge are ferroelectric, magnetic and phase change memories. They are not only promising for the replacement of flash but show also characteristic that may allow replacement of other types of memories such as DRAM. Phase change memories are a possible solution for the unified memory being an important step in the electronics art. OTP ("on time programmable") and MTP ("multiple times programmable") memories open a field that may present a great opportunity for phase change memories as well.

Phase change materials may be used to store information. The operational principle of these materials is a change of phase. In a crystalline phase, the material structure is, and thus properties are, different from the properties in the amorphous phase.

The information storage in a phase change material is based on the difference between the resistivity of the material in its amorphous and crystalline phase. To switch between both phases, an increase of the temperature is required. Very high temperatures with rapid cooling down will result in an amorphous phase, whereas a smaller increase in temperature or slower cooling down leads to a crystalline phase. Sensing the different resistances may be done with a small current that does not cause substantial heating to prevent undesired phase change.

The increase in temperature may be obtained by applying a pulse to the memory cell. A high current density caused by the pulse may lead to a local temperature increase. Depending on the duration and amplitude of the pulse, the resulting phase will be different. Larger pulse amplitudes, so-called RESET pulses, may amorphize the cells, whereas smaller pulse amplitudes (causing an initial voltage drop above a certain threshold voltage) will SET the cell to its crystalline state, these pulses are also called SET pulses.

US 6,816,404 discloses a phase-change nonvolatile memory array formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

However, according to US 6,816,404, the word lines are connected to a normal decoder with Vdd as supply. The currents are controlled via a MOST (low Vt ) in the current path. More column selection transistors are used, creating extra voltage drops (higher supply voltage needed).

US 7,075,841 discloses a memory device of a phase change type, wherein a memory cell has a memory element of chalcogenic material switchable between at least two phases associated with two different states of the memory cell. A write stage is connected to the memory cell and has a capacitive circuit configured to generate a discharge current having no constant portion and to cause the memory cell to change state.

However, according to US 7,075,841, the current is controlled via charge pumps connected via selection transistors to the selected bit lines. The word lines are connected to a normal decoder (with Vdd as supply).

Thus, the current control of conventional memory cells may involve a lot of overhead in the periphery and may thus be cumbersome.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the invention to provide an electronic component having a convertible structure, which has a simple construction. In order to achieve the object defined above, an electronic component, an electronic array, and a method of operating an electronic component according to the independent claims are provided.

According to an exemplary embodiment of the invention, an electronic component (such as a memory cell) is provided, the electronic component comprising a convertible structure (such as a phase change material) being convertible between at least two states (such as a crystalline state and an amorphous state) by heating (such as ohmic heating by an electric current) and having different electrical properties (such as different conductivity) in different ones of the at least two states, a signal source (which may be arranged as part of a bit line control circuitry) adapted for triggering conversion of the convertible structure between the at least two states by supplying an electric conversion signal (for instance an electric current pulse) to the convertible structure, a controllable selection resistance (such as a gate-controlled selection transistor) electrically coupled to the convertible structure and adapted for controlling an electric current value flowing through the convertible structure upon application of the electric conversion signal, and a control unit (which may be arranged as part of a word line control circuitry) adapted for controlling an electric resistance value of the controllable selection resistance to thereby define into which of the at least two states the convertible structure is converted upon application of the electric conversion signal. According to another exemplary embodiment of the invention, an electronic array (such as a memory array) is provided which comprises a plurality of electronic components having the above mentioned features and arranged in rows and columns (for instance in a matrix- like manner), a plurality of bit lines each adapted for coupling a signal source (which may be provided in common for electronic components of a column) to convertible structures of a respective column of electronic components, and a plurality of word lines each adapted for coupling a control unit (which may be provided in common for electronic components of a row) to controllable selection resistances of a respective row of electronic components.

According to still another exemplary embodiment of the invention, a method of operating an electronic component is provided, the method comprising triggering conversion of a convertible structure of the electronic component being convertible between at least two states by heating and having different electrical properties in different ones of the at least two states by supplying an electric conversion signal to the convertible structure, and controlling an electric resistance value of a controllable selection resistance of the electronic component electrically coupled to the convertible structure for controlling an electric current value flowing through the convertible structure upon application of the electric conversion signal to thereby define into which of the at least two states the convertible structure is converted upon application of the electric conversion signal. - A -

The term "electronic component" may particularly denote any component, member or apparatus, which fulfils any electric, magnetic and/or electronic functionality. This means that electric, magnetic and/or electromagnetic signals may be applied to and/or generated by the electronic component during regular use. The term "convertible structure" may particularly denote any physical structure having convertible properties. Examples are a phase change structure or a structure with thermo-dependent properties. Phase change materials can have not only two phases but also more than two phases, for instance crystalline, amorphous, meta-amorphous, meta-crystalline, crystalline with a different lattice orientation, etc. A "phase change by heating" may particularly denote any change of any physical parameter or material property under the influence of heat generated by ohmic losses of an electric current flowing through the structure.

The term "memory cell" may particularly denote a physical structure (such as a layer sequence, for instance monolithically integrated on/in a substrate such as a silicon substrate) which allows to store information in an electronic manner. An amount of information stored in a memory cell may be 1 bit (particularly when the phase change material is switched between two phases representing logical values "1" or "0") or may be more than 1 bit (particularly when the phase change material is switched between at least three phases or between more than two resistive values). The memory cell may be formed on and/or in a substrate which may denote any suitable material, such as a semiconductor, glass, plastic, etc. According to an exemplary embodiment of the invention, an electric member is provided which is capable of converting a convertible structure between different phase states using an electric conversion signal, wherein a specific phase state to be adjusted by the programming procedure can be adjusted by modulating an ohmic resistance of a controllable selection resistance on the basis of a corresponding control signal, thereby exposing the convertible structure to a data in signal dependent selection signal.

Particularly, in a memory array (for instance a matrix- like array of rows and columns), a single programming voltage may be sufficient to be provided to a bit line, wherein the decision whether a phase change material memory cell is brought to a crystalline or to an amorphous state is taken by making a corresponding selection transistor coupled to a word line more or less conductive, thereby modulating a current value flowing through the phase change material by a selection signal at the word line.

In contrast to conventional approaches requiring a complex circuitry in a bit line configuration for generating different currents for setting a phase change cell, for resetting a phase change cell, and for reading out a phase change cell, which complex bit line circuitry involves a voltage drop in the bit line configuration reducing an available supply voltage, embodiments of the invention allow for a very simple bit line configuration by configuring a word line configuration in a manner that a voltage drop of a selection element such as a selection transistor may be modulated to different values for resetting and setting a phase change cell. Thus, the rest of a voltage applied between a serially coupled phase change cell and the selection element drops at the phase change cell, thereby allowing to choose the state of the phase change cell by modifying the conductivity of the selection element. According to an exemplary embodiment of the invention, a memory architecture is provided that allows the control of the SET and RESET currents via the gate voltage on the memory access transistor (for instance nominal Vaa or about 2*Vdd), eliminating the need of input data controlled current sources in the bit line path. This may simplify the design, can save area (for a good control over the currents, large transistors are needed) and fits better in embedded applications with its low supply voltage range, since a current source needs an extra voltage drop. If needed, generators of higher voltages with very limited current drive may be much easier to be made than large controlled current generators.

Logic processes are in many times optimized for low supply voltages. Transistors are allowed to see "overvoltages" depending on the limited time. Chalcogenide material needs a relative large current per cell to switch from low to high (RESET) while this low resistor is in the kOhm range. This requires that almost the supply voltage or even a larger one has to be over the resistor itself. The other transition needs a current well below the RESET one but first it has to surpass a "threshold voltage" over the high resistor. The material can optimized so that this threshold voltage is below the nominal supply voltage. Conventionally implemented charge pumps to generate a higher voltage from the low nominal supply, that can deliver a large current, are area consuming, and adding current control devices in the current path causes extra voltage drops. These effects make embedding of phase change memories with the devices available in a logic process challenging.

According to an exemplary embodiment of the invention, a solution for embedding phase change memory as replacement of EEPROM, OTP or flash EPROM can be based on following concepts:

- Maximize in the write modes the voltage over the cell (almost supply voltage Vdd) by minimizing the bit line and ground line resistances (two or more shorted metal layers) and minimizing the number of column selection transistors (only one full CMOS switch with a pMOST to conduct the high current), and implement a data-in dependent selection transistor (one pMOST).

- Control the write time and the current via the word line selection voltage and timing. A short pulse of two voltages is applied to the selected word line. The highest one if a

RESET is needed and a lower one if a SET is needed. Mostly for the highest voltage an "overvoltage" may be appropriate.

- In the read mode the selected word line may be switched to Vdd but the bit line may be charged to a voltage lower than the threshold voltage of the chalcogenide material.

Addition of level shifters in word line drivers may allow differentiating the SET and RESET conditions. A simplified current path for SET and RESET may reduce voltage losses. By taking these measures, achievable advantages are that operation at lower voltages and the program conditions may be realized with voltage switching which may have less overhead in the periphery and may be more suitable for embedded applications.

Thus, a phase change memory may be provided, such as a chalcogenide RAM, in which input data dependent voltage limiters are used within the write paths in conjunction with a pulsed signal such that in a RESET operation, most of the available voltage is over the resistor and in a SET operation the voltage over the high ohmic resistor is larger than a material dependent voltage and, in the low ohmic condition, a crystallization current which is smaller than the melt current freezes the state. Data dependent voltage limiters may be used in the write path thus resulting in a system in which only the voltages have to be switched.

Next, further exemplary embodiments of the electronic component will be explained. However, these embodiments also apply to the method of operating an electronic component.

The electric conversion signal may be the same for converting the convertible structure from a crystalline state into an amorphous state and for converting the convertible structure from an amorphous state into a crystalline state. Thus, it may be sufficient, as electric conversion signal, to use a single common programming signal, wherein in the context of a phase change material as the convertible structure, the decision whether a SET of RESET pulse is applied does not have to be taken necessarily by varying the electric conversion signal, but by varying an electric resistance of the controllable selection resistance, i.e. by a signal applied via a word line. The signal source may be adapted for sampling a present state of the convertible structure by supplying an electric sampling signal to the convertible structure and by detecting a response signal indicative of the present state of the convertible structure. Therefore, not only a programming signal is provided by the signal source, but also a reading signal may be applied via the same signal source. Such a reading signal may differ from the electric conversion signal, for instance may be smaller in amplitude to prevent undesired phase change triggered by a read signal. The response signal may then depend on the actual state of the convertible structure, thereby allowing recovering or reconstructing the encoded information stored in the memory cell on the basis of such a response signal. The controllable selection resistance may be electrically coupled between the convertible structure and an electric reference potential. The controllable selection resistance and the convertible structure may be serially connected so that a voltage applied between the controllable selection resistance and the convertible structure is partially dropped at the controllable selection resistance, and is partially dropped at the convertible structure (in dependence of the individual resistance values). For example, the electric reference potential may be an electric ground potential. The controllable selection resistance such as a gate controlled selection transistor may be sandwiched between the convertible structure and a terminal to the electric reference potential. For example, in a memory array architecture, each memory cell may have such an arrangement of controllable selection resistance, convertible structure and electric reference potential coupled to a bit line, whereas a gate of a selection transistor as the controllable selection resistance may be coupled to a word line. By such architecture, by adjusting the present conductivity of the controllable selection resistance between different values, it is possible to locally adjust the writing status of the corresponding memory cell, using a global programming signal. The controllable selection resistance may be a switch, a transistor, a field effect transistor, a bipolar transistor, a FinFet, a diode, or an ohmic resistance having an adjustable value. A preferred embodiment may use a transistor having source/drain regions connected between the convertible structure and the ground potential, wherein a gate is used for adjusting the variable resistance value. The control unit may be adapted for controlling the electric resistance value of the controllable selection resistance in such a manner that the convertible structure is heated above a melting point for bringing the convertible structure in an amorphous state (this may be denoted as a RESET mode). Thus, the resistance value of the controllable selection resistance may be reduced to such a value that a sufficient current flows through the convertible structure that a so-called RESET pulse applied. Such a pulse is sufficiently intense and sufficiently short to bring the convertible structure such as a phase change material in the amorphous state. The control unit may further be adapted for controlling the electric resistance value of the controllable selection resistance in such a manner that the convertible structure is maintained below the melting point but is made subject to an electric voltage exceeding a material dependent threshold voltage for bringing the convertible structure in a crystalline state (this may be denoted as a SET mode). Thus, the electric current flowing through the convertible structure may be controlled such that the melting temperature of the convertible material is not reached, but a threshold voltage value being characteristic for the convertible material is reached, which drives (particularly when a corresponding pulse is sufficiently long in time) the convertible material into a crystalline state.

Particularly, the controllable selection resistance may be a selection transistor having a source/drain terminal which is electrically coupled to the convertible structure and having a gate terminal which is electrically coupled to the control unit so that the electric resistance value is controllable by a control signal supplyable to the gate terminal to thereby define into which of the at least two states the convertible structure is converted. In other words, the control signal applied to the gate terminal of the transistor regulates conductivity of a channel region by the field effect. Thus, the electric resistance of a field effect transistor may be adjusted by the control signal. By taking this measure, assuming a fixed programming voltage, it may be controlled whether the convertible structure receives sufficient energy to be brought in the amorphous state or less energy to be brought in a crystalline state.

The convertible structure may form a thermo-dependent structure, particularly a phase change structure which is convertible between at least two phase states. Thus, under the influence of heat which may be generated by ohmic losses of a programming current flowing through the phase change structure and/or electrodes connected thereto, the switch between the two phases can be initiated.

Particularly, the phase change structure may be adapted such that a value of the electrical conductivity differs between the two phase states. In one of the at least two phase states, the phase change structure may be electrically conductive (for instance essentially metallically conductive). In the other phase state, the electrical conductivity may be larger or lower than in the first state, for instance the phase change structure may be superconductive or may be semiconductive or may be isolating or may be conductive as well with a modified value of conductivity . In a normal operation of the electronic component, the function of the electronic component will be influenced, will be defined or will depend on the present value of the electrical conductivity of the phase change structure. This may allow manufacturing memory cells, switches, actuators, sensors, etc. using the different value of the electrical conductivity of the phase change structure in the different phase modes.

A current pulse or a current signal may generate heat in a convertible material to thereby change its phase state and consequently its value of the electrical conductivity. The applied current pulses may have a certain shape (for instance may have a fast raising edge and a slow falling edge, or may have a raising edge which is curved to the right and a falling edge which is curved to the left) and may be characterized by different parameters (such as current amplitude, pulse duration, etc.). By adjusting the pulse parameters, it is possible to control whether the phase change material is converted into a crystalline phase or is converted into an amorphous phase. Very high internal temperatures with rapid cooling down may result in an amorphous phase. A smaller increase in temperature or slower cooling down may lead to a crystalline phase.

The phase change structure may be adapted such that one of the two phase states relates to a crystalline phase and the other one of the two phase states relates to an amorphous phase of the phase change structure. Such a material property can be found in chalcogenide materials. A chalcogenide glass may be used which is a glass containing a chalcogenide element (sulphur, selenium or tellurium) as a substantial constituent. Examples for phase change materials are GeSbTe, AgInSbTe, InSe, SbSe, SbTe, InSbSe, InSbTe, GeSbSe, GeSbTeSe or AgInSbSeTe.

The electronic component may be adapted as a memory device. In such a memory device, the information of one or more bits may be stored in the present phase of the phase change material, particularly depending on the present one of two or more resistivity levels in the phase change structure.

The electronic component may also be adapted as a memory array, that is a configuration of a (large) plurality of memory devices of the aforementioned type. In such a memory array, the memory cells may be arranged in a matrix- like manner and may be controlled via bit lines and word lines with transistors serving as gradually changeable switches to get or prevent access to desired individual memory cells and memory devices. The multiple memory cells may be monolithically integrated in a common (for instance silicon) substrate.

The electronic component may also serve as an actuator, since a change of the electrical conductivity of the phase change structure may result in a modification of an actuation signal. It is also possible to adapt the electronic component as a microelectromechanical structure (MEMS). An electrical signal modified by a phase change of the convertible material may result in a specific motion of a movable component of the microelectromechanical structure (MEMS).

It is clear that the modification of the phase change material, and therefore of its electrical conductivity, may be used to construct controllers, switches, transductors, etc. As an example, the low resistance value of the phase change material can be about 1.5 kOhm, with a high resistive level of more than 100 kOhm. The melting temperature can be reached with a current of about 500 μA, while the crystallization current may be about 250 μA with a switching threshold voltage level of just below IV. An exemplary RESET and SET time may be between 10 ns and 100 ns. Fast reading can be performed with a cell current of about 50 μA. For embedded applications, it is possible to use a nominal supply voltage Vaa =1.2 V, but a 2.5V IO supply (and corresponding transistors) can be possible as well.

The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in more detail hereinafter with reference to examples of embodiment but to which the invention is not limited. Fig. 1 illustrates a memory cell according to an exemplary embodiment of the invention.

Fig. 2 illustrates a memory array according to an exemplary embodiment of the invention.

Fig. 3 shows a diagram illustrating an electric conversion signal and a control signal being applied for programming or reading a memory cell according to an exemplary embodiment of the invention.

Fig. 4 illustrates a resistor level of the convertible structure on the basis of the programming and reading that is shown in Fig. 3. Fig. 5 illustrates a level of an electric current flowing through the convertible structure upon application of the voltage levels of Fig. 3.

Fig. 6 illustrates a memory array having a level shifter for word lines according to an exemplary embodiment of the invention. Fig. 7 illustrates a write path to a bit line of a memory array according to an exemplary embodiment of the invention.

DESCRIPTION OF EMBODIMENTS

The illustration in the drawing is schematical. In different drawings, similar or identical elements are provided with the same reference signs.

A non- volatile memory considered as a potential successor of flash memory when this does not scale any more uses a resistor made from some chalcogenide material to store the data. The resistor is programmed via the transition of the materials phase. Therefore this memory type is mostly referred to as phase change memory. The memory cell comprises a switching (selecting) element and a resistor. The material in the resistor can be brought from crystalline to amorphous or vice versa by heating. This can be done by forcing a current through the resistor. This material may be an alloy of Germanium, Antimony and Tellurium. The most common names for this memory are CRAM (Chalcogenide RAM), PCM (phase change memory), PRAM (Phase-change RAM) or OUM (Ovonyx unified memory). The switching element can be a bipolar transistor or a diode or a MOS transistor. For an application embedded in a CMOS process, a nMOST is a preferred switching (selecting) element.

To switch the resistor from low ohmic (crystalline state) to high ohmic (amorphous state) a current, large enough to locally melt the resistor material, is forced through the resistor and during the fast cooling the melted material becomes amorphous resulting in a high ohmic resistor ("RESET" operation). To switch the resistor from high ohmic to low ohmic values a voltage larger than a material dependent threshold voltage has to be applied over the high ohmic resistor to bring it to a low ohmic state and some current need to flow to heat the material and let it crystallize. This current needs to be lower than in the one in the RESET operation to avoid melting of the material ("SET" operation). For reading a voltage lower than the material's threshold voltage of the SET mode can be forced over the resistor and the current can be sensed to determined if a one (low resistor) or a zero (high resistor) was stored in the cell. Maintaining these three discrete conditions within the matrix of a memory module and assuring that the needed actions can be performed at the low voltage and in a short time (1 ns to tens of ns) and only for the selected memory cells, is quite challenging. According to an exemplary embodiment of the invention, a memory architecture, meeting all requirements without the need of accurate switching circuitry for high currents is provided.

In contrast to stand-alone memory processes, processes for logic are mostly optimized for lower supply voltages. Further to RESET the phase change material some heat is needed to locally melt it. This is achieved by forcing a relative large current (100 μA to 1 mA) through the resistor and the cell selection MOST. To reach this, most of the voltage available for the RESET needs to be over the resistor. In the SET operation the voltage over the high ohmic resistor needs to be larger than a material dependent voltage and in the subsequent low ohmic condition, crystallization current has to freeze the state. This current needs to be smaller than the melt current. These two conditions can be realized by adding input data dependent current limiters in the write paths. These circuitry components cause some voltage drops. Furthermore, the on chip generation of a voltage larger than the supply voltage that can deliver sufficient current to write a number of cells in parallel will be expensive in area. Alternatively, the normal supply voltage can be forced over the memory cell while the current through the cell can be controlled via the cell selection transistor. To avoid excessive voltage drops outside the cell all the connections and selecting devices (CMOS switches to allow passing the full supply voltage) in the current path have to be designed for small or minimal resistance.

Commonly, a memory array comprises a number of rows and a number of columns. Only one row can be selected at the same time. The number of selected columns mostly equals the number of bits in an internal word (number of sense amplifiers and data input buffers). In this case, the row connects all the gates of the selection device, which can connect one terminal of the memory resistor to ground, in a row. The bit line connects the second terminal of the resistor in a column and can be switched to sensing and data input circuitry. The non-selected bit lines are kept to ground level.

Since all selection devices in a selected row are on and since different conditions are needed for RESET and SET, in this configuration it is impossible to switch in the same cycle one bit from high to low and another from low to high. Here the concept as in EEPROM or flash memory is applicable: first bring all bits in a word to the same state (erase operation), and in another cycle modify the needed cells according to the input data (write operation). The erase before write can be implemented automatically (mostly as in EEPROM) or under "external" control (via a memory controller) to allow erase of a portion of the memory prior to usage. Since both state transitions (SET or RESET) can be done very quickly, either state can be chosen as the erased state. Assume that after an erase or SET operation all resistors in the selected bits are low ohmic, what corresponds with the storage of an all 1 word. This can be reached by designing the cell resistance (material and shape) and select transistor in such way that with the supply voltage forced to all the selected bit lines and with the selected row pulsed for a short time to a first voltage level (for instance the supply voltage) the current through each cell stays below the melting current but above the crystallization current. The time of this operation is set by the width of the row select pulse. In case of a cell with a low ohmic resistor the voltage will be divided over the select transistor (with low drive strength) and the resistor and the current will stay below the melting one. Hence the low ohmic state does not change. In case of a high ohmic resistor, the voltage over the resistor will increase until the material threshold (below the supply voltage) and then switch to the low ohmic state keeping the current also below the melting one. The low ohmic state will be frozen in the cell. For writing an erased word, only the zero's need to cause a change in the cell state. So only these selected bit lines are forced to the supply voltage, the other ones are kept at ground level. The selected row is now pulsed to a second voltage level that is higher than the previous one (for instance twice the supply voltage). The drive strength of the select transistor is now much higher and only a small voltage will be over the transistor and the largest part over the low ohmic resistor. The current through the cell has to exceed the melting current. After a quick cooling down (switching off selected row) the resistor ends in a high ohmic state (corresponding to a zero). For the detection of the state stored in a cell, a small voltage (much smaller than the material threshold voltage) is forced to the selected bit line while the selected row is pulsed to the supply voltage. When the bit line current is below a certain fixed value a zero is stored in the cell and when the current is above the value a one is stored in the cell. With these conditions the selected cell will not change state and keep its stored data.

With this architecture only voltages have to be switched and the higher voltage for the RESET operation can be easily generated on chip or derived from the higher IO voltage that is available in most system-on-chip (SOC) structures.

In the following, referring to Fig. 1, a memory cell 100 according to an exemplary embodiment of the invention will be explained. The memory cell 100 comprises a phase change material structure 102 (made of a chalcogenide material) which is convertible between two states by heating and which has different electrical properties in different ones of the two states, namely a low ohmic crystalline state and a high ohmic amorphous state. A signal source 104 is provided and adapted for triggering conversion of the phase change material structure 102 between the crystalline and the amorphous state by supplying an electric conversion signal 112 (a current or voltage pulse) travelling on a connection line between the signal source 104 and the phase change material structure 102.

Furthermore, the memory cell 100 comprises a controllable selection resistance 106 such as a transistor which is serially coupled to the phase change material structure 102, i.e. is directly connected thereto and which is adapted for controlling an electric current value flowing through the phase change material structure 102 upon application of the electric conversion signal 112. A control unit 108, such as a CPU (central processing unit) or a microprocessor, is provided and adapted for controlling a value of the ohmic resistance of the controllable selection resistance 106 to thereby define whether the phase change material structure 102 is brought into the crystalline state or into the amorphous state upon application of the electric conversion signal 112. For that purpose, the control unit 108 is capable of sending an electric control signal 114 to the controllable selection resistance 106. In an embodiment in which the controllable selection resistance 106 is a transistor, the control signal 114 may be applied to the gate of the transistor, whereas the electric conversion voltage signal 112 may be applied, after having passed the phase change material structure 102, to a first source/drain region of the selection transistor. A second source/drain region of the selection transistor may be coupled to an electric ground potential 110. As can be taken from Fig. 1, the control unit 108 is also capable of optionally controlling the signal source 104 via a control loop 116. The control unit 108 and the signal source 104 may be two separate entities, or a single common entity.

As will be explained in the following, the amplitude of the electric conversion voltage signal 112 can be the same (in an alternative embodiment it may also be different) for converting the phase change material structure 102 from a crystalline state into an amorphous state and for converting the phase change material structure 102 from an amorphous state into a crystalline state. The information whether the phase change material structure 102 is to be brought into the crystalline state or into the amorphous state is provided by the modulating impact of the control signal 114 generated by the control unit 108 and applied to change the ohmic resistance of the controllable selection resistance 106.

The signal source 104 can also contribute to read out information stored in the phase change material structure 102. For example, the logical value "0" may be encoded with the phase change material structure 102 being in a high ohmic amorphous state. In contrast to this, a logic value "1" can be identified with the phase change material structure 102 being in the low ohmic crystalline state. To determine which state the phase change material structure 102 presently assumes, the signal source 104 may apply a low amplitude electric sampling signal to the phase change material structure 102 and may detect a response signal indicative of the present state of the phase change material structure 102 (not shown in Fig. 1). Particularly, assuming a defined and constant read signal applied by the control unit 108 to the controllable selection resistance 106, and assuming a constant sampling signal applied by the signal source 104, a current to be detected which flows through the phase change material structure 102 is larger in the crystalline state than in the amorphous state, thereby allowing to reconstruct the encoded information. Coming back to the programming procedure, the control unit 108 is adapted for controlling the electric resistance value of the controllable selection resistance 106 in such a manner that the phase change material structure 102 is heated above a melting point for bringing the phase change material structure 102 in an amorphous state. For such a RESET pulse, a sufficiently intensive programming signal being followed by a sufficiently fast cooling procedure may be appropriate.

Furthermore, the control unit 108 is adapted for controlling the electric resistance value of the controllable selection resistance 106 in such a manner that the phase change material structure 102 is maintained below the melting point but initially is made subject to an electric voltage exceeding a material dependent threshold voltage for bringing the phase change material structure 102 in a crystalline state. Such a so-called SET pulse may require a smaller amplitude as in the case of a RESET pulse, but a slower cooling procedure, to result in a crystalline lattice configuration. Thus, it may be appropriate to vary the signal duration of such a programming pulse in dependence on whether a crystalline state or an amorphous state shall be adjusted. For a crystalline state, the duration may be larger than for an amorphous state.

Fig. 2 illustrates a memory array 200 according to an exemplary embodiment of the invention.

The memory array 200 comprises a plurality of memory cells according to exemplary embodiments, each having a phase change material structure 102 and a selection transistor 106. The matrix-like arrangement 200 comprises a number of bit lines 202. Furthermore, a plurality of word lines 204 are provided which are aligned perpendicular to the bit lines 202. Each word line 204 is electrically coupled to a gate terminal 206 of the respective selection transistor 106. Each of the bit lines 202 is coupled to a respective column of memory cells, more particularly is coupled with a first terminal of the respective phase change material structure 102. The other terminal of the respective phase change material structure 102 is coupled to a first source/drain terminal 208 of the respective selection transistor 106, and a second source/drain region 210 of the respective selection transistor 106 is coupled to the electric ground potential 110.

The word lines 204 are coupled to a corresponding row decoder (not shown), fulfilling the function of the control unit 108 of Fig. 1. The bit lines 202 are coupled to corresponding column decoder (not shown), which fulfils the function of the signal source 104 of Fig. 1. Thus, Fig. 2 shows a part of the memory matrix 200 which can be driven with signals, which are indicated in the timing diagrams 300, 400, 500 shown in Fig. 3, Fig. 4, and Fig. 5. The timing diagrams 300, 400, 500 are indicative of the function, but are not to scale. They show the signals applied to a selected cell, i,i.

Fig. 3 illustrates a diagram 300 for operating a memory cell of the memory arrangement 200 according to an exemplary embodiment of the invention.

The diagram 300 comprises an abscissa 302 along which the time is plotted in arbitrary units. Along an ordinate 304, the voltage level applied to the word lines 204 or the bit lines 202 are plotted in arbitrary units. More particularly, operation signals 306 indicate signals applied to the word lines 204. Control pulses 308 are pulses, which are applied at the respective time to the bit lines 202.

Fig. 4 illustrates a diagram 400 having an abscissa 302 along which a time is plotted in arbitrary unit and which matches to the abscissa 302 of Fig. 3. Along an ordinate 402, a resistor level of the phase change material structure 102 of the respective memory cell is plotted as a curve 402. Furthermore, Fig. 5 illustrates a diagram 500 having an abscissa 302 along which the time is plotted in arbitrary unit and which matches to the abscissa 302 of Fig. 3 and of Fig. 4. Along an ordinate 502, a cell current is shown flowing through the phase change material structure 102 upon application of the respective signals of Fig. 3. Fig. 5 shows a first read operation 504, a RESET operation 506, a second read operation 508, a SET operation 510, and a third read operation 512.

Fig. 3 to Fig. 5 relate to selected memory cells. Non-selected word lines 204 or bit lines 202 are at a ground level 110. As can be taken from Fig. 3, the voltage 308 applied to the bit line 202 for performing the RESET operation 506 and performing the SET operation 510 is identical. Thus, for programming, regardless whether the phase change material structure 102 is to be brought in the crystalline state (SET) or in the amorphous state (RESET), the corresponding bit line voltage 308 is the same. In contrast to this, the determination whether the programming results in an amorphous phase change material structure 102 or in a crystalline phase change material structure 102 is taken by the voltage 306 applied to the word lines and from there to the gate 206 of the respective selection transistor 106. During the RESET performance 506, the voltage 306 can be about twice the voltage 308, whereas during the SET performance 510, the two voltages 306, 308 can be identical. For reading in the cycles 504, 508 or 512, the respective word line 204 is brought to a specific potential, and the respective bit line 202 is brought to a small voltage to provide a small amplitude sample signal.

Thus, it is not needed to provide a complex level shifter for the bit lines 202, resulting in a simple construction of the memory. According to an exemplary embodiment of the invention, instead of providing a level shifter for the bit lines 202, a level shifter may be provided for the word lines 204.

A corresponding architecture is illustrated in Fig. 6 illustrating a memory array 600 according to an exemplary embodiment of the invention.

Although not shown in Fig. 6, a plurality of matrix- like arranged memory cells are arranged in a memory matrix 602, in a manner similar to Fig. 2.

Moreover, a row decoder 604 is provided for providing row decoding signals. Between the row decoder and the memory matrix 602, a level shifter 606 is arranged for shifting the corresponding word line 204 signals to desired values.

A column decoder 608 provides column decoding signals. Fig. 7 illustrates a write path 700 to the bit line 202.

A bit line 202 is coupled to a first column selection transistor 702 and a complementary second column selection transistor 704. The column selection transistors 702, 704 serve for selecting a certain column of the memory matrix 602. For triggering read out of information stored in a memory cell, a corresponding read signal may be applied to a gate of a read transistor 706. For avoiding bus conflicts during programming, the read transistor 706 may be switched off during programming. A sense amplifier (not shown) may be coupled to a lower source/drain region of the read transistor 706. Furthermore, a pair of programming transistors 708, 710 are connected between a ground potential 110 and a supply voltage Vaa 712, thereby providing a programming signal to the bit line 202 indicative of a value of a data signal applied to the gate of the programming transistors 708, 710.

Finally, it should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. In a device claim enumerating several means, several of these means may be embodied by one and the same item of software or hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. An electronic component (100), the electronic component (100) comprising a convertible structure (102) being convertible between at least two states by heating and having different electrical properties in different ones of the at least two states; a signal source (104) adapted for triggering conversion of the convertible structure (102) between the at least two states by supplying an electric conversion signal to the convertible structure (102); a controllable selection resistance (106) electrically coupled to the convertible structure (102) and adapted for controlling an electric current value flowing through the convertible structure (102) upon application of the electric conversion signal; a control unit (108) adapted for controlling an electric resistance value of the controllable selection resistance (106) to thereby define into which of the at least two states the convertible structure (102) is converted upon application of the electric conversion signal.

2. The electronic component (100) according to claim 1, wherein the electric conversion signal, particularly an electric conversion voltage, is the same for converting the convertible structure (102) from a crystalline state into an amorphous state and for converting the convertible structure (102) from an amorphous state into a crystalline state.

3. The electronic component (100) according to claim 1, wherein the signal source (104) is adapted for sampling a present state of the convertible structure (102) by supplying an electric sampling signal to the convertible structure (102) and by detecting a response signal indicative of the present state of the convertible structure (102).

4. The electronic component (100) according to claim 1, wherein the controllable selection resistance (106) is electrically coupled between the convertible structure (102) and an electric reference potential (110), particularly an electric ground potential (110).

5. The electronic component (100) according to claim 1, wherein the controllable selection resistance (106) comprises one of the group consisting of a switch, a transistor, a field effect transistor, a bipolar transistor, a FinFet, a phase change material, and a diode.

6. The electronic component (100) according to claim 1, wherein, in a first programming mode, the control unit (108) is adapted for adjusting the electric resistance value of the controllable selection resistance (106) in such a manner that the convertible structure (102) is heated above a melting point for bringing the convertible structure (102) in an amorphous state.

7. The electronic component (100) according to claim 6, wherein, in a second programming mode, the control unit (108) is adapted for adjusting the electric resistance value of the controllable selection resistance (106) in such a manner that the convertible structure (102) is maintained below the melting point but initially is made subject to an electric voltage exceeding a material dependent threshold value for bringing the convertible structure (102) in a crystalline state.

8. The electronic component (100) according to claim 1, wherein the controllable selection resistance (106) is a selection transistor having a source/drain terminal which is electrically coupled to the convertible structure (102) and having a gate terminal which is electrically coupled to the control unit (108) so that the electric resistance value is controllable by a control signal supplyable to the gate terminal to thereby define into which of the at least two states the convertible structure (102) is converted.

9. The electronic component (100) according to claim 1, wherein the convertible structure (102) is a thermo-dependent structure, particularly a phase change structure which is convertible between at least two phase states.

10. The electronic component (100) according to claim 1, wherein the convertible structure (102) is electrically conductive in at least one in the at least two states.

11. The electronic component (100) according to claim 1, wherein the convertible structure (102) is adapted such that a value of the electrical conductivity differs between the at least two states.

12. The electronic component (100) according to claim 1, wherein the convertible structure (102) is adapted such that one of the at least two states relates to a crystalline phase of the convertible structure (102) and another one of the at least two states relates to an amorphous phase of the convertible structure (102).

13. The electronic component (100) according to claim 1, adapted as one of the group consisting of a memory device, a memory array, an actuator, a microelectromechanical structure, a controller, a controllable logic element, and a switch.

14. An electronic array (200), comprising a plurality of electronic components (100) according to claim 1 arranged in rows and columns; a plurality of bit lines (202) each adapted for coupling a signal source (104) to convertible structures (102) of a respective column of electronic components (100); a plurality of word lines (204) each adapted for coupling a control unit (108) to controllable selection resistances (106) of a respective row of electronic components (100).

15. A method of operating an electronic component (100), the method comprising triggering conversion of a convertible structure (102) of the electronic component (100) being convertible between at least two states by heating and having different electrical properties in different ones of the at least two states by supplying an electric conversion signal to the convertible structure (102); controlling an electric resistance value of a controllable selection resistance

(106) of the electronic component (100) electrically coupled to the convertible structure (102) for controlling an electric current value flowing through the convertible structure (102) upon application of the electric conversion signal to thereby define into which of the at least two states the convertible structure (102) is converted upon application of the electric conversion signal.