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WO2009116202A1 - Mounted board, mounted board set, and panel unit - Google Patents

Mounted board, mounted board set, and panel unit Download PDF

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Publication number
WO2009116202A1
WO2009116202A1 PCT/JP2008/070383 JP2008070383W WO2009116202A1 WO 2009116202 A1 WO2009116202 A1 WO 2009116202A1 JP 2008070383 W JP2008070383 W JP 2008070383W WO 2009116202 A1 WO2009116202 A1 WO 2009116202A1
Authority
WO
WIPO (PCT)
Prior art keywords
mounting
circuit element
corner
wiring
area
Prior art date
Application number
PCT/JP2008/070383
Other languages
French (fr)
Japanese (ja)
Inventor
裕喜 中濱
稲田　紀世史
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to US12/933,159 priority Critical patent/US20110019125A1/en
Priority to CN2008801278657A priority patent/CN101960587B/en
Publication of WO2009116202A1 publication Critical patent/WO2009116202A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01005—Boron [B]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2009—Reinforced areas, e.g. for a specific part of a flexible printed circuit

Definitions

  • the present invention relates to a mounting board set that is a mounting board on which a mounting board, circuit elements, and the like are mounted, and a panel unit that is a panel (liquid crystal display panel or the like) including the mounting board set.
  • the mounting substrate 111 (specifically, the base of the mounting substrate 111 and The main substrate 112) is subjected to plastic deformation. More specifically, the inverted U-shaped wall 151 is formed in a partial region of the main board 112 around the circuit element 121.
  • a circuit generated in the mounting substrate 111 that does not include the inverted U-shaped wall 151 as shown in FIGS. 11A and 11B (a cross-sectional view taken along line aa ′ in FIG. 11A).
  • the element 121 is peeled off, for example, the corner of the circuit element 121 where the fillet 152 of the adhesive 131 is difficult to be formed is not peeled off from the mounting substrate 111 (note that an arrow f in the figure means a load).
  • the mounting substrate 111 as described in Patent Document 1 requires a step of plastic deformation, and is limited to a material that can be plastically deformed. Therefore, the manufacturing process of the mounting substrate 111 is troublesome, and a highly versatile material cannot be used for the mounting substrate 111 (the cost of the mounting substrate 111 may increase due to the material cost).
  • the bump 122 is preferably connected to a wiring (not shown) included in the mounting substrate 111, and the wiring is preferably covered with a solder resist film.
  • the mounting surface 112 ⁇ / b> A of the mounting substrate 111 has the inverted U-shaped wall portion 151, it also becomes a cause of peeling and breaking of the solder resist film.
  • the present invention has been made in view of the above situation.
  • the object of the present invention is, when a circuit element is mounted, a simple mounting board that prevents the circuit element from peeling from the mounting board, and a mounting board set that is completed by mounting the circuit element on the mounting board,
  • Another object of the present invention is to provide a panel set in which the mounting board set and a liquid crystal display panel are connected.
  • a mounting board including a supply wiring for supplying current to a circuit element
  • the mounting surface area of the mounting board that overlaps the circuit element to be mounted is defined as a mounting area
  • at least the mounting surface and the non-mounting surface that is the back surface of the mounting surface Reinforcing wiring that overlaps the corner of the mounting area is formed on one surface.
  • the corner of the circuit element overlaps the corner of the mounting area. Therefore, if the vicinity of the corner of the mounting area is bent, the corner of the circuit element may be peeled off from the mounting substrate due to the bending.
  • the reinforcing wiring is positioned so as to overlap with the corner of the mounting area, the vicinity of the corner of the mounting area increases in rigidity and does not bend. Therefore, with such a mounting substrate, even if the circuit element is mounted, the corners of the circuit element are not peeled off from the mounting substrate.
  • the reinforcing wiring advance from the corner of the mounting area to the outside of the mounting area.
  • the bent portion of the mounting board is outside the mounting area where no reinforcing wiring exists. Therefore, the corners of the mounting area are surely not bent, and even if the circuit elements are mounted on the mounting board, the corners of the circuit elements are not peeled off from the mounting board.
  • the mounting substrate satisfy the following conditional expression (1) by extending a line that bisects the angle at the corner of the mounting region to a virtual bisector. 0 ⁇ L / D ⁇ 30 Conditional expression (1)
  • L The longest length from one end of the virtual bisector that overlaps the corner of the mounting area to the outside of the mounting area and overlaps the virtual bisector and reaches the edge of the reinforcing wiring
  • D Reinforcement It is the thickness of the wiring.
  • a region for mounting circuit elements (mounting region) must be ensured with high accuracy.
  • a solder resist film (first protection) by photolithography capable of forming a film with high accuracy Film) is formed.
  • the non-mounting surface does not require film forming accuracy as high as the mounting surface, and thus, for example, a highly rigid cover lay film (second protective film) is formed which is superior to the solder resist film. .
  • a protective film that covers at least the supply wiring on the mounting surface is a first protective film (solder resist film, etc.), and a protective film that covers at least the supply wiring on the non-mounting surface is a second protective film (coverlay film, etc.).
  • a line that bisects the angle at the corner is extended into a virtual bisector. Then, in the mounting substrate, the shortest distance between one end of the reinforcing wiring that overlaps the virtual bisector and one end of the second protective film that overlaps the virtual bisector is the main substrate that is the base of the mounting substrate and the first protective film. It is desirable to form only with.
  • the mounting board can be prevented from bending the mounting area in itself.
  • one end that overlaps the bump of the circuit element in the mounting area is set as an electrode overlapping point, and a group of a plurality of electrode overlapping points is set as an electrode overlapping point group, and a line that bisects the angle at the corner of the mounting area is extended.
  • Reinforcement wiring when a virtual bisector is used, and a line connecting the electrode overlap points adjacent to each other at the shortest distance between the virtual bisectors at the outermost electrode overlap point in the electrode overlap point group It is desirable to advance from the corner of the mounting area to the inside and beyond the boundary line.
  • the reinforcing wiring extends to the center of the mounting area. Therefore, the inside of the mounting area on the mounting substrate is not reliably bent due to the presence of the reinforcing wiring.
  • the reinforcing wiring may also serve as the supply wiring. In such a case, even if the bumps of the circuit elements are relatively large and the bump arrangement pitch is narrow, the area of the reinforcing wiring increases.
  • an adhesive is interposed between the circuit element and the mounting area. If it becomes like this, a mounting area
  • a mounting board set including the above mounting board and a circuit element mounted on the mounting board can also be said to be the present invention.
  • the bump included in the circuit element is a mounting board set connected to the supply wiring connected to the electrode overlapping point, a part of the supply wiring connected to the circuit element is not bent due to the presence of the reinforcing wiring. As a result, peeling between the bumps of the circuit element and the supply wiring is prevented.
  • a panel unit including the above mounting board set and a liquid crystal display panel connected to the mounting board set can also be said to be the present invention.
  • FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 2.
  • FIG. 3 is a cross-sectional view taken along line B-B ′ of FIG. 2.
  • FIG. 3 is a plan view showing bumps of a circuit element.
  • FIG. 11 is a perspective view of a conventional mounting board set different from FIG. 10.
  • FIG. 11B is a cross-sectional view taken along the line a-a ′ of FIG. 11A.
  • Mounting board 12 Main board 13 Supply wiring 14 Connection wiring (supply wiring) 15 Solder resist film (first protective film) 16 Coverlay film (second protective film) 17 Reinforcing wiring MA Mounting area PP Corner of mounting area AA Open area IL Virtual bisecting line BL Boundary line WL Bending line 21 Circuit element 22 Bump 31 Adhesive PU Liquid crystal display panel ST Mounting board set UT Panel unit
  • FIG. 5 is a plan view showing a liquid crystal display panel PU built in an electronic device such as a mobile phone and a mounting board set ST connected to the liquid crystal display panel PU.
  • FIG. 2 is an enlarged plan view of the mounting board set ST.
  • There is a unit (a unit in which the liquid crystal display panel PU and the mounting substrate set ST are combined is referred to as a panel unit UT).
  • 3A and 3B are a cross-sectional view taken along line AA ′ and a cross-sectional view taken along line BB ′ in FIG. 2 (the line AA ′ is a virtual bisector described later). IL).
  • the mounting board set ST shown in these drawings includes various circuit elements 21 and a mounting board 11 on which the circuit elements 21 are mounted.
  • the circuit element 21 is an ACF (Anisotropic Conductive Film) or NCF (NCF). Mounted with adhesive 31 such as Non Conductive Film ⁇ .
  • FIG. 1 which is a plan view excluding the circuit element 21 is added to the above drawings, and the mounting substrate 11 will be described in detail.
  • the mounting substrate 11 includes a main substrate 12, a supply wiring 13, a connection wiring 14, a solder resist film (first protective film) 15, a coverlay film (second protective film) 16, and a reinforcing wiring 17.
  • the main board 12 is a member that becomes a base of the mounting board 11 and has flexibility. Therefore, the mounting board 11 including the main board 12 is also referred to as an FPC (Flexible Printed Circuits) board.
  • FPC Flexible Printed Circuits
  • substrate 12 a polyimide resin and PET (polyethylene terephthalate) are mentioned, for example.
  • the supply wiring 13 is connected to, for example, a bump (projection electrode) 22 included in the circuit element 21 and supplies a current from a power source (not shown) to the circuit element 21. Therefore, as shown in FIG. 3B, the bump 22 and the supply wiring 13 are connected.
  • the supply wiring 13 may be formed on at least one of the front surface (mounting surface) 12A and the back surface (non-mounting surface) 12B of the main substrate 12.
  • connection wiring 14 is a wiring formed on the back surface 12B of the main substrate 12, as shown in FIG. 3A, for example, and connects the supply wirings 13 to each other. Note that this connection wiring 14 also plays a role similar to that of the supply wiring 13 in that current is supplied to the circuit element 21, and thus can be said to be a kind of the supply wiring 13.
  • the solder resist film 15 is a resin film formed by photolithography, and protects the supply wiring 13 by covering the surface 12A of the main substrate 12 (more specifically, the solder resist film 15 is provided on the mounting surface 12A by the supply wiring 13). Covering at least).
  • the solder resist film 15 does not cover the entire surface 12A of the main substrate 12, but as shown in FIG. 1, a partial region (opening region) of the surface 12A on the main substrate 12 on which the circuit element 21 is scheduled to be mounted. AA) is not covered. For this reason, photolithography capable of patterning with high accuracy is used in order to secure a region not covered with the solder resist film 15.
  • the cover lay film 16 is a film that covers the wiring (the supply wiring 13 and the connection wiring 14 and the like) formed on the back surface 12B of the main substrate 12 (more specifically, the cover lay film 16 covers the connection wiring 14 on the non-mounting surface 12B. Cover at least the supply wiring 13). Therefore, the coverlay film 16 does not exist in a region where the wiring is not formed on the back surface 12B of the main substrate 12 (for example, a region of the back surface 12B immediately below the circuit element 21).
  • the cover lay film 16 is inferior to the solder resist film obtained by photolithography in patterning accuracy, but is higher in insulation and rigidity than the solder resist film 15.
  • the reinforcing wiring 17 prevents a part of the mounting substrate 11 from being bent, and determines a place where the mounting substrate 11 is bent. As an example, as shown in FIG. 1, the reinforcing wiring 17 overlaps the corner PP of the mounting area MA that is the area of the surface 12 ⁇ / b> A on the main substrate 12 that overlaps the circuit element 21. Specifically, the reinforcing wiring 17 advances from the corner PP of the mounting area MA to the outside of the mounting area MA.
  • the side that deviates from the mounting area MA is bent with the reinforcing wiring 17 as a boundary, not near the corner of the circuit element 21.
  • the reinforcing wiring 17 is positioned so as to overlap the corner of the circuit element 21 so that the vicinity of the corner of the circuit element 21 on the mounting substrate 11 can withstand the load F.
  • the reinforcing wiring 17 allows the partial region of the mounting board 11 to withstand the load F, so that the partial region of the mounting substrate 11 on the side deviating from the mounting region MA with respect to itself as a boundary. By the bend area.
  • the corner of the circuit element 21 is not peeled off from the mounting substrate 11 due to the load F. And if such peeling does not occur, the performance defect (for example, contact failure) of the circuit element 21 does not occur, and the quality as the mounting board set ST is improved.
  • the corners of the circuit elements 21 are peeled off from the mounting substrate 11 occupy most of the connection failures of the circuit elements 21 in the mounting substrate set ST (note that the fillet of the adhesive 31 is unlikely to occur at the corners of the circuit elements 21. (This is one reason why the corner of the circuit element 21 is peeled off from the mounting substrate 11). Therefore, if the corners of the circuit element 21 are not peeled off from the mounting substrate 11, the process defects are reduced, and the high-quality mounting substrate installation ST is used for a long time.
  • the shape of the reinforcing wiring 17 is not particularly limited.
  • it may be a square shape, or may be other polygonal shapes, circular shapes, linear shapes, net shapes, and detour shapes.
  • the mounting substrate 11 it is desirable that the following conditional expression (1) is satisfied.
  • This conditional expression (1) is from one end of the reinforcing wiring 17 that overlaps the corner PP of the mounting area MA to the outside of the mounting area MA and overlaps the virtual bisector IL and reaches the edge of the reinforcing wiring 17. Is standardized by the length of the thickness of the reinforcing wiring 17. Note that “L” in the figure indicates only the interval of + notation described below.
  • the reinforcing wiring 17 overlaps only inside the mounting area MA. Therefore, when the load F is applied to the mounting substrate 11, the mounting substrate 11 does not bend along the bending line WL (see FIG. 2), and the mounting substrate 11 can be bent near the corner of the circuit element 21. As a result, the corners of the circuit element 21 may be peeled off from the mounting substrate 11.
  • the mounting substrate 11 when the value of L / D exceeds the upper limit value, the length of the reinforcing wiring 17 overlapping the virtual bisector IL becomes excessively long, and the reinforcing wiring 17 itself is easily bent. Therefore, when the load F is applied to the mounting substrate 11, the mounting substrate 11 may be bent and the reinforcing wiring 17 may be bent. Then, one end of the reinforcing wiring 17 that overlaps the corner of the circuit element 21 (the corner PP of the mounting area MA) may be bent. If the reinforcing wiring 17 is bent in this way, the mounting board 11 is bent near the corner of the circuit element 21, and the corner of the circuit element 21 may be peeled off from the mounting board 11.
  • the mounting substrate 11 is not bent near the corner of the circuit element 21 and the corner of the circuit element 21 is not peeled off from the mounting substrate 11. As a result, the performance defect of the circuit element 21 does not occur, and the quality as the mounting board set ST is improved.
  • conditional expression (1a) that defines the following conditional ranges is satisfied. 0 ⁇ L / D ⁇ 20 Conditional expression (1a)
  • the shortest distance K between one end of the reinforcing wiring 17 that overlaps the virtual bisector IL and one end of the coverlay film 16 that overlaps the virtual bisector IL is the main substrate 12 and the solder. It is desirable to form only with the resist film 15.
  • the shortest distance K including two members (main substrate 12 and solder resist film 15) having relatively low rigidity is more easily bent than the distance L including relatively high rigidity reinforcing wiring 17. . Therefore, when the load F is applied to the mounting substrate 11, the interval L in the mounting substrate 11 is bent without bending the interval L in the mounting substrate 11. Therefore, the corners of the circuit element 21 are not reliably peeled off from the mounting substrate 11.
  • the reinforcing wiring 17 does not prevent only the corner of the circuit element 21 from being peeled off from the mounting substrate 11.
  • the reinforcing wiring 17 does not bend the inside of the mounting area MA in the mounting substrate 11 and reliably prevents the bumps 22 of the circuit element 21 and the supply wiring 13 from peeling off. .
  • the reinforcing wiring 17 has only to advance from the corner PP of the mounting area MA to the inside of the mounting area MA.
  • the reinforcing wiring 17 that has advanced to the inside of the mounting area MA extends toward the center of the mounting area MA. Therefore, the inside of the mounting area MA on the mounting substrate 11 is not bent due to the presence of the reinforcing wiring 17.
  • the reinforcing wiring 17 is more preferably inward from the corner PP of the mounting area MA and advanced beyond the boundary line BL.
  • the reinforcing wiring 17 extends further to the center side of the mounting area MA than the front end of the supply wiring 13. Therefore, the inside of the mounting area MA on the mounting substrate 11 is not further bent due to the presence of the reinforcing wiring 17.
  • the bumps 22 included in the circuit element 21 may be arranged in a grid as shown in FIG. Then, the electrode overlapping points BP of the mounting area MA corresponding to such circuit elements 21 are arranged in a grid pattern as shown in FIG.
  • the electrodes adjacent to each other with the virtual bisector IL sandwiched between them at the shortest distance A line connecting the overlapping points BP can be said to be a boundary line BL.
  • the boundary line BL is the outermost electrode at the grouped electrode overlapping point BP.
  • the line overlaps the electrode overlapping points BP that are adjacent to each other with the shortest distance between the virtual bisector IL.
  • FIG. 1, FIG. 6, and FIG. 8 are summarized, the following can be said. That is, a group of a plurality of electrode overlapping points BP is used as an electrode overlapping point group, and the reinforcing wiring 17 advances from the corner PP of the mounting area MA so as to overlap the shortest outer peripheral range in the electrode overlapping point group. If this is the case, the inside of the mounting area MA on the mounting substrate 11 is not reliably bent due to the presence of the reinforcing wiring 17.
  • the reinforcing wiring 17 overlaps the shortest outer peripheral range in the electrode overlapping point group while overlapping its corner with the virtual bisector IL. With this configuration, the interior of the mounting area MA near the corner of the circuit element 21 is not reliably bent due to the presence of the reinforcing wiring 17.
  • the reinforcing wiring 17 is formed on the mounting surface 12A of the mounting substrate 11, but is not limited thereto. That is, the supply wiring 17 may be formed on the non-mounting surface 12 ⁇ / b> B of the mounting substrate 11.
  • the bump 22 of the circuit element 21 may be connected to the reinforcing wiring 17. That is, the reinforcing wiring 17 may perform the same function as the supply wiring 13 (in short, the reinforcing wiring 17 may also serve as the supply wiring 13).
  • the reinforcing wiring 17 The area increases. For example, as shown in FIG. 8, when the electrode overlapping points BP of the mounting area MA are dense, it can be useful that the reinforcing line 17 also serves as the supply line 13.
  • the mounting area MA is connected to the circuit element 21 having a relatively high rigidity via the adhesive 31. Therefore, the mounting area MA on the mounting substrate 11 is not bent.
  • the mounting area MA is connected to the relatively high-rigidity circuit element 21 and the reinforcing wiring 17 via the adhesive 31.
  • the reinforcing wiring 17, the adhesive 31, and the circuit element 21 are stacked in this order on the mounting area MA, and a four-layer structure of the mounting area MA, the reinforcing wiring 17, the adhesive 31, and the circuit element 21 is formed. . Therefore, even if the load F is applied to the mounting substrate 11, the mounting area MA that is part of the multilayer structure is not bent.
  • liquid crystal display panel PU was mentioned as a panel, it is not limited to this.
  • it may be an organic EL (electroluminescence) panel or a plasma panel.

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Abstract

Disclosed is a mounted board (11) comprising a feed wire (13) for supplying a current to a circuit element (21). In this mounted board (11), when a region of a mounting surface (12A) of the mounted board (11) overlapping the circuit element (21) is defined as a mounting area (MA), a reinforcing wire (17) overlapping a corner (PP) of the mounting area (MA) is formed on the mounting surface (12A).

Description

実装基板、実装基板セット、およびパネルユニットMounting board, mounting board set, and panel unit
　本発明は、実装基板、回路素子等を実装した実装基板である実装基板セット、および、実装基板セットを備えるパネル（液晶表示パネル等）であるパネルユニットに関するものである。 The present invention relates to a mounting board set that is a mounting board on which a mounting board, circuit elements, and the like are mounted, and a panel unit that is a panel (liquid crystal display panel or the like) including the mounting board set.
　昨今の小型の電子機器、例えば、携帯電話等のモバイルツールでは、可撓性を有する実装基板が多用される。そして、このような実装基板には、種々の回路素子が接着剤を介して実装される。ただし、回路素子の実装された実装基板（実装基板セットとも称する）に対して負荷（応力）がかかる場合、それに起因して、回路素子が実装基板から剥離しやすい。 In recent small electronic devices such as mobile tools such as mobile phones, flexible mounting boards are often used. Various circuit elements are mounted on such a mounting substrate via an adhesive. However, when a load (stress) is applied to a mounting board on which circuit elements are mounted (also referred to as a mounting board set), the circuit elements are easily peeled from the mounting board.
　そこで、図１０の断面図に示すように、特許文献１に記載の回路素子１２１を実装した実装基板１１１では、回路素子１２１を囲むように、実装基板１１１（詳説すると、実装基板１１１の基体となる主基板１１２）に塑性変形加工が施される。詳説すると、逆Ｕ字型壁部１５１が、回路素子１２１周辺の主基板１１２の一部領域に作成される。 Therefore, as shown in the cross-sectional view of FIG. 10, in the mounting substrate 111 on which the circuit element 121 described in Patent Document 1 is mounted, the mounting substrate 111 (specifically, the base of the mounting substrate 111 and The main substrate 112) is subjected to plastic deformation. More specifically, the inverted U-shaped wall 151 is formed in a partial region of the main board 112 around the circuit element 121.
　このようになっていると、図１１Ａおよび図１１Ｂ（図１１Ａのａ－ａ’線矢視断面図）に示されるような、逆Ｕ字型壁部１５１を含まない実装基板１１１にて生じる回路素子１２１の剥離、例えば、接着剤１３１のフィレット１５２の形成されにくい回路素子１２１の隅が実装基板１１１から剥がれない（なお、図中の矢印ｆは負荷を意味する）。
特開２０００－３９３５号公報 In this case, a circuit generated in the mounting substrate 111 that does not include the inverted U-shaped wall 151 as shown in FIGS. 11A and 11B (a cross-sectional view taken along line aa ′ in FIG. 11A). The element 121 is peeled off, for example, the corner of the circuit element 121 where the fillet 152 of the adhesive 131 is difficult to be formed is not peeled off from the mounting substrate 111 (note that an arrow f in the figure means a load).
JP 2000-3935 A
　しかしながら、特許文献１に記載されるような実装基板１１１は、塑性変形させる工程を要し、さらに、塑性変形可能な材料に限定される。そのため、この実装基板１１１の製造工程は煩わしく、また、汎用性の高い材料が実装基板１１１に使用できない（材料費に起因して実装基板１１１のコストが高くなりかねない）。 However, the mounting substrate 111 as described in Patent Document 1 requires a step of plastic deformation, and is limited to a material that can be plastically deformed. Therefore, the manufacturing process of the mounting substrate 111 is troublesome, and a highly versatile material cannot be used for the mounting substrate 111 (the cost of the mounting substrate 111 may increase due to the material cost).
　また、図１０では図示されていないが、バンプ１２２は、実装基板１１１に含まれる配線（不図示）に接続され、その配線は、ソルダーレジスト膜で覆われると望ましい。しかしながら、実装基板１１１の実装面１１２Ａに逆Ｕ字型の壁部１５１が有ると、ソルダーレジスト膜の剥離および破断の一因にもなる。 Although not shown in FIG. 10, the bump 122 is preferably connected to a wiring (not shown) included in the mounting substrate 111, and the wiring is preferably covered with a solder resist film. However, if the mounting surface 112 </ b> A of the mounting substrate 111 has the inverted U-shaped wall portion 151, it also becomes a cause of peeling and breaking of the solder resist film.
　本発明は、上記の状況を鑑みてなされたものである。そして、本発明の目的は、回路素子を実装した場合、その回路素子の実装基板からの剥離を防止する簡易な実装基板、さらに、その実装基板に回路素子を実装して完成する実装基板セット、および、この実装基板セットと、液晶表示パネルとをつなげたパネルセットを提供することにある。 The present invention has been made in view of the above situation. The object of the present invention is, when a circuit element is mounted, a simple mounting board that prevents the circuit element from peeling from the mounting board, and a mounting board set that is completed by mounting the circuit element on the mounting board, Another object of the present invention is to provide a panel set in which the mounting board set and a liquid crystal display panel are connected.
　回路素子に対して電流供給する供給配線を含む実装基板では、実装される回路素子に重なる実装基板の実装面の領域を実装領域とすると、実装面および実装面の裏面である非実装面の少なくとも一方の面に、実装領域の隅に重なる補強配線が形成される。 In a mounting board including a supply wiring for supplying current to a circuit element, if the mounting surface area of the mounting board that overlaps the circuit element to be mounted is defined as a mounting area, at least the mounting surface and the non-mounting surface that is the back surface of the mounting surface Reinforcing wiring that overlaps the corner of the mounting area is formed on one surface.
　通常、実装基板に回路素子が実装されると、実装領域の隅には、回路素子の隅が重なる。そのため、実装領域の隅付近が曲がると、それに起因して、回路素子の隅が実装基板から剥離しかねない。しかし、補強配線が実装領域の隅に重なるように位置すると、実装領域の隅付近は、剛性を増して曲がらなくなる。そのため、このような実装基板であれば、回路素子が実装されたとしても、その回路素子の隅が実装基板から剥がれない。 Normally, when a circuit element is mounted on a mounting board, the corner of the circuit element overlaps the corner of the mounting area. Therefore, if the vicinity of the corner of the mounting area is bent, the corner of the circuit element may be peeled off from the mounting substrate due to the bending. However, if the reinforcing wiring is positioned so as to overlap with the corner of the mounting area, the vicinity of the corner of the mounting area increases in rigidity and does not bend. Therefore, with such a mounting substrate, even if the circuit element is mounted, the corners of the circuit element are not peeled off from the mounting substrate.
　なお、補強配線は、実装領域の隅から、実装領域の外側へと進出すると望ましい。このようになっていると、実装基板の曲がる箇所が、補強配線の存在しない実装領域の外側になる。そのため、確実に、実装領域の隅付近が曲がらず、実装基板に回路素子が実装されたとしても、その回路素子の隅が実装基板から剥がれない。 Note that it is desirable that the reinforcing wiring advance from the corner of the mounting area to the outside of the mounting area. In this case, the bent portion of the mounting board is outside the mounting area where no reinforcing wiring exists. Therefore, the corners of the mounting area are surely not bent, and even if the circuit elements are mounted on the mounting board, the corners of the circuit elements are not peeled off from the mounting board.
　また、実装領域の隅における角度を２等分する線を延ばして仮想２等分線とし、下記条件式（１）が満たされる実装基板であると望ましい。
　　０＜Ｌ／Ｄ≦３０　…　条件式（１）
　　　ただし、
　　　　　Ｌ　：実装領域の隅に重なる仮想２等分線の一端から、実装領域の外側に向
　　　　　　　　かい、かつ仮想２等分線に重なって、補強配線の縁に至るまでの最長
　　　　　　　　の長さ
　　　　　Ｄ　：補強配線の厚み長
　　　である。 Further, it is desirable that the mounting substrate satisfy the following conditional expression (1) by extending a line that bisects the angle at the corner of the mounting region to a virtual bisector.
0 <L / D ≦ 30 Conditional expression (1)
However,
L: The longest length from one end of the virtual bisector that overlaps the corner of the mounting area to the outside of the mounting area and overlaps the virtual bisector and reaches the edge of the reinforcing wiring D: Reinforcement It is the thickness of the wiring.
　回路素子が実装基板に実装された場合に、回路素子の隅が実装基板から剥離する一因としては、例えば、実装領域の隅にかかる負荷が挙げられる。すると、この負荷が実装領域の隅に伝達されぬように、補強配線が形成されるとよい。そのため、補強配線が、実装領域の隅にかかる仮想２等分線に沿って伝達される実装基板への負荷に耐えなくてはならない。そこで、補強配線が一定以上の剛性を有すべく、条件式（１）が満たされる。すなわち、一定以上の剛性を有すべく、補給配線は過剰に長くならない。 When the circuit element is mounted on the mounting board, one reason that the corner of the circuit element peels from the mounting board is, for example, a load applied to the corner of the mounting area. Then, it is preferable to form reinforcing wiring so that this load is not transmitted to the corner of the mounting area. For this reason, the reinforcing wiring must endure the load on the mounting board transmitted along the virtual bisector at the corner of the mounting area. Therefore, conditional expression (1) is satisfied so that the reinforcing wiring has a certain level of rigidity. That is, the supply wiring does not become excessively long so as to have a certain level of rigidity.
　ところで、通常、実装面では、回路素子を実装させるための領域（実装領域）が精度よく確保されなくてはならず、例えば、高精度で成膜可能なフォトリソグラフィーによるソルダーレジスト膜（第１保護膜）が形成される。一方で、非実装面には、実装面ほどの成膜精度は不要であるので、例えば、ソルダーレジスト膜よりも絶縁性に優れ、高剛性のカバーレイフィルム（第２保護膜）が形成される。 By the way, usually, on the mounting surface, a region for mounting circuit elements (mounting region) must be ensured with high accuracy. For example, a solder resist film (first protection) by photolithography capable of forming a film with high accuracy Film) is formed. On the other hand, the non-mounting surface does not require film forming accuracy as high as the mounting surface, and thus, for example, a highly rigid cover lay film (second protective film) is formed which is superior to the solder resist film. .
　そこで、実装面における供給配線を少なくとも覆う保護膜を第１保護膜（ソルダーレジスト膜等）、非実装面における供給配線を少なくとも覆う保護膜を第２保護膜（カバーレイフィルム等）とし、実装領域の隅における角度を２等分する線を延ばして仮想２等分線とする。すると、実装基板において、仮想２等分線に重なる補強配線の一端と仮想２等分線に重なる第２保護膜の一端との最短間隔は、実装基板の基体である主基板と第１保護膜とだけで形成されると望ましい。 Therefore, a protective film that covers at least the supply wiring on the mounting surface is a first protective film (solder resist film, etc.), and a protective film that covers at least the supply wiring on the non-mounting surface is a second protective film (coverlay film, etc.). A line that bisects the angle at the corner is extended into a virtual bisector. Then, in the mounting substrate, the shortest distance between one end of the reinforcing wiring that overlaps the virtual bisector and one end of the second protective film that overlaps the virtual bisector is the main substrate that is the base of the mounting substrate and the first protective film. It is desirable to form only with.
　このようになっていれば、実装領域の隅にかかる仮想２等分線に沿って伝達される実装基板への負荷で、比較的低剛性（可撓性の高い、屈曲性の高い）の実装基板の基体である主基板と第１保護膜とだけで形成される一部領域、すなわち、仮想２等分線に重なる補強配線の一端と仮想２等分線に重なる第２保護膜の一端との最短間隔を含む実装基板が曲がる。その結果、実装領域の隅付近が曲がらず、実装基板に回路素子が実装されたとしても、その回路素子の隅が実装基板から剥がれない。 If this is the case, mounting with a relatively low rigidity (high flexibility and high flexibility) with a load on the mounting board transmitted along a virtual bisector at the corner of the mounting area A partial region formed only by the main substrate, which is the base of the substrate, and the first protective film, that is, one end of the reinforcing wiring that overlaps the virtual bisector and one end of the second protective film that overlaps the virtual bisector The mounting board including the shortest interval is bent. As a result, the corner of the mounting area does not bend, and even if the circuit element is mounted on the mounting board, the corner of the circuit element does not peel from the mounting board.
　また、補強配線が、実装領域の隅から、実装領域の内側へと進出していれば、実装基板は、自身における実装領域の内部を曲げないようにもできる。 Also, if the reinforcing wiring has advanced from the corner of the mounting area to the inside of the mounting area, the mounting board can be prevented from bending the mounting area in itself.
　特に、実装領域にて回路素子のバンプに重なる一端を電極重畳点とするとともに、複数の電極重畳点の集まりを電極重畳点群とし、実装領域の隅における角度を２等分する線を延ばして仮想２等分線とし、電極重畳点群での最外の電極重畳点において、仮想２等分線を挟みかつ最短距離で隣り合う電極重畳点同士を結ぶ線を境界線とする場合、補強配線は、実装領域の隅から内側に向かい、境界線を越えて進出すると望ましい。 In particular, one end that overlaps the bump of the circuit element in the mounting area is set as an electrode overlapping point, and a group of a plurality of electrode overlapping points is set as an electrode overlapping point group, and a line that bisects the angle at the corner of the mounting area is extended. Reinforcement wiring when a virtual bisector is used, and a line connecting the electrode overlap points adjacent to each other at the shortest distance between the virtual bisectors at the outermost electrode overlap point in the electrode overlap point group It is desirable to advance from the corner of the mounting area to the inside and beyond the boundary line.
　このようになっていると、実装領域の中心側まで補強配線は延びる。そのため、実装基板における実装領域の内部が、補強配線の存在によって確実に曲がらない。 If this is the case, the reinforcing wiring extends to the center of the mounting area. Therefore, the inside of the mounting area on the mounting substrate is not reliably bent due to the presence of the reinforcing wiring.
　なお、補強配線が、供給配線も兼ねてもかまわない。このようになっていると、回路素子のバンプが比較的多く、バンプの配置ピッチが狭かったとしても、補強配線の面積が増大する。 Note that the reinforcing wiring may also serve as the supply wiring. In such a case, even if the bumps of the circuit elements are relatively large and the bump arrangement pitch is narrow, the area of the reinforcing wiring increases.
　また、回路素子と実装領域との間に接着剤が介在すると望ましい。このようになっていれば、実装領域が接着剤を介して高剛性の回路素子につながる。そのため、実装基板における実装領域が曲がらない。 Also, it is desirable that an adhesive is interposed between the circuit element and the mounting area. If it becomes like this, a mounting area | region will be connected to a highly rigid circuit element via an adhesive agent. Therefore, the mounting area on the mounting board is not bent.
　なお、以上の実装基板と、実装基板に実装された回路素子と、を含む実装基板セットも本発明といえる。 A mounting board set including the above mounting board and a circuit element mounted on the mounting board can also be said to be the present invention.
　また、回路素子に含まれるバンプが、電極重畳点につながる供給配線に接続される実装基板セットであれば、回路素子に接続した供給配線の一部分は、補強配線の存在によって曲がらない。その結果、回路素子のバンプと供給配線との剥離が防止される。 Also, if the bump included in the circuit element is a mounting board set connected to the supply wiring connected to the electrode overlapping point, a part of the supply wiring connected to the circuit element is not bent due to the presence of the reinforcing wiring. As a result, peeling between the bumps of the circuit element and the supply wiring is prevented.
　なお、以上の実装基板セットと、実装基板セットにつながる液晶表示パネルと、を含むパネルユニットも本発明といえる。 It should be noted that a panel unit including the above mounting board set and a liquid crystal display panel connected to the mounting board set can also be said to be the present invention.
　本発明の実装基板に回路素子が実装されたとしても、補強配線の存在によって、回路素子の隅付近における実装基板の一部領域が曲がらない。そのため、回路素子の隅が実装基板から剥がれない。 Even if the circuit element is mounted on the mounting board of the present invention, a part of the mounting board near the corner of the circuit element is not bent due to the presence of the reinforcing wiring. For this reason, the corners of the circuit element are not peeled off from the mounting substrate.
は、表面（実装面）からみた実装基板の平面図である。These are the top views of the mounting board | substrate seen from the surface (mounting surface). は、実装面からみた実装基板セットの平面図である。These are the top views of the mounting substrate set seen from the mounting surface. は、図２のＡ－Ａ’線矢視断面図である。FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 2. は、図２のＢ－Ｂ’線矢視断面図である。FIG. 3 is a cross-sectional view taken along line B-B ′ of FIG. 2. は、実装基板の曲がる状態を示す断面図である。These are sectional drawings which show the state which the mounting board | substrate bends. は、パネルユニットの平面図である。These are top views of a panel unit. は、図１とは異なる実装基板の平面図である。These are the top views of the mounting board | substrate different from FIG. は、回路素子のバンプを示す平面図である。FIG. 3 is a plan view showing bumps of a circuit element. は、図１および図６とは異なる実装基板の平面図である。These are the top views of the mounting board | substrate different from FIG. 1 and FIG. は、図２とは異なる実装基板セットの平面図である。These are the top views of the mounting substrate set different from FIG. は、従来の実装基板セットの断面図である。These are sectional drawings of the conventional mounting substrate set. は、図１０とは異なる従来の実装基板セットの斜視図である。FIG. 11 is a perspective view of a conventional mounting board set different from FIG. 10. は、図１１Ａのａ－ａ’線矢視断面図である。FIG. 11B is a cross-sectional view taken along the line a-a ′ of FIG. 11A.
符号の説明Explanation of symbols
　　　１１　　実装基板
　　　１２　　主基板
　　　１３　　供給配線
　　　１４　　連絡配線（供給配線）
　　　１５　　ソルダーレジスト膜（第１保護膜）
　　　１６　　カバーレイフィルム（第２保護膜）
　　　１７　　補強配線
　　　ＭＡ　　実装領域
　　　ＰＰ　　実装領域の隅
　　　ＡＡ　　開口領域
　　　ＩＬ　　仮想２等分線
　　　ＢＬ　　境界線
　　　ＷＬ　　屈曲線
　　　２１　　回路素子
　　　２２　　バンプ
　　　３１　　接着剤
　　　ＰＵ　　液晶表示パネル
　　　ＳＴ　　実装基板セット
　　　ＵＴ　　パネルユニット 11 Mounting board 12 Main board 13 Supply wiring 14 Connection wiring (supply wiring)
15 Solder resist film (first protective film)
16 Coverlay film (second protective film)
17 Reinforcing wiring MA Mounting area PP Corner of mounting area AA Open area IL Virtual bisecting line BL Boundary line WL Bending line 21 Circuit element 22 Bump 31 Adhesive PU Liquid crystal display panel ST Mounting board set UT Panel unit
　［実施の形態１］
　実施の一形態について、図面に基づいて説明すれば、以下の通りである。なお、便宜上、ハッチングや部材符号等を省略する場合もあるが、かかる場合、他の図面を参照するものとする。 [Embodiment 1]
The following describes one embodiment with reference to the drawings. For convenience, hatching, member codes, and the like may be omitted, but in such a case, other drawings are referred to.
　図５は携帯電話等の電子機器に内蔵される液晶表示パネルＰＵと、この液晶表示パネルＰＵにつながる実装基板セットＳＴを示す平面図であり、図２は実装基板セットＳＴを拡大した平面図である（なお、液晶表示パネルＰＵと実装基板セットＳＴとの組み合わさったユニットは、パネルユニットＵＴと称する）。また、図３Ａおよび図３Ｂは、図２におけるＡ－Ａ’線矢視断面図およびＢ－Ｂ’線矢視断面図である（なお、Ａ－Ａ’線は、後述する仮想２等分線ＩＬでもある）。 FIG. 5 is a plan view showing a liquid crystal display panel PU built in an electronic device such as a mobile phone and a mounting board set ST connected to the liquid crystal display panel PU. FIG. 2 is an enlarged plan view of the mounting board set ST. There is a unit (a unit in which the liquid crystal display panel PU and the mounting substrate set ST are combined is referred to as a panel unit UT). 3A and 3B are a cross-sectional view taken along line AA ′ and a cross-sectional view taken along line BB ′ in FIG. 2 (the line AA ′ is a virtual bisector described later). IL).
　そして、これらの図に示される実装基板セットＳＴは、種々の回路素子２１と、この回路素子２１を実装する実装基板１１を含む｛なお、回路素子２１は、ＡＣＦ（Anisotropic　Conductive　Film）またはＮＣＦ（Non　Conductive　Film）のような接着剤３１で、実装される｝。 The mounting board set ST shown in these drawings includes various circuit elements 21 and a mounting board 11 on which the circuit elements 21 are mounted. Note that the circuit element 21 is an ACF (Anisotropic Conductive Film) or NCF (NCF). Mounted with adhesive 31 such as Non Conductive Film}.
　ここで、以上の図面に対し、さらに回路素子２１を除いて図示した平面図である図１を加えて、実装基板１１を詳説する。実装基板１１は、主基板１２、供給配線１３、連絡配線１４、ソルダーレジスト膜（第１保護膜）１５、カバーレイフィルム（第２保護膜）１６、および補強配線１７を含む。 Here, FIG. 1 which is a plan view excluding the circuit element 21 is added to the above drawings, and the mounting substrate 11 will be described in detail. The mounting substrate 11 includes a main substrate 12, a supply wiring 13, a connection wiring 14, a solder resist film (first protective film) 15, a coverlay film (second protective film) 16, and a reinforcing wiring 17.
　主基板１２は、実装基板１１の基体となる部材であり可撓性を有する。そのため、主基板１２を含む実装基板１１は、ＦＰＣ（Flexible　Printed　Circuits）基板とも称される。なお、主基板１２の材料としては、例えば、ポリイミド樹脂やＰＥＴ（ポリエチレンテレフタレート）が挙げられる。 The main board 12 is a member that becomes a base of the mounting board 11 and has flexibility. Therefore, the mounting board 11 including the main board 12 is also referred to as an FPC (Flexible Printed Circuits) board. In addition, as a material of the main board | substrate 12, a polyimide resin and PET (polyethylene terephthalate) are mentioned, for example.
　供給配線１３は、例えば、回路素子２１に含まれるバンプ（突起電極）２２につながり、不図示の電源からの電流を回路素子２１に供給する。したがって、図３Ｂに示すように、バンプ２２と供給配線１３とは接続する。なお、供給配線１３は、主基板１２の表面（実装面）１２Ａおよび裏面（非実装面）１２Ｂの少なくとも一方に形成されればよい。 The supply wiring 13 is connected to, for example, a bump (projection electrode) 22 included in the circuit element 21 and supplies a current from a power source (not shown) to the circuit element 21. Therefore, as shown in FIG. 3B, the bump 22 and the supply wiring 13 are connected. The supply wiring 13 may be formed on at least one of the front surface (mounting surface) 12A and the back surface (non-mounting surface) 12B of the main substrate 12.
　連絡配線１４は、例えば図３Ａに示すように、主基板１２の裏面１２Ｂに形成される配線であり、供給配線１３同士を接続する。なお、この連絡配線１４も、回路素子２１に電流を供給する点では、供給配線１３と同様の役割を果たすので、供給配線１３の一種ともいえる。 The connection wiring 14 is a wiring formed on the back surface 12B of the main substrate 12, as shown in FIG. 3A, for example, and connects the supply wirings 13 to each other. Note that this connection wiring 14 also plays a role similar to that of the supply wiring 13 in that current is supplied to the circuit element 21, and thus can be said to be a kind of the supply wiring 13.
　ソルダーレジスト膜１５は、フォトリソグラフィーで形成される樹脂膜であり、主基板１２の表面１２Ａを覆うことで、供給配線１３を保護する（詳説すると、ソルダーレジスト膜１５は実装面１２Ａにおける供給配線１３を少なくとも覆う）。 The solder resist film 15 is a resin film formed by photolithography, and protects the supply wiring 13 by covering the surface 12A of the main substrate 12 (more specifically, the solder resist film 15 is provided on the mounting surface 12A by the supply wiring 13). Covering at least).
　なお、ソルダーレジスト膜１５は、主基板１２の表面１２Ａ全面を覆うのではなく、図１に示すように、回路素子２１の実装を予定される主基板１２における表面１２Ａの一部領域（開口領域ＡＡ）を覆わない。そのため、このようなソルダーレジスト膜１５に覆われない領域を確保すべく、精度よくパターニング可能なフォトリソグラフィーが用いられる。 The solder resist film 15 does not cover the entire surface 12A of the main substrate 12, but as shown in FIG. 1, a partial region (opening region) of the surface 12A on the main substrate 12 on which the circuit element 21 is scheduled to be mounted. AA) is not covered. For this reason, photolithography capable of patterning with high accuracy is used in order to secure a region not covered with the solder resist film 15.
　カバーレイフィルム１６は、主基板１２の裏面１２Ｂに形成される配線（供給配線１３および連絡配線１４等）を覆うフィルムである（詳説すると、カバーレイフィルム１６は非実装面１２Ｂにおける連絡配線１４のような供給配線１３を少なくとも覆う）。したがって、主基板１２の裏面１２Ｂにて配線の形成されない領域（例えば、回路素子２１直下の裏面１２Ｂの領域）には、カバーレイフィルム１６は存在しない。なお、このカバーレイフィルム１６は、パターニング精度はフォトリソグラフィーによるソルダーレジスト膜には劣るものの、絶縁性および剛性はソルダーレジスト膜１５よりも高い。 The cover lay film 16 is a film that covers the wiring (the supply wiring 13 and the connection wiring 14 and the like) formed on the back surface 12B of the main substrate 12 (more specifically, the cover lay film 16 covers the connection wiring 14 on the non-mounting surface 12B. Cover at least the supply wiring 13). Therefore, the coverlay film 16 does not exist in a region where the wiring is not formed on the back surface 12B of the main substrate 12 (for example, a region of the back surface 12B immediately below the circuit element 21). The cover lay film 16 is inferior to the solder resist film obtained by photolithography in patterning accuracy, but is higher in insulation and rigidity than the solder resist film 15.
　補強配線１７は、実装基板１１の一部領域を曲がらないようにするとともに、実装基板１１の曲がる箇所を決定づける。一例として、補強配線１７は、図１に示すように、回路素子２１に重なる主基板１２における表面１２Ａの領域である実装領域ＭＡの隅ＰＰに重なる。詳説すると、補強配線１７は、実装領域ＭＡの隅ＰＰから、実装領域ＭＡの外側へと進出する。 The reinforcing wiring 17 prevents a part of the mounting substrate 11 from being bent, and determines a place where the mounting substrate 11 is bent. As an example, as shown in FIG. 1, the reinforcing wiring 17 overlaps the corner PP of the mounting area MA that is the area of the surface 12 </ b> A on the main substrate 12 that overlaps the circuit element 21. Specifically, the reinforcing wiring 17 advances from the corner PP of the mounting area MA to the outside of the mounting area MA.
　すると、主基板１２の表面１２Ａにて、補強配線１７の一部はソルダーレジスト膜１５に覆われるととともに、補強配線１７の残部はソルダーレジスト膜１５に覆われず回路素子２１の実装を予定される領域（開口領域）ＡＡに進出する。 Then, on the surface 12A of the main substrate 12, a part of the reinforcing wiring 17 is covered with the solder resist film 15, and the remaining part of the reinforcing wiring 17 is not covered with the solder resist film 15, and the circuit element 21 is to be mounted. Advance to the area (opening area) AA.
　そして、このような補強配線１７であれば、例えば、図２および図３Ａに示すように、負荷Ｆが実装基板１１にかかった場合に、実装基板１１は線（屈曲線）ＷＬに沿って折れ曲がろうとする。そして、実装基板１１が折れ曲がると、図４の断面図のようになる。 With such a reinforcing wiring 17, for example, as shown in FIGS. 2 and 3A, when a load F is applied to the mounting substrate 11, the mounting substrate 11 is bent along a line (bending line) WL. Try to bend. Then, when the mounting substrate 11 is bent, a sectional view of FIG. 4 is obtained.
　詳説すると、図４に示すように、実装基板１１において、回路素子２１の隅付近ではなく、補強配線１７を境にして実装領域ＭＡから乖離する側が曲がる。これは、補強配線１７が、回路素子２１の隅に重なるように位置することで、実装基板１１における回路素子２１の隅付近を負荷Ｆに耐えられるようにしたためである。 More specifically, as shown in FIG. 4, in the mounting substrate 11, the side that deviates from the mounting area MA is bent with the reinforcing wiring 17 as a boundary, not near the corner of the circuit element 21. This is because the reinforcing wiring 17 is positioned so as to overlap the corner of the circuit element 21 so that the vicinity of the corner of the circuit element 21 on the mounting substrate 11 can withstand the load F.
　いいかえると、補強配線１７は、実装基板１１の一部領域を負荷Ｆに耐えられるようにすることで、自身を境にして実装領域ＭＡから乖離する側の実装基板１１の一部領域を負荷Ｆによって曲がる領域にしている。 In other words, the reinforcing wiring 17 allows the partial region of the mounting board 11 to withstand the load F, so that the partial region of the mounting substrate 11 on the side deviating from the mounting region MA with respect to itself as a boundary. By the bend area.
　そして、このように回路素子２１の隅付近から離れた実装基板１１の一部領域が曲がるようになれば、負荷Ｆに起因して、回路素子２１の隅が実装基板１１からは剥がれない。そして、このような剥離が生じなければ、回路素子２１の性能不良（例えば、接触不良）が起きず、実装基板セットＳＴとしての品質が向上する。 Then, if a partial region of the mounting substrate 11 that is away from the vicinity of the corner of the circuit element 21 is bent as described above, the corner of the circuit element 21 is not peeled off from the mounting substrate 11 due to the load F. And if such peeling does not occur, the performance defect (for example, contact failure) of the circuit element 21 does not occur, and the quality as the mounting board set ST is improved.
　なお、回路素子２１の隅が実装基板１１から剥がれることが、実装基板セットＳＴでの回路素子２１の接続不良の大部分を占める（なお、接着剤３１のフィレットが回路素子２１の隅に生じにくいことが、実装基板１１から回路素子２１の隅が剥がれる一因である）。そのため、回路素子２１の隅が実装基板１１からは剥がれなければ、工程不良が減少し、さらに長時間にわたって高品質な実装基板設置ＳＴが使用されることになる。 Note that the corners of the circuit elements 21 are peeled off from the mounting substrate 11 occupy most of the connection failures of the circuit elements 21 in the mounting substrate set ST (note that the fillet of the adhesive 31 is unlikely to occur at the corners of the circuit elements 21. (This is one reason why the corner of the circuit element 21 is peeled off from the mounting substrate 11). Therefore, if the corners of the circuit element 21 are not peeled off from the mounting substrate 11, the process defects are reduced, and the high-quality mounting substrate installation ST is used for a long time.
　ところで、補強配線１７の形状は、特に限定されるものではない。例えば、図１に示すように四角状でもよいし、その他の多角形状、円状、線状、網状、および迂回状であってもかまわない。ただし、実装基板１１では、以下の条件式（１）が満たされると望ましい。 By the way, the shape of the reinforcing wiring 17 is not particularly limited. For example, as shown in FIG. 1, it may be a square shape, or may be other polygonal shapes, circular shapes, linear shapes, net shapes, and detour shapes. However, in the mounting substrate 11, it is desirable that the following conditional expression (1) is satisfied.
　詳説すると、実装領域ＭＡの隅ＰＰにおける角度を２等分する線を延ばして仮想２等分線ＩＬ（図１参照）とするとともに、下記の条件式（１）が満たされると望ましい（図３Ａも参照）。この条件式（１）は、実装領域ＭＡの隅ＰＰに重なる補強配線１７の一端から、実装領域ＭＡの外側に向かい、かつ仮想２等分線ＩＬに重なって、補強配線１７の縁に至るまでの最長の長さを、補強配線１７の厚みの長さで規格化する。なお、図中の“Ｌ”は、下記に説明する＋表記の間隔のみを示す。 More specifically, it is desirable that a line that bisects the angle at the corner PP of the mounting area MA is extended to a virtual bisector IL (see FIG. 1) and that the following conditional expression (1) is satisfied (FIG. 3A). See also). This conditional expression (1) is from one end of the reinforcing wiring 17 that overlaps the corner PP of the mounting area MA to the outside of the mounting area MA and overlaps the virtual bisector IL and reaches the edge of the reinforcing wiring 17. Is standardized by the length of the thickness of the reinforcing wiring 17. Note that “L” in the figure indicates only the interval of + notation described below.
　　０＜Ｌ／Ｄ≦３０　…　条件式（１）
　　　ただし、
　　　　　Ｌ　：実装領域ＭＡの隅ＰＰに重なる補強配線１７の一端から、実装領域ＭＡ
　　　　　　　　の外側に向かい、かつ仮想２等分線ＩＬに重なって、補強配線１７の縁
　　　　　　　　に至るまでの最長の長さ（ただし、仮想２等分線ＩＬに重なって、実装
　　　　　　　　領域ＭＡの外側に向かって延びるＬは “＋”表記され、実装領域ＭＡ
　　　　　　　　の内側に向かって延びるＬは“－”表記される）
　　　　　Ｄ　：補強配線１７の厚み長
　　　である。 0 <L / D ≦ 30 Conditional expression (1)
However,
L: From one end of the reinforcing wiring 17 overlapping the corner PP of the mounting area MA, the mounting area MA
The longest length until it reaches the edge of the reinforcement wiring 17 (however, it overlaps the virtual bisector IL and goes outside the mounting area MA). The extending L is indicated by “+”, and the mounting area MA
L that extends toward the inside is marked with "-")
D: Thickness length of the reinforcing wiring 17
　Ｌ／Ｄ（アスペクト比）の値が下限値以下である場合、例えば、補強配線１７は、実装領域ＭＡの内部にしか重ならない。そのため、実装基板１１に負荷Ｆがかかる場合、屈曲線ＷＬ（図２参照）に沿って実装基板１１が曲がらず、回路素子２１の隅付近にて実装基板１１が曲がり得る。その結果、回路素子２１の隅が実装基板１１から剥がれかねない。 When the value of L / D (aspect ratio) is equal to or lower than the lower limit value, for example, the reinforcing wiring 17 overlaps only inside the mounting area MA. Therefore, when the load F is applied to the mounting substrate 11, the mounting substrate 11 does not bend along the bending line WL (see FIG. 2), and the mounting substrate 11 can be bent near the corner of the circuit element 21. As a result, the corners of the circuit element 21 may be peeled off from the mounting substrate 11.
　一方、Ｌ／Ｄの値が上限値を上回る場合、仮想２等分線ＩＬに重なる補強配線１７の長さが過剰に長くなり、補強配線１７自体が撓みやすくなる。そのため、実装基板１１に負荷Ｆがかかる場合、実装基板１１が曲がるとともに補強配線１７までも曲がりかねない。すると、回路素子２１の隅（実装領域ＭＡの隅ＰＰ）に重なる補強配線１７の一端も曲がりかねない。そして、このようにして、補強配線１７が曲がってしまうと、回路素子２１の隅付近にて実装基板１１が曲がることになり、回路素子２１の隅が実装基板１１から剥がれかねない。 On the other hand, when the value of L / D exceeds the upper limit value, the length of the reinforcing wiring 17 overlapping the virtual bisector IL becomes excessively long, and the reinforcing wiring 17 itself is easily bent. Therefore, when the load F is applied to the mounting substrate 11, the mounting substrate 11 may be bent and the reinforcing wiring 17 may be bent. Then, one end of the reinforcing wiring 17 that overlaps the corner of the circuit element 21 (the corner PP of the mounting area MA) may be bent. If the reinforcing wiring 17 is bent in this way, the mounting board 11 is bent near the corner of the circuit element 21, and the corner of the circuit element 21 may be peeled off from the mounting board 11.
　したがって、Ｌ／Ｄの値が条件式（１）の範囲内であれば、回路素子２１の隅付近にて実装基板１１が曲がらず、回路素子２１の隅が実装基板１１から剥がれない。その結果、回路素子２１の性能不良が起きず、実装基板セットＳＴとしての品質が向上する。 Therefore, if the value of L / D is within the range of the conditional expression (1), the mounting substrate 11 is not bent near the corner of the circuit element 21 and the corner of the circuit element 21 is not peeled off from the mounting substrate 11. As a result, the performance defect of the circuit element 21 does not occur, and the quality as the mounting board set ST is improved.
　なお、条件式（１）の条件範囲のなかでも、以下の条件範囲を定めた条件式（１ａ）が満たされると望ましい。
　　０＜Ｌ／Ｄ≦２０　…　条件式（１ａ） Of the conditional ranges of conditional expression (1), it is desirable that conditional expression (1a) that defines the following conditional ranges is satisfied.
0 <L / D ≦ 20 Conditional expression (1a)
　また、図３Ａに示すように、仮想２等分線ＩＬに重なる補強配線１７の一端と、仮想２等分線ＩＬに重なるカバーレイフィルム１６の一端との最短間隔Ｋは、主基板１２とソルダーレジスト膜１５とだけで形成されると望ましい。 Further, as shown in FIG. 3A, the shortest distance K between one end of the reinforcing wiring 17 that overlaps the virtual bisector IL and one end of the coverlay film 16 that overlaps the virtual bisector IL is the main substrate 12 and the solder. It is desirable to form only with the resist film 15.
　このようになっていると、比較的低剛性な２つの部材（主基板１２・ソルダーレジスト膜１５）を含む最短間隔Ｋは、比較的高剛性な補強配線１７を含む間隔Ｌに比べて曲がりやすい。したがって、実装基板１１に負荷Ｆが加わった場合、実装基板１１における間隔Ｌは曲がることなく、実装基板１１における間隔Ｋが曲がる。そのため、回路素子２１の隅が実装基板１１から確実に剥がれない。 In this case, the shortest distance K including two members (main substrate 12 and solder resist film 15) having relatively low rigidity is more easily bent than the distance L including relatively high rigidity reinforcing wiring 17. . Therefore, when the load F is applied to the mounting substrate 11, the interval L in the mounting substrate 11 is bent without bending the interval L in the mounting substrate 11. Therefore, the corners of the circuit element 21 are not reliably peeled off from the mounting substrate 11.
　なお、図３Ａに示される実装基板１１における一部領域の曲がりやすさを順番付けると、間隔Ｋを含む実装基板１１の一部領域、間隔Ｌを含む実装基板１１の一部領域、カバーレイフィルム１６の重なる実装基板１１の一部領域、回路素子２１の重なる実装基板１１の一部領域、の順になる。 In addition, when the bendability of the partial areas in the mounting substrate 11 shown in FIG. This is in the order of a partial region of the mounting substrate 11 that overlaps 16 and a partial region of the mounting substrate 11 that overlaps the circuit element 21.
　ところで、補強配線１７は、回路素子２１の隅が実装基板１１から剥がれることのみを防止するわけではない。例えば、回路素子２１が薄く撓みやすい場合、補強配線１７は、実装基板１１における実装領域ＭＡの内部を曲がらないようにして、回路素子２１のバンプ２２と供給配線１３との剥離を確実に防止する。 Incidentally, the reinforcing wiring 17 does not prevent only the corner of the circuit element 21 from being peeled off from the mounting substrate 11. For example, when the circuit element 21 is thin and easily bent, the reinforcing wiring 17 does not bend the inside of the mounting area MA in the mounting substrate 11 and reliably prevents the bumps 22 of the circuit element 21 and the supply wiring 13 from peeling off. .
　このような防止のためには、以下のようになっているとよい。すなわち、補強配線１７は、実装領域ＭＡの隅ＰＰから、実装領域ＭＡの内側へと進出すればよい。 In order to prevent such a situation, the following is recommended. That is, the reinforcing wiring 17 has only to advance from the corner PP of the mounting area MA to the inside of the mounting area MA.
　このようになっていれば、実装領域ＭＡの内側に進出した補強配線１７は、実装領域ＭＡの中心に向かって延びる。そのため、実装基板１１における実装領域ＭＡの内部が、補強配線１７の存在によって曲がらない。 If this is the case, the reinforcing wiring 17 that has advanced to the inside of the mounting area MA extends toward the center of the mounting area MA. Therefore, the inside of the mounting area MA on the mounting substrate 11 is not bent due to the presence of the reinforcing wiring 17.
　さらに、図６に示すように、実装領域ＭＡにて回路素子２１のバンプ２２に重なる一端を電極重畳点ＢＰ、仮想２等分線ＩＬを挟みかつ最短距離で隣り合う電極重畳点ＢＰ同士を結ぶ線を境界線ＢＬとすると、補強配線１７は、実装領域ＭＡの隅ＰＰから内側に向かい、境界線ＢＬを越えて進出するとさらに望ましい。 Further, as shown in FIG. 6, in the mounting area MA, one end overlapping the bump 22 of the circuit element 21 is connected to the electrode overlapping point BP, and the adjacent electrode overlapping points BP are connected to each other with the virtual bisector IL interposed therebetween. Assuming that the line is a boundary line BL, the reinforcing wiring 17 is more preferably inward from the corner PP of the mounting area MA and advanced beyond the boundary line BL.
　このようになっていると、供給配線１３の先端よりもさらに実装領域ＭＡの中心側まで補強配線１７は延びる。そのため、実装基板１１における実装領域ＭＡの内部が、補強配線１７の存在によって一層曲がらない。 In this case, the reinforcing wiring 17 extends further to the center side of the mounting area MA than the front end of the supply wiring 13. Therefore, the inside of the mounting area MA on the mounting substrate 11 is not further bent due to the presence of the reinforcing wiring 17.
　なお、回路素子２１に含まれるバンプ２２は、図７に示すように、格子状に配置されることもある。そして、このような回路素子２１に対応する実装領域ＭＡの電極重畳点ＢＰは、図８に示すように、格子状に並ぶ。このような配置の場合、格子状の群（電極重畳点群）になった電極重畳点ＢＰでの最外の電極重畳点ＢＰにおいて、仮想２等分線ＩＬを挟みかつ最短距離で隣り合う電極重畳点ＢＰ同士を結ぶ線が境界線ＢＬともいえる。 Note that the bumps 22 included in the circuit element 21 may be arranged in a grid as shown in FIG. Then, the electrode overlapping points BP of the mounting area MA corresponding to such circuit elements 21 are arranged in a grid pattern as shown in FIG. In the case of such an arrangement, at the outermost electrode superimposition point BP at the electrode superimposition point BP that is a lattice-shaped group (electrode superimposition point group), the electrodes adjacent to each other with the virtual bisector IL sandwiched between them at the shortest distance A line connecting the overlapping points BP can be said to be a boundary line BL.
　もちろん、図１および図６に示されるような、格子状の配置されていない電極重畳点ＢＰの群であっても、境界線ＢＬは、群になった電極重畳点ＢＰでの最外の電極重畳点ＢＰにおいて、仮想２等分線ＩＬを挟みかつ最短距離で隣り合う電極重畳点ＢＰ同士を結ぶ線である。 Of course, as shown in FIG. 1 and FIG. 6, even in the group of electrode overlapping points BP that are not arranged in a grid pattern, the boundary line BL is the outermost electrode at the grouped electrode overlapping point BP. In the overlapping point BP, the line overlaps the electrode overlapping points BP that are adjacent to each other with the shortest distance between the virtual bisector IL.
　なお、図１、図６、図８を総括すると、以下のようにもいえる。すなわち、複数の電極重畳点ＢＰの集まりを電極重畳点群とし、その電極重畳点群における最短の外周範囲に重なるように、補強配線１７は、実装領域ＭＡの隅ＰＰから進出する。このようになっていれば、実装基板１１における実装領域ＭＡの内部が、補強配線１７の存在によって確実に曲がらない。 In addition, when FIG. 1, FIG. 6, and FIG. 8 are summarized, the following can be said. That is, a group of a plurality of electrode overlapping points BP is used as an electrode overlapping point group, and the reinforcing wiring 17 advances from the corner PP of the mounting area MA so as to overlap the shortest outer peripheral range in the electrode overlapping point group. If this is the case, the inside of the mounting area MA on the mounting substrate 11 is not reliably bent due to the presence of the reinforcing wiring 17.
　また、補強配線１７は、電極重畳点群における最短の外周範囲に重なりつつ、自身の隅を仮想２等分線ＩＬに重ねると望ましい。このようになっていれば、回路素子２１の隅付近の実装領域ＭＡの内部が、補強配線１７の存在によって確実に曲がらない。 Further, it is desirable that the reinforcing wiring 17 overlaps the shortest outer peripheral range in the electrode overlapping point group while overlapping its corner with the virtual bisector IL. With this configuration, the interior of the mounting area MA near the corner of the circuit element 21 is not reliably bent due to the presence of the reinforcing wiring 17.
　［その他の実施の形態］
　なお、本発明は上記の実施の形態に限定されず、本発明の趣旨を逸脱しない範囲で、種々の変更が可能である。 [Other embodiments]
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
　例えば、以上では、補強配線１７は、実装基板１１の実装面１２Ａ上に形成されていたが、これに限定されるものではない。すなわち、補給配線１７は、実装基板１１の非実装面１２Ｂ上に形成されてもかまわない。 For example, in the above description, the reinforcing wiring 17 is formed on the mounting surface 12A of the mounting substrate 11, but is not limited thereto. That is, the supply wiring 17 may be formed on the non-mounting surface 12 </ b> B of the mounting substrate 11.
　要は、回路素子２１が実装基板１１に実装される場合に、回路素子２１の隅に重なるように、補強配線１７が位置すれば、実装基板１１の実装面１２Ａであっても非実装面１２Ｂであってもかまわない。なお、以上での重なるとは、主基板１２の厚み方向における種々部材の重なりを意味する。 In short, when the circuit element 21 is mounted on the mounting substrate 11, if the reinforcing wiring 17 is positioned so as to overlap the corner of the circuit element 21, even the mounting surface 12A of the mounting substrate 11 is not mounted surface 12B. It doesn't matter. Note that the term “overlap” as described above means an overlap of various members in the thickness direction of the main substrate 12.
　また、図９に示すように、補強配線１７に回路素子２１のバンプ２２がつながってもよい。すなわち、補強配線１７が供給配線１３と同様の機能を果たしてもよい（要は、補強配線１７が供給配線１３を兼ねてもよい）。 Further, as shown in FIG. 9, the bump 22 of the circuit element 21 may be connected to the reinforcing wiring 17. That is, the reinforcing wiring 17 may perform the same function as the supply wiring 13 (in short, the reinforcing wiring 17 may also serve as the supply wiring 13).
　このようになっていると、回路素子２１の実装基板１１からの剥離が防止されるだけでなく、回路素子２１のバンプの配置ピッチ（電極重畳点ＢＰ）が狭かったとしても、補強配線１７の面積が増大する。例えば、図８に示すように、実装領域ＭＡの電極重畳点ＢＰが密になっている場合、補強回線１７が供給回線１３を兼ねていると有用といえる。 In this case, not only the circuit element 21 is prevented from being peeled off from the mounting substrate 11, but even if the bump arrangement pitch (electrode overlap point BP) of the circuit element 21 is narrow, the reinforcing wiring 17 The area increases. For example, as shown in FIG. 8, when the electrode overlapping points BP of the mounting area MA are dense, it can be useful that the reinforcing line 17 also serves as the supply line 13.
　また、図２～図４に示すように、回路素子２１と実装領域ＭＡとの間に接着剤３１が介在すると望ましい。このようになっていれば、実装領域ＭＡが接着剤３１を介して比較的高剛性の回路素子２１につながる。そのため、実装基板１１における実装領域ＭＡは曲がらない。 Further, as shown in FIGS. 2 to 4, it is desirable that an adhesive 31 is interposed between the circuit element 21 and the mounting area MA. In this case, the mounting area MA is connected to the circuit element 21 having a relatively high rigidity via the adhesive 31. Therefore, the mounting area MA on the mounting substrate 11 is not bent.
　特に、補強配線１７が実装領域ＭＡの内側にまで延びていると、実装領域ＭＡは、接着剤３１を介して比較的高剛性な回路素子２１および補強配線１７につながる。要は、実装領域ＭＡ上に、補強配線１７、接着剤３１、回路素子２１がこの順で積み上がり、実装領域ＭＡ・補強配線１７・接着剤３１・回路素子２１の４層構造が形成される。そのため、負荷Ｆが実装基板１１にかかったとしても、多層構造の一部となった実装領域ＭＡは、曲がらない。 Particularly, when the reinforcing wiring 17 extends to the inside of the mounting area MA, the mounting area MA is connected to the relatively high-rigidity circuit element 21 and the reinforcing wiring 17 via the adhesive 31. In short, the reinforcing wiring 17, the adhesive 31, and the circuit element 21 are stacked in this order on the mounting area MA, and a four-layer structure of the mounting area MA, the reinforcing wiring 17, the adhesive 31, and the circuit element 21 is formed. . Therefore, even if the load F is applied to the mounting substrate 11, the mounting area MA that is part of the multilayer structure is not bent.
　なお、図５では、パネルとして液晶表示パネルＰＵを挙げたが、これに限定されるものではない。例えば、有機ＥＬ（electroluminescence）のパネルであっても、プラズマパネルであってもかまわない。 In addition, in FIG. 5, although liquid crystal display panel PU was mentioned as a panel, it is not limited to this. For example, it may be an organic EL (electroluminescence) panel or a plasma panel.

Claims (12)

  1. 　回路素子に対して電流供給する供給配線を含む実装基板にあって、
    　実装される上記回路素子に重なる上記実装基板の実装面の領域を実装領域とすると、
    　上記実装面および上記実装面の裏面である非実装面の少なくとも一方の面に、上記実装領域の隅に重なる補強配線が形成される実装基板。     In a mounting board including supply wiring for supplying current to circuit elements,
    When the area of the mounting surface of the mounting board that overlaps the circuit element to be mounted is a mounting area,
    A mounting substrate in which a reinforcing wiring is formed on at least one of the mounting surface and the non-mounting surface, which is the back surface of the mounting surface, and overlaps with a corner of the mounting region.
  2. 　上記補強配線は、上記実装領域の隅から、上記実装領域の外側へと進出する請求項１に記載の実装基板。 The mounting board according to claim 1, wherein the reinforcing wiring advances from a corner of the mounting area to the outside of the mounting area.
  3. 　上記実装領域の隅における角度を２等分する線を延ばして仮想２等分線とし、
    　下記条件式（１）が満たされる請求項２に記載の実装基板。
    　　０＜Ｌ／Ｄ≦３０　…　条件式（１）
    　　　ただし、
    　　　　　Ｌ　：上記実装領域の隅に重なる上記仮想２等分線の一端から、上記実装領
    　　　　　　　　域の外側に向かい、かつ上記仮想２等分線に重なって、上記補強配線
    　　　　　　　　の縁に至るまでの最長の長さ
    　　　　　Ｄ　：上記補強配線の厚み長
    　　　である。     Extend the line that bisects the angle at the corner of the mounting area into a virtual bisector,
    The mounting substrate according to claim 2, wherein the following conditional expression (1) is satisfied.
    0 <L / D ≦ 30 Conditional expression (1)
    However,
    L: The longest distance from one end of the virtual bisector that overlaps the corner of the mounting area to the outside of the mounting area and overlaps the virtual bisector to the edge of the reinforcing wiring Length D: The thickness length of the reinforcing wiring.
  4. 　上記実装面における上記供給配線を少なくとも覆う保護膜を第１保護膜、上記非実装面における上記供給配線を少なくとも覆う保護膜を第２保護膜とし、
    　上記実装領域の隅における角度を２等分する線を延ばして仮想２等分線とすると、
    　上記仮想２等分線に重なる上記補強配線の一端と上記仮想２等分線に重なる上記第２保護膜の一端との最短間隔は、上記実装基板の基体である主基板と上記第１保護膜とだけで形成される請求項１に記載の実装基板。     A protective film covering at least the supply wiring on the mounting surface is a first protective film, and a protective film covering at least the supply wiring on the non-mounting surface is a second protective film,
    If the line that bisects the angle at the corner of the mounting area is extended to be a virtual bisector,
    The shortest distance between one end of the reinforcing wiring that overlaps the virtual bisector and one end of the second protective film that overlaps the virtual bisector is the main substrate as the base of the mounting substrate and the first protective film. The mounting substrate according to claim 1, which is formed only by.
  5. 　上記補強配線は、上記実装領域の隅から、上記実装領域の内側へと進出する請求項１に記載の実装基板。 The mounting board according to claim 1, wherein the reinforcing wiring advances from the corner of the mounting area to the inside of the mounting area.
  6. 　上記実装領域にて上記回路素子のバンプに重なる一端を電極重畳点とするとともに、複数の電極重畳点の集まりを電極重畳点群とし、
    　上記実装領域の隅における角度を２等分する線を延ばして仮想２等分線とし、
    　上記電極重畳点群での最外の電極重畳点において、仮想２等分線を挟みかつ最短距離で隣り合う上記電極重畳点同士を結ぶ線を境界線とすると、
    　上記補強配線は、上記実装領域の隅から内側に向かい、上記境界線を越えて進出する請求項５に記載の実装基板。     One end overlapping the bump of the circuit element in the mounting area is an electrode overlapping point, and a group of a plurality of electrode overlapping points is an electrode overlapping point group,
    Extend the line that bisects the angle at the corner of the mounting area into a virtual bisector,
    In the outermost electrode overlapping point in the electrode overlapping point group, a line connecting the electrode overlapping points adjacent to each other with a shortest distance between the virtual bisector is defined as a boundary line.
    The mounting board according to claim 5, wherein the reinforcing wiring extends inward from a corner of the mounting area and extends beyond the boundary line.
  7. 　上記補強配線が、上記供給配線も兼ねる請求項１に記載の実装基板。 The mounting board according to claim 1, wherein the reinforcing wiring also serves as the supply wiring.
  8. 　上記回路素子と上記実装領域との間に接着剤が介在する請求項１に記載の実装基板。 The mounting substrate according to claim 1, wherein an adhesive is interposed between the circuit element and the mounting region.
  9. 　請求項１～８のいずれか１項に記載の実装基板と、
    　上記実装基板に実装された回路素子と、
    を含む実装基板セット。     A mounting substrate according to any one of claims 1 to 8,
    A circuit element mounted on the mounting board;
    Mounting board set including
  10. 　請求項６に記載の実装基板と、
    　上記実装基板に実装された回路素子と、
    を含み、
    　上記回路素子に含まれるバンプが、上記電極重畳点につながる上記供給配線に接続される実装基板セット。     The mounting board according to claim 6;
    A circuit element mounted on the mounting board;
    Including
    A mounting board set in which bumps included in the circuit element are connected to the supply wiring connected to the electrode overlapping point.
  11. 　請求項９に記載の実装基板セットと、
    　上記実装基板セットにつながる液晶表示パネルと、
    を含むパネルユニット。     The mounting board set according to claim 9,
    A liquid crystal display panel connected to the mounting board set;
    Including panel unit.
  12. 　請求項１０に記載の実装基板セットと、
    　上記実装基板セットにつながる液晶表示パネルと、
    を含むパネルユニット。     The mounting board set according to claim 10,
    A liquid crystal display panel connected to the mounting board set;
    Including panel unit.
PCT/JP2008/070383 2008-03-19 2008-11-10 Mounted board, mounted board set, and panel unit WO2009116202A1 (en)

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US9117774B2 (en) 2004-09-28 2015-08-25 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
CN106330212A (en) * 2016-08-31 2017-01-11 联想(北京)有限公司 Carrier aggregation receiving device and radio frequency front-end device
US11842972B2 (en) 2004-09-28 2023-12-12 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner

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KR20140026844A (en) 2012-08-23 2014-03-06 삼성전자주식회사 Method and system for authenticating transaction request from device
JP7202785B2 (en) * 2018-04-27 2023-01-12 新光電気工業株式会社 Wiring board and method for manufacturing wiring board
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US9117774B2 (en) 2004-09-28 2015-08-25 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US9721865B2 (en) 2004-09-28 2017-08-01 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US9831204B2 (en) 2004-09-28 2017-11-28 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US10522494B2 (en) 2004-09-28 2019-12-31 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US10818628B2 (en) 2004-09-28 2020-10-27 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US11355462B2 (en) 2004-09-28 2022-06-07 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
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CN106330212A (en) * 2016-08-31 2017-01-11 联想(北京)有限公司 Carrier aggregation receiving device and radio frequency front-end device

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US20110019125A1 (en) 2011-01-27
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