WO2009156450A1

WO2009156450A1 - Temporal adjustment of the cut-off frequency of a packet reception device connected to a network

Info

Publication number: WO2009156450A1
Application number: PCT/EP2009/057914
Authority: WO
Inventors: Thierry Tapie; Serge Defrance; Gael Mace
Original assignee: Thomson Licensing
Priority date: 2008-06-27
Filing date: 2009-06-24
Publication date: 2009-12-30

Abstract

The present invention relates to the domain of video equipment, it relates more specifically to a reception device able to receive packets in a packet communication network that comprises: means for receiving packets from the network, the packets containing samples PCR_r, from data sampled every T_ech period, where T_ech is from a time base synchronised on all the stations of said network, the means to regenerate a counting ramp CSR_PCR₁ using a phase locked loop PLL₁ receiving the samples PCR_r and also delivering local samples PCR_loc₁ every T_ech period and a reconstituted clock CLK_out₁, the means for initialising, at every zero-crossing of the counting ramp CSR-PCR₁, an counter CPT, the rhythm of which is determined by the reconstituted clock. The loop PLL₁ is notably characterized by a cut-off frequency f_c. According to the invention, the device also comprises an adjustment device for the cut-off frequency DAC₁ that temporaily adjusts the cut-off frequency of the phase locked loop.

Description

TEMPORAL ADJUSTMENT OF THE CUT-OFF FREQUENCY OF A PACKET RECEPTION DEVICE CONNECTED TO A NETWORK

Scope of the invention

The present invention relates to the domain of video equipment. The present invention relates more particularly to a device for the reception of a synchronisation signal on a packet switching network, for example of IP (Internet Protocol) type, whether the network is wired (for example Ethernet (IEEE802.3)) or wireless (for example IEEE 802.16 D- 2004).

Prior art

Progress in the ability of IP networks to transport all types of signal (data or video) has made it possible to use these networks as the "backbone" architecture for video studios. Of capital importance to this change is therefore having a single infrastructure for the transport of data. Whereas in the past, several media were necessary to transport different signal types between items of equipment The multiplexing properties offered by the IP layer enable a reduction in the number of media necessary: an IP network that links the different items of equipment.

In the prior art, the synchronisation of items of video equipment (cameras, etc.) in a studio is carried out by the transmission of a synchronisation signal commonly called "Genlock" or "Black burst". For example, the Genlock signal includes information from the start of the image, repeated every 40 ms, and information from the start of the line repeated every 64 μs. The waveforms of synchronisation signals are a function of the format of the image transmitted on the network. For example, for a high definition image, the synchronisation signal has a tri-level form (-30OmV, OV, +300 mV). When a synchronisation signal is routed to different items of equipment to be synchronised by a dedicated coaxial cable, a constant transmission time, without jitter is ensured. From such a signal, all items of equipment are able to reconstruct a timing clock that is specific to its operation, which guarantees that its operation is rigorously in phase with all the equipment connected to the same network. For example, two cameras synchronised by a Genlock signal circulating on a dedicated coaxial cable each generate a video with different contents but rigorously in frequency and in phase with one another. A known disadvantage presented by an IP/Ethernet network is that it introduces a strong jitter in a transmission of signals, and particularly for the transmission of a synchronisation signal. The transmission duration is on average constant but different for each packet transmitted. When such a signal is routed by an IP/Ethernet connection to different items of equipment for synchronising, this jitter results in fluctuations in the length of time required for the information carried by the synchronisation signal to reach the equipment.

In the prior art, for a set of devices, for example cameras, connected to an IP network, devices are known to reconstruct at the level of each camera, a timing clock specific to each camera enabling it to overcome jitter. The underlying principle of these devices is based on a high attenuation of the synchronisation signal jitter amplitude at the level of reception. In such a way, it can be guaranteed that an image generated by a camera is rigorously in phase with all of the images generated by neighbouring cameras connected to the same network. Examples of such video synchronisation devices for jitter attenuation are described in the international PCT application FR2007/050918, they act on program clock reference (PCR) signals that represent very accurate reference clock signals. These digital signals are sent to cameras across a network so that they can locally reconstruct clock signals that are in phase with the reference clock. The creation of the digital signal transported on the network and the reconstruction of clock signals are realised at dates according to a sampling clock CLK_eCh common to the transmission device and the reception devices. Specifically this clock CLK_eCh must be perfectly identical for the transmission device and all the reception devices. According to the prior art, the reception device comprises: - the means to receive packets containing data samples realized according to pulses of a sampling clock CLKech with a period T_eCh,

- means for regenerating a first counter CSR_PCRi using a phase-locked loop PLL₁,

- means for initialising a second CPT counter every zero-crossing of said first counter CSR_PCRi,

- means for generating image cues at every zero-crossing of the said second CPT counter, and

- means for reconstituting a synchronisation signal from said image cues and the reconstituted clock. The phase-locked loop PLL₁ of the reception device acts as a low-pass filter that partially attenuates the jitter present in the samples received PCR_r that have circulated on the network.

It is classic to characterize the phase locked loop PLL₁ receiving an input signal and delivering a signal filtered by:

- a loop gain G_Bo, also called "open loop gain" constituted by the product of gains of different stages constituting the phase locked loop,

- a cut-off frequency f_c that determines the frequency beyond which the input signal is attenuated, - a filter order that represents an attenuation factor of an input signal for a frequency domain situated beyond f_c, the more the filter order is heightened, and the more the attenuation of the input signal is severe in the frequency domain situated beyond the cut-off frequency f_c.

- a damping factor ξ of over-oscillations observed on an internal error signal ERR at the phase locked loop PLL. This error signal is shown in more detail in figure

4a described later. More often a constant value of ξ is chosen for example ξ equal to 0.7.

Moreover, the more the cut-off frequency f_c is heightened, the more the loop PLL₁ has a heightened reaction speed. In exchange, the more the cut-off frequency f_c of the filter is heightened, and the more the loop PLL₁ is sensitive to the transitory variations of the input signal.

Usually, two phases are distinguished in the functioning of the loop PLL₁:

- a first phase, known as the "acquisition phase", during which the phase- locked loop PLL₁ internally produces local samples PCRJoC₁ that are very different from the received samples PCR_r. This phase begins with a reception of samples

PCR_r and ends when the local samples PCRJoC₁ produced by the loop PLL₁ are very close to the samples received PCP_R. During this functioning phase, a synchronisation signal reconstructed on the reception side by means of the loop PLL₁ is not in phase with the synchronisation signal on the transmission side, - a second phase, known as the "continuation phase" begins at the end of the acquisition phase and ends when a significant difference between the local samples PCRJoC₁ and the received samples PCR_r is detected. During this functioning phase, a reconstructed synchronisation signal on the reception side is in phase with the synchronisation signal on the transmission side. To rapidly obtain a synchronization of items of equipment that are connected to a network, it appears therefore of interest to reduce a duration of the acquisition phase, that is to say that it is of interest to select a cut-off frequency f_c that is as high as possible. Moreover, during the continuation phase, in order to maintain a synchronization as long as possible, it appears of interest to overcome the transitory variations on the received samples PCR_r, that is to say to have a cut-off frequency f_c that is as low as possible.

The choice of a cut-off frequency value f_c ensuring a compromise between the conflicting requirements that correspond to the two functioning phases is a very delicate problem. The period for which the remote item of equipment connected to the network synchronizes with a Master equipment on one hand, and the sensitivity of the synchronization to interferences of the input signal on the other hand are two criteria of merit that are of equal importance for users of items of equipment to be synchronized.

One solution to this problem consists in modifying the cut-off frequency of a reception device currently functioning: a heightened cut-off frequency is preferentially assigned during the acquisition phase, a cut-off frequency preferably low is assigned during the continuation phase. It is known that a phase locked loop PLL₁ can be adapted from VHDL (Very

High Speed Integrated Circuit Hardware Description Language) codes. A redefinition completes the parameters of the filter, necessary to ensure balance between the cut-off frequency f_c, the loop gain G_Bo and a constant attenuation factor value ξ requires a great quantity of calculations to determine a series of coefficients defining the new filter, in addition these redefinitions must be reiterated in the time according to the functioning phase of the current loop PLL₁. Moreover, a complete redefinition of the filter parameters requires temporary storage means for sample due to the iterative functioning and the filter that requires having several successive samples. These different constraints constitute a difficulty that can be overcome by realizing a partial modification of the parameters of the phase locked loop PLL₁ according to the operating phase in which the reception device is found. This then comes back to finding a means to modify the value of the cut-off frequency of the phase locked loop according to the operating phase of the reception device. A first embodiment of this solution is described in the international patent application PCT FR2008/057092. It consists in a modification of the gain of the phase locked loop PLL₁ controlled from a measurement of the difference between the local samples PCRJoci and the samples received PCR_R. This difference constitutes an indicator of the nature of the phase ("acquisition" or "continuation").

This modification takes the form of a servo loop controlling the gain of the configurable digital oscillator VCOi of the loop PLL₁ as presented in the International patent application PCT FR2008/057092. A similar servo loop that pilots a configurable gain stage placed between the corrector COR₁ and the oscillator VCO₁ constitutes an equivalent solution.

This first embodiment presents however the inconvenience of affecting the stability of the phase locked loop PLL₁.

If a phase locked loop PLL₁ is considered that has a cut-off frequency f_c, a gain in open loop G_Bo and a damping factor ξ, when an additional gain G is introduced in the loop PLL₁, that is to say when the gain of the loop PLL₁ being considered while opoerating is equal to G. G_Bo, the damping factor is modified and is then equal to ξ /(1 +G).

The modification of the gain of the loop PLL₁ leads to a modification of the value of ξ that can cause an amplification of the over-oscillations on the error signal ERR. Modifying the gain of the loop PLL₁ thus affects the stability of this loop.

Naturally it is possible on the basis of a criterion, for example the JURY criterion or some other, to determine a range limit of the gain around a nominal gain value, below which the stability of the phase locked loop PLL₁ is guaranteed. However, even remaining below this range limit, there is no less than the stability of the loop PLL₁ modified.

This inconvenience is resolved by a second embodiment of the solution described above. This second embodiment constitutes the invention covered by the present application. It consists in progressively adjusting the cut-off frequency of the loop PLL₁ between two predefined values f_c1, f_C2 according to a determinist temporal law easy to evaluate without piloting of the gain in open loop of the phase locked loop. The temporal law must be sufficiently progressive so that the cut-off frequency adjustment of f_c1 to f_C2 does not cause oscillation on the signal produced by the loop PLL₁ signal of reconstituted synchronization.

One purpose of the present invention is to progressively adjust the cut-off frequency of the phase locked loop between two predefined values f_c1, f_C2 according to an adapted predefined determinist law. The present invention enables the conservation of the margin of gain and the margin of phase of the phase locked loop and thus of its stability.

Summary of the invention

The technical problem that the present invention intends to resolve is to adapt a synchronization device described in the international patent application PCT FR2007/050918 to enable it to adjust the cut-off frequency of the phase locked loop that it comprises without affecting the stability of this phase locked loop.

For this purpose, the present invention relates to, according to a first aspect, a reception device able to receive packets in a packet communication network, said device comprises: the device (DACi) adjusts the cut-off frequency f_c in accordance with a first predefined temporal change law over a period τ.

According to the invention, the device DACi adjusts the cut-off frequency f_c in accordance with a first predefined temporal change law over a periodτ.

The present invention realates to, according to a second aspect, a method for temporal adjustment of a cut-off frequency value of a phase locked loop PLL₁. According to the invention, it comprises steps aiming to:

- determine a first cut-off frequency fd adapted to a transitory operating mode of the loop PLL₁ and a second cut-off frequency fc2 adapted to a permanent operating mode of the loop PLL₁,

- determine a first temporal change law of the cut-off frequency of the loop (PLL₁) so that it changes the value fd to the value fc2 over a period τ,

- determine the second laws of temporal change of the set of coefficients (a1 , a2, ..., an) so that the cut-off frequency fc of the loop PLL₁ changes according to the first temporal law,

- adjust the value of the set of coefficients (a1 , a2, ..., an) in accordance with said second temporal change laws at a frequency 1/Tupd where Tupd is less than τ/10. A first advantage of the device according to the invention is that it does not require the implementation of a servo loop to control the gain of the phase locked loop in order to adjust the cut-off frequency value of the phase locked loop that it comprises without effecting its stability. As a consequence, a device according to the invention comprising a phase locked loop is more stable than the reception devices of the prior art.

A second advantage of the device according to the invention is provided by the choice of the determinist change law that guarantees a constant alignment period of the acquisition phase with the continuation phase. A choice particularly adapted is that constituted by a law enabling the avoidance of reliance on means of calculation that require a great deal of ressources during operation: this is the case for a temporal change law of the polynomial cut-off frequency of the order of 1 or 2.

Brief description of the drawings

The invention will be better understood from the following description of an embodiment of the invention provided as an example by referring to the annexed figures, wherein:

- figure 1 shows the transmission of Genlock information between two cameras linked via an IP/Ethernet network, - figure 2 shows the interfacing between the analogue domain and the

IP/Ethernet network,

- figure 3 shows the regeneration of the Genlock signal on the reception side according to the prior art,

- Figures 4a and 4b each diagrammatically show a phase-locked loop architecture of a reception device according to the prior art,

- Figure 5 shows in a very diagrammatic and functional manner an embodiment of a phase locked loop corrector according to the prior art,

- Figure 6 diagrammatically shows a phase-locked loop architecture of a reception device according to the invention. - Figure 7 shows the steps of the temporal adjustment method of a ferequency cut-off value of a phase locked loop according to the invention.

The figures presented above enable illustration of the problem of transmission of an "image cue" that is to say a period pulse and a clock, in the scope of video equipment synchronization. It is recalled however that the invention also enables the problems posed only by the transmission of clock signals to be resolved and that the domain of the invention is not limited to the domain of video equipment, considered here as a simple example. Detailed description of the embodiments of the invention

The current analogue domain is interfaced with the IP/Ethernet network on the transmission side, and the IP/Ethernet network is interfaced with the analogue domain on the reception side, as illustrated in figure 1. On this same figure, the transmission side is constituted by a 'Genlock master'

MGE that is connected to an interface Analogique/IP I_AIP. The Genlock master MGE produces a Genlock signal SGO intended for the interfaces I AI P .

The reception side is constituted by two cameras (CAM1 , CAM2) each connected to an IP/Analogue interface IJPA. The interfaces IJPA that will eventually be included in the cameras themselves are responsible for reconstructing the Genlock signals SG1 , SG2 intended for cameras CAM1 , CAM2. The cameras CAM1 , CAM2 each produce a video signal SV1 , SV2 that is required to be synchronised perfectly.

The transmission and reception sides are linked together by a packet switching network that is the source of a jitter occurring in the Genlock signal SGO.

A sampling image cue is generated at the period T_eCh from a first synchronization layer, for example IEEE 1588, addressed to the transmission and reception sides and playing the role of a sampling clock CLKech perfectly synchronized on all the items of equipment connected to the network. Indeed, the PTP protocol (Precision Time Protocol) based on IEEE1588 enables synchronisation to be obtained between the equipment connected on the Ethernet network to an order of microseconds. In other words, all the time bases of every item of equipment progress at the same time with a precision close to the order of microseconds. Each of these time bases can be used in this case to generate its own sampling pulse in the T_eCh, period. Use of the IEEE1588 layer is not a required route. Any system capable of providing sampling pulses to the various items of equipment on the network in the T_eCh period could be suitable. For example, a 5 ms sampling pulse from a wireless transmission physical layer can be used.

Figure 2 details the processing of the Genlock signal SGO from MGE within the interface I AI P .

First, a module EXS extracts the synchronisation information from the signal

SGO in order to recover a video timing clock (noted as CIk video on figure 2). More specifically, the module EXS is responsible for the generation of an image cue at the beginning of each image. Furthermore, the module EXS comprises an image counter, for example a 40 ms counter, which is not shown on Figure 2. The output of this image counter progresses according to the counting ramp, crossing 0 at each image period, that is every 40 ms in the case of the image counter cited in the aforementioned example.

"Counting ramp" designates a "stair-step" signal for which the steps have a unitary height. The "counting ramp range" is the term applied to the difference in level between the highest step and the lowest step of the signal.

The range of the counting ramp delivered by the image counter is equal to 40ms. F_out, where F_out is the frequency of the clock CIk video. The image counter successively delivers all of the integer values from 0 to 40 ms.F_0Ut-1. The timing video clock is used to time a counter CPT_PCR. The output of the counter CPT_PCR is a counting ramp, whose period is m image periods. Every "m" image, the counter CPT_PCR is reset, that is to say that the counting ramp CSE_PCR is reset to 0.

The counting ramp range delivered by the image counter is equal to m.40ms. F_out. The counter CPT_PCR delivers successively all of the integer values from 0 to m.40 ms.F_0Ut-1.

Next, a module LCH samples the counting ramp CSE_PCR at the period T_eCh given by CLKech to produce the samples PCR_e. These samples PCR_e are sent on the network and circulate to the reception side via a network interface (bloc INTE). Figure 3 shows the reception side according to the prior art. The interface

IJPA recovers the PCR samples that have been sent on the network. These samples PCR_e are received via a network interface (module INTR) with a variable delay linked to the transport between the transmission device and the reception device: the module INTR produces samples PCR_r. The samples PCR_e, which are produced at printed regular T_eCh intervals on the transmission side, arrive at irregular intervals on the reception side: this is largely due to the jitter introduced during transport on the network. The samples PCR_r are taken into account at regular T_eCh intervals and hence, the majority of the jitter introduced during packet transport is eliminated. The imprecision between the transmission and reception sampling times is absorbed by a phase-locked loop PLL₁ whose bandwidth is appropriated. The characteristics of the phase-locked loop PLL₁ guarantee a reconstituted clock generation CLK_out-ι with a reduced jitter. The phase locked loop PLL₁ acts as a system receiving PCR_r samples and delivering: a reconstituted clock CLK-OUt₁, a counting ramp CSR-PCR₁ and, local samples PCRJoC₁.

When the phase locked loop PLL₁ operates in a steady state, the samples PCR_r are noticeably equal to the samples PCRJoC₁.

The reconstituted clock CLK-OUt₁ determines the rhythm of a CPT image counter similar to the image counter on the transmission side, for example a 40 ms counter. The counter CPT is reset each time the counting ramp CSR-PCR₁ crosses 0. Between two successive initialisations, the counter CPT progresses freely and produces an image cue that supplies a local Genlock generator, GEG to produce a reconstructed Genlock signal SG1 , SG2 designed to synchronise the cameras CAM1 , CAM2. The reconstructed Genlock signal SG1 , SG2 that is generated from the counting ramp CSR-PCR₁ and the reconstituted clock CLK-OUt₁ is in phase with the Genlock signal SGO on the transmission side, to the nearest clock pulse.

Figure 4 diagrammatically shows a first PLL₁ phase-locked loop architecture used in an I-IPA interface according to the prior art. As shown in figure 4a, the phase locked loop PLL₁ comprises:

- a sample comparator CMP₁ that compares the samples PCR_r and local samples delivering a comparison result of the samples , or an error signal ERR,

- a corrector COR₁ receiving the signal ERR and delivering a corrected error signal ERC, - a configurable digital oscillator VCO₁ receiving the corrected error signal

ERC and delivering a reconstituted clock CLK-OUt₁, the clock CLK-OUt₁ has a frequency F_out that depends on the signal ERC,

- a counter CPT-PCR₁ that produces a counting ramp CSR-PCR₁ according to a rate that is printed by a rerconstituted clock CLK-OUt₁ , - a support system with the value LATCH₁, that generates local samples

PCRJoC₁ from values of the counting ramp CSR-PCR₁ at instants T_eCh-

A non-restrictive embodiment of the corrector COR₁ is diagrammatically shown in Figure 5. The corrector COR₁ shown enables a loop PLL₁ for which the pulse response is of the second order. The corrector implements a method known as Zdan (but other methods known to those skilled in the art can be implemented). This type of corrector COR₁ enables having a null position and speed error in the direction of the servos.

The references a1 and a2 of the corrector COR₁ designating the coefficients whose values are chosen to obtain a stable system with a damping coefficient ξ chosen. For example, a1 =1250370 and a2=1247598. The values a1 , a2 for a set of coefficients that are constant in time. The reference INT designates an integration module charged with determining a configuration value (ERC(n), or corrected error signal, that must be used by the digital oscillator VCO₁ for the "n^th" sampling period Tec_h(n) considered. This integration module INT guarantees a null error speed. ERR(n) designates the comparison signal, or error signal, that has been determined by the comparison module CMP₁ for the current T_eCh(n) sampling period.

ERR(n-1 ) designates the comparison signal, or error signal, that has been determined by the comparison module CMP₁ for the preceding T_eCh(n-1 ) sampling period. Thus, in this example, the loop PLL₁ ensures a filtering that can be modelled as a low-pass filter of the order of 2. The order of the filter is defined by the architecture of the corrector COR₁.

Figure 4b shows a second PLL₁ phase-locked loop architecture used in an

IJPA interface according to the prior art. In this architecture, the set of coefficients (a1 , a2) is constant in time, the loop PLL₁ comprises a gain adjustment device DAG₁ that determines a gain value G that is added to the open loop gain G_BO according to the error signal ERR.

Figure 6 shows a PLL₁ phase-locked loop architecture used in an MPA interface according to the invention. In this embodiment, the corrector COR₁ receives a set of coefficients (a1 , a2) delivered by a cut-off frequency adjustment device DAC₁. The cut-off frequency of the loop PLL₁ changes from a first value f_c1 at the instant of start up of the phase locked loop to a second value f_C2 after a period τ in accordance with a first predefined temporal change law.

Advantageously, the device DAC₁ adjusts the cut-off frequency in accordance with a predefined first temporal change law.

Advantageously, the device DAC₁ delivers the updates of the set of coefficients (a^ a₂, ..., a_n) to the corrector COR₁ at a frequency 1/T_upd according to the second temporal change laws.

The device DAC₁ produces updates of the coefficients (a1 , a2) at a refreshment frequency equal to 1/T_upd where T_upd is the period that separates two successive updates of the set of coefficients. Each coefficient of the set of coefficients (a1 , a2) changes temporarily according to a second temporal change law.

Figure 7 shows the steps of the method for temporal adjustment of the value of the cut-off frequency of a phase locked loop PLL₁ according to the invention.

In what follows it is considered that the set of coefficients of the corrector CORi comprises 2 coefficients (a1 , a2).

On the top right quarter of figure 7 (ref. 7.1 ) is represented the first law of temporal change of the cut-off frequency f_c of the phase locked loop PLL₁ between fd and f_C2, where f_c1 is a cut-off frequency adapted to a transitory operating mode of the phase locked loop such as for example the acquisition phase and f_C2 is a cut-off frequency adapted to a permanent operating mode of the phase locked loop such as for example the continuation phase.

The origin of the abscissa corresponds to the start up of the reception device: the reference instant t=0 corresponds to the instant at which the reception device starts up. The temporal change of the cut-off frequency is frozen after a period τ. At the instant t=τ the value of the cut-off frequency is equal to f_C2-

The frequencies f_c1 and f_C2 are to be determined, a reception device architecture as the first temporal change law leads from f_c1 to f_C2- The temporal law is determined while taking account of different requirements, for example:

- a value of τ that is as short as possible in order to have the shortest transition possible,

- an easy to calculate temporal form, that enables a value of the cut-off frequency to be rapidly evaluated, without mobilizing resources currently being used. The purpose of this requirement is to avoid overloading the reception device with calculating means dedicated to the temporal calculation of the cut-off frequency,

- a "slow" change of the value of f_c of the reception device. This requirement favours a transition of the cut-off frequency without loss. If it is considered that the cut-off frequency is updated following the updating of the coefficient (a1 , a2), that is to say at a period T_upd, this constraint can also be expressed so that Δf_c that is the change f_c over a period T_upd or very much lower than a threshold related to a minimum value between f_c1 and f_C2- For example Δf_c must be less than 10% of the minimum value between f_c1 and f_c2. A first temporal change law of the cut-off frequency that is a polynomial function of an order equal to two, derived null for t=τ is perfectly adapted to the above requirements. For reasons of simplicity, figure 7 shows a first temporal change law of the cut-off frequency between f_c1 and f_C2 that is a polynomial temporal function of the order of 1.

On the upper left quarter of figure 7 (ref. 7.2), is reported the change in the values of the set of coefficients (a1 , a2) of the corrector CORi (horizontal axis directed towards the left) according to the value of cut-off frequency values considered in the 7.1 part of figure 7 (vertical axis directed towards the top). In fact, the architecture of the phase locked loop PLL₁ recognizes the relationship that links each of the coefficients (a-i, 8₂) to the cut-off frequency. An

example of such a relationship is a_x = — and

w_{here Av∞}

is the gain of the digital oscillator VCO₁. When these relationships are not simple to calculate, for example because they require digital calculation libraries as for example above, it is possible to approximate them on the interval between f_c1 and f_C2 by simple relaionships that do not require such libraries, for example the linear laws or the polynomial laws of the order 2.

Advantageously, the second temporal change laws of the set of coefficients (a-i, a₂, ..., a_n) are determined from an approximation of the relationships linking the coefficients (ai, a₂, ..., a_n) to the cut-off frequency value.

Finally, in the lower right quarter of figure 7 (ref. 7.3), are reported the second temporal change laws of the values of coefficients (a1 , a2) between the instants t=0 and t=τ.Each of these second laws is sampled at the frequency 1/T_Up_d: the corresponding samples constitute the updates of the set of coefficients and are transmitted to the corrector COR-i.

Advantageously, the second temporal change laws of the set of coefficients (ai, a₂ , ..., a_n) are polynomial functions of time.

Advantageously, the first change law is a polynomial function of time. Advantageously, the second temporal change laws are polynomial functions of time.

Claims

1. Reception device able to receive packets in a packet switching network, said device comprising:

- the means to receive packets from said network, said packets containing samples (PCR_r), said samples (PCR_r) coming from data sampled according to a sampling clock (CLKech) delivering pulses of a period T_eCh, said sampling clock (CLKec_h) being synchronized on devices belonging to said network.

- the means to regenerate a counting ramp (CSR_PCR-i) using a phase locked loop (PLL₁) receiving the samples (PCR_n) and also delivering samples (PCRJoci) every T_eCh period and a reconstituted clock (CLK-OUt₁),

- the means for initialising, at every zero-crossing of the counting ramp (CSR-PCR₁), an counter (CPT), the rhythm of which is determined by the reconstituted clock (CLK-OUt₁), the phase locked loop (PLL₁) being characterized by a cut-off frequency f_c, - a device for adjustment of the cut-off frequency (DAC₁) that temporarily adjusts the cut-off frequency of the phase locked loop, characterized in that the device (DAC₁) adjusts the cut-off frequency f_c in accordance with a predefined first temporal change law over a period τ.

2. Reception device according to claim 2, characterized in that the first temporal change law is a polynomial function of time.

3. Reception device according to one of claims 1 to 2, the phase locked loop (PLL₁) comprising: - a sample comparator (CMP₁) comparing the samples (PCR_r) and the local samples (PCRJoC₁) and delivering an error signal (ERR),

- a corrector (COR₁) receiving the signal (ERR) and delivering a corrected error signal ERC, the corrector (COR₁) being f=defined from a set of coefficients (a-i, a_n), - a digital oscillator (VCO₁) receiving the corrected error signal ERC and delivering the reconstituted clock (CLK-OUt₁), characterized in that the device (DAC₁) delivers updates of the set of coefficients (a^ a₂, ..., a_n) to the corrector (COR₁) at a frequency f =1/T_upd according to the second temporal change laws.

4. Reception device according to claim 3, characterized in that the second temporal change laws are polynomial functions of time.

5. Reception device according to claim 3, characterized in that Tupd is less than τ/10

6. Method for temporal adjustment of a cut-off frequency value of a phase locked loop (PLL₁), the loop (PLL₁) comprising a corrector COR₁ being defined from a set of coefficients (a^ a₂, ..., a_n), the cut-off frequency f_c of the loop PLL₁ being determined from the value of the set of coefficients

a₂, ..., a_n), characterized in that it comprises steps aiming to:

- determine a first cut-off frequency f_c1 adapted to a transitory operating mode of the loop (PLL₁) and a second cut-off frequency f_C2 adapted to a permanent operating mode of the loop (PLL₁),

- determine a first temporal change law of the cut-off frequency of the loop (PLL₁) for which the value of f_c1 changes to the value of f_C2 over a period τ,

- determine second temporal change laws for the set of coefficients (a^ a₂, ..., a_n) so that the cut-off frequency f_c of the loop (PLL₁) changes according to the first temporal law,

- adjust the value of the set of coefficients

a₂, ..., a_n) in accordance with said second temporal change laws at a frequency 1/T_upd.

7. Method for temporal adjustment of a cut-off frequency value according to claim 6, characterized in that the first change law is a polynomial function of time.

8. Method for temporal adjustment of a cut-off frequency value according to one of claims 6 or 7, characterized in that the second temporal change laws of the set of coefficients

a₂, ..., a_n) are detrermined from an approximation of the relationships linking the coefficients (a-i, a₂, ..., a_n) to the value of the cut-off frequency.

9. Method for temporal adjustment of a cut-off frequency value according to one of claims 6 to 8, characterized in that the second temporal change laws of the set of coefficients

a₂, ... , a_n) are polynomial functions of time.

10. Method for temporal adjustment of a cut-off frequency value according to one of claims 6 to 8, characterized in that Tupd is less than τ/10