WO2009140299A2

WO2009140299A2 - Self-stabilizing sensor circuit for resistive memories

Info

Publication number: WO2009140299A2
Application number: PCT/US2009/043661
Authority: WO
Inventors: Jolanta Celinska; Carlos A. Paz De Araujo; Christopher Randolph Mcwilliams
Original assignee: Symetrix Corporation
Priority date: 2008-05-12
Filing date: 2009-05-12
Publication date: 2009-11-19
Also published as: WO2009140299A3

Abstract

An integrated circuit resistance memory comprising: a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; a sensing circuit for sensing the resistance of the variable resistance element, the sensing circuit comprising a Wheatstone bridge circuit; and wherein the variable resistance element in the memory cell is electrically connectable to provide at least a portion of the resistance in one leg of the Wheatstone bridge circuit.

Description

SELF-STABILIZING SENSOR CIRCUIT FOR RESISTIVE MEMORIES BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to the field of resistive memories, and more particularly to a sensing circuit for such memories.

2. Statement of the Problem

There has been much research over the last ten to twenty years on memories based on certain materials that exhibit a resistance change associated with a change of phase of the material. In one type of variable resistance memory called an RRAM, a change in resistance occurs when the memory element is briefly melted and then cooled to either a conductive crystalline state or a nonconductive amorphous state. Typical materials vary and include GeSbTe, where Sb and Te can be exchanged with other elements of same properties on the periodic table. These materials are often referred to as chalcogenides. See, for example, Stephan Lai, "Current Status of the Phase Change Memory and Its Future", Intel Corporation,

Research note RN2-05 (2005); United States Patent No. 7,038,935 issued to Darrell Rinerson et al., May 2, 2006; United States Patent No. 6,903,361 issued to Terry L. Gilton on June 7, 2005; and United States Patent No. 6,841 ,833 issued to Sheng Teng Hsu et al., January 1 1 , 2005. Recently, a resistance switching field effect transistor has been disclosed using a Mott-Brinkman-Rice insulator, such as LaTiU3. In this material, according to the theory proposed, the addition of holes via an interface with a Ba₍i-χ₎SrχTiθ3 layer changes the material from an insulator to a conductor. See United States Patent No. 6,624,463 issued to Hyun-Tak Kim et al. on September 23, 2003. This FET uses the Mott-Brinkman-Rice insulator as the channel in the FET. However, no examples of fabrication of actual devices are given.

Another variable resistance memory category includes materials that require an initial high "forming" voltage and current to activate the variable resistance function. These materials include Pr_xCa_yMn_zO_ε, with x, y, z and e of varying stoichiometry, transition metal oxides, such as CuO, CoO, VO_x, NiO, TiO₂, Ta₂Os, and some perovskites such as Cr; SrTiθ3. See, for example, "Resistive Switching Mechanisms Of TiO₂ Thin Films Grown By Atomic-Layer Deposition", B. J. Choi et al., Journal of Applied Physics 98, 033715(2005), "Reproducible Resistive Switching In Nonstoichiomethc Nickel Oxide Films Grown By RF Reactive Sputtering For Resistive Random Access Memory Applications", Jae-Wan Park, et al., J. Vac. Sci. Technol. A 23(5), Sept/Oct 2005, "Influence Of Oxygen Content On Electrical Properties Of NiO films grown By RF Reactive Sputtering", Jae-Wan Park, et al., J. Vac. Sci. Technol. B 24(5), Sept/Oct 2006, "Nonpolar Resistance Switching Of Metal/Binary-Transition-Metal Oxides/Metal Sandwiches:

Homogeneous/inhomogeneous Transition of Current Distribution", I. H. lnone et al., arXiv:Cond-mat/07025Q4 v.1 26Feb2007, and United States Patent Application Publication No. 2007/01 14509 A1 , Memory Cell Comprising Nickel-Cobalt Oxide Switching Element, on an application of S. Brad Herner. These memories are referred to as ReRAMs, to distinguish them from the chalcogenide type memories.

Recently a resistance memory that operates on a purely quantum mechanical basis has been disclosed. This memory has been referred to as a correlated electron random access memory, or CeRAM, because the principal it relies on is the correlation of electrons via the coulomb force which results in a Mott transition which changes the resistance state of the electron system. See United States Patent Application Serial No. 1 1/937,461 filed November 8, 2007, which is incorporated herein by reference to the same extent as though fully disclosed herein. In the above memories, the resistance in the low resistance state is very small as compared to the resistance in the high resistance state. The low resistance state essentially creates a short circuit across the memory element, while the high resistance state essentially creates an electrical open circuit. This creates a problem with all of the above-mentioned resistance memories, since a sensing circuit that can detect that high resistance state will result in a very high current in the low resistance state, which high current can damage the memory.

It would be highly desirable to have a resistance memory that is stable throughout the read/write cycle and in which the memory can be read in the low resistance state without excessive current. If this was possible in a memory that had a read window large enough to be easily read with a commercially manufacturable sensing circuit, this would be a significant advance in the resistance memory art. SUMMARY OF THE INVENTION

A suggested solution to the above problem for a resistance memory that is not believed to be prior art, depends on filaments created by a forming circuit has been to use a limit the current using the saturation current of a MOSFET (metal oxide semiconductor field effect transistor). See "Sub-100-μA Reset Current of Nickel Oxide Resistive Memory Through Control of Filamentary Conductance by Current Limit of MOSFET", Yoshihiro Sato et al., IEEE Transactions on Electron Devices, Vol. 55, No. 5, May 2008, pp. 1 185-87. However, in manufacturable devices, the saturation current of a MOSFET is itself dependent on many variables. Moreover, the resistance change of the filament-type circuit is not as large as other resistance memories. In fact, because the low and high resistance states are not sufficiently separated, the read window is not large enough for a useful memory. For these and other reasons, the above solution still results in unacceptable instabilities that lead to small yields of useable devices. Thus, no commercially successful resistance memory is yet available.

The circuit configurations disclosed herein solves the above problems, as well as other problems of the prior art, at least by providing self-stabilizing sensing circuit and resistance memory with such a circuit, although other features will be apparent to one skilled in the art in light of this disclosure. In one embodiment a current limiting transistor is utilized to regulate the current in the variable resistor. In another embodiment, a Wheatstone bridge is incorporated into the sensing circuit. In one alternative, the memory is a chain cell memory with a Wheatstone bridge circuit provided for each column of the memory. In another alternative, the resistance element in each cell forms one leg of the Wheatstone bridge. In yet another alternative, resistance of the access resistor also is incorporated into this leg of the bridge.

The invention provides an integrated circuit resistance memory comprising: a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; and a sensing circuit for sensing the resistance of the variable resistance element; the resistance memory characterized by a current regulating circuit interconnected with the resistive switching cell, the current regulating circuit regulating the current through the resistance so that sufficient current to the resistance to switch the resistance when it is in the high resistance state and the current applied in the low resistance state is sufficiently limited to prevent damage to the variable resistance. Preferably, the current regulating circuit comprises a transistor. Preferably, the current regulating circuit includes a parameter analyzer for measuring an electrical parameter applied to the resistor. Preferably, the current regulating circuit comprises a Wheatstone bridge. Preferably, the variable resistance element comprises a correlated electron material.

The invention also provides a method of reducing reset current in a resistive memory, the method comprising: providing a resistive memory having a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; applying a reset voltage to the variable resistance element to change it from the low resistance state to the high resistance state; and applying a set voltage to the variable resistance element to change it from the high resistance state to the low resistance state; the method characterized by regulating the current flow through the variable resistance element so that sufficient current is applied to the resistance to switch the resistance when it is in the high resistance state and the current applied in the low resistance state is sufficiently limited to prevent damage to the variable resistance. Preferably, the regulating comprises adjusting the voltage across the variable resistance. Preferably, the regulating comprises limiting the current with a current limiting transistor.

The invention further provides a method of preventing snapback in a correlated electron random access memory cell, the method comprising: switching a resistive switching cell by applying a set-point voltage, wherein the resistive switching cell includes a correlated electron material (CEM), wherein the resistive switching cell is in a high resistance state before the switching and in a low resistance state after the switching; the method characterized by scaling the variable resistance element to reduce parasitic capacitance without significantly changing the resistance.

The invention also provides and integrated circuit resistance memory comprising: a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; and a sensing circuit for sensing the resistance of the variable resistance element; the resistance memory characterized by the sensing circuit comprising a Wheatstone bridge circuit; wherein the variable resistance element in the memory cell is electrically connectable to provide at least a portion of the resistance in one leg of the Wheatstone bridge circuit. Preferably, the variable resistance element comprises a correlated electron material. Preferably, the Wheatstone bridge comprises: a first leg and a second leg; the first leg having a first resistance, a second resistance, and a first node located between the first and second resistances, the first and second resistances being balanced; and the second leg including a resistance element and a third resistance, wherein RmO « R3 « Rm1 , where RmO is the resistance of the variable resistance element in the low resistance state and Rm1 is the resistance of the resistance element in the high resistance state. Preferably, the sensing circuit further comprises a shunt electrically connected in parallel with one leg of the Wheatstone bridge. Preferably, the shunt comprises an electronic component selected from the group consisting of a Schottky diode, a PN junction diode and a transistor.

The invention also provides a method of reading a resistance memory having a variable resistance element capable of existing in a low resistance state and a high resistance state, the method comprising: providing a Wheatstone bridge circuit having a first leg and a second leg; the first leg having a first resistance, a second resistance, and a first node located between the first and second resistances, the first and second resistances being balanced; and a second leg including the variable resistance element, a third resistance, and a second node located between the variable resistance element and the third resistance, wherein RmO « R3 « Rm1 , where RmO is the resistance of the resistance element in the low resistance state and Rm 1 is the resistance of the resistance element in the high resistance state; and reading the state of the variable resistance element by sensing an electrical parameter across the first node and the second node.

In one embodiment, a method of preventing snapback in a correlated electron random access memory cell, the method includes switching a resistive switching cell by applying a set-point voltage. The resistive switching cell includes a correlated electron material (CEM). The resistive switching cell is in a second state and in the second state the resistive switching cell has dielectric characteristics before the switching and in a first state exhibiting conductive characteristics after the switching. The method further includes regulating the current applied to the resistive switching cell to maintain a low current level, such that during the second state the capacitance of the resistive switching cell in minimized. In one alternative, the regulating of is accomplished using a transistor. In another alternative, the resistive switching cell is designed in order to minimize the dielectric capacitance. In another alternative, the size of the CEM material is minimized in order to reduce the dielectric capacitance. Optionally, the CEM material is approximately 100 micrometers squared.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram a CeRAM memory cell with current compliance; FIG. 2 is a graph of CEM scaling and compliance;

FIG. 3 is one embodiment of a 1T1 R NiO-CeRAM circuits; FIG. 4 is a graph of current vs. voltage for a 1T1 R CeRAM circuit; FIG. 5 is a diagram of a circuit diagram for a Wheatstone bridge; FIG. 6a shows the current in amperes versus bias voltage in volts curves for an NiO resistor;

FIG. 6b is the same curves as shown in FIG. 6a except on a logarithmic scale which shows higher resolution at the smaller values of current;

FIG. 7a illustrates a silicon wafer with CEM "elements" comprising a CEM material sandwiched between two electrodes; FIG. 7b shows a cross-sectional view of one of the "elements" of

FIG. 7a taken through the line 4-4 of FIG. 7a;

FIG. 8 shows an idealized current versus voltage curve for a resistive switching film with unipolar switching, illustrating the ON, OFF, RESET, and SET modes; FIG. 9 is an illustration of the energy bands of a Mott-Hubbard insulator taken from Introduction to the Electron Theory of Metals by Uichiro Mizutani;

FIG. 10 is a logic circuit diagram for an application of the CeRAM and Wheatstone Bridge;

FIG. 1 1 is a logic circuit diagram for an application of the CeRAM and Wheatstone Bridge;

FIG. 12 is a diagram of an array of logic circuits;

FIG. 13 is a memory cell including a variable resistor and a transistor; FIG. 14 is an example of an array of memory cells; FIG. 15 is a graph of current vs. voltage for a 5um x 5um CeRAM; FIG. 16 is a graph of the ON state resistance and OFF state resistance versus number of read/write cycles for a CeRAM memory element; FIG. 17(a) illustrates one embodiment of a modified Wheatstone bridge circuit utilizing a pn-diode shunt;

FIG. 17(b) illustrates one embodiment of a modified Wheatstone bridge circuit utilizing a Shottky diode shunt;

FIG. 18 is a hysteresis curve showing voltage versus current for a CeRAM memory element in the configuration of FIG. 17(b);

FIG. 19 is a hysteresis curve showing voltage versus current for a CeRAM memory element in the configuration of FIG. 17(a);

FIG. 20 is a graph of voltage versus current showing a SET pulse with a Wheatstone bridge current limiting circuit; FIG. 21 is a graph of voltage versus current showing a RESET pulse with a

Wheatstone bridge current limiting circuit according to one embodiment; and

FIG. 22 is a circuit diagram for one embodiment of a Wheatstone bridge with a NMOS.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The methods and apparatuses are described in detail in the following description. 1. Introduction

In a resistive memory, the resistance value tells if we have a logical "1 " or "0". When we have a Logical "0" the resistance is very low and behaves as an electrical short circuit. When we have a logical "1 " the resistance is very high and behaves as an electrical open circuit. The challenge is to implement a self-stabilizing sensing circuit that is also capable of limiting the current across the device during a write operation. For the purposes herein, the discussion will focus on, but is not limited to, the CeRAM device. 1.1. CeRAM Device Requirements

Because the two resistance states in the CeRAM are so drastically different, it is necessary to take care when switching the device from one state to another. For instance, when switching the CeRAM from the off state (Logical "1 ") to the on state (Logical'O") it is necessary to limit the current very precisely to ensure reliable switching without damaging the CeRAM. Alternatively, when switching the device from a "0" to a "1 ", it is important to allow enough current to flow through the CeRAM for the transition to occur as well as limiting the maximum current to a safe level. A graphical representation of this can be seen in FIG. 8. 1.2. Current Compliance (Regulation)

In one embodiment, current regulation may be imposed by a variable resistor. FIG. 1 shows an example of a configuration of a compliance circuit for a CEM memory device, TMO MIM cell 10. As can be seen in FIG. 1 , a parameter analyzer 13 analyzes the incoming parameters and sends a response signal 14 accordingly by managing the resistance of the variable resistance resistor 17. This current compliance mechanism is implemented in order to manage parasitic capacitance 16 resulting from cables and probes as well as dielectric capacitance in off state that causes a current "snapback" during set of the CEM material 15. As discussed herein, the scaling of the device will minimize parasitic capacitance while the on resistance stays constant. Good current compliance is needed for repeatable CEM operation. Current compliance adds to the precision of the set and reset point of the CEM device, especially the reset current. Furthermore, imposing a current compliance prevents burn-in of the CEM device, which might occur from the application of high voltages to the CEM device. The reset current may be controlled by imposing current compliance using a cell transistor. Reducing the stray capacitance between Pt/NiO/Pt and the cell transistor used as a current limiter may be desirable. In one embodiment, the parameter analyzer analyzes the current (and optionally the voltage) being applied to the circuit and adjusts the variable resistor accordingly in order to enable a low reset current for the CEM device.

FIG. 2 shows the results of scaling the CEM device to a very small size and applying a compliance mechanism. As can be seen by the graph, by applying a current compliance limit designated lcomp(A), the reset current of the CEM device can be reduced. In addition to the current compliance, the size of the CEM device affects the achievable reset current. As can be seen in FIG. 2, a lower reset current can be achieved by imposing current compliance for a CEM device of 10um by 10um as compared to a 20um device. 1.3. 1TIR CeRAM CeII

In a 1T1 R NiO-CeRAM circuits based the reset current (Ireset) may be suppressed by imposing current compliance (lcomp) using a cell transistor. Reducing the stray capacitance between Pt/NiO/Pt and the cell transistor used as a current limiter is crucial in this issue. FIG. 3 shows one embodiment of a 1T1 R CeRAM circuit including a transistor 32 and a CeRAM memory cell 31. It is of note that stray capacitance between Pt/NiO/Pt and a transistor in forms another current path which causes additional current, since it becomes short at the moment that the "forming" or "set" process takes place. The Ireset-lcomp characteristic approaches asymptotically to Ireset = lcomp if the current flowing through Pt/NiO/Pt during the "set" process can be limited ideally. This means that Ireset followed by the "set" process doesn't depend on the point 33 on the I-V plane (FIG. 4) but on the point 34, where the resistance of Pt/NiO/Pt jumps from the point 33 to the point 34 during the "set" process. Therefore, resistance of Pt/NiO/Pt is thought to continue decreasing after a jump at the point 33 until the current flowing through Pt/NiO/Pt reaches to lcomp at the point 34. Moreover, Ireset ~ lcomp means that the point 35, at which the "reset" process takes place, approaches to the point 34. Namely, additional current caused by an insufficient current limit results in notable difference between Ireset and lcomp observed before. The dependence Ireset-lcomp characteristic is dependent on the stray capacitance between Pt/NiO/Pt and a transistor. Asymptotical approach of Ireset to lcomp with decreasing the stray capacitance enables low Ireset and the multi-level application of CeRAM possible. 1.4. Wheatstone Bridge

In one embodiment, to meet the requirements of the CeRAM device, a modified Wheatstone Bridge circuit is used, with two balanced legs which form potential dividers. The total output of the circuit is given by Vout = vi - V2 and if all resistors are equal, Vout = OV. FIG. 5 shows the basic circuit diagram of the Wheatstone bridge. In the embodiment shown in FIG. 5 output v1 is a output 23 and output v2 is at output 26. A voltage source 21 provide voltage to the circuit. Resistors, 22, 24, 25, 20 control the output Vout In this example, the CeRAM resistor is resistor 20, however it could be located at any of the resistor areas.

For our purposes, we will be replacing resistor 20 with a CeRAM which will be referred to as Rm. Because the Wheatstone bridge configuration compares the ratio of R1/R2 to Rs/Rm, (resistor 22/ resistor 24 to resistor 25/ resistor 20) the maximum output variation (ΔV ) is achieved if Ri = R2, and R3 is chosen such that Rmo « R3 « Rmi . If these values are chosen correctly, vi = Vm/2, and OV <V2<Vm. With this large of a swing on the output, the read circuitry for a memory device is greatly simplified. Just as important as reading the present state of the device is appropriately limiting the current while toggling the state. For this task, the Wheatstone bridge configuration is also very useful. Given,

Where vi = VR∑ = ii_R2, and V2 = VR_m = i2><Rm

From Equation 1 you can see that by varying the resistance of R3 vou can linearly affect the current that can drop across Rm. Additionally, because the voltage applied to Rm during a set operation is a result of the voltage divider given by R3 and Rm, the moment the resistance of Rm changes from a high resistance state to a low resistance state, the voltage at that node drops. Because of this behavior, we end up with a situation where the current is precisely limited and the voltage necessary to switch the device is only applied to the device for as long as it takes to change states. 1.5. CeRAM background Nickel oxide, NiO, is disclosed as the exemplary transition metal oxide. The exemplary NiO materials discussed herein are doped with extrinsic ligands which stabilize the variable resistance properties. In general, this may be written as NiO(Lx), where Lx is a ligand element or compound and x indicates the number of units of the ligand for one unit of NiO. One skilled in the art can determine the value of x for any specific ligand and any specific combination of ligand with NiO or any other transition metal, simply by balancing valences. The preferred NiO variable resistance materials disclosed herein include at least a ligand containing carbon, which may indicated by NiO(Cx).

The preferred variable resistance materials discussed herein are Correlated Electron Materials. A Correlated Electron Material (CEM) is a material that switches from a first resistive state to a second resistive state, with the second resistive state having a resistance at least one hundred times higher than the first resistance state, and the change in resistance is primarily due to correlations between the electrons. Preferably, the CEM material changes from a paramagnetic conductive state to an anti-ferromagnetic insulative state when the Mott transition condition (nC)1/3a = 0.26 is reached, where nC is the concentration of electrons and "a" is the Bohr radius. More preferably, the resistance of the second state is at least two hundred times the resistance of the first state, and most preferably, five hundred times. Generally, these materials include any transition metal oxide, such as perovskites, Mott insulators, charge exchange insulators, and Anderson disorder insulators. Several embodiments representing switching materials are nickel oxide, cobalt oxide, iron oxide, yttrium oxide, and perovskites such as Cr doped strontium titanate, lanthanum titanate, and the manganate family including praesydium calcium manganate and praesydium lanthanum manganate. In general, oxides incorporating elements with incomplete d and f orbital shells exhibit CEM resistive switching properties. Preferably, resistance can be changed by setting at one voltage and resetting at a second voltage. Preferably, no electroforming is required to prepare a CEM. This disclosure contemplates that many other transition metal compounds can be used. For example, {M(chxn)2Br}Br2 where M can be Pt, Pd, or Ni, and chxn is 1 R,2R- cyclohexanediamine, and other such metal complexes may be used.

It is a feature that the conduction of the CEM materials is area independent. That is because the conduction is a quantum mechanical phenomenon and is related to the transition probability through the film. This conduction, G, is given by:

G = (q2pmpNiO/hm)T, where q is the electron charge, pm is the density of states in the electrode, pNiO is the density of states in the nickel oxide, m is the mass of the charge carrier, and T is the transmission probability through the film.

A number of advances to the technology of CEM materials is explained below. Briefly, these advances relate to a number of aspects of CEM memory materials. The discussion herein, includes, but is not limited to the following advances: the usage of a capping layer, annealing in methane, filamentary carbon in the surface, the usage of a graded extrinsic ligand, and the choice of electrodes.

FIG. 6a shows the current in amperes (amps) versus bias voltage in volts curves for an NiO(Cx) CEM. FIG. 6b shows the same curves except the absolute value of the current is plotted logarithmically to show more detail in the low current values. As has become the nomenclature in the art, the point at which the CEM changes in resistance from a conductor to an insulator is called the RESET point, while the point at which the resistance changes from an insulator to a conductor is called the SET point. Unlike other variable resistance materials, the CEMs are crystallized in the conducting state. We shall refer to this as the ON state and the insulative state will be called the OFF state. The solid line 40 is the ON state curve for positive voltages and the solid line 60 is the ON curve for negative voltages. The dotted line 54 is the OFF curve for positive voltages, while the dotted line 62 is the OFF curve for negative voltages. As the voltage is increased, the current rises at 47, until the RESET voltage is reached, which is about 0.65 volts, which is also the point at which critical electron density is reached, then, at point 48 the material suddenly becomes insulative and the current drops sharply along curve 49. The current stays low along the line 52 as the voltage rises until the SET voltage is reached at about 1.65 volts, which corresponds to the Neel temperature for these materials, at which point the material again becomes conductive and the current rises along line 54. If the voltage is returned to zero and then raised again when the CEM is in the insulative state, the current follows the line 44, while if the voltage is returned to zero after the material becomes conducting, that is after the VSET point, the current follows the line 47. It is evident from FIGS. 6a and 6b that the write memory window exists between VRESET and VSET, while the read memory window exists between the ON and OFF state current level. It is also evident from FIGS. 6a and 6b that these memory windows are easily large enough for a viable commercial memory. Thus, it can be seen that a CEM is a preferable VRM, though the architectures disclosed herein can be used with any variable resistance switching material. Turning now to FIGS. 7a and 7b, a silicon wafer 1 having CEM integrated circuit elements, such as 77 and 80 formed on it is shown. FIG. 7b shows a cross- section through element 80 taken through line 4-4 of FIG. 7a. Element 80 is formed on a silicon substrate 82 having a silicon dioxide coating 84. Optionally, a thin layer 86 of titanium or titanium oxide may be formed on oxide layer 84, though the elements reported on herein did not have such a layer. A bottom electrode layer 88 is formed on either layer 86 or directly on oxide layer 84. Layer 86 is an adhesion layer to assist the bottom electrode layer 88 in adhering to silicon dioxide layer 84. CEM material 90 (composed of a transition metal oxide is formed on bottom electrode 88, preferably by a liquid deposition process, such as spin coating, misted deposition, CVD or atomic layer deposition. The deposition of the CEM material will be described in greater detail below. Then top electrode 92 is formed on CEM layer 90. The elements 77, 80, etc. are then patterned by etching down to bottom electrode 88. The CEM material is subjected to a recovery annealing. Then an inter-layer dielectric 94 is deposited. At this point a contact vias 96 is added. Typically, integrated circuit formation techniques, known to those skilled in the art, may then be applied to the CEM Integrated circuit elements, such as interconnect metallization, further interconnection etching, passivation, etc. The CEM integrated circuit element appears to have no fundamental issues with mainstream metallization processes and materials that are know to those skilled in the art.

In one embodiment, the bottom electrode layer 88 may be formed of Titanium Nitride (TiN) and Tungsten (W). Alternatively, the electrode is formed with a layer of TiN, followed by a layer of W, followed by a layer of TiN. Alternatively, the bottom electrode layer 88 is formed by a 200 angstrom layer of TiN, a 200 angstrom layer of W, and a 200 angstrom layer of TiN.

After the CEM is deposited, it must be annealed. During the annealing process, due to oxidation, an interfacial dielectric layer may form over the bottom electrode. A purely tungsten electrode is oxidized by the annealing yielding an interfacial dielectric of over 1000 angstroms. A protective layer of titanium nitride provides some protection against oxidation and yields only a 100-200 angstrom thick interfacial dielectric as a result of annealing. The top electrode layer 92 may be formed of Titanium Nitride (TiN) and

Tungsten Aluminum (Al). In one alternative embodiment, the electrode is formed with a layer of TiN, followed by a layer of Al, followed by a layer of TiN. In one alternative embodiment, the top electrode layer 92 is formed by a 200 angstrom layer of TiN, a 200 angstrom layer of Al, and a 200 angstrom layer of TiN. The bottom electrode layer 88 and the top electrode layer 92 may be formed of platinum.

In another embodiment, a stack configuration of Si/SiO2/TiOx/Pt/NiO/Pt is used. In this case the top and bottom electrodes are formed of platinum (top electrode 92 and bottom electrode 88). The adhesion layer 86 is titanium oxide. In another embodiment, a stack configuration of Si/SiO2/ Pt/NiO/Pt is used, omitting the adhesion layer 86. In one alternative a top layer of TiN may be deposited over layer 92. This top layer is used as a hard mark. It may be in a range of thicknesses from 10nm to 200nm. In one alternative it is 60 nm thick.

The various elements 77, 88 can then be tested by attaching one probe to platinum surface 88 and touching a fine probe to the top electrode, such as 92, of the element to be tested, such as 80. The various curves discussed below were generated in this manner.

It should be understood that figures depicting integrated circuit devices are not meant to be actual plan or cross-sectional views of any particular portion of actual integrated circuit devices. In actual devices, the layers will not be as regular and the thicknesses may have different proportions. The various layers in actual devices often are curved and possess overlapping edges. The figures instead show idealized representations which are employed to explain more clearly and fully the method than would otherwise be possible. Also, the figures represent only one of innumerable variations of devices that could be fabricated using the designs and methods disclosed herein. As conventional in the art, the term "metal" when referring to an electrode or other wiring layer generally means a conductor. As known in the art, such "metal" electrodes and/or wiring layers can be made of polysilicon or other conductive material and are not necessarily made of metal.

FIG. 8 shows an idealized current versus voltage curve for a resistive switching film with unipolar switching, to better illustrate the ON, OFF, RESET, and SET modes. The material is crystallized in the ON state and the current rises along the ON curve as voltage is increased up VRESET. The current then drops to the OFF curve and increases gradually along the OFF curve until VSET is reached, at which point it increases toward the ON curve. However, in devices, the current is limited the dotted line, lset to prevent overcurrent. The read and write margins are shown in the figure. As shown by FIG. 8, the NiO(Cx) films follow these idealized curves better than any prior art material.

Some ligands may be less useful than others because they are not stabilizing under all circumstances. Preferably, ligands stabilize the orbital valence states, and particularly the 3d orbital states. For example, the complex [Ti(H2O)6]3+ is not stabilizing for conventional CMOS processing because when it is annealed the water evaporates leaving uncompensated titanium, which can take many different valence states. Such a material will require electroforming. However, it can be stabilizing in other processes.

The preferred ligands comprise one or more elements selected from the group consisting of oxygen, hydrogen, fluorine, carbon, nitrogen, chlorine, bromine, sulphur, and iodine. Some useful ligands for various metals are shown in Table I. In this table, the metal of interest is given in bold, followed by the formula for the complex the metal forms with the ligand of interest.

Aluminum [AI(OH)4]-

[AIF6]3- Cadmium [Cd(CN)4]2- cis-Cd(NH3)4CI2 trans-Cd(NH3)4CI2

Chromium Cr(acac)3 [Cr(CN)6]4- [Cr(en)3]3+ [CrF6]4- [Cr(NH3)6]3+ [Cr(OH2)6]3+

[CrO4]2- cis-Cr(acac)2(OH2)2 trans-Cr(acac)2(OH2)2 cis-[Cr(NH3)4CI2]+ trans-[Cr(NH3)4CI2]+

[Cr(NH3)5Br]2+ [Cr(NH3)5CI]2+ [Cr(NH3)5(0S03)]+ cis-[Cr(OH2)4C12]+ trans-[Cr(OH2)4C12]+

[Cr(OH2)5Br]2+ [Cr(OH2)5CI]2+ [Cr2O7]2- Cobalt [CoBr4]2-

[CoBr6]4- [CoCI4]2- [Co(CN)6]3- [Co(en)3]3+ [CoF6]3-

[Co(NH3)6]2+ [Co(NH3)6]3+ [Co(OH2)6]2+ [Co(03C)3]3- Cis[Co(en)2CI2]+ trans-[Co(en)2CI2]+ cis-[Co(OH2)4(SCN)2]+ trans-[Co(OH2)4(SCN)2]+ cis-[Co(NH3)4CI2]+ trans-[Co(NH3)4CI2]+ cis-Co(NH3)4(N02)2 trans-Co(NH3)4(N02)2 cis-Co(NH3)4(ONO)2 trans-Co(NH3)4(ONO)2 cis-[Co(ox)2(OH2)2]- trans-[Co(ox)2(OH2)2]- cis-[Co(en)2(N02)CI]+ trans-[Co(en)2(N02)CI]+ [Co(NH3)5CI]2+ [Co(NH3)5(N02)]2+ cis-[Co(NH3)Br(en)2]2+ trans-[Co(NH3)Br(en)2]2+

Copper [Cu(CN)2]- [Cu(NH3)4]2+ [Cu(OH2)6]2+ cis-[Cu(en)2(0H2)2]2+ trans-[Cu(en)2(OH2)2]2+

Gold

[Au(CN)2]- lron [Fe(CI4)-

[Fe(CN)6]3- [Fe(CN)6]4- Fe(CO)5 [Fe(EDTA]2- [Fe(en)3]3+

[Fe(OH2)6]2+ [Fe(OH2)6]3+ [fe(ox)3]3- [Fe(SCN)6]3- cis-[Fe(en)2(NO2)2]+ trans-[Fe(en)2(NO2)2]+ [Fe(OH)(OH2)5]2+

Manganese [MnCI6]4- [Mn(CN)6]3- [MN(CN)6]4- [Mn(en)3]2+

[Mn(OH2)6]2+ [MnO4]- Mercury [HgS2]2- [HgCI3]-

[Hgl4]2- Molybdenum [Mo04]2- Nickel [NiBr4]2-

[Ni(CN)4]2- Ni(CO)4 [Ni(en)3]2+ [Ni(NH3)4]2+ [Ni(NH3)6]2+

[Ni(OH2)6]2+ [Ni(ox)2]2- [Ni(penten)]2+ cis-Ni(en)2CI2 trans-Ni(en)2CI2

Palladium [PdCI4]2- Platinum [PtCI4]2- [PtCI6]2- [PtCI6]4- [Ptl4]2-

[Ptl6]2- [Pt(NH3)4]2+ Pt(en)CI2 cis-Pt(NH3)2CI2 trans-Pt(NH3)2CI2 cis-Pt(NH3)2CI4 trans-Pt(NH3)2CI4 Pt(NH3)2(ox) [Pt(NH3)3Br]+ trans-[Pt(NH3)4CI2]2+ cis-[Pt(NH3)4CI2]2+ cis-[Pt(NH3)4l2]2+ trans-[Pt(NH3)4l2]2+ Rhenium [ReO4]-

Rhodium [RhCI6]3- [Rhl2(CO)2]- cis[Rh(phen)2CI2]+ Ruthenium

[Ru(NH3)6]2+ [Ru(phen)3]2+ [Ru(NH3)5CI]2+ Silver [Ag(S2O3)2]3-

[Ag(NH3)2]+ Tin [SnCI6]2- [Sn(OH)6]2- [Sn(OH)3]- Titanium [TiO]2+

Vanadium [V(en)3]3+ [VO]2+ [VO2]+ [VOC I4]2-

Zinc

[Zn(CN)4]2- [Zn(NH3)4]2+

Table I Based on the above discoveries, Applicants have for the first time applied ligand field theory to the understanding of a resistance switching mechanism in transition metal compounds. Ligand field theory was developed in the 1930's and 1940's as an extension of crystal field theory. See for example, "Ligand Field Theory" in Wikepedia, the free encyclopedia at http://en.wikipedia.org/wik/Ligand _field theory, which is incorporated by reference herein to the same extent as though fully disclosed herein. As explained therein, the energy difference between certain molecular orbitals (MO's) is called ΔO, where the "O" stands of octahedral. This size of this energy difference, ΔO, determines the electronic structure of d orbitals. We have found that, in the thin-film regime used in the fabrication of the devices, the stability of the memory window between the OFF state and the on state is substantially proportional to the stability of ΔO. Thus, the preferred dopant ligands are those which result in a large and stable ΔO. Some useful dopant ligands in descending order of the size of the ΔO they create are: CO, CN-, PPh3, N02-, phen (1 ,10-phenanthroline, biby (2,2'-bipyridine), en (enthylenediamine), NH3, py (pyridine), CH3CN, NCS-, H20, C2O42-, OH-, F-, N3-, N03-, Cl-, SCN-, S2-, Br-, and I-. Theoretically, the crystal field splitting energy (ΔO) is not directly related to the Mott-charge transfer barrier or the Rice-Bhckman mass. But, the stability of the metal-native ligand coordination sphere allows the electron-electron correlations inductive of these transitions to occur in a particular material as the nuances of the bonding and crystal structures are set in place. In any case, the technical relevant effect is to control or stabilize the oxidation number (or coordination sphere) in such a way the local stoichiometry is "nominal" or otherwise suitable to induce the necessary electron correlation conditions.

"Extrinsic ligand" or "dopant ligand" is defined herein to be the ligand material added to transition metal complexes to stabilize the multiple valence states of the transition metals. The ligand splits the d-orbitals. We use the term "extrinsic" or "dopant" because the ligand complex is an extrinsic material added to the lattice that is not intrinsic to the lattice structure of the transition metal compound. For example, in NiO, the oxygen is an intrinsic ligand, and (CO)4, in forming Ni(CO)4, is the extrinsic ligand. Similarly, other variants such Ni5(CO)12 (nickel carbonate) include a form of CO as extrinsic ligands to the basic NiO lattice. This is analogous to the use of the term dopant in semiconductor technology. That is, in semiconductor technology adding a dopant to silicon, for example, does not change the silicon so much that we refer to it as another compound. Likewise, the dopant ligand added to say, nickel oxide, does not change the fact that the material is nickel oxide. But, local correction of the many possible oxidation numbers (valences) of Ni, such as Ni vacancies, interstitials and oxygen vacancies that modify the nominal "+2" valence value, is achieved with ligands that mediate with the intrinsic ligand yielding a stable net oxidation number and eliminate the defect induced change in charge state. In the Mott-Hubbard insulator of FIG. 9 ,when the density of electrons is small, U is small, and the d-orbitals 183, 192 and 184, 193 overlap forming a wide d band with few electrons, while the filled p-orbital 182, 191 is split from and below the d-band. The d-orbital thus behaves much like a metal, and the material is conducting. As the density of electrons becomes large, differences occur. When Δt is larger then U, the d-orbitals split into a pair of separated bands 189 and 190, and the p-orbital 188 remains below the d-orbital bands. When Δt is smaller than U, the p-orbital of the intrinsic ligand splits the d- orbital which tends to stabilize the d-orbital valence, yielding a net oxidation state of zero, for example, Ni+20-2. In such conditions, the insulator is a charge-transfer insulator, which leads to lower operating voltages. Thus, correlated electron systems in which Δt < U are preferred systems. One way of understanding the resistive change of the CEM materials can be seen most easily using FIG. 9. As indicated above, when the density of electrons is small, the two d-orbital bands 192 and 193 overlap and a conductor results. As the density of electrons increases, it will reach a point where the coulomb repulsion is so high that the d-orbitals 194 and 195 split with the filled p-orbital valence band between them. One d-orbital 194 is essentially filled, while the other 196 is empty. It requires a large amount of energy for electrons to jump from the lower band 194 into the upper band 196. And, even if a d-d transition could occur with the aid of a hole in the p-orbital band, this requires a higher voltage, which is useful in the insulator to metal transition but not in the metal to insulator transition. Thus, this material will be an insulator with high resistance when the lower voltage induces a metal to insulator transition purely caused by increasing the local density of electrons. However, when the electric field created by the applied voltage becomes large enough, some electrons will begin to jump to the upper band 196. This creates an overlap of the upper empty band and lower filled d- bands, the condition of a highly conductive state with small coulomb repulsion, and the system collapses back to the state shown at the left in FIG. 9. From FIG. 9, it is also clear that transitions can be made from the p-orbital to the d-orbital which create "holes", which can be filled by electrons from filled d-bands. The interaction of d-d orbital transitions is highly dependent on the existence of p-orbitals in these CEM compounds. The absence of an oxygen atom in the lattice induces a +2 charge, i.e., a doubly charged vacancy, which would be neutralized if the oxygen would return with its -2 valence. Since this does not happen once the defect is in place, the Ni or other transition metal no longer coordinates or bonds normally with the oxygen, Thus, the emission of up to two electrons into this positive potential, makes the Ni become +4, with the result that it is no longer useful for a Mott or charge transfer condition. It is at this point that mediation between the defect and an extrinsic ligand, re-establishes the oxidation state of the nickel. Without the ligand, the unbalanced, unstable insulative state is either heavily saturated with coordination destroying oxygen vacancies or equally detrimental and related excess nickel anions in interstitial sites in the lattice. The metal-ligand-anion (MLA) bond which stabilizes the correlated electron material in some embodiments can be formed in many ways. For example, it may be formed in an anneal or other reaction process. For example, the CEMs may be annealed in a gas that contains the ligand chemical element, the anion element, and preferably also includes both the ligand element and the anion. Any gas incorporating any of the ligands above may be used. The gas may be formed through conventional precursor vaporization processes, such as heating and bubbling. As another example, the CEM may be reactive sputtered in a gas containing the ligand chemical element, the anion or both. Again, any of the ligands above may be used. As an example, for NiO, with a carbon ligand and an oxygen anion, CO and CO2 are possible annealing gases. The anneal may be performed with one or more of these gases, or may be performed in a mixture of an inert gas, such as argon or nitrogen, with the gas containing either the ligand element, the anion element, or both. Alternative explanations for the experimentally observed phenomenon may be available. 1.6. Resistive Memory Function

In a resistive memory, the resistance value tells if we have a logical "1 " or "0." When we have a logical "0" the current is too high because the resistor is basically a short circuit (-60 Ω ). Current must be limited and the state detected at the same time.

From above, FIG. 5 shows a Wheatstone Bridge. If all resistances are balanced V₁ = O .

In one embodiment of a memory: R₂ = FET circuit that provides a variable resistance, resistor 25

R_x = Resistor from the resistive memory array (of any architecture), resistor 20

R ₌ EA When balanced

" R₁

For example:

(Set by circuit) Case i : R_x= R_[nsulatmR (State of bit is "1 ") Then V₂ « 0

The equivalent logic circuit for this example is shown in FIG. 10, where input 1010 is "1 ", input 1020 is "1 ", logic circuit 1030 yields an output 1040 of "0". Case 2: R = R_Conductive (state of bit is "0")

Then V₂ ≠ O → V₂ = "V

The equivalent logic circuit for this example is shown in FIG. 1 1 , where input 1 1 10 is

"0", input 1 120 is "1 ", logic circuit 1 130 yields an output 1 140 of "1 ".

R₁ could be set as equal to R_Conductne- But that would be a high current and high power. One can see, however, that the truth table would be:

R₂ Output

1 0 1 = Excusive OR circuit

1 1 0

0 0 0

Current Limiting Aspect

0 1 1

15 Since R = R₂R₃ R₁

Any change in R_x with respect to R₂ (adaptive with FET circuit) will be a constant, or in other words, ciR_x R₃ ΔR_x .

— ^ = ^ « — *- (Good noise margin)

JR₂ R, AR₂

But ΔR₂ is a function of the gate voltage of the FET (and peripheral biasing circuits). According to this embodiment, the swings in ΔR₂ and ΔR_x are limited by the

R₃ /R₁ ratio. This is a more controllable result than the prior art.

For array or any difficulties in balancing the array as you read a row (column)

(see FIG. 12), the R₂ (FET) can be adjusted to counteract the drop in voltage in a row (column). In FIG. 12 each intersection point is a CeRAM memory cell. For example, consider a simple array in which each cell includes a variable resistor and a transistor. An example of such a configuration is shown in FIG. 13, where column 1310 represents the column, row 1340 represents the row, 1320 is a transistor, and 1330 is a variable resistor (CeRAM cell).

Then, referring to FIG. 12, where (i = row, j = column) R_xQ + U) R_xQ, j + ^) R_xQJ)

KQJ-V In one example, a row may have only 8 cells, i.e., there are 8 columns in a row. In a commercial example, there would clearly be exponentially more cells. FIG. 14 shows an example of a memory unit with 8 cells. Each cell includes sense amplifiers 1445 (or Row Buffer), a bridge 1440 (Wheatstone bridge, see above FIG. 5 for more detail) and incoming voltage 1435 is "R₂ " or the voltage in the FET circuit which yields a resistance value. Resistor 1430 is the variable resistor (CeRAM) corresponding to each column, e.g. Rx(i, 1 ), Rx(i, 2)... Rx(i, 8). Row 1420 is denoted by i in the present example and the corresponding column is from 1-8 (Rx (row, column)). Figure 14 can be easily generalized for N-cells. Where V_F = FET circuit control voltage R-^l = dI_Ds /d V_Ds

Continuing now with the 8-bit example of FIG. 14: 1. V_Row turns on every "FET" in row;

²- ^v c_olumn drops for every R_x(i,j) , so bit 7 will give different results for R_x then bit

1 for example. 3. But, in the design, R₁ , R₃ or even R₂ (with a bit counting circuit connected to it) can be put into each bridge to correct for the voltage drop. That is, in the chain cell memory, each time a cell further down the chain is read or written to, there is an additional resistance, i.e., the resistance of the access transistors above the cell in the column, that is added to the resistance of the variable resistance R_x (i, j) of the cell. However, the size of the memory window and the ability to set R₁, R₃, and R₂ provide sufficient flexibility in the design, that the voltage drop across the access transistors will not affect the ability to read and write to each cell in the column. In the case of longer columns, a bit counting circuit can keep track of which cell along a column is being read or written to, and the voltage Vcoiu_mn can be adjusted to account for the voltage drop along the access transistors. In this resistance memory, the read operation is so fast that a read can be performed before writing to a cell, and the cell is written to only if the state of the cell is different from the state to be written. Thus, the cell is not continually rewritten to the same state. This prevents imprinting of the cell.

2. Circuit Verification and Lab Results

2.1. Device Properties

A typical 5_m x 5_m CeRAM structure with Hysteresis shown in FIG. 15 was used to test the feasibility of using a self stabilizing Wheatstone bridge circuit to program the state as well as provide a reliable means to read the state of a CeRAM memory cell. To provide an appropriate ratio for R₁/R₂, Ri = R2 = 1 MΩ. Taking the average of 50 cycles (Figure 16), the ratio of Ron/Rofffor a 5um x 5um CeRAM cell (Rm) is approximately 1/10000. This ratio is used to determine the appropriate value for R3 which for this case was chosen to be 2kΩ. This value for R3 provides adequate series resistance for limiting the current of a Set operation as well as meet the requirements outlined in the previous section for maximum Vout.

2.2. Diode Circuit

Because our structures show Bi-polar stability, it was possible to use a diode shunt in parallel with R3 in the modified Wheatstone bridge configuration so the cell could be current limited on a positive set pulse via the series resistance of R3 , and be unlimited on a negative reset pulse. To prove versatility in the design, a Schottky diode and pn-junction diode were both used as the shunt device (FIGS. 17A and 17B). These configurations give the Hysteresis as shown in figures 18 and 19. The voltage at Vout is used to read the state of Rm. After a known set sweep (Figure 20) Vout = 0.244V indicating a device in the ON state. Subsequently, after a known reset sweep (Figure 21 ) Vout =-0.24V indicating a device in the OFF state.

In FIG. 17A the circuit includes a voltage source 1710, resistors, 1715, 1720, 1725, v1 output 1735 and v2 output 1740, CeRAM 1730, and pn-junction diode 1745. In FIG. 17B the circuit includes a voltage source 1710, resistors, 1715, 1720, 1725, v1 output 1735 and v2 output 1740, CeRAM 1730, and Schottsky diode 1745. 2.3. Transistor Circuit

Though the diode circuit successfully performs as a shunt leg to meet the basic requirements of the CeRAM, it also introduced two new factors into the behavior of the circuit. Firstly, by using the diode in the circuit it became necessary to use positive and negative voltages to switch the CeRAM from state to state. Though this is very doable, it would increase the complexity of the design of the peripheral drive circuitry needed for a memory array. Secondly, the threshold voltage in the diode, though relatively small, is large enough to increase the voltage necessary in performing a reset operation, closing the write margin. As a solution to the issues presented by the diode circuit, an n-channel

MOSFET transistor was used as the shunt device. From the circuit in FIG. 22, it was possible to hold the gate at a bias allowing current to flow between the source and drain of the transistor during a reset operation, and also bring the gate to ground pinching off current flow and forcing the current to move through R3for a set operation. With this configuration and the appropriate timing circuits, it was possible to achieve a hysteresis closely resembling that of Figure 15. In FIG. 22 the circuit includes a voltage source 2210, resistors, 2215, 2220, 2225, v1 output 2235 and v2 output 2240, CeRAM 2230, and n-channel MOSFET transistor 2245.

Since certain changes may be made in the above systems and methods without departing from the scope of the disclosure, it is intended that all subject matter contained in the above description or shown in the accompanying drawings may be interpreted as illustrative and not in a limiting sense.

Claims

CLAIMS We claim:

1. An integrated circuit resistance memory comprising: a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; and a sensing circuit for sensing the resistance of said variable resistance element; said resistance memory characterized by a current regulating circuit interconnected with the resistive switching cell, said current regulating circuit regulating said current through said resistance so that sufficient current to said resistance to switch said resistance when it is in said high resistance state and the current applied in said low resistance state is sufficiently limited to prevent damage to said variable resistance.

2. The integrated circuit resistance memory of claim 1 wherein said current regulating circuit comprises a transistor.

3. The integrated circuit resistance memory of claim 1 wherein said current regulating circuit includes a parameter analyzer for measuring an electrical parameter applied to said resistor.

4. The integrated circuit resistance memory of claim 1 wherein said current regulating circuit comprises a Wheatstone bridge.

5. The integrated circuit resistance memory of claim 1 wherein said variable resistance element comprises a correlated electron material.

6. A method of reducing reset current in a resistive memory, said method comprising: providing a resistive memory having a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; applying a reset voltage to said variable resistance element to change it from said low resistance state to said high resistance state; and applying a set voltage to said variable resistance element to change it from said high resistance state to said low resistance state; said method characterized by regulating the current flow through said variable resistance element so that sufficient current is applied to said resistance to switch said resistance when it is in said high resistance state and the current applied in said low resistance state is sufficiently limited to prevent damage to said variable resistance.

7. The method of claim 6 wherein said regulating comprises adjusting the voltage across said variable resistance.

8. The method of claim 6 wherein said regulating comprises limiting said current with a current limiting transistor.

9. A method of preventing snapback in a correlated electron random access memory cell, the method comprising: switching a resistive switching cell by applying a set-point voltage, wherein the resistive switching cell includes a correlated electron material (CEM), wherein the resistive switching cell is in a high resistance state before the switching and in a low resistance state after the switching; said method characterized by scaling said variable resistance element to reduce parasitic capacitance without significantly changing the resistance.

10. An integrated circuit resistance memory comprising: a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; and a sensing circuit for sensing the resistance of said variable resistance element; said resistance memory characterized by said sensing circuit comprising a Wheatstone bridge circuit; wherein said variable resistance element in said memory cell is electrically connectable to provide at least a portion of the resistance in one leg of said Wheatstone bridge circuit.

1 1. An integrated circuit resistance memory as in claim 10 wherein said variable resistance element comprises a correlated electron material.

12. An integrated circuit memory as in claim 10 wherein said Wheatstone bridge comprises: a first leg and a second leg; said first leg having a first resistance, a second resistance, and a first node located between said first and second resistances, said first and second resistances being balanced; and said second leg including a resistance element and a third resistance, wherein RmO « R3 « Rm 1 , where RmO is the resistance of said variable resistance element in said low resistance state and Rm1 is the resistance of said resistance element in said high resistance state.

13. An integrated circuit resistance memory as in claim 10 wherein said sensing circuit further comprises a shunt electrically connected in parallel with one leg of said Wheatstone bridge.

14. An integrated circuit resistance memory as in claim 13 wherein said shunt comprises an electronic component selected from the group consisting of a Schottky diode, a PN junction diode and a transistor.

15. A method of reading a resistance memory having a variable resistance element capable of existing in a low resistance state and a high resistance state, said method comprising: providing a Wheatstone bridge circuit having a first leg and a second leg; said first leg having a first resistance, a second resistance, and a first node located between said first and second resistances, said first and second resistances being balanced; and a second leg including said variable resistance element, a third resistance, and a second node located between said variable resistance element and said third resistance, wherein RmO« R3 « Rm1 , where RmO is the resistance of said resistance element in said low resistance state and Rm 1 is the resistance of said resistance element in said high resistance state; and reading said state of said variable resistance element by sensing an electrical parameter across said first node and said second node.