[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2009034834A1 - セラミック多層基板及びその製造方法 - Google Patents

セラミック多層基板及びその製造方法 Download PDF

Info

Publication number
WO2009034834A1
WO2009034834A1 PCT/JP2008/065217 JP2008065217W WO2009034834A1 WO 2009034834 A1 WO2009034834 A1 WO 2009034834A1 JP 2008065217 W JP2008065217 W JP 2008065217W WO 2009034834 A1 WO2009034834 A1 WO 2009034834A1
Authority
WO
WIPO (PCT)
Prior art keywords
ceramic
multilayer substrate
electrode
inner conductor
ceramic multilayer
Prior art date
Application number
PCT/JP2008/065217
Other languages
English (en)
French (fr)
Inventor
Yoshiko Okada
Osamu Chikagawa
Hidekiyo Takaoka
Shodo Takei
Original Assignee
Murata Manufacturing Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co., Ltd. filed Critical Murata Manufacturing Co., Ltd.
Priority to JP2009532128A priority Critical patent/JP5293605B2/ja
Publication of WO2009034834A1 publication Critical patent/WO2009034834A1/ja
Priority to US12/720,745 priority patent/US8802998B2/en
Priority to US14/320,765 priority patent/US9370111B2/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02—Mountings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Ceramic Capacitors (AREA)

Abstract

　セラミック多層基板にチップ型セラミック部品を内蔵し、セラミック多層基板の表面にチップ型セラミック部品を搭載しても、チップ型セラミック部品とセラミック多層基板の内部導体や表面電極との接合強度を高めることができるセラミック多層基板を提供する。 　本発明のセラミック多層基板１０は、複数のセラミック層１１Ａが積層されてなるセラミック積層体１１と、セラミック積層体１１内に形成された内部導体１２と、セラミック積層体１１の上面に形成された表面電極１３と、内部導体１２または表面電極１３に外部電極１４Ａを介して接合されたチップ型セラミック部品１４と、を備え、内部導体１２または表面電極１３と外部電極１４Ａは接続電極１５を介して接合され、且つ、接続電極１５は内部導体１２、表面電極１３及び外部電極１４Ａの何れとも固溶している。
PCT/JP2008/065217 2007-09-10 2008-08-26 セラミック多層基板及びその製造方法 WO2009034834A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009532128A JP5293605B2 (ja) 2007-09-10 2008-08-26 セラミック多層基板及びその製造方法
US12/720,745 US8802998B2 (en) 2007-09-10 2010-03-10 Ceramic multilayer substrate and method for producing the same
US14/320,765 US9370111B2 (en) 2007-09-10 2014-07-01 Ceramic multilayer substrate and method for producing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007234771 2007-09-10
JP2007-234771 2007-09-10

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/720,745 Continuation US8802998B2 (en) 2007-09-10 2010-03-10 Ceramic multilayer substrate and method for producing the same

Publications (1)

Publication Number Publication Date
WO2009034834A1 true WO2009034834A1 (ja) 2009-03-19

Family

ID=40451845

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/065217 WO2009034834A1 (ja) 2007-09-10 2008-08-26 セラミック多層基板及びその製造方法

Country Status (3)

Country Link
US (2) US8802998B2 (ja)
JP (1) JP5293605B2 (ja)
WO (1) WO2009034834A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015018917A (ja) * 2013-07-10 2015-01-29 株式会社村田製作所 Ｐｔｃサーミスタ用外部電極ペーストおよびそれを用いたｐｔｃサーミスタ
JPWO2016052284A1 (ja) * 2014-09-30 2017-06-22 株式会社村田製作所 多層基板

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5693940B2 (ja) * 2010-12-13 2015-04-01 株式会社トクヤマ セラミックスビア基板、メタライズドセラミックスビア基板、これらの製造方法
CN104253884A (zh) * 2013-06-28 2014-12-31 深圳富泰宏精密工业有限公司 外壳及其制造方法
EP3541563B1 (de) 2016-11-18 2020-07-15 SMS Group GmbH Verfahren und vorrichtung zur herstellung eines kontinuierlichen bandförmigen verbundmaterials
KR102019790B1 (ko) * 2017-06-29 2019-09-09 주식회사 디아이티 층별 소재가 다른 다층 세라믹 기판 및 그의 제조 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1187918A (ja) * 1997-09-08 1999-03-30 Murata Mfg Co Ltd 多層セラミック基板およびその製造方法
JP2002110444A (ja) * 2000-09-26 2002-04-12 Murata Mfg Co Ltd 導電性ペーストおよび積層セラミック電子部品
JP2003168619A (ja) * 2001-09-20 2003-06-13 Murata Mfg Co Ltd 積層セラミック電子部品の端子電極用導電性ペースト、積層セラミック電子部品の製造方法、積層セラミック電子部品
JP2007194580A (ja) * 2005-12-21 2007-08-02 E I Du Pont De Nemours & Co 太陽電池電極用ペースト

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0632378B2 (ja) 1985-06-14 1994-04-27 株式会社村田製作所 電子部品内蔵多層セラミック基板
GB2197540B (en) * 1986-11-12 1991-04-17 Murata Manufacturing Co A circuit structure.
JPS63122295A (ja) 1986-11-12 1988-05-26 株式会社村田製作所 電子部品内蔵多層セラミツク基板
JP2529489B2 (ja) * 1991-07-09 1996-08-28 三菱電機株式会社 銅−ニッケル基合金
JP3129261B2 (ja) 1997-11-25 2001-01-29 株式会社村田製作所 多層セラミック基板の製造方法
US6241838B1 (en) * 1997-09-08 2001-06-05 Murata Manufacturing Co., Ltd. Method of producing a multi-layer ceramic substrate
US6074499A (en) * 1998-01-09 2000-06-13 South Dakoga School Of Mines And Technology Boron-copper-magnesium-tin alloy and method for making same
JP4136113B2 (ja) 1998-09-18 2008-08-20 Ｔｄｋ株式会社 チップ型積層電子部品
JP2000151104A (ja) 1998-11-11 2000-05-30 Sony Corp 多層基板
JP3391322B2 (ja) * 1999-12-10 2003-03-31 株式会社村田製作所 積層コンデンサ及びその製造方法
JP4683770B2 (ja) 2001-05-31 2011-05-18 京セラ株式会社 電気素子内蔵配線基板およびその製法
JP2003018619A (ja) * 2001-07-03 2003-01-17 Olympus Optical Co Ltd 立体映像評価装置およびそれを用いた表示装置
JP4596936B2 (ja) * 2004-02-26 2010-12-15 京セラ株式会社 ビア導体用導電性ペーストとこれを用いたセラミック配線板およびその製造方法
US20080078484A1 (en) * 2004-09-23 2008-04-03 Middlesex Silver Co. Limited Copper-Boron Master Alloy And Its Use In Making Silver-Copper Alloys
KR100790694B1 (ko) * 2006-06-30 2008-01-02 삼성전기주식회사 캐패시터 내장형 ｌｔｃｃ 기판 제조방법
US8501088B2 (en) * 2007-07-25 2013-08-06 Nippon Steel & Sumikin Materials Co., Ltd. Solder alloy, solder ball and electronic member having solder bump

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1187918A (ja) * 1997-09-08 1999-03-30 Murata Mfg Co Ltd 多層セラミック基板およびその製造方法
JP2002110444A (ja) * 2000-09-26 2002-04-12 Murata Mfg Co Ltd 導電性ペーストおよび積層セラミック電子部品
JP2003168619A (ja) * 2001-09-20 2003-06-13 Murata Mfg Co Ltd 積層セラミック電子部品の端子電極用導電性ペースト、積層セラミック電子部品の製造方法、積層セラミック電子部品
JP2007194580A (ja) * 2005-12-21 2007-08-02 E I Du Pont De Nemours & Co 太陽電池電極用ペースト

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015018917A (ja) * 2013-07-10 2015-01-29 株式会社村田製作所 Ｐｔｃサーミスタ用外部電極ペーストおよびそれを用いたｐｔｃサーミスタ
JPWO2016052284A1 (ja) * 2014-09-30 2017-06-22 株式会社村田製作所 多層基板

Also Published As

Publication number Publication date
US20140312539A1 (en) 2014-10-23
JP5293605B2 (ja) 2013-09-18
US20100155118A1 (en) 2010-06-24
JPWO2009034834A1 (ja) 2010-12-24
US9370111B2 (en) 2016-06-14
US8802998B2 (en) 2014-08-12

Similar Documents

Publication Publication Date Title
EP1739747A3 (en) Semiconductor chip and method of manufacturing the same
WO2010104744A3 (en) Electronic devices formed of two or more substrates bonded together, electronic systems comprising electronic devices and methods of making electronic devices
WO2008146487A1 (ja) 回路基板およびその製造方法
TW200737380A (en) Multilayer interconnection substrate, semiconductor device, and solder resist
WO2008143099A1 (ja) 積層配線基板及びその製造方法
EP2423948A3 (en) Lateral connection for a via-less thin film resistor and method of forming the same
WO2009105367A3 (en) Integrated circuit package and method of manufacturing same
TW200802690A (en) Three dimensional integrated circuit and method of making the same
WO2010116694A3 (en) Method of manufacturing semiconductor device
EP2693472A3 (en) Power semiconductor module and its method of manufacturing
WO2009034834A1 (ja) セラミック多層基板及びその製造方法
TW200737383A (en) Substrate with built-in chip and method for manufacturing substrate with built-in chip
WO2008129526A3 (en) Electronic interface apparatus and method and system for manufacturing same
WO2009011077A1 (ja) 半導体装置及びその製造方法
WO2011056306A3 (en) Microelectronic package and method of manufacturing same
JP2011071315A5 (ja)
EP2019577A4 (en) MULTILAYER MODULE WITH HOUSING
WO2008155967A1 (ja) 部品内蔵基板及びその製造方法
WO2011046809A3 (en) Ic package with non-uniform dielectric layer thickness
WO2009061789A3 (en) Methods of forming magnetic vias to maximize inductance in integrated circuits and structures formed thereby
WO2010116698A3 (en) Method of manufacturing semiconductor chip
WO2007070356A3 (en) Package using array capacitor core
WO2009037833A1 (ja) 立体プリント配線板およびその製造方法ならびに電子部品モジュール
WO2008111408A1 (ja) 多層配線基板及びその製造方法
WO2012060657A3 (ko) 신규 인쇄회로기판 및 이의 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08830855

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2009532128

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08830855

Country of ref document: EP

Kind code of ref document: A1