[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2009023462A1 - Semiconductor device and method for manufacturing thereof - Google Patents

Semiconductor device and method for manufacturing thereof Download PDF

Info

Publication number
WO2009023462A1
WO2009023462A1 PCT/US2008/072161 US2008072161W WO2009023462A1 WO 2009023462 A1 WO2009023462 A1 WO 2009023462A1 US 2008072161 W US2008072161 W US 2008072161W WO 2009023462 A1 WO2009023462 A1 WO 2009023462A1
Authority
WO
WIPO (PCT)
Prior art keywords
hole
electrode
semiconductor substrate
semiconductor device
forming
Prior art date
Application number
PCT/US2008/072161
Other languages
French (fr)
Inventor
Masataka Hoshino
Ryota Fukuyama
Koji Taya
Original Assignee
Spansion Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2007209980A external-priority patent/JP5302522B2/en
Application filed by Spansion Llc filed Critical Spansion Llc
Publication of WO2009023462A1 publication Critical patent/WO2009023462A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the discussed technology relates to a semiconductor device, and more particularly, to a semiconductor device provided with a through electrode which penetrates a semiconductor substrate, and a method for manufacturing thereof
  • Japanese Patent Application Publication No 2002-50738 (Document 1) and Japanese Patent Application Publication No 2005-19521 (Document 2) disclose the semiconductor device m which a through hole is formed in the semiconductor chip, and a through electrode separated from the semiconductor chip with the insulation member is disposed inside the through hole
  • the aforementioned semiconductor device may be electrically coupled with another semiconductor device or the interposer with the solder ball applied onto the connection electrode of the semiconductor chip
  • the step of forming the through electrode for connecting interconnections on the upper and the lower surfaces of the semiconductor chip is performed independently of the step of forming the solder ball for connecting the semiconductor chip to another semiconductor device or the interposer, resulting in the complicated manufacturing step and the increased manufacturing cost
  • the present invention was devised in light of the foregoing problems, and it is an attempt of the invention to provide a semiconductor device including a through electrode, which may be produced through the simplified manufacturing step, and the method for manufacturing thereof
  • a semiconductor device which includes a semiconductor substrate, a connection electrode disposed on an upper surface of the semiconductor substrate and connected to an integrated circuit on the semiconductor substrate, a through electrode which penetrates the semiconductor substrate and the connection electrode, and an insulation portion interposed between the semiconductor substrate and the through electrode
  • the through electrode is integrally formed to protrude outward from upper surfaces of the semiconductor substrate and the connection electrode, and connected to the connection electrode in a region where the through electrode penetrates the connection electrode
  • a method for manufacturing a semiconductor device including bonding a first support member formed of a support base material and a support adhesive agent on an upper surface of a semiconductor substrate provided with a connection electrode by directing the support adhesive agent downward, forming a first through hole which penetrates the semiconductor substrate, forming an insulation portion inside the first through hole, forming a second thiough hole which vertically penetrates the insulation portion and the connection electrode, and further penetrates the support adhesive agent inside the first through hole, and integrally forming a through electrode in a region corresponding to the semiconductor substrate, the connection electrode and the support adhesive agent inside the second through hole
  • FIGS 1 A through 1 E illustrate a method for manufacturing a semiconductor device according to a first embodiment
  • FlG 2 is a sectional view showing a structure of the semiconductor device according to the first embodiment
  • FIG 3 illustrates a method for manufacturing a semiconductor device according to a second embodiment
  • FIG 4 is a sectional view showing a structure of the semiconductor device according to the second embodiment
  • FIGS 5A through 5E illustrate a method for manufacturing a semiconductor device according to a third embodiment
  • FIGS 6A through 6F illustrate a method for manufacturing a semiconductor device according to a fourth embodiment
  • FIG 7 is a sectional view showing a structure of the semiconductor device according to the fourth embodiment.
  • FIGS 8A through SE illustrate a method for manufacturing a semiconductor device according to a fifth embodiment
  • FIG 9 is a sectional view showing a structure of the semiconductor device according to the fifth embodiment
  • FIGS 1 OA through 1 OC illustrate a method for manufacturing a semiconductor device according to a comparative example of the fifth embodiment
  • FIQ 11 is a sectional view showing a structure of a semiconductor device according to a sixth embodiment
  • FIG 12 is a sectional view showing an enlarged portion of the view shown in FIG 1 1,
  • FIG 13 is a sectional view showing a structure of another semiconductor device according to the sixth embodiment (part 1), and
  • FIG 14 is a sectional view showing a structure of another type of the semiconductor device according to the sixth embodiment (part 2)
  • FIGS IA through I E are cross-sectional views showing an enlarged portion around a through electrode of the semiconductor device according to the first embodiment
  • an interconnection 13 formed of copper, aluminum, or the like, and an interconnection layer 16 formed of an insulation layer 15 formed of a silicon oxide or the like are formed on the upper surface of a semiconductor substrate 14 formed of silicon
  • the interconnection layer 16 contains a connection electrode 12 as a region where a through electrode 20 (not shown in Fig IA, see FIG IE) is formed in the subsequent step of a manufacturing method
  • the connection electrode 12 is formed to be directly connected to the through electrode 20 (see FIG 2) to be described later
  • the interconnection layer 16 partially forms an integrated circuit (the circuit including the transistor or memory, for example) formed on the semiconductor substrate 14, and is electrically coupled with the connection electrode 12
  • a first support member 43 formed by applying a support adhesive agent 42 as an acrylic adhesive agent to a support base material 40 formed of a polyester is bonded to an upper surface of the semiconductor substrate 14 by directing the side of the support adhesive agent 42 downward
  • the first support member 43 is provided for supporting the semiconductor substrate 14 and the interconnection layer 16 in the subsequent step of forming a through hole
  • the first support member 43 may be formed of any material so long as the same function as described above is obtained
  • the support adhesive agent 42 has a predetermined thickness (for example, 20 mm) to allow the through electrode to protrude from the upper surface of the semiconductor substrate 14 in the subsequent step
  • a first through hole 32 is formed in the semiconductor substrate 14 so as to at least penetrate therethrough
  • the first through hole 32 may have any cross section shape (in parallel with the upper surface of the semiconductor substrate 14) but is required to have the size (for example, circle with a diameter of 40 mm) which accommodates the through electrode inside the first through hole 32 in the subsequent step
  • the first through hole 32 may be formed to the region in contact with the interconnection layer 16, or to penetrate the interconnection layer 16
  • the first through hole 32 is formed through the laser irradiation or dry etching to eliminate the corresponding portion of the semiconductor substrate 14 from the lower surface thereof Alternatively, the lower surface of the semiconductor substrate 14 is polished to have the predetermined thickness so as to form the first through hole 32
  • the total thickness of the semiconductor substrate 14 and the interconnection layer 16 is set to 50 mm
  • an insulation portion 30 is applied to an inner surface of the first through hole 32 and the lower surface of the semiconductor substrate 14
  • the insulation portion 30 is formed in order to electrically insulate the through electrode 20 (not shown in FIG 1C, see FIG IE) formed in the step (to be described later) from the semiconductor substrate 14, and is formed of such member as a resin, an oxide film and a nitride film is applied at least to an entire inner surface of the first through hole 32
  • the insulation film 30 may be formed as a thin film through a chemical vapor deposition (CVD) process so as to be applied to the inner wall of the first through hole 32 (see FIG 1C)
  • such portion may be formed by coating a liquid insulation member (spin coat, for example)
  • spin coat for example
  • a second through hole 34 is formed inside the first through hole 32 to vertically penetrate the insulation portion 30 and the connection electrode 12, and to further penetrate the support adhesive agent 42
  • the second through hole 34 may be formed by combining a hollow portion inside the first through hole 32 resulting from etching of the insulation portion 30 on the upper surface of the first through hole 32 and a hollow portion separately formed as shown in FIG 1 D
  • the second through hole 34 is formed so as to penetrate at least the semiconductor substrate 14, the connection electrode 12, and the support adhesive agent 42 to reach the support base material 40 from the lower surface of the semiconductor substrate 14
  • a cross section of the second through hole 34 may have any shape, but is required to have the size smaller than that of the first through hole 32 As shown in the drawing, it is preferable to form the second through hole 34 to reach the region in contact with the support base material 40 However, the second through hole 34 may be formed to penetrate the support base material 40 to a slight extent The second through hole 34 is formed through the laser irradi
  • the through electrode 20 is formed inside the second through hole 34 so as to be electrically coupled with the connection electrode 12
  • the through electrode 20 is integrally formed with the region corresponding to at least the semiconductor substrate 14, the connection electrode 12 and the support adhesive agent 42 inside the second through hole 34
  • the through electrode 20 is electrically coupled with the connection electrode 12 at the portion where the through electrode 20 penetrates the connection electrode 12
  • the member with high conductivity such as copper it is preferable to use the member with high conductivity such as copper for forming the through electrode 20
  • the through electrode 20 is formed by filling the copper paste 22 in the second through hole 34 from the lower surface
  • the through electrode 20 may also be formed through the plating
  • the support base material 40 and the support adhesive agent 42 are eliminated after forming the through electrode 20 As a result, the upper portion of the through electrode 20 protrudes from the upper surfaces of the semiconductor substrate 14 and the connection electrode 12 to be formed as a bump 21
  • a semiconductor device 100 according to the first embodiment is then produced in the aforementioned steps
  • FIG 2 is a sectional view of the semiconductor device 100 according to the first embodiment
  • the connection electrode 12 is formed on the upper surface of the semiconductor substrate 14 and electrically coupled with the interconnection layer 16 which partially forms an integrated circuit
  • the through electrode 20 is formed in the semiconductor substrate 14 to penetrate through the semiconductor substrate 14 as well as the connection electrode 12
  • the through electrode 20 is integrally formed to penetrate the semiconductor substrate 14 and the connection electrode 12 vertically from the lower surface of the semiconductor substrate 14, and to protrude from the upper surfaces of the semiconductor substrate 14 and the connection electrode 12
  • the through electrode 20 contacts the connection electrode 12 so as to be electrically coupled therewith in a region 19, where the penetration electrode 20 penetrates the connection electrode 12
  • the insulation portion 30 formed of the insulating resin is applied to the space between the semiconductor substrate 14 and the through electrode 20, and the lower surface of the semiconductor substrate 14
  • the semiconductor device 100 includes the first through hole 32 which penetrates the semiconductor substrate 14
  • the insulation portion 30 is formed on the inner surface of the first through hole 32
  • the second through hole 34 which vertically penetrates the insulation portion 30 is formed
  • the insulation portion 30 may be formed as the film as shown in the drawing, or formed by filling the first through hole 32 to be described later
  • the through electrode 20 is provided inside the second through hole 34
  • the upper portion of the through electrode 20 protrudes from the upper surfaces of the semiconductor substrate 14 and the connection electrode 12 to form the bump 21
  • the through electrode 20 protrudes from the upper surface of the semiconductor device 100, it may be easily brought into contact with the electrode of another semiconductor device or interposer
  • the bump 21 may be crushed in contact with such surface to absorb the irregularity in the height of the connection surface
  • the semiconductor device 100 may be connected to another semiconductor device or the interpose in the stable manner
  • the through electrode 20 may be formed to have any structure so long as it protrudes at least from the upper surface of the semiconductor device 100 so as to be electrically coupled with the electrode of another semiconductor device or the interposer
  • the through electrode 20 may be structured to protrude from the upper surface of the insulating resin which covers the upper surfaces of the semiconductor substrate 14 and the interconnection layer 16 (connection electrode 12
  • the etching is performed not only to the insulation portion 30 and the connection electrode 12 but also to the support adhesive agent 42 upon formation of the second through hole 34 for forming the through electrode 20
  • the bump 21 is formed in the region corresponding to the support adhesive agent 42 in the second through hole 34 simultaneously with formation of the through electrode 20
  • the through electrode 20 is electrically coupled with the connection electrode 12 in the region where the through electrode 20 penetrates the connection electrode 12
  • the formation of the through electrode 20 and the bump 21 , and the electrical coupling between the through electrode 20 and the connection electrode 12 may be peif ⁇ med in a single step, thus simplifying the manufacturing step
  • the process which uses the support base material 40 and the support adhesive agent 42 does not require formation of a mask for forming the bump 21 , thus reducing a manufacturing cost
  • connection electrode 12 is not limited to the aforementioned structure
  • connection electrode 12 may be formed separately from the interconnection 13 according to the fifth embodiment to be described later Second Embodiment
  • FIG 3 illustrates a method for manufacturing a semiconductor device according to a second embodiment and corresponds to FIG IE according to the first embodiment
  • the manufacturing steps p ⁇ or to the one corresponding to those shown m FIG 3 are the same as those of the manufacturing steps of the first embodiment, and explanations thereof, thus will be omitted
  • a bonding paste 26 as a solder paste is buried in a region corresponding to the support adhesive agent 42 above the second through hole 34
  • a copper paste 22 is then filled in the second through hole 34
  • the support base material 40 and the support adhesive agent 42 are eliminated to produce a semiconductor device 102 according to the second embodiment
  • FIG 4 is a sectional view showing the structure of the semiconductor device 102 according to the second embodiment
  • the first bonding bump 24 is formed on the upper surface of the through electrode 20 It is preferable to set the planar size of the first bonding bump 24 to be equal to or smaller than that of the through electrode 20
  • the other structure is the same as that of the first embodiment, and the explanation thereof, thus will be omitted
  • the semiconductor device 102 according to the second embodiment has the first bonding bump 24 formed on the upper surface of the through electrode 20
  • the melting point of the first bonding bump 24 is lower than that of the through electrode 20 so as to be mechanically and electrically connected to the electrode of another semiconductor device or the interposer This makes it possible to improve the stability on the connection surface compared with the connection by only the through electrode 20
  • the first bonding bump 24 is formed using the second through hole 34 for forming the through electrode 20 Therefore, the mask for forming the first bonding bump 24 is not required to be formed, thus simplifying the manufacturing step and reducing the cost
  • the solder of tm-silvei type or tin-silver-copper type is used for forming the first bonding bump 24
  • the bonding paste 26 is filled in the second through hole 34 to form the first bonding bump 24
  • the first bonding bump 24 may be formed through plating Third Embodiment
  • FIGS 5 A through 5E illustrate a method for manufacturing a semiconductor device according to a third embodiment and correspond to FIGS IA to IE according to the first embodiment
  • the same structures as those of the first embodiment will be designated with the same codes, and the explanations thereof, thus will be omitted
  • a first support member 43a having a stopper layer 44 interposed between the support base material 40 and the support adhesive agent 42 is bonded to the upper surface of the semiconductor substrate 14 by directing the support adhesive agent 42 downward
  • the stopper layer 44 serves to stop etching in the step of forming the second through hole 34 to be described later
  • the stopper layer 44 is formed of the member which is unlikely to be etched through laser irradiation or dry etching, for example, the metal layer formed of copper
  • the steps for forming the first through hole 32 and forming the insulation portion 30 on the inner surface of the first through hole 32 are the same as those described in the first embodiment
  • the second through hole 34 which penetrates the insulation portion 30, the connection electrode 12 and the support adhesive agent 42 to reach the stopper layer 44 is formed inside the first through hole 32 as shown in FIG 5D Likewise the first embodiment, the second through hole 34 is formed through laser irradiation or dry etching The etching is blocked by the stopper layer 44 formed of the material which is unlikely to be etched Therefore, the second through hole 34 is formed from the lower surface of the semiconductor substrate 14 to the lower surface of the stopper layer 44 without penetrating the stopper layer 44
  • the copper paste 22 is filled into the second through hole 34 as shown in FIG 5E to form the through electrode 20
  • the first support member 43a formed of the support base material 40, the support adhesive agent 42 and the stopper layer 44 is eliminated to produce the semiconductor device according to the third embodiment
  • the structure of the semiconductor device according to the third embodiment is the same as that of the semiconductor device 100 according to the first embodiment as shown in FIG 2
  • the use of the first support member 43a having the stopper layer 44 interposed between the support base material 40 and the support adhesive agent 42 allows the stopper layer 44 to block etching for forming the second through hole 34 This may prevent the support base material 40 from being penetrated upon the etching, thus allowing the second through hole 34 to be formed in the stable manner
  • the height of the bump 21 of the through electrode 20 may be set to the predetermined value Fourth Embodiment
  • FIGS 6A through 6F illustrate a method for manufacturing a semiconductor device 104 according to the fourth embodiment
  • the same structures as those described in the first to the third embodiments will be designated with the same codes, and the explanations thereof, thus will be omitted In the process shown in FIGS 6A and 6B corresponding to that shown in FIGS 5A and
  • the first support member 43a including the stopper layer 44 is bonded to the upper surface of the semiconductor substrate 14, and the first through hole 32 is formed in the semiconductor substrate 14
  • the insulation portion 30 is formed on the inner surface of the first through hole 32 and the lower surface of the semiconductor substrate 14 as shown in FlG 6C Thereafter, a second support member 36 as a polyimide tape is bonded to the lower surface of the semiconductor substrate 14 via the insulation portion 30
  • the second support member 36 serves to support the semiconductor substrate 14 in place of the first support member 43a in the step of forming the second bonding bump to be described later
  • the second support member 36 is formed of the member which resists the temperature (for example, 230 c C) to form the bonding bump
  • the second through hole 34 which penetiates the second support member 36, the insulation portion 30, the connection electrode 12 and the support adhesive agent 42 is formed as shown in FIG 6D
  • the second through hole 34 in the support adhesive agent 42 may be formed to have the size different from that of the second through hole 34 in the second support member 36
  • the copper paste 22 is filled in the second through hole 34 using the second support member 36 as a mask to form the through electrode 20
  • the second support member 36 prevents the contact between the copper paste 22 and the insulation portion 30 on the lower surface of the semiconductor substrate 14
  • the second support member 36 supports the semiconductor substrate 14, thus preventing the crack of the semiconductor substrate 14
  • a second bonding bump 28 is then formed on the lower surface of the through electrode 20 using the second support member 36 as a mask
  • the second bonding bump 28 may be formed by printing the bonding paste 26 on the lower surface of the semiconductor substrate 14 and performing the reflow at 230 0 C for 5 minutes Thereafter, the second support member 36 is peeled off to eliminate the copper paste 22 and the bonding paste 26 adhered on the lower surface of the second support member 36 simultaneously In this manner, a semiconductor device 104 according to the fourth embodiment is produced
  • FIG 7 is a sectional view showing the structure of the semiconductor device 104 according to the fourth embodiment
  • the second bonding bump 28 is formed on the lower surface of the through electrode 20
  • the planar size of the second bonding bump 28 is smaller than that of the through electrode 20
  • the other structures of the embodiment are the same as those of the first embodiment as shown in FIG 2, and the explanations thereof, thus will be omitted
  • the semiconductor device 104 according to the fourth embodiment is provided with the second bonding bump 28 on the lower surface of the through electrode 20
  • the second bonding bump 28 makes it easy to connect the semiconductor device 104 to another semiconductor device or the interposer
  • the copper paste 22 is filled to form the through electrode 20 using the second support member 36 as a mask
  • the photo mask may be used for forming the through electrode 20 to prevent adhesion of the copper paste 22 to the insulation portion 30 formed on the lower surface of the semiconductor substrate 14
  • the use of the photo mask requires the cost higher than the one required by the use of the second support member 36 as the mask, thus reducing the manufacturing costs
  • the mask for forming the second bonding bump 28 is not required to be formed This makes it possible to simplify the manufacturing step and to reduce the manufacturing costs
  • FIGS 8A through 8E illustrate the step of manufacturing a semiconductor device 105 according to the fifth embodiment
  • FIGS 8A through 8E illustrate the step of manufacturing a semiconductor device 105 according to the fifth embodiment
  • the interconnection layer 16 is formed on the upper surface of the semiconductor substrate 14 as shown in FIG 8A
  • a first through hole 32a which penetrates the interconnection layer 16 and the semiconductor substrate 14 is formed from the upper surface to the lower surface of the semiconductor substrate 14
  • the first through hole 32a is tapered toward the lower surface of the semiconductor substrate 14
  • the first through hole 32a may be formed through laser irradiation or dry etching
  • connection electrode 12 connection electrode 12
  • I he insulation portion 30 is formed inside of the first through hole 32a and on the lower surface of the semiconductor substrate 14 as shown in FIG 8C Unlike the first to the fourth embodiments, inside the first through hole 32a is filled with the insulation portion 30, which is formed of an organic insulating resin, for example
  • the insulation portion 30, the bonding layer 29 (connection electrode 12) and the support adhesive agent 42 are eliminated from the lower surface to the upper surface of the semiconductor substrate 14 to form a second through hole 34a as shown in FIG 8D
  • the second through hole 34a is tapered in the direction from the lower surface to the upper surface of the semiconductor substrate 14
  • the second through hole 34a is formed through laser irradiation or dry etching from the lower surface thereof
  • the first through hole 32a and the second through hole 34a are formed from the opposite directions
  • the second through hole 34a is filled with the copper paste 22 to form a through electrode 20a as shown in FlG 8E Thereafter, the first support member 43 formed of the support base material 40 and the support adhesive agent 42 is eliminated to produce a semiconductor device 105 according to the fifth embodiment
  • FIG 9 is a sectional view showing the structure of the semiconductor device 105 according to the fifth embodiment
  • the first through hole 32a is tapered in the direction from the upper surface to the lower surface of the semiconductor substrate 14
  • the second through hole 34a is tapered in the direction from the lower surface to the upper surface of the semiconductor substrate 14
  • the second through hole 34a is provided with the through electrode 20a so as to be connected to the connection electrode 12 via the bonding layer 29 Likewise the second through hole 34a, the through electrode 20a is tapered in the direction from the lower surface to the upper surface of the semiconductor substrate 14
  • the insulation portion 30 is provided so as to fill the first through hole 32a
  • the other structures are the same as those of the first embodiment, and the explanations thereof, thus will be omitted
  • FIGS 1 OA through 1OC illustrate the part of the step of manufacturing the semiconductor device as a comparative example of the fifth embodiment and correspond to FIGS 9A through 9D
  • the etching is performed from the lower surface of the semiconductor substrate 14 to form the first through hole 32b as shown in FIG 1 OA
  • the first support member 43 is bonded to form the bonding layer 29 and the insulation portion 30 as shown in FIG I0B
  • the etching is performed from the lower surface of the semiconductor substrate 14 again to form the second through hole 34b as shown in FIG 1OC
  • both the first and the second through holes 32b and 34b are formed by etching from the lower surface of the semiconductor substrate 14 as shown in FIG 1OC
  • the resultant through hole is likely to be tapered in the direction away from the surface where the etching starts
  • both the first and the second through holes 32b and 34b are likely to be tapered in the direction from the lower surface to the upper surface of the semiconductor substrate 14
  • the insulation portion 30 applied on the side surface of the first through hole 32b may be cut in the course of the etching for forming the second through hole 34b to expose the semiconductor substrate 14
  • FIG 1 OC shows that the insulation portion 30 is overetched due to ⁇ ghtward displacement of the laser irradiation axis upon formation of the second through hole 34b to expose the semiconductor substrate 14 around a region 17
  • the aforementioned case is likely to occur especially when the first through hole 32b has the diameter close
  • the first through hole 32a is formed from the upper surface to the lower surface of the semiconductor substrate 14, and the second through hole 34a is formed from the lower surface to the upper surface
  • the resultant first through hole 32a is tapered in the direction from the upper surface to the lower surface
  • the second through hole 34a is tapered in the direction from the lower surface to the upper surface This makes it possible to prevent the insulation portion 30 formed on the side surface of the first through hole 32a from being cut by etching upon formation of the second through hole 34a
  • the etching for forming the second through hole 34a is performed from the direction opposite the direction of etching for forming the first through hole 32a This makes it possible to effectively insulate the through electrode 20 from the semiconductor substrate 14
  • the special device for IR radioscopy or positioning from the lower surface is required
  • the etching to form the first through hole 32a is performed from the upper surface of the semiconductor substrate 14 This makes it possible to easily perform the positioning without using the aforementioned special device
  • the positioning for etching to form the second through hole 34a may also be easily performed in reference to the first through hole 32a
  • the inspection whether or not the insulation portion 30 has been destroyed may be easily conducted after forming the second through hole 34a
  • FIG 11 is a sectional view showing the structure of a semiconductor device 106 according to the sixth embodiment
  • the semiconductor device 100 is stacked on an interposer 50 formed of the silicon resin, for example, by directing the surface of the interconnection layer 16 downward
  • the vertically stacked semiconductor devices 100 are electrically coupled via the respective through electrodes 20 formed therein
  • Outer connection terminals 56 each formed of a pad electrode and a solder ball are formed on the lower surface of the interposer 50
  • FIG 12 is a sectional view showing an enlarged portion of the through electrode shown in FIG 11
  • the scale of the view showing the interposer 50 and the outer connection terminal 56 is the same as the one of the view shown in FIG 11
  • the bump 21a of the through electrode 20a is connected to an electrode 52 formed on the upper surface of the interposer 50
  • the space between the semiconductor device 100a and the interposer 50 is filled with an underfill agent 54a
  • the underfill agent 54a is used to stably fix the semiconductor device 100a on the interposer 50 and formed of the organic insulating resm, for example
  • the semiconductor device 100b is mounted on the semiconductor device 100a by directing the surface of the interconnection layer 16b downward
  • the bump 21 b of the through electrode 20b is connected to the through electrode 20a of the semiconductor device 100a
  • the space between the semiconductor devices 100b and 100a is filled with the underfill agent 54b In this manner, the plurality of the semiconductor devices 100a and 100b are stacked on the upper surface of the interposer 50
  • the bump 21 of the through electrode 20 is connected to the side opposite the bump-forming surface of another through electrode 20 such that the vertically stacked semiconductor devices are connected with each other via the through electrode 20
  • the plurality of the vertically stacked semiconductor devices 100 may be mounted on the interposer 50, thus enhancing the packaging density of the semiconductor device
  • the bump 21 protruding outside the semiconductor device 100 is capable of absorbing the irregularity of the mounted surface, even if the mounted surface is not flat Therefore, the semiconductor device 100 may be stably mounted
  • the semiconductor devices 100 according to the first embodiment are stacked on the interposer 50
  • the semiconductors 102 to 105 according to the second to the fifth embodiments, or any combination thereof may also be stacked
  • FIG 13 shows a case where the plurality of the semiconductor devices 104 according to the fourth embodiment are stacked on the interposer 50
  • the structures are the same as those shown in FIG 12 except that the through electrode 20 is provided with a second bonding bump 28
  • the bump 21 of the through electrode 20 is connected to the second bonding bump 28 provided on another through electrode
  • the through electrodes 20 maybe connected with each other via the second bonding bump 28 to improve the connection stability
  • FIG 14 shows a case where the plurality of the semiconductor devices 105 according to the fifth embodiment are stacked on the interposer 50
  • the structures are the same as those shown in FIG 12 except that the first through hole 32 is tapered in the direction from the upper portion to the lower portion, and the second through hole 34 is tapered in the direction from the lower portion to the upper portion
  • the second through 34 hole may be formed by etching from the side opposite the first through hole 32, the conduction between the through electrode 20 and the semiconductor substrate 14 inside the first through hole 32 is unlikely to occur This makes it possible to boost the yield of the semiconductor device
  • the interposer 50 is used as a portion on which any of the semiconductor devices 100 to 105 are mounted
  • the mounted portion may be formed of any member so long as it functions for mounting the any of the semiconductor devices 100 to 105
  • a semiconductor device which includes a semiconductor substrate, a connection electrode disposed on an upper surface of the semiconductor substrate and connected to an integrated circuit on the semiconductor substrate, a through electrode which penetrates the semiconductor substrate and the connection electrode, and an insulation portion interposed between the semiconductor substrate and the through electrode
  • the through electrode is integrally formed to protrude outward from upper surfaces of the semiconductor substrate and the connection electrode, and connected to the connection electrode in a region where the through electrode penetrates the connection electrode
  • the through electrode is connected to the connection electrode, and protrudes from the upper surfaces of the semiconductor substrate and the connection electrode This makes it possible to easily connect the semiconductor device to another semiconductor device or the inlerposer
  • the through electrode may be integrally formed, the manufacturing step of the semiconductor device may be simplified, and the manufacturing cost may further be reduced
  • the semiconductor substrate includes a first through hole which penetrates the semiconductor substrate, and a second through hole which vertically penetrates the insulation portion inside the first through hole
  • the insulation portion is disposed inside the first through hole, and the through electrode is disposed inside the second through hole
  • the insulation portion may be formed to fill the first through hole
  • the first through hole may be tapered in a direction from the upper surface to a lower surface of the semiconductor substrate, and the second through hole may be tapered from the lower surface to the upper surface of the semiconductor substrate.
  • the through electrode maybe tapered in the direction from the lower surface to the upper surface of the semiconductor substrate
  • the insulation portion may be formed as a film applied to the inner surface of the first through hole This makes it possible to form the insulation portion as a thin film
  • the aforementioned structure is provided with at least one of a first bonding bump formed on an upper surface of the through electrode and a second bonding bump formed on a lower surface of the through electrode
  • the structure allows the through electrode to be connected to another semiconductor device or the interposer further easily using the first or the second bonding bump
  • a method for manufacturing a semiconductor device including steps of bonding a first support member formed of a support base material and a support adhesive agent on an upper surface of a semiconductor substrate provided with a connection electrode by directing the support adhesive agent downward, forming a first through hole which penetrates the semiconductor substrate, forming an insulation portion inside the first through hole, forming a second through hole which vertically penetrates the insulation portion and the connection electrode,
  • the first support member may be provided with a stopper layer interposed between the support base material and the support adhesive agent, and the step of forming the second through hole includes forming the second through hole which penetrates the insulation portion, the connection electrode and the support adhesive agent from a lower surface of the semiconductor substrate to reach the stopper layer
  • the method may include a step of forming a first bonding bump in a region corresponding to the support adhesive agent inside the second through hole This method makes it possible to form the first bonding bump on the upper surface of the through electrode without additionally forming the mask, thus reducing manufacturing cost further
  • the method may include a step of bonding a second support member to a lower surface of the semiconductor substrate, and a step of forming a second bonding bump to a lower surface of the through electrode after eliminating the support adhesive agent and the support base material
  • the step of forming the second through hole includes forming the second through hole which penetrates the second support member, the insulation portion, the connection electrode, and the support adhesive agent inside the first through hole The method allows the second bonding bump to be formed on the lower surface of the through electrode
  • the step of forming the through electrode includes forming the through electrode using the second support member as the mask
  • the step of forming the second bonding bump includes forming the second bonding bump using the second support member as the mask
  • the through electrode and the second bonding bump may be formed using the second support member as the mask. The resultant manufactu ⁇ ng step may be simplified, and the manufacturing cost may be reduced.
  • the step of forming the first through hole includes eliminating the semiconductor substrate in a direction from an upper surface to a lower surface thereof
  • the step of forming the second through hole includes eliminating the insulation portion, the connection electrode and the support adhesive agent in the direction from the lower surface to the upper surface of the semiconductor substrate
  • the method is capable of preventing the side surface of the insulation portion from being cut erroneously upon formation of the second through hole The conduction between the semiconductor substrate and the through electrode inside the first through hole may be suppressed.
  • a plurality of the above-structured semiconductor devices are stacked, and vertically stacked semiconductor devices among the plurality of the semiconductor devices are connected with each other via the through electrode
  • the method is capable of connecting the vertically stacked semiconductor devices using the through electrode This makes it possible to easily stack the semiconductor devices
  • the through electrodes of the plurality of the semiconductor devices may be connected with each other via the bonding bump This makes it possible to connect the through electrodes further reliably using the bonding bump
  • the through electrode protruding from the upper surfaces of the semiconductor substrate and the connection electrode allows the semiconductor device to be connected to another semiconductor device or the interposer.
  • the through electrode may be integrally formed, the method for manufactu ⁇ ng the semiconductor device may be simplified, thus reducing the manufacturing cost.
  • a semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20.
  • the through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.

Description

SEMICONDUCTOR DEVlCEAND METHOD FOR MANUFACTURING THEREOF
Cross Reference To Related Application
This application claims the benefit of U S Provisional Application No 60/958,084, filed July 2, 2007, U S Non-Provisional Application No XX/XXX.XXX filed July 1 , 2008, and Japanese Application No 2007-209980 filed August 10, 2007, all of which are incorporated herein by reference
Technical Field
The discussed technology relates to a semiconductor device, and more particularly, to a semiconductor device provided with a through electrode which penetrates a semiconductor substrate, and a method for manufacturing thereof
Background
Recently, accompanied with miniaturization and sophistication of an electronic device, a technique for improving a packaging density of a semiconductor device mounted on the electronic device has been developed Various lands of the semiconductor device with the stack structure having a plurality of semiconductor chips stacked have been developed as a high packaging density technique
Japanese Patent Application Publication No 2002-50738 (Document 1) and Japanese Patent Application Publication No 2005-19521 (Document 2) disclose the semiconductor device m which a through hole is formed in the semiconductor chip, and a through electrode separated from the semiconductor chip with the insulation member is disposed inside the through hole The aforementioned semiconductor device may be electrically coupled with another semiconductor device or the interposer with the solder ball applied onto the connection electrode of the semiconductor chip
In the semiconductor device disclosed in Documents 1 and 2, the step of forming the through electrode for connecting interconnections on the upper and the lower surfaces of the semiconductor chip is performed independently of the step of forming the solder ball for connecting the semiconductor chip to another semiconductor device or the interposer, resulting in the complicated manufacturing step and the increased manufacturing cost
Summary
The present invention was devised in light of the foregoing problems, and it is an attempt of the invention to provide a semiconductor device including a through electrode, which may be produced through the simplified manufacturing step, and the method for manufacturing thereof
According to an aspect of the present invention, there is provided a semiconductor device which includes a semiconductor substrate, a connection electrode disposed on an upper surface of the semiconductor substrate and connected to an integrated circuit on the semiconductor substrate, a through electrode which penetrates the semiconductor substrate and the connection electrode, and an insulation portion interposed between the semiconductor substrate and the through electrode The through electrode is integrally formed to protrude outward from upper surfaces of the semiconductor substrate and the connection electrode, and connected to the connection electrode in a region where the through electrode penetrates the connection electrode
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device including bonding a first support member formed of a support base material and a support adhesive agent on an upper surface of a semiconductor substrate provided with a connection electrode by directing the support adhesive agent downward, forming a first through hole which penetrates the semiconductor substrate, forming an insulation portion inside the first through hole, forming a second thiough hole which vertically penetrates the insulation portion and the connection electrode, and further penetrates the support adhesive agent inside the first through hole, and integrally forming a through electrode in a region corresponding to the semiconductor substrate, the connection electrode and the support adhesive agent inside the second through hole
Brief Description of the Drawings
FIGS 1 A through 1 E illustrate a method for manufacturing a semiconductor device according to a first embodiment,
FlG 2 is a sectional view showing a structure of the semiconductor device according to the first embodiment,
FIG 3 illustrates a method for manufacturing a semiconductor device according to a second embodiment,
FIG 4 is a sectional view showing a structure of the semiconductor device according to the second embodiment, FIGS 5A through 5E illustrate a method for manufacturing a semiconductor device according to a third embodiment,
FIGS 6A through 6F illustrate a method for manufacturing a semiconductor device according to a fourth embodiment,
FIG 7 is a sectional view showing a structure of the semiconductor device according to the fourth embodiment,
FIGS 8A through SE illustrate a method for manufacturing a semiconductor device according to a fifth embodiment,
FIG 9 is a sectional view showing a structure of the semiconductor device according to the fifth embodiment, FIGS 1 OA through 1 OC illustrate a method for manufacturing a semiconductor device according to a comparative example of the fifth embodiment, FIQ 11 is a sectional view showing a structure of a semiconductor device according to a sixth embodiment,
FIG 12 is a sectional view showing an enlarged portion of the view shown in FIG 1 1,
FIG 13 is a sectional view showing a structure of another semiconductor device according to the sixth embodiment (part 1), and
FIG 14 is a sectional view showing a structure of another type of the semiconductor device according to the sixth embodiment (part 2)
Detailed Descriptiou Hereinafter, embodiments according to the present invention will be described referring to the drawings First Embodiment
A method for manufacturing a semiconductor device according to a first embodiment will be described referring to FIGS IA through I E Each of FIGS IA through I E is a cross-sectional view showing an enlarged portion around a through electrode of the semiconductor device according to the first embodiment Referring to FIG IA, an interconnection 13 formed of copper, aluminum, or the like, and an interconnection layer 16 formed of an insulation layer 15 formed of a silicon oxide or the like are formed on the upper surface of a semiconductor substrate 14 formed of silicon The interconnection layer 16 contains a connection electrode 12 as a region where a through electrode 20 (not shown in Fig IA, see FIG IE) is formed in the subsequent step of a manufacturing method The connection electrode 12 is formed to be directly connected to the through electrode 20 (see FIG 2) to be described later The interconnection layer 16 partially forms an integrated circuit (the circuit including the transistor or memory, for example) formed on the semiconductor substrate 14, and is electrically coupled with the connection electrode 12
As shown m FIG 1 A, a first support member 43 formed by applying a support adhesive agent 42 as an acrylic adhesive agent to a support base material 40 formed of a polyester is bonded to an upper surface of the semiconductor substrate 14 by directing the side of the support adhesive agent 42 downward The first support member 43 is provided for supporting the semiconductor substrate 14 and the interconnection layer 16 in the subsequent step of forming a through hole The first support member 43 may be formed of any material so long as the same function as described above is obtained The support adhesive agent 42 has a predetermined thickness (for example, 20 mm) to allow the through electrode to protrude from the upper surface of the semiconductor substrate 14 in the subsequent step
Referring to FIG 1 B, a first through hole 32 is formed in the semiconductor substrate 14 so as to at least penetrate therethrough The first through hole 32 may have any cross section shape (in parallel with the upper surface of the semiconductor substrate 14) but is required to have the size (for example, circle with a diameter of 40 mm) which accommodates the through electrode inside the first through hole 32 in the subsequent step As shown in the drawing, the first through hole 32 may be formed to the region in contact with the interconnection layer 16, or to penetrate the interconnection layer 16 The first through hole 32 is formed through the laser irradiation or dry etching to eliminate the corresponding portion of the semiconductor substrate 14 from the lower surface thereof Alternatively, the lower surface of the semiconductor substrate 14 is polished to have the predetermined thickness so as to form the first through hole 32 In the first embodiment, the total thickness of the semiconductor substrate 14 and the interconnection layer 16 is set to 50 mm
Referring to FIG 1C, an insulation portion 30 is applied to an inner surface of the first through hole 32 and the lower surface of the semiconductor substrate 14 The insulation portion 30 is formed in order to electrically insulate the through electrode 20 (not shown in FIG 1C, see FIG IE) formed in the step (to be described later) from the semiconductor substrate 14, and is formed of such member as a resin, an oxide film and a nitride film is applied at least to an entire inner surface of the first through hole 32 The insulation film 30 may be formed as a thin film through a chemical vapor deposition (CVD) process so as to be applied to the inner wall of the first through hole 32 (see FIG 1C) In addition, such portion may be formed by coating a liquid insulation member (spin coat, for example) Furthermore, such portion may be formed so as to entirely fill the first through hole 32
Referring to FIG ID, a second through hole 34 is formed inside the first through hole 32 to vertically penetrate the insulation portion 30 and the connection electrode 12, and to further penetrate the support adhesive agent 42 In the case where the film-like insulation portion 30 is formed as shown in FIG 1 C, the second through hole 34 may be formed by combining a hollow portion inside the first through hole 32 resulting from etching of the insulation portion 30 on the upper surface of the first through hole 32 and a hollow portion separately formed as shown in FIG 1 D The second through hole 34 is formed so as to penetrate at least the semiconductor substrate 14, the connection electrode 12, and the support adhesive agent 42 to reach the support base material 40 from the lower surface of the semiconductor substrate 14 A cross section of the second through hole 34 may have any shape, but is required to have the size smaller than that of the first through hole 32 As shown in the drawing, it is preferable to form the second through hole 34 to reach the region in contact with the support base material 40 However, the second through hole 34 may be formed to penetrate the support base material 40 to a slight extent The second through hole 34 is formed through the laser irradiation or dry etching from the lower surface of the semiconductor substrate 14 to eliminate the respective regions of the insulation portion 30, the connection electrode 12, and the support adhesive agent 42
Referring to FIG IE, the through electrode 20 is formed inside the second through hole 34 so as to be electrically coupled with the connection electrode 12 The through electrode 20 is integrally formed with the region corresponding to at least the semiconductor substrate 14, the connection electrode 12 and the support adhesive agent 42 inside the second through hole 34 As shown in the drawing, the through electrode 20 is electrically coupled with the connection electrode 12 at the portion where the through electrode 20 penetrates the connection electrode 12 It is preferable to use the member with high conductivity such as copper for forming the through electrode 20 The through electrode 20 is formed by filling the copper paste 22 in the second through hole 34 from the lower surface In addition, the through electrode 20 may also be formed through the plating
Referring to FIG 2, the support base material 40 and the support adhesive agent 42 are eliminated after forming the through electrode 20 As a result, the upper portion of the through electrode 20 protrudes from the upper surfaces of the semiconductor substrate 14 and the connection electrode 12 to be formed as a bump 21 A semiconductor device 100 according to the first embodiment is then produced in the aforementioned steps
FIG 2 is a sectional view of the semiconductor device 100 according to the first embodiment The connection electrode 12 is formed on the upper surface of the semiconductor substrate 14 and electrically coupled with the interconnection layer 16 which partially forms an integrated circuit The through electrode 20 is formed in the semiconductor substrate 14 to penetrate through the semiconductor substrate 14 as well as the connection electrode 12 The through electrode 20 is integrally formed to penetrate the semiconductor substrate 14 and the connection electrode 12 vertically from the lower surface of the semiconductor substrate 14, and to protrude from the upper surfaces of the semiconductor substrate 14 and the connection electrode 12 The through electrode 20 contacts the connection electrode 12 so as to be electrically coupled therewith in a region 19, where the penetration electrode 20 penetrates the connection electrode 12 The insulation portion 30 formed of the insulating resin is applied to the space between the semiconductor substrate 14 and the through electrode 20, and the lower surface of the semiconductor substrate 14
Referring to FIG 2, the structure of the semiconductor device 100 will be described in more detail The semiconductor device 100 according to the first embodiment includes the first through hole 32 which penetrates the semiconductor substrate 14 The insulation portion 30 is formed on the inner surface of the first through hole 32 The second through hole 34 which vertically penetrates the insulation portion 30 is formed The insulation portion 30 may be formed as the film as shown in the drawing, or formed by filling the first through hole 32 to be described later The through electrode 20 is provided inside the second through hole 34
In the semiconductor device 100 according to the first embodiment, the upper portion of the through electrode 20 protrudes from the upper surfaces of the semiconductor substrate 14 and the connection electrode 12 to form the bump 21 This makes it possible to be electrically coupled the semiconductor device 100 with another semiconductor device via the bump 21 As the through electrode 20 protrudes from the upper surface of the semiconductor device 100, it may be easily brought into contact with the electrode of another semiconductor device or interposer In the case where the contact surface has a concavo-convex shape, the bump 21 may be crushed in contact with such surface to absorb the irregularity in the height of the connection surface Accordingly, the semiconductor device 100 may be connected to another semiconductor device or the interpose in the stable manner The through electrode 20 may be formed to have any structure so long as it protrudes at least from the upper surface of the semiconductor device 100 so as to be electrically coupled with the electrode of another semiconductor device or the interposer For example, the through electrode 20 may be structured to protrude from the upper surface of the insulating resin which covers the upper surfaces of the semiconductor substrate 14 and the interconnection layer 16 (connection electrode 12)
In the first embodiment, the etching is performed not only to the insulation portion 30 and the connection electrode 12 but also to the support adhesive agent 42 upon formation of the second through hole 34 for forming the through electrode 20 As a result, the bump 21 is formed in the region corresponding to the support adhesive agent 42 in the second through hole 34 simultaneously with formation of the through electrode 20 The through electrode 20 is electrically coupled with the connection electrode 12 in the region where the through electrode 20 penetrates the connection electrode 12 In this manner, the formation of the through electrode 20 and the bump 21 , and the electrical coupling between the through electrode 20 and the connection electrode 12 may be peifα med in a single step, thus simplifying the manufacturing step The process which uses the support base material 40 and the support adhesive agent 42 does not require formation of a mask for forming the bump 21 , thus reducing a manufacturing cost
According to the first embodiment, the case where the interconnection 13 serves as the connection electrode 12 is described However, the connection electrode 12 is not limited to the aforementioned structure For example, the connection electrode 12 may be formed separately from the interconnection 13 according to the fifth embodiment to be described later Second Embodiment
In a second embodiment, a solder bonding bump is formed on the upper surface of the through electrode FIG 3 illustrates a method for manufacturing a semiconductor device according to a second embodiment and corresponds to FIG IE according to the first embodiment The manufacturing steps pπor to the one corresponding to those shown m FIG 3 are the same as those of the manufacturing steps of the first embodiment, and explanations thereof, thus will be omitted Referring to FIG 3, a bonding paste 26 as a solder paste is buried in a region corresponding to the support adhesive agent 42 above the second through hole 34 After the bonding paste 26 is solidified to form a first bonding bump 24, a copper paste 22 is then filled in the second through hole 34 Thereafter, the support base material 40 and the support adhesive agent 42 are eliminated to produce a semiconductor device 102 according to the second embodiment
FIG 4 is a sectional view showing the structure of the semiconductor device 102 according to the second embodiment The first bonding bump 24 is formed on the upper surface of the through electrode 20 It is preferable to set the planar size of the first bonding bump 24 to be equal to or smaller than that of the through electrode 20 The other structure is the same as that of the first embodiment, and the explanation thereof, thus will be omitted The semiconductor device 102 according to the second embodiment has the first bonding bump 24 formed on the upper surface of the through electrode 20 The melting point of the first bonding bump 24 is lower than that of the through electrode 20 so as to be mechanically and electrically connected to the electrode of another semiconductor device or the interposer This makes it possible to improve the stability on the connection surface compared with the connection by only the through electrode 20
In the second embodiment, the first bonding bump 24 is formed using the second through hole 34 for forming the through electrode 20 Therefore, the mask for forming the first bonding bump 24 is not required to be formed, thus simplifying the manufacturing step and reducing the cost
The solder of tm-silvei type or tin-silver-copper type is used for forming the first bonding bump 24 In the second embodiment, the bonding paste 26 is filled in the second through hole 34 to form the first bonding bump 24 Alternatively, the first bonding bump 24 may be formed through plating Third Embodiment
In a third embodiment, the support member including a stopper layer is used in the method for manufacturing the semiconductor device 100 according to the first embodiment FIGS 5 A through 5E illustrate a method for manufacturing a semiconductor device according to a third embodiment and correspond to FIGS IA to IE according to the first embodiment The same structures as those of the first embodiment will be designated with the same codes, and the explanations thereof, thus will be omitted
Referring to FIG 5 A, a first support member 43a having a stopper layer 44 interposed between the support base material 40 and the support adhesive agent 42 is bonded to the upper surface of the semiconductor substrate 14 by directing the support adhesive agent 42 downward The stopper layer 44 serves to stop etching in the step of forming the second through hole 34 to be described later The stopper layer 44 is formed of the member which is unlikely to be etched through laser irradiation or dry etching, for example, the metal layer formed of copper
As shown m FIG 5B, the steps for forming the first through hole 32 and forming the insulation portion 30 on the inner surface of the first through hole 32 are the same as those described in the first embodiment
The second through hole 34 which penetrates the insulation portion 30, the connection electrode 12 and the support adhesive agent 42 to reach the stopper layer 44 is formed inside the first through hole 32 as shown in FIG 5D Likewise the first embodiment, the second through hole 34 is formed through laser irradiation or dry etching The etching is blocked by the stopper layer 44 formed of the material which is unlikely to be etched Therefore, the second through hole 34 is formed from the lower surface of the semiconductor substrate 14 to the lower surface of the stopper layer 44 without penetrating the stopper layer 44
Likewise the first embodiment, the copper paste 22 is filled into the second through hole 34 as shown in FIG 5E to form the through electrode 20 Thereafter, the first support member 43a formed of the support base material 40, the support adhesive agent 42 and the stopper layer 44 is eliminated to produce the semiconductor device according to the third embodiment The structure of the semiconductor device according to the third embodiment is the same as that of the semiconductor device 100 according to the first embodiment as shown in FIG 2
In the third embodiment, the use of the first support member 43a having the stopper layer 44 interposed between the support base material 40 and the support adhesive agent 42 allows the stopper layer 44 to block etching for forming the second through hole 34 This may prevent the support base material 40 from being penetrated upon the etching, thus allowing the second through hole 34 to be formed in the stable manner In addition, the height of the bump 21 of the through electrode 20 may be set to the predetermined value Fourth Embodiment
In a fourth embodiment, the bonding bump is formed on the lower surface of the through electrode 20 FIGS 6A through 6F illustrate a method for manufacturing a semiconductor device 104 according to the fourth embodiment The same structures as those described in the first to the third embodiments will be designated with the same codes, and the explanations thereof, thus will be omitted In the process shown in FIGS 6A and 6B corresponding to that shown in FIGS 5A and
5Baccording to the third embodiment, the first support member 43a including the stopper layer 44 is bonded to the upper surface of the semiconductor substrate 14, and the first through hole 32 is formed in the semiconductor substrate 14
The insulation portion 30 is formed on the inner surface of the first through hole 32 and the lower surface of the semiconductor substrate 14 as shown in FlG 6C Thereafter, a second support member 36 as a polyimide tape is bonded to the lower surface of the semiconductor substrate 14 via the insulation portion 30 The second support member 36 serves to support the semiconductor substrate 14 in place of the first support member 43a in the step of forming the second bonding bump to be described later The second support member 36 is formed of the member which resists the temperature (for example, 230cC) to form the bonding bump
The second through hole 34 which penetiates the second support member 36, the insulation portion 30, the connection electrode 12 and the support adhesive agent 42 is formed as shown in FIG 6D Referring to the drawing, the second through hole 34 in the support adhesive agent 42 may be formed to have the size different from that of the second through hole 34 in the second support member 36 As shown in FlG 6E, the copper paste 22 is filled in the second through hole 34 using the second support member 36 as a mask to form the through electrode 20 The second support member 36 prevents the contact between the copper paste 22 and the insulation portion 30 on the lower surface of the semiconductor substrate 14
The first support member 43a formed of the support base material 40, the support adhesive agent 42 and the stopper layer 44, which cannot resist the temperature to form the bonding bump (for example, 230°C), is eliminated as shown in FIG 6F In this case, the second support member 36 supports the semiconductor substrate 14, thus preventing the crack of the semiconductor substrate 14 A second bonding bump 28 is then formed on the lower surface of the through electrode 20 using the second support member 36 as a mask The second bonding bump 28 may be formed by printing the bonding paste 26 on the lower surface of the semiconductor substrate 14 and performing the reflow at 2300C for 5 minutes Thereafter, the second support member 36 is peeled off to eliminate the copper paste 22 and the bonding paste 26 adhered on the lower surface of the second support member 36 simultaneously In this manner, a semiconductor device 104 according to the fourth embodiment is produced
FIG 7 is a sectional view showing the structure of the semiconductor device 104 according to the fourth embodiment The second bonding bump 28 is formed on the lower surface of the through electrode 20 The planar size of the second bonding bump 28 is smaller than that of the through electrode 20 The other structures of the embodiment are the same as those of the first embodiment as shown in FIG 2, and the explanations thereof, thus will be omitted
The semiconductor device 104 according to the fourth embodiment is provided with the second bonding bump 28 on the lower surface of the through electrode 20 The second bonding bump 28 makes it easy to connect the semiconductor device 104 to another semiconductor device or the interposer
In the fourth embodiment, the copper paste 22 is filled to form the through electrode 20 using the second support member 36 as a mask The photo mask may be used for forming the through electrode 20 to prevent adhesion of the copper paste 22 to the insulation portion 30 formed on the lower surface of the semiconductor substrate 14 However, the use of the photo mask requires the cost higher than the one required by the use of the second support member 36 as the mask, thus reducing the manufacturing costs In the fourth embodiment, as the second bonding bump 28 is formed using the second support member 36 as the mask, the mask for forming the second bonding bump 28 is not required to be formed This makes it possible to simplify the manufacturing step and to reduce the manufacturing costs Fifth Embodiment In a fifth embodiment, the step of forming the through hole is modified FIGS 8A through 8E illustrate the step of manufacturing a semiconductor device 105 according to the fifth embodiment The same structures as those of the first to the fourth embodiments will be designated with the same codes, and explanations thereof, thus will be omitted
The interconnection layer 16 is formed on the upper surface of the semiconductor substrate 14 as shown in FIG 8A A first through hole 32a which penetrates the interconnection layer 16 and the semiconductor substrate 14 is formed from the upper surface to the lower surface of the semiconductor substrate 14 The first through hole 32a is tapered toward the lower surface of the semiconductor substrate 14 The first through hole 32a may be formed through laser irradiation or dry etching
The first support member 43 formed of the support base material 40 and the support adhesive agent 42 is bonded to the upper surface of the semiconductor substrate 14 as shown in FIG 8B Thereafter, a thin bonding layer 29 (connection electrode 12) formed of the solder, for example, is formed in the region where the interconnection layer 16 is cut as shown in FIG 8A Therefore, the interconnection 13 which has been cut is connected again to form the connection electrode 12
I he insulation portion 30 is formed inside of the first through hole 32a and on the lower surface of the semiconductor substrate 14 as shown in FIG 8C Unlike the first to the fourth embodiments, inside the first through hole 32a is filled with the insulation portion 30, which is formed of an organic insulating resin, for example
The insulation portion 30, the bonding layer 29 (connection electrode 12) and the support adhesive agent 42 are eliminated from the lower surface to the upper surface of the semiconductor substrate 14 to form a second through hole 34a as shown in FIG 8D The second through hole 34a is tapered in the direction from the lower surface to the upper surface of the semiconductor substrate 14 In addition, the second through hole 34a is formed through laser irradiation or dry etching from the lower surface thereof Specifically, the first through hole 32a and the second through hole 34a are formed from the opposite directions
The second through hole 34a is filled with the copper paste 22 to form a through electrode 20a as shown in FlG 8E Thereafter, the first support member 43 formed of the support base material 40 and the support adhesive agent 42 is eliminated to produce a semiconductor device 105 according to the fifth embodiment
FIG 9 is a sectional view showing the structure of the semiconductor device 105 according to the fifth embodiment The first through hole 32a is tapered in the direction from the upper surface to the lower surface of the semiconductor substrate 14 The second through hole 34a is tapered in the direction from the lower surface to the upper surface of the semiconductor substrate 14 The second through hole 34a is provided with the through electrode 20a so as to be connected to the connection electrode 12 via the bonding layer 29 Likewise the second through hole 34a, the through electrode 20a is tapered in the direction from the lower surface to the upper surface of the semiconductor substrate 14 The insulation portion 30 is provided so as to fill the first through hole 32a The other structures are the same as those of the first embodiment, and the explanations thereof, thus will be omitted
FIGS 1 OA through 1OC illustrate the part of the step of manufacturing the semiconductor device as a comparative example of the fifth embodiment and correspond to FIGS 9A through 9D In the semiconductor device according to the comparative example, the etching is performed from the lower surface of the semiconductor substrate 14 to form the first through hole 32b as shown in FIG 1 OA Then the first support member 43 is bonded to form the bonding layer 29 and the insulation portion 30 as shown in FIG I0B Thereafter, the etching is performed from the lower surface of the semiconductor substrate 14 again to form the second through hole 34b as shown in FIG 1OC
In the comparative example, both the first and the second through holes 32b and 34b are formed by etching from the lower surface of the semiconductor substrate 14 as shown in FIG 1OC Generally, in the case of forming the through hole by performing the laser irradiation or dry etching, the resultant through hole is likely to be tapered in the direction away from the surface where the etching starts Referring to FIG 1OC, both the first and the second through holes 32b and 34b are likely to be tapered in the direction from the lower surface to the upper surface of the semiconductor substrate 14 Accordingly, the insulation portion 30 applied on the side surface of the first through hole 32b may be cut in the course of the etching for forming the second through hole 34b to expose the semiconductor substrate 14 For example, FIG 1 OC shows that the insulation portion 30 is overetched due to πghtward displacement of the laser irradiation axis upon formation of the second through hole 34b to expose the semiconductor substrate 14 around a region 17 The aforementioned case is likely to occur especially when the first through hole 32b has the diameter close to that of the through hole 34b When the semiconductor substrate 14 is exposed outside from the insulation portion 30 applied on the side surface of the first through hole 32b, the copper paste 22 to be filled in the subsequent step of forming the through electrode 20 is brought into contact with the semiconductor substrate 14, resulting in the conduction between the semiconductor substrate 14 and the through electrode 20
In the step of manufacturing the semiconductor device 105 according to the fifth embodiment, the first through hole 32a is formed from the upper surface to the lower surface of the semiconductor substrate 14, and the second through hole 34a is formed from the lower surface to the upper surface The resultant first through hole 32a is tapered in the direction from the upper surface to the lower surface, and the second through hole 34a is tapered in the direction from the lower surface to the upper surface This makes it possible to prevent the insulation portion 30 formed on the side surface of the first through hole 32a from being cut by etching upon formation of the second through hole 34a The etching for forming the second through hole 34a is performed from the direction opposite the direction of etching for forming the first through hole 32a This makes it possible to effectively insulate the through electrode 20 from the semiconductor substrate 14
For etching from the lower surface of the semiconductor substrate 14, the special device for IR radioscopy or positioning from the lower surface is required However, the etching to form the first through hole 32a is performed from the upper surface of the semiconductor substrate 14 This makes it possible to easily perform the positioning without using the aforementioned special device The positioning for etching to form the second through hole 34a may also be easily performed in reference to the first through hole 32a Furthermore, the inspection whether or not the insulation portion 30 has been destroyed may be easily conducted after forming the second through hole 34a Sixth Embodiment
In a sixth embodiment, the semiconductor device 100 according to the first embodiment is stacked on the interposer FIG 11 is a sectional view showing the structure of a semiconductor device 106 according to the sixth embodiment The semiconductor device 100 is stacked on an interposer 50 formed of the silicon resin, for example, by directing the surface of the interconnection layer 16 downward The vertically stacked semiconductor devices 100 are electrically coupled via the respective through electrodes 20 formed therein Outer connection terminals 56 each formed of a pad electrode and a solder ball are formed on the lower surface of the interposer 50
FIG 12 is a sectional view showing an enlarged portion of the through electrode shown in FIG 11 The scale of the view showing the interposer 50 and the outer connection terminal 56 is the same as the one of the view shown in FIG 11 The bump 21a of the through electrode 20a is connected to an electrode 52 formed on the upper surface of the interposer 50 The space between the semiconductor device 100a and the interposer 50 is filled with an underfill agent 54a The underfill agent 54a is used to stably fix the semiconductor device 100a on the interposer 50 and formed of the organic insulating resm, for example The semiconductor device 100b is mounted on the semiconductor device 100a by directing the surface of the interconnection layer 16b downward The bump 21 b of the through electrode 20b is connected to the through electrode 20a of the semiconductor device 100a The space between the semiconductor devices 100b and 100a is filled with the underfill agent 54b In this manner, the plurality of the semiconductor devices 100a and 100b are stacked on the upper surface of the interposer 50 by directing each surface of the interconnection layer 16 downward
In the semiconductor device 106 according to the sixth embodiment, the bump 21 of the through electrode 20 is connected to the side opposite the bump-forming surface of another through electrode 20 such that the vertically stacked semiconductor devices are connected with each other via the through electrode 20 The plurality of the vertically stacked semiconductor devices 100 may be mounted on the interposer 50, thus enhancing the packaging density of the semiconductor device The bump 21 protruding outside the semiconductor device 100 is capable of absorbing the irregularity of the mounted surface, even if the mounted surface is not flat Therefore, the semiconductor device 100 may be stably mounted
In the sixth embodiment, the semiconductor devices 100 according to the first embodiment are stacked on the interposer 50 However, the semiconductors 102 to 105 according to the second to the fifth embodiments, or any combination thereof may also be stacked
FIG 13 shows a case where the plurality of the semiconductor devices 104 according to the fourth embodiment are stacked on the interposer 50 The structures are the same as those shown in FIG 12 except that the through electrode 20 is provided with a second bonding bump 28 The bump 21 of the through electrode 20 is connected to the second bonding bump 28 provided on another through electrode The through electrodes 20 maybe connected with each other via the second bonding bump 28 to improve the connection stability
FIG 14 shows a case where the plurality of the semiconductor devices 105 according to the fifth embodiment are stacked on the interposer 50 The structures are the same as those shown in FIG 12 except that the first through hole 32 is tapered in the direction from the upper portion to the lower portion, and the second through hole 34 is tapered in the direction from the lower portion to the upper portion As the second through 34 hole may be formed by etching from the side opposite the first through hole 32, the conduction between the through electrode 20 and the semiconductor substrate 14 inside the first through hole 32 is unlikely to occur This makes it possible to boost the yield of the semiconductor device
Referring to FIGS 12 Io 14, two units of the semiconductor devices are stacked on the interposer 50. However, three or more units of the semiconductor devices may be stacked The interposer 50 is used as a portion on which any of the semiconductor devices 100 to 105 are mounted However, the mounted portion may be formed of any member so long as it functions for mounting the any of the semiconductor devices 100 to 105
Now, several aspects of the present invention are summarized below
According to an aspect of the present invention, there is provided a semiconductor device which includes a semiconductor substrate, a connection electrode disposed on an upper surface of the semiconductor substrate and connected to an integrated circuit on the semiconductor substrate, a through electrode which penetrates the semiconductor substrate and the connection electrode, and an insulation portion interposed between the semiconductor substrate and the through electrode The through electrode is integrally formed to protrude outward from upper surfaces of the semiconductor substrate and the connection electrode, and connected to the connection electrode in a region where the through electrode penetrates the connection electrode In the invention, the through electrode is connected to the connection electrode, and protrudes from the upper surfaces of the semiconductor substrate and the connection electrode This makes it possible to easily connect the semiconductor device to another semiconductor device or the inlerposer In addition, as the through electrode may be integrally formed, the manufacturing step of the semiconductor device may be simplified, and the manufacturing cost may further be reduced
In the aforementioned structure, the semiconductor substrate includes a first through hole which penetrates the semiconductor substrate, and a second through hole which vertically penetrates the insulation portion inside the first through hole The insulation portion is disposed inside the first through hole, and the through electrode is disposed inside the second through hole In the aforementioned structure, the insulation portion may be formed to fill the first through hole
This makes it possible to effectively insulate the semiconductor substrate from the through electrode inside the first through hole
In the aforementioned structure, the first through hole may be tapered in a direction from the upper surface to a lower surface of the semiconductor substrate, and the second through hole may be tapered from the lower surface to the upper surface of the semiconductor substrate The structure allows the semiconductor substrate to be insulated from the through electrode inside the first through hole further effectively
In the aforementioned structure, the through electrode maybe tapered in the direction from the lower surface to the upper surface of the semiconductor substrate In the aforementioned structure, the insulation portion may be formed as a film applied to the inner surface of the first through hole This makes it possible to form the insulation portion as a thin film The aforementioned structure is provided with at least one of a first bonding bump formed on an upper surface of the through electrode and a second bonding bump formed on a lower surface of the through electrode The structure allows the through electrode to be connected to another semiconductor device or the interposer further easily using the first or the second bonding bump According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device including steps of bonding a first support member formed of a support base material and a support adhesive agent on an upper surface of a semiconductor substrate provided with a connection electrode by directing the support adhesive agent downward, forming a first through hole which penetrates the semiconductor substrate, forming an insulation portion inside the first through hole, forming a second through hole which vertically penetrates the insulation portion and the connection electrode, and further penetrates the support adhesive agent inside the first through hole, and integrally forming a through electrode in a region corresponding to the semiconductor substrate, the connection electrode and the support adhesive agent inside the second through hole In the method, the through electrode which protrudes from the upper surfaces of the semiconductor substrate and the connection electrode, and is connected to the connection electrode may be manufactured in the single step This makes it possible to simplify the manufacturing step, and to reduce the manufacturing cost
In the method, the first support member may be provided with a stopper layer interposed between the support base material and the support adhesive agent, and the step of forming the second through hole includes forming the second through hole which penetrates the insulation portion, the connection electrode and the support adhesive agent from a lower surface of the semiconductor substrate to reach the stopper layer This method makes it possible to prevent overetching of the support base material in the step of forming the second through hole because the stopper layer serves to prevent etching
The method may include a step of forming a first bonding bump in a region corresponding to the support adhesive agent inside the second through hole This method makes it possible to form the first bonding bump on the upper surface of the through electrode without additionally forming the mask, thus reducing manufacturing cost further
The method may include a step of bonding a second support member to a lower surface of the semiconductor substrate, and a step of forming a second bonding bump to a lower surface of the through electrode after eliminating the support adhesive agent and the support base material The step of forming the second through hole includes forming the second through hole which penetrates the second support member, the insulation portion, the connection electrode, and the support adhesive agent inside the first through hole The method allows the second bonding bump to be formed on the lower surface of the through electrode
In the method, the step of forming the through electrode includes forming the through electrode using the second support member as the mask The step of forming the second bonding bump includes forming the second bonding bump using the second support member as the mask In the method, the through electrode and the second bonding bump may be formed using the second support member as the mask. The resultant manufactuπng step may be simplified, and the manufacturing cost may be reduced. In the method, the step of forming the first through hole includes eliminating the semiconductor substrate in a direction from an upper surface to a lower surface thereof, and the step of forming the second through hole includes eliminating the insulation portion, the connection electrode and the support adhesive agent in the direction from the lower surface to the upper surface of the semiconductor substrate The method is capable of preventing the side surface of the insulation portion from being cut erroneously upon formation of the second through hole The conduction between the semiconductor substrate and the through electrode inside the first through hole may be suppressed. In the method, a plurality of the above-structured semiconductor devices are stacked, and vertically stacked semiconductor devices among the plurality of the semiconductor devices are connected with each other via the through electrode The method is capable of connecting the vertically stacked semiconductor devices using the through electrode This makes it possible to easily stack the semiconductor devices In the aforementioned method, the through electrodes of the plurality of the semiconductor devices may be connected with each other via the bonding bump This makes it possible to connect the through electrodes further reliably using the bonding bump
In the present invention, the through electrode protruding from the upper surfaces of the semiconductor substrate and the connection electrode allows the semiconductor device to be connected to another semiconductor device or the interposer. As the through electrode may be integrally formed, the method for manufactuπng the semiconductor device may be simplified, thus reducing the manufacturing cost.
As a short summary, the technology disclosed now includes at least the following A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.
While the preferred embodiments of the present invention have been described in details above, the present invention is not limited to those specific embodiments, and within the spirit and scope of the present invention, various modifications and alterations can be made

Claims

We claim:
1 A semiconductor device comprising a semiconductor substrate, a connection electrode disposed on an upper surface of the semiconductor substrate and connected to an integrated circuit on the semiconductor substrate, a through electrode which penetrates the semiconductor substrate and the connection electrode, and an insulation portion interposed between the semiconductor substrate and the through electrode, wherein the through electrode is integrally formed to protrude outward from upper surfaces of the semiconductor substrate and the connection electrode, and connected to the connection electrode m a region where the through electrode penetrates the connection electrode
2 The semiconductor device according to claim 1, wherein the semiconductor substrate includes a first through hole which penetrates the semiconductor substrate, and a second through hole which vertically penetrates the insulation portion inside the first through hole, the insulation portion is disposed mside the first through hole, and the through electrode is disposed inside the second through hole
3 The semiconductor device according to claim 2, wherein the first through hole is tapered in a direction from the upper surface to a lower surface of the semiconductor substrate, the insulation portion is formed to fill the first through hole, and the second through hole is tapered from the lower surface to the upper surface of the semiconductor substrate
4 The semiconductor device according to claim 1 , further comprising at least one of a first bonding bump formed on an upper surface of the through electrode and a second bonding bump formed on a lower surface of the through electrode
5 A method for manufacturing a semiconductor device comprising bonding a first support member formed of a support base matenal and a support adhesive agent on an upper surface of a semiconductor substrate provided with a connection electrode by directing the support adhesive agent downward, forming a first through hole which penetrates the semiconductor substrate, forming an insulation portion inside the first through hole, forming a second through hole which vertically penetrates the insulation portion and the connection electrode, and further penetrates the support adhesive agent inside the first through hole, and integrally forming a through electrode in a region corresponding to the semiconductor substrate, the connection electrode and the support adhesive agent inside the second through hole
6 The method for manufacturing the semiconductor device according to claim 5, wherein the first support member is provided with a stopper layer interposed between the support base material and the support adhesive agent, and forming the second through hole includes forming the second through hole which penetrates the insulation portion, the connection electrode and the support adhesive agent from a lower surface of the semiconductor substrate to reach the stopper layer
7 The method for manufacturing the semiconductor device according to claim 5, further comprising forming a first bonding bump in a region corresponding to the support adhesive agent inside the second through hole
8 The method for manufacturing the semiconductor device according to claim 5, further comprising bonding a second support member to a lower surface of the semiconductor substrate, and forming a second bonding bump to a lower surface of the through electrode using the second support member as a mask after eliminating the support adhesive agent and the support base material, wherein forming the second through hole includes forming the second through hole which penetrates the second support member, the insulation portion, the connection electrode, and the support adhesive agent inside the first through hole, and forming the through electrode includes forming the through electrode using the second support member as the mask
9 The method for manufactuπng the semiconductor device according to claim 5, wherein forming the first through hole includes eliminating the semiconductor substrate in a direction from an upper surface to a lower surface thereof, and forming the second through hole includes eliminating the insulation portion, the connection electrode and the support adhesive agent in the direction from the lower surface to the upper surface of the semiconductor substrate 10 A semiconductor device wherein a plurality of the semiconductor devices according to claim 1 are stacked, and vertically stacked semiconductor devices among the plurality of the semiconductor devices are connected with each other via the through electrode
PCT/US2008/072161 2007-08-10 2008-08-04 Semiconductor device and method for manufacturing thereof WO2009023462A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007209980A JP5302522B2 (en) 2007-07-02 2007-08-10 Semiconductor device and manufacturing method thereof
JP2007-209980 2007-08-10
US12/217,096 US7786587B2 (en) 2007-07-02 2008-07-01 Semiconductor device and method for manufacturing thereof
US12/217,096 2008-07-01

Publications (1)

Publication Number Publication Date
WO2009023462A1 true WO2009023462A1 (en) 2009-02-19

Family

ID=39850342

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/072161 WO2009023462A1 (en) 2007-08-10 2008-08-04 Semiconductor device and method for manufacturing thereof

Country Status (1)

Country Link
WO (1) WO2009023462A1 (en)

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010104610A2 (en) * 2009-03-13 2010-09-16 Tessera Technologies Hungary Kft. Stacked microelectronic assemblies having vias extending through bond pads
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US8076788B2 (en) 2006-10-10 2011-12-13 Tessera, Inc. Off-chip vias in stacked chips
WO2012037216A3 (en) * 2010-09-17 2012-06-07 Tessera, Inc. Staged via formation from both sides of chip
US8310036B2 (en) 2007-03-05 2012-11-13 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8426957B2 (en) 2006-10-10 2013-04-23 Tessera, Inc. Edge connect wafer level stacking
US8431435B2 (en) 2006-10-10 2013-04-30 Tessera, Inc. Edge connect wafer level stacking
US8513794B2 (en) 2007-08-09 2013-08-20 Tessera, Inc. Stacked assembly including plurality of stacked microelectronic elements
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US8686565B2 (en) 2010-09-16 2014-04-01 Tessera, Inc. Stacked chip assembly having vertical vias
US8685793B2 (en) 2010-09-16 2014-04-01 Tessera, Inc. Chip assembly having via interconnects joined by plating
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
EP2731133A2 (en) * 2012-11-13 2014-05-14 Delta Electronics, Inc. Interconnection structure and fabrication thereof
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8883562B2 (en) 2007-07-27 2014-11-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
WO2024126197A1 (en) 2022-12-15 2024-06-20 Koninklijke Philips N.V. A system and method for imaging tissue

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020017710A1 (en) * 2000-08-04 2002-02-14 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US20030060000A1 (en) * 2001-03-07 2003-03-27 Seiko Epson Corporation Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument
US20030183943A1 (en) * 2002-03-28 2003-10-02 Swan Johanna M. Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US20060267206A1 (en) * 2004-08-20 2006-11-30 Kazumasa Tanida Semiconductor chip manufacturing method, semiconductor chip, semiconductor device manufacturing method, and semiconductor device
WO2008101093A1 (en) * 2007-02-15 2008-08-21 Cufer Asset Ltd. L.L.C. Post-seed deposition process

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020017710A1 (en) * 2000-08-04 2002-02-14 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US20030060000A1 (en) * 2001-03-07 2003-03-27 Seiko Epson Corporation Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument
US20030183943A1 (en) * 2002-03-28 2003-10-02 Swan Johanna M. Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US20060267206A1 (en) * 2004-08-20 2006-11-30 Kazumasa Tanida Semiconductor chip manufacturing method, semiconductor chip, semiconductor device manufacturing method, and semiconductor device
WO2008101093A1 (en) * 2007-02-15 2008-08-21 Cufer Asset Ltd. L.L.C. Post-seed deposition process

Cited By (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048234B2 (en) 2006-10-10 2015-06-02 Tessera, Inc. Off-chip vias in stacked chips
US8461673B2 (en) 2006-10-10 2013-06-11 Tessera, Inc. Edge connect wafer level stacking
US9899353B2 (en) 2006-10-10 2018-02-20 Tessera, Inc. Off-chip vias in stacked chips
US8076788B2 (en) 2006-10-10 2011-12-13 Tessera, Inc. Off-chip vias in stacked chips
US9378967B2 (en) 2006-10-10 2016-06-28 Tessera, Inc. Method of making a stacked microelectronic package
US8999810B2 (en) 2006-10-10 2015-04-07 Tessera, Inc. Method of making a stacked microelectronic package
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US8476774B2 (en) 2006-10-10 2013-07-02 Tessera, Inc. Off-chip VIAS in stacked chips
US8426957B2 (en) 2006-10-10 2013-04-23 Tessera, Inc. Edge connect wafer level stacking
US8431435B2 (en) 2006-10-10 2013-04-30 Tessera, Inc. Edge connect wafer level stacking
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
US8653644B2 (en) 2006-11-22 2014-02-18 Tessera, Inc. Packaged semiconductor chips with array
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US8349654B2 (en) 2006-12-28 2013-01-08 Tessera, Inc. Method of fabricating stacked packages with bridging traces
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US8310036B2 (en) 2007-03-05 2012-11-13 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8735205B2 (en) 2007-03-05 2014-05-27 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8883562B2 (en) 2007-07-27 2014-11-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US8513794B2 (en) 2007-08-09 2013-08-20 Tessera, Inc. Stacked assembly including plurality of stacked microelectronic elements
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
WO2010104610A3 (en) * 2009-03-13 2011-01-13 Tessera Technologies Hungary Kft. Stacked microelectronic assembly with microelectronic elements having vias extending through bond pads
WO2010104610A2 (en) * 2009-03-13 2010-09-16 Tessera Technologies Hungary Kft. Stacked microelectronic assemblies having vias extending through bond pads
US8466542B2 (en) 2009-03-13 2013-06-18 Tessera, Inc. Stacked microelectronic assemblies having vias extending through bond pads
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8835223B2 (en) 2010-09-16 2014-09-16 Tessera, Inc. Chip assembly having via interconnects joined by plating
US8685793B2 (en) 2010-09-16 2014-04-01 Tessera, Inc. Chip assembly having via interconnects joined by plating
US8686565B2 (en) 2010-09-16 2014-04-01 Tessera, Inc. Stacked chip assembly having vertical vias
US9355948B2 (en) 2010-09-17 2016-05-31 Tessera, Inc. Multi-function and shielded 3D interconnects
US10354942B2 (en) 2010-09-17 2019-07-16 Tessera, Inc. Staged via formation from both sides of chip
US8809190B2 (en) 2010-09-17 2014-08-19 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
WO2012037216A3 (en) * 2010-09-17 2012-06-07 Tessera, Inc. Staged via formation from both sides of chip
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9224649B2 (en) 2010-12-08 2015-12-29 Tessera, Inc. Compliant interconnects in wafers
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8796828B2 (en) 2010-12-08 2014-08-05 Tessera, Inc. Compliant interconnects in wafers
EP2731133A2 (en) * 2012-11-13 2014-05-14 Delta Electronics, Inc. Interconnection structure and fabrication thereof
WO2024126197A1 (en) 2022-12-15 2024-06-20 Koninklijke Philips N.V. A system and method for imaging tissue

Similar Documents

Publication Publication Date Title
US7786587B2 (en) Semiconductor device and method for manufacturing thereof
WO2009023462A1 (en) Semiconductor device and method for manufacturing thereof
US7208838B2 (en) Semiconductor device, circuit board, and electronic instrument suitable for stacking and having a through hole
CN100573854C (en) Semiconductor device, circuit substrate and electronic equipment
KR100687980B1 (en) Semiconductor device, circuit board, and electronic device
JP3651596B2 (en) Semiconductor package, semiconductor device, electronic device, and semiconductor package manufacturing method
US8617926B2 (en) Semiconductor chip device with polymeric filler trench
JP3821125B2 (en) Semiconductor device manufacturing method, semiconductor device, circuit board, electronic device
US9147587B2 (en) Interconnect substrate with embedded semiconductor device and built-in stopper and method of making the same
US9984900B2 (en) Semiconductor device including at least one element
US10985138B2 (en) Semiconductor package having a plurality of chips and method of manufacturing the same
US20110284887A1 (en) Light emitting chip package and method for forming the same
US9087847B2 (en) Thermally enhanced interconnect substrate with embedded semiconductor device and built-in stopper and method of making the same
US8564133B2 (en) Chip package and method for forming the same
US20040207089A1 (en) Semiconductor device, method of manufacturing three-dimensional stacking type semiconductor device, circuit board, and electronic instrument
JP4155154B2 (en) Semiconductor device, circuit board, and electronic device
JP4967340B2 (en) SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE
CN112563220A (en) Chip package, manufacturing method thereof and electronic device
JP4509486B2 (en) Semiconductor device manufacturing method, semiconductor device, and electronic apparatus
CN111081554A (en) Embedded packaging structure and manufacturing method thereof
KR20100070285A (en) Semiconductor device and method for fabricating the same
US11329029B2 (en) Semiconductor package including embedded solder connection structure
US20230317565A1 (en) Electronic package and manufacturing method thereof
KR20120093730A (en) Semiconductor device and method for manufacturing the same
CN118553707A (en) Electronic package and method for manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08827239

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08827239

Country of ref document: EP

Kind code of ref document: A1