WO2009096192A1 - バッファ回路及びそれを備えたイメージセンサチップ並びに撮像装置 - Google Patents
バッファ回路及びそれを備えたイメージセンサチップ並びに撮像装置 Download PDFInfo
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- the present invention relates to a buffer circuit, and more particularly to a source follower type buffer circuit.
- a source follower is often used as a buffer circuit for driving a large load at high speed.
- a general source follower includes a constant current source and a driving transistor connected in series to the constant current source, and uses a gate voltage and a source voltage of the driving transistor as an input signal and an output signal, respectively.
- the drain current of the driving transistor is ideally constant regardless of the drain-source voltage, but actually the drain current increases as the drain-source voltage increases due to the channel length modulation effect. This means that even when the driving transistor is biased with a constant current, the gate-source voltage changes according to the change in the drain-source voltage.
- the gate-source voltage of the driving transistor changes according to the input signal, and a gain error or distortion occurs.
- the gain error and distortion become larger. For this reason, the source follower has a problem that it is difficult to drive a large load with low gain error and low distortion.
- a common source follower includes a transistor having a source and a gate connected to a drain and a source of a driving transistor, respectively, and a drain connected to a predetermined voltage node. It is known to additionally provide a constant current source connected to (see, for example, Patent Document 1). In this improved source follower, the gate-source voltage of the driving transistor is kept substantially constant even when the input signal changes, so that gain error and distortion can be improved.
- JP 60-136405 A pages 6-7, FIG. 4
- an object of the present invention is to realize a wide range input buffer circuit capable of driving a high load with high accuracy. It is another object of the present invention to realize a buffer circuit capable of driving a resistive load with high accuracy. It is another object of the present invention to provide an image sensor chip and an image pickup apparatus that include these buffer circuits.
- the buffer circuit includes a first and second cascode constant current source, a constant current source, one end connected to the output of the first cascode constant current source, and the other end constant current.
- a resistive load connected to the output of the source, a first transistor whose source is connected to the output of the second cascode constant current source, a source connected to a predetermined power supply node, and a drain connected to the first transistor.
- a second transistor having a gate connected to a connection point between the first cascode constant current source and the resistive load; a source connected to the drain of the first transistor; and a drain connected to the constant current source
- a third transistor having a gate connected to a source of the first transistor and connected to a connection point with the resistive load.
- the gate voltage and the source voltage of the first transistor are an input signal and an output signal of the buffer circuit, respectively.
- a buffer circuit includes first and second cascode constant current sources, a first cascode current mirror circuit whose output is connected to the output of the first cascode constant current source, and an output. Is connected to the input of the first cascode current mirror circuit, the first transistor is connected to the output of the second cascode constant current source, the source is a predetermined power supply node A second transistor having a drain connected to the drain of the first transistor, a gate connected to a connection point between the first cascode constant current source and the first cascode current mirror circuit, and a source connected to the first transistor 1 is connected to the drain of the first transistor, the drain is connected to the input of the second cascode current mirror circuit, and the gate is connected to the first transistor. And a third transistor connected to the data source. The gate voltage and the source voltage of the first transistor are an input signal and an output signal of the buffer circuit, respectively.
- the first and third transistors each operate as a source follower, and the drain-source voltage of the first transistor matches the gate-source voltage of the third transistor and is kept substantially constant. It is. Furthermore, although the second transistor is connected to the drain of the first transistor in one stage, the second transistor is equivalent to a cascode constant current source by negative feedback control of the gate voltage of the second transistor. High-precision constant current flows. Therefore, these buffer circuits can drive a high load with high accuracy while ensuring a sufficiently large input range.
- the buffer circuit further includes a constant current source connected in parallel to the second transistor, one end connected to the drain of the second transistor, and the other end connected to the gate of the second transistor. It is assumed that at least one of capacitive elements is provided. According to this, it is possible to suppress oscillation caused by the negative feedback control of the second transistor.
- a buffer circuit in one embodiment, includes a first cascode constant current source, a first transistor having a source connected to an output of the second cascode constant current source, and a source having a first source.
- the drain is connected to the drain of the first transistor, the gate is biased to the second transistor, the source is connected to the drain of the first transistor, and the drain is the first cascode constant current.
- a third transistor having a gate connected to the source of the first transistor; a source connected to the second power supply node; a drain connected to the drain of the second transistor; And a fourth transistor connected to the drain of the third transistor.
- the gate voltage and the source voltage of the first transistor are an input signal and an output signal of the buffer circuit, respectively. This makes it possible to drive a high load with high accuracy while ensuring a sufficiently large input range in the same manner as the buffer circuit, although the configuration is easier than that of the buffer circuit.
- the buffer circuit includes a first cascode constant current source, a drain connected to the output of the first cascode constant current source, and a source connected to the second cascode constant current source.
- a first transistor connected to the output; a second transistor having a source connected to the gate of the first transistor; a drain connected to the output of the second cascode constant current source; and a source having a predetermined power supply node
- a third transistor having a drain connected to the source of the second transistor and a gate connected to the drain of the first transistor.
- the gate voltage and the source voltage of the second transistor are an input signal and an output signal of the buffer circuit, respectively.
- the buffer circuit includes a third cascode constant current source that supplies a constant current to the source of the second transistor.
- each of the first and second transistors operates as a source follower, and the drain-source voltage of the second transistor is kept substantially constant in accordance with the gate-source voltage of the first transistor. It is. Further, when a resistive external load is connected, negative feedback control is performed on the gate voltage of the third transistor 24 so as to compensate the current flowing through the external load. Therefore, this buffer circuit can drive the resistive load with high accuracy.
- an image sensor chip includes an image sensor and a column ADC.
- the column ADC generates a ramp signal that supplies a ramp signal to any of the buffer circuits described above.
- the imaging apparatus includes the image sensor chip described above.
- a wide-range input buffer circuit capable of driving a high load with high accuracy and a buffer circuit capable of driving a resistive load with high accuracy can be realized. Further, it is possible to improve the quality of imaging data for an image sensor chip including such a buffer circuit and an imaging apparatus including the image sensor chip.
- FIG. 1 is a configuration diagram of a buffer circuit according to the first embodiment.
- FIG. 2 is a configuration diagram of a buffer circuit according to the second embodiment.
- FIG. 3 is a configuration diagram of a buffer circuit according to the third embodiment.
- FIG. 4 is a configuration diagram of a buffer circuit according to the fourth embodiment.
- FIG. 5 is an overview of the imaging apparatus.
- FIG. 6 is a configuration diagram of the image sensor chip.
- Cascode constant current source (first cascode constant current source, second cascode constant current source) 12 cascode constant current source (second cascode constant current source, third cascode constant current source) 13 constant current source 14 constant current source 15 cascode constant current source (first cascode constant current source) 16 cascode current mirror circuit (first cascode current mirror circuit) 17 Cascode current mirror circuit (second cascode current mirror circuit) 20 Resistive load 21 PMOS transistor (first transistor, second transistor) 22 NMOS transistor (second transistor) 23 NMOS transistor (third transistor, first transistor) 24 PMOS transistor (fourth transistor, third transistor) 30 capacitive element 100 imaging device 101 image sensor chip 102 image sensor 103 column ADC 1032 Comparator 1034 Ramp generation circuit 1035 Buffer circuit
- FIG. 1 shows a configuration of a buffer circuit according to the first embodiment.
- the buffer circuit can be manufactured by a CMOS process.
- the cascode constant current source 11 is configured by cascode connection of two NMOS transistors each having a bias voltage Vbn1 and Vbn2 applied to the gate, and supplies a constant current I11.
- the cascode constant current source 12 is configured by cascode connection of two PMOS transistors each having a bias voltage Vbp1 and Vbp2 applied to the gate, and supplies a constant current I12.
- the constant current source 13 includes a PMOS transistor having a gate to which a bias voltage Vbp1 is applied, and supplies a constant current I13.
- the resistive load 20 is connected to the output of the cascode constant current source 11, and the other end of the resistive load 20 is connected to the output of the constant current source 13.
- the resistive load 20 can be composed of a PMOS transistor, a resistance element, a variable resistance element, or the like with a bias voltage applied to the gate.
- the source of the PMOS transistor 21 is connected to the output of the cascode constant current source 12.
- the input signal Vin of the buffer circuit is applied to the gate of the PMOS transistor 21, and the output signal Vout of the buffer circuit is output from the source. That is, the PMOS transistor 21 operates as a source follower biased with a constant current I12.
- the drain of the NMOS transistor 22 is connected to the drain of the PMOS transistor 21.
- the source and gate of the NMOS transistor 22 are connected to a ground node and a connection point between the cascode constant current source 11 and the resistive load 20, respectively.
- the gate and source of the NMOS transistor 23 are connected to the source and drain of the PMOS transistor 21, respectively.
- the drain of the NMOS transistor 23 is connected to a connection point between the constant current source 13 and the resistive load 20. That is, the NMOS transistor 23 is biased with a constant current I13-I11 and operates as a source follower that receives the output signal Vout of the buffer circuit.
- the constant current source 14 is connected in parallel to the NMOS transistor 22.
- the constant current source 14 includes an NMOS transistor having a gate to which a bias voltage Vbn3 is applied, and supplies a constant current I14. Further, a capacitive element 30 for phase correction is connected between the gate and drain of the NMOS transistor 22.
- the gate voltage of the NMOS transistor 22 is subjected to negative feedback control so that the constant current I13 ⁇ I11 + I12 ⁇ I14 flows through the NMOS transistor 22.
- a voltage lower than the source voltage (output signal Vout) of the PMOS transistor 21 by the gate-source voltage of the NMOS transistor 23 is applied to the drain of the PMOS transistor 21. Therefore, the drain-source voltage of the PMOS transistor 21 matches the gate-source voltage of the NMOS transistor 23 regardless of the value of the input signal Vin, and is kept substantially constant.
- the PMOS transistor 21 is biased with a high-accuracy constant current I12 supplied from the cascode constant current source 12.
- the buffer circuit according to the present embodiment can drive a high load with high accuracy while ensuring a sufficiently large input range.
- FIG. 2 shows a configuration of the buffer circuit according to the second embodiment.
- the buffer circuit can also be manufactured by a CMOS process.
- Each of the cascode constant current sources 12 and 15 is configured by cascode connection of two PMOS transistors having bias voltages Vbp1 and Vbp2 applied to their gates, respectively.
- the former supplies a constant current I12
- the latter supplies a constant current I15.
- the cascode current mirror circuit 16 is configured by cascode-connecting two NMOS transistors on both the input side and the output side, and a bias voltage Vbn2 is applied to the gates of the NMOS transistors in the cascode stage on the input side and the output side. ing.
- the cascode current mirror circuit 17 is configured by cascode-connecting two PMOS transistors on both the input side and the output side, and a bias voltage Vbp2 is applied to the gates of the PMOS transistors in the cascode stage on the input side and the output side. ing.
- the output of the cascode current mirror circuit 17 is connected to the input of the cascode current mirror circuit 16.
- the output of the cascode constant current source 15 is connected to the output of the cascode current mirror circuit 16.
- the source of the PMOS transistor 21 is connected to the output of the cascode constant current source 12.
- the input signal Vin of the buffer circuit is applied to the gate of the PMOS transistor 21, and the output signal Vout of the buffer circuit is output from the source. That is, the PMOS transistor 21 operates as a source follower biased with a constant current I12.
- the drain of the NMOS transistor 22 is connected to the drain of the PMOS transistor 21.
- the source and gate of the NMOS transistor 22 are connected to a ground node and a connection point between the cascode constant current source 15 and the cascode current mirror circuit 16, respectively.
- the gate and source of the NMOS transistor 23 are connected to the source and drain of the PMOS transistor 21, respectively.
- the drain of the NMOS transistor 23 is connected to the input of the cascode current mirror circuit 17.
- the drain current of the NMOS transistor 23 is compared with the constant current I15, and negative feedback is applied to match it.
- the NMOS transistor 23 operates as a source follower biased with a constant current I15 that receives the output signal Vout of the buffer circuit.
- the constant current source 14 is connected in parallel to the NMOS transistor 22.
- the constant current source 14 includes an NMOS transistor having a gate to which a bias voltage Vbn3 is applied, and supplies a constant current I14. Further, a capacitive element 30 for phase compensation is connected between the gate and drain of the NMOS transistor 22.
- the gate voltage of the NMOS transistor 22 is subjected to negative feedback control so that the constant current I15 + I12 ⁇ I14 flows through the NMOS transistor 22.
- the drain-source voltage of the PMOS transistor 21 matches the gate-source voltage of the NMOS transistor 23 regardless of the value of the input signal Vin, and is kept substantially constant. It is.
- the PMOS transistor 21 is biased by the highly accurate constant current I12 supplied from the cascode constant current source 12, and the NMOS transistor 23 that determines the drain-source voltage is used as the NMOS transistor 23.
- the buffer circuit according to this embodiment since there is only one transistor between the drain of the PMOS transistor 21 and the ground, the input signal Vin can be lowered to the ground voltage. Therefore, the buffer circuit according to the present embodiment can drive a high load with high accuracy while ensuring a sufficiently large input range.
- the buffer circuit according to the present embodiment requires the cascode current mirror circuits 16 and 17, the circuit scale is larger than that of the buffer circuit according to the first embodiment.
- the buffer circuit according to the first embodiment does not use a current mirror, the buffer circuit according to the first embodiment can be configured with a smaller number of elements than the buffer circuit according to the second embodiment, and is excellent in stability.
- At least one of the constant current source 14 and the capacitive element 30 may be omitted.
- the capacitive element 30 is provided for the purpose of preventing the negative feedback oscillation, but the oscillation phenomenon can be sufficiently suppressed by providing the constant current source 14 without the capacitive element 30. Even if neither the constant current source 14 nor the capacitor 30 is omitted, the oscillation phenomenon can be suppressed by adjusting the characteristics of the transistors to appropriate values.
- FIG. 3 shows a configuration of the buffer circuit according to the third embodiment.
- the buffer circuit can also be manufactured by a CMOS process.
- Each of the cascode constant current sources 12 and 15 is configured by cascode connection of two PMOS transistors having bias voltages Vbp1 and Vbp2 applied to their gates, respectively.
- the former supplies a constant current I12
- the latter supplies a constant current I15.
- the source of the PMOS transistor 21 is connected to the output of the cascode constant current source 12.
- the input signal Vin of the buffer circuit is applied to the gate of the PMOS transistor 21, and the output signal Vout of the buffer circuit is output from the source. That is, the PMOS transistor 21 operates as a source follower biased with a constant current I12.
- the drain of the NMOS transistor 22 is connected to the drain of the PMOS transistor 21.
- the source of the NMOS transistor 22 is connected to the ground node, and the bias voltage Vbn1 is applied to the gate of the NMOS transistor 22. That is, the NMOS transistor 22 operates as a constant current source that supplies the constant current I22.
- the gate and source of the NMOS transistor 23 are connected to the source and drain of the PMOS transistor 21, respectively.
- the drain of the NMOS transistor 23 is connected to the output of the cascode constant current source 15. That is, the NMOS transistor 23 is biased with a constant current I15 and operates as a source follower that receives the output signal Vout of the buffer circuit.
- the drain of the PMOS transistor 24 is connected to the drain of the NMOS transistor 22.
- the source and gate of the PMOS transistor 24 are connected to the power supply voltage node and the drain of the NMOS transistor 23.
- the gate voltage of the PMOS transistor 24 is subjected to negative feedback control so that the constant currents I22-I15-I12 flow through the PMOS transistor 24.
- the drain-source voltage of the PMOS transistor 21 matches the gate-source voltage of the NMOS transistor 23 regardless of the value of the input signal Vin, and is kept substantially constant. It is.
- the PMOS transistor 21 is biased by the highly accurate constant current I12 supplied from the cascode constant current source 12, and the NMOS transistor 23 that determines the drain-source voltage is used as the NMOS transistor 23.
- the buffer circuit according to this embodiment since there is only one transistor between the drain of the PMOS transistor 21 and the ground, the input signal Vin can be lowered to the ground voltage. Therefore, the buffer circuit according to the present embodiment can drive a high load with high accuracy while ensuring a sufficiently large input range.
- the phase compensation capacitive element 30 provided in the buffer circuits according to the first and second embodiments is unnecessary. Therefore, the circuit area can be remarkably reduced as compared with the buffer circuits according to the first and second embodiments.
- FIG. 4 shows a configuration of the buffer circuit according to the fourth embodiment.
- the buffer circuit can also be manufactured by a CMOS process.
- the cascode constant current source 11 is configured by cascode connection of two NMOS transistors each having a bias voltage Vbn1 and Vbn2 applied to the gate, and supplies a constant current I11.
- Each of the cascode constant current sources 12 and 15 is configured by cascode connection of two PMOS transistors having bias voltages Vbp1 and Vbp2 applied to their gates, respectively.
- the former supplies a constant current I12, and the latter supplies a constant current I15.
- the drain and source of the PMOS transistor 21 are connected to the outputs of the cascode constant current sources 11 and 12, respectively.
- the input signal Vin of the buffer circuit is applied to the gate of the PMOS transistor 21, and the output signal Vout of the buffer circuit is output from the source.
- the gate and source of the NMOS transistor 23 are connected to the source and drain of the PMOS transistor 21, respectively.
- the drain of the NMOS transistor 23 is connected to the output of the cascode constant current source 15. That is, the NMOS transistor 23 is biased with a constant current I15 and operates as a source follower that receives the output signal Vout of the buffer circuit.
- the PMOS transistor 21 is biased with a constant current I11-I15.
- the drain of the PMOS transistor 24 is connected to the source of the PMOS transistor 21.
- the source and gate of the PMOS transistor 24 are connected to the power supply voltage node and the drain of the NMOS transistor 23.
- the drain-source voltage of the PMOS transistor 21 matches the gate-source voltage of the NMOS transistor 23 regardless of the value of the input signal Vin, and is kept substantially constant. It is. Further, in the buffer circuit according to the present embodiment, the PMOS transistor 21 is biased by I11-I15 which is a difference between the high-precision constant currents supplied from the cascode constant current sources 11 and 15, and between the drain and source thereof. Since the highly accurate constant current I15 supplied from the cascode constant current source 15 also flows through the NMOS transistor 23 that determines the voltage, the gain error and distortion can be greatly reduced. Therefore, the buffer circuit according to the present embodiment can drive a resistive external load with high accuracy.
- the cascode constant current source 12 may be omitted. Even in this case, the above-described effect produced by the buffer circuit according to the present embodiment is not impaired.
- the buffer circuit configured by reversing all the polarities of the transistors constituting the buffer circuit according to each of the above embodiments also has the same effect as described above.
- FIG. 5 shows an overview of the imaging apparatus.
- the imaging device 100 is a digital still camera, a digital video camera, or the like.
- the imaging apparatus 100 has an image sensor chip 101 built therein.
- FIG. 6 shows the configuration of the image sensor chip 101.
- the image sensor chip 101 includes an image sensor 102 and a column ADC 103.
- the column ADC 103 includes a counter 1031, a comparator 1032 provided corresponding to each pixel column of the image sensor 102, a digital memory 1033, a ramp generation circuit 1034, and a buffer circuit 1035.
- the ramp generation circuit 1034 generates a ramp signal in synchronization with the clock signal CLK.
- the counter 1031 counts pulses of the clock signal CLK and supplies a common count value to the plurality of digital memories 1033.
- the buffer circuit 1035 receives the ramp signal from the ramp generation circuit 1034 and supplies a common ramp signal to the plurality of comparators 1032.
- the comparator 1032 compares the signal output for each pixel column of the image sensor 102 with the output of the buffer circuit 1035.
- Each digital memory 1033 stores the count value of the counter 1031 when the output of each comparator 1032 changes. Then, by sequentially shifting and outputting the values stored in the plurality of digital memories 1033, the electric signal output from the image sensor 102 is taken out as imaging data.
- the buffer circuit 1035 must be capable of driving a high load with high accuracy in order to realize accurate A / D conversion and variable gain. Therefore, the buffer circuit according to the first to fourth embodiments may be used as the buffer circuit 1035. As a result, the electrical signal output from the image sensor 102 can be A / D converted with high accuracy, and the quality of the imaging data can be improved.
- the buffer circuit according to the present invention has a large input range and can drive a high load with high accuracy, a ramp signal is supplied to a column ADC that performs A / D conversion on thousands of electrical signals output from the image sensor. It is useful as a buffer circuit for supplying
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Abstract
Description
12 カスコード定電流源(第2のカスコード定電流源、第3のカスコード定電流源)
13 定電流源
14 定電流源
15 カスコード定電流源(第1のカスコード定電流源)
16 カスコードカレントミラー回路(第1のカスコードカレントミラー回路)
17 カスコードカレントミラー回路(第2のカスコードカレントミラー回路)
20 抵抗性負荷
21 PMOSトランジスタ(第1のトランジスタ、第2のトランジスタ)
22 NMOSトランジスタ(第2のトランジスタ)
23 NMOSトランジスタ(第3のトランジスタ、第1のトランジスタ)
24 PMOSトランジスタ(第4のトランジスタ、第3のトランジスタ)
30 容量素子
100 撮像装置
101 イメージセンサチップ
102 イメージセンサ
103 カラムADC
1032 比較器
1034 ランプ発生回路
1035 バッファ回路
図1は、第1の実施形態に係るバッファ回路の構成を示す。当該バッファ回路はCMOSプロセスによって製造可能である。カスコード定電流源11は、ゲートにバイアス電圧Vbn1及びVbn2がそれぞれ印加された二つのNMOSトランジスタがカスコード接続されて構成されており、定電流I11を供給する。カスコード定電流源12は、ゲートにバイアス電圧Vbp1及びVbp2がそれぞれ印加された二つのPMOSトランジスタがカスコード接続されて構成されており、定電流I12を供給する。定電流源13は、ゲートにバイアス電圧Vbp1が印加されたPMOSトランジスタで構成されており、定電流I13を供給する。
図2は、第2の実施形態に係るバッファ回路の構成を示す。当該バッファ回路もまたCMOSプロセスによって製造可能である。カスコード定電流源12及び15は、いずれも、ゲートにバイアス電圧Vbp1及びVbp2がそれぞれ印加された二つのPMOSトランジスタがカスコード接続されて構成されている。前者は定電流I12を供給し、後者は定電流I15を供給する。
図3は、第3の実施形態に係るバッファ回路の構成を示す。当該バッファ回路もまたCMOSプロセスによって製造可能である。カスコード定電流源12及び15は、いずれも、ゲートにバイアス電圧Vbp1及びVbp2がそれぞれ印加された二つのPMOSトランジスタがカスコード接続されて構成されている。前者は定電流I12を供給し、後者は定電流I15を供給する。
図4は、第4の実施形態に係るバッファ回路の構成を示す。当該バッファ回路もまたCMOSプロセスによって製造可能である。カスコード定電流源11は、ゲートにバイアス電圧Vbn1及びVbn2がそれぞれ印加された二つのNMOSトランジスタがカスコード接続されて構成されており、定電流I11を供給する。カスコード定電流源12及び15は、いずれも、ゲートにバイアス電圧Vbp1及びVbp2がそれぞれ印加された二つのPMOSトランジスタがカスコード接続されて構成されている。前者は定電流I12を供給し、後者は定電流I15を供給する。
図5は、撮像装置の概観を示す。具体的には、撮像装置100は、デジタルスチルカメラ、デジタルビデオカメラなどである。撮像装置100はイメージセンサチップ101を内蔵している。図6は、イメージセンサチップ101の構成を示す。イメージセンサチップ101は、イメージセンサ102及びカラムADC103を備えている。カラムADC103は、カウンタ1031、イメージセンサ102の各画素列に対応して設けられた比較器1032、デジタルメモリ1033、ランプ発生回路1034及びバッファ回路1035を備えている。
Claims (12)
- 第1及び第2のカスコード定電流源と、
定電流源と、
一端が前記第1のカスコード定電流源の出力に接続され、他端が前記定電流源の出力に接続された抵抗性負荷と、
ソースが前記第2のカスコード定電流源の出力に接続された第1のトランジスタと、
ソースが所定の電源ノードに接続され、ドレインが前記第1のトランジスタのドレインに接続され、ゲートが前記第1のカスコード定電流源と前記抵抗性負荷との接続点に接続された第2のトランジスタと、
ソースが前記第1のトランジスタのドレインに接続され、ドレインが前記定電流源と前記抵抗性負荷との接続点に接続され、ゲートが前記第1のトランジスタのソースに接続された第3のトランジスタとを備え、
前記第1のトランジスタのゲート電圧及びソース電圧を、それぞれ、入力信号及び出力信号とする
ことを特徴とするバッファ回路。 - 第1及び第2のカスコード定電流源と、
出力が前記第1のカスコード定電流源の出力に接続された第1のカスコードカレントミラー回路と、
出力が前記第1のカスコードカレントミラー回路の入力に接続された第2のカスコードカレントミラー回路と、
ソースが前記第2のカスコード定電流源の出力に接続された第1のトランジスタと、
ソースが所定の電源ノードに接続され、ドレインが前記第1のトランジスタのドレインに接続され、ゲートが前記第1のカスコード定電流源と前記第1のカスコードカレントミラー回路との接続点に接続された第2のトランジスタと、
ソースが前記第1のトランジスタのドレインに接続され、ドレインが前記第2のカスコードカレントミラー回路の入力に接続され、ゲートが前記第1のトランジスタのソースに接続された第3のトランジスタとを備え、
前記第1のトランジスタのゲート電圧及びソース電圧を、それぞれ、入力信号及び出力信号とする
ことを特徴とするバッファ回路。 - 請求項1及び2のいずれか一つのバッファ回路において、
前記第2のトランジスタに並列に接続された定電流源を備えた
ことを特徴とするバッファ回路。 - 請求項1、2及び3のいずれか一つのバッファ回路において、
一端が前記第2のトランジスタのドレインに接続され、他端が前記第2のトランジスタのゲートに接続された容量素子を備えた
ことを特徴とするバッファ回路。 - 請求項1に記載のバッファ回路において、
前記抵抗性負荷は、ゲートがバイアスされたトランジスタである
ことを特徴とするバッファ回路。 - 請求項1に記載のバッファ回路において、
前記抵抗性負荷は、抵抗素子である
ことを特徴とするバッファ回路。 - 請求項6に記載のバッファ回路において、
前記抵抗素子は、抵抗値が可変の可変抵抗素子である
ことを特徴とするバッファ回路。 - 第1及び第2のカスコード定電流源と、
ソースが前記第2のカスコード定電流源の出力に接続された第1のトランジスタと、
ソースが第1の電源ノードに接続され、ドレインが前記第1のトランジスタのドレインに接続され、ゲートがバイアスされた第2のトランジスタと、
ソースが前記第1のトランジスタのドレインに接続され、ドレインが前記第1のカスコード定電流源の出力に接続され、ゲートが前記第1のトランジスタのソースに接続された第3のトランジスタと、
ソースが第2の電源ノードに接続され、ドレインが前記第2のトランジスタのドレインに接続され、ゲートが前記第3のトランジスタのドレインに接続された第4のトランジスタとを備え、
前記第1のトランジスタのゲート電圧及びソース電圧を、それぞれ、入力信号及び出力信号とする
ことを特徴とするバッファ回路。 - 第1及び第2のカスコード定電流源と、
ドレインが前記第1のカスコード定電流源の出力に接続され、ソースが前記第2のカスコード定電流源の出力に接続された第1のトランジスタと、
ソースが前記第1のトランジスタのゲートに接続され、ドレインが前記第2のカスコード定電流源の出力に接続された第2のトランジスタと、
ソースが所定の電源ノードに接続され、ドレインが前記第2のトランジスタのソースに接続され、ゲートが前記第1のトランジスタのドレインに接続された第3のトランジスタとを備え、
前記第2のトランジスタのゲート電圧及びソース電圧を、それぞれ、入力信号及び出力信号とする
ことを特徴とするバッファ回路。 - 請求項9のバッファ回路において、
前記第2のトランジスタのソースに定電流を供給する第3のカスコード定電流源を備えた
ことを特徴とするバッファ回路。 - イメージセンサと、カラムADCとを備えたイメージセンサチップであって、
前記カラムADCは、
請求項1から10のいずれか一つのバッファ回路と、
前記バッファ回路にランプ信号を供給するランプ発生回路と、
前記イメージセンサの画素列ごとに出力される信号と前記バッファ回路の出力とを比較する複数の比較器とを有する
ことを特徴とするイメージセンサチップ。 - 請求項11に記載のイメージセンサチップを備えた
ことを特徴とする撮像装置。
Priority Applications (2)
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JP2009551437A JPWO2009096192A1 (ja) | 2008-01-31 | 2009-01-30 | バッファ回路及びそれを備えたイメージセンサチップ並びに撮像装置 |
US12/809,921 US20100289936A1 (en) | 2008-01-31 | 2009-01-30 | Buffer circuit, image sensor chip comprising the same, and image pickup device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008-021483 | 2008-01-31 | ||
JP2008021483 | 2008-01-31 |
Publications (1)
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WO2009096192A1 true WO2009096192A1 (ja) | 2009-08-06 |
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PCT/JP2009/000363 WO2009096192A1 (ja) | 2008-01-31 | 2009-01-30 | バッファ回路及びそれを備えたイメージセンサチップ並びに撮像装置 |
Country Status (3)
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US (1) | US20100289936A1 (ja) |
JP (1) | JPWO2009096192A1 (ja) |
WO (1) | WO2009096192A1 (ja) |
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KR101181310B1 (ko) * | 2010-06-30 | 2012-09-11 | 에스케이하이닉스 주식회사 | 램프 신호 발생기 및 이미지 센서 |
KR20160121189A (ko) | 2015-04-10 | 2016-10-19 | 삼성전자주식회사 | 아날로그-디지털 변환기의 선형성을 향상시키는 이미지 센서 및 이를 포함하는 이미지 처리 시스템 |
US10133292B1 (en) * | 2016-06-24 | 2018-11-20 | Cadence Design Systems, Inc. | Low supply current mirror |
CN106301379B (zh) * | 2016-08-17 | 2023-05-05 | 宁波大学 | 一种输出光滑的dac单元电路 |
CN108063905B (zh) * | 2016-11-09 | 2020-04-14 | 京东方科技集团股份有限公司 | 像素感应电路及其驱动方法、图像传感器、电子设备 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01125108A (ja) * | 1987-11-10 | 1989-05-17 | Nec Corp | Fet負荷増幅回路 |
JPH05284008A (ja) * | 1992-03-30 | 1993-10-29 | Hitachi Ltd | 半導体集積回路装置 |
JPH06152385A (ja) * | 1992-10-30 | 1994-05-31 | Oki Electric Ind Co Ltd | 半導体論理回路 |
JPH09232936A (ja) * | 1995-12-21 | 1997-09-05 | Toshiba Corp | 出力回路 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4495472A (en) * | 1982-11-22 | 1985-01-22 | At&T Bell Laboratories | Stable fast-settling voltage reference buffer amplifier |
US5198782A (en) * | 1991-01-15 | 1993-03-30 | Crystal Semiconductor | Low distortion amplifier output stage for dac |
US6924674B2 (en) * | 2003-10-27 | 2005-08-02 | Agere Systems Inc. | Composite source follower |
TWI474597B (zh) * | 2006-05-31 | 2015-02-21 | Intersil Americas LLC | 用於轉移電荷的裝置 |
JP5251765B2 (ja) * | 2009-07-15 | 2013-07-31 | ソニー株式会社 | 固体撮像素子の出力回路、固体撮像素子及び撮像装置 |
-
2009
- 2009-01-30 JP JP2009551437A patent/JPWO2009096192A1/ja not_active Ceased
- 2009-01-30 US US12/809,921 patent/US20100289936A1/en not_active Abandoned
- 2009-01-30 WO PCT/JP2009/000363 patent/WO2009096192A1/ja active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01125108A (ja) * | 1987-11-10 | 1989-05-17 | Nec Corp | Fet負荷増幅回路 |
JPH05284008A (ja) * | 1992-03-30 | 1993-10-29 | Hitachi Ltd | 半導体集積回路装置 |
JPH06152385A (ja) * | 1992-10-30 | 1994-05-31 | Oki Electric Ind Co Ltd | 半導体論理回路 |
JPH09232936A (ja) * | 1995-12-21 | 1997-09-05 | Toshiba Corp | 出力回路 |
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US20100289936A1 (en) | 2010-11-18 |
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