WO2009086433A2

WO2009086433A2 - Non-volatile memory cell with charge storage layer in u-shaped groove

Info

Publication number: WO2009086433A2
Application number: PCT/US2008/088255
Authority: WO
Inventors: Gary Bela Bronner
Original assignee: Rambus Inc.
Priority date: 2007-12-27
Filing date: 2008-12-23
Publication date: 2009-07-09
Also published as: WO2009086433A3

Abstract

A non-volatile memory cell includes a charge storage layer formed in a groove in a semiconductor substrate, and a source region and a drain region on opposite sides of the groove, with at least part of the charge storage layer not overlapping with the source region and the drain region. The non-volatile memory cell may be a flash memory cell or a SONOS type memory cell.

Description

NON- VOLATILE MEMORY CELL WITH CHARGE STORAGE LAYER

FORMED IN U-SHAPED GROOVE

INVENTOR

Gary BeIa Bronner

BACKGROUND

[0001] This present disclosure relates to a non- volatile memory and, more specifically, to a non- volatile memory cell with a charge storage layer formed deep in a U-shaped groove.

[0002] A flash memory is a type of non- volatile memory device that does not need power to maintain the information stored therein. Flash memories can be electrically erased and reprogrammed. Flash memory stores information in an array of memory cells, with each cell including a charge trapping layer commonly referred to as a floating gate. The data stored in the flash memory cell depends upon whether or not charges are trapped in the floating gate. In single-level cell devices, each flash memory cell stores one bit of information (for example, "1" or "0"). Other multi-level cell devices store more than one bit (for example, "11" or "10" or "01" or "00") per cell by including circuitry to distinguish between multiple levels of electrical charge trapped in the floating gates of its cells. Other types of flash memory include, for example, a SONOS (Silicon/Oxide/Nitride/Oxide/Silicon) type memory cell or a TANOS (TaN-Al₂Os-SiSN₄-SiO₂-Si) type memory cell, where charges are trapped in a Silicon Nitride (Si₃N₄) layer to store data in the memory cell.

[0003] A flash memory cell resembles a standard MOSFET (Metal Oxide Semiconductor Field Effect Transistor), except that it has two gates instead of just one gate. On top is the control gate (CG), as in other MOS transistors, but below the control gate is the floating gate (FG). The floating gate is placed between the control gate and the channel, and the channel is disposed between the source and the drain. Because the floating gate is electrically isolated from the control gate and channel by respective insulating layers, any electrons placed on it are, under normal conditions, trapped therein. Accordingly, absent application of an electric field to discharge electrons from the floating gate, charge trapped on the floating gate will remain trapped for an extended period of time (e.g., years) even when power is removed from the flash memory device, thereby providing the non- volatile character of the flash memory device.

[0004] Reading data stored within a flash memory cell involves sensing the presence or absence of stored charge in a single-bit (binary) storage device (i.e., distinguishing between charge-present and charge-absent states), or distinguishing between multiple levels of stored charge in a multi-bit (multi-level) storage device. More specifically, when the floating gate holds charge, the charge screens (partially cancels) the electrical field from the control gate, effectively modifying the threshold voltage (V_T) of the flash memory cell. That is, the formation of a conductive channel (i.e., enhancement channel) between the source and the drain of the flash memory cell is a function of the voltage level applied to the control gate less the opposite -polarity charge captured on the floating gate. Accordingly, during read-out from the flash memory cell, a voltage is applied to the control gate, and the channel will become conducting or remain insulating, depending on the V_T of the flash memory cell, which is in turn controlled by whether or not charges are trapped in the floating gate. The presence or absence of current flow through the MOSFET channel is sensed to reproduce the stored data. In a multi-level cell device, the control gate is set at multiple levels to determine the exact Vt of the memory cell. For example, in a flash memory cell storing 2 bits, there are 4 possible Vt levels. An initial sense will set the control gate voltage at the mid-point of the "00" level and the "11" level and then depending on the result the second sense will set the control gate at either the A point or the ³A point between the "00" level and the "11" level in order to determine more precisely the level of trapped charge in the floating gate.

[0005] There are two leading types of flash memory array architectures, NOR type and NAND type. Both NOR type and NAND type flash memories include essentially the same physical memory cell architecture, but the memory cells are interconnected to bit lines differently such that different programming and reading mechanisms are used to access the flash memory cells. A single-level NOR flash cell in its default state is logically equivalent to a binary " 1 " value, because current will flow through the channel under application of an appropriate voltage to the control gate. A NOR flash cell can be programmed, or set to a binary "0" value, by applying an elevated on- voltage (e.g., > 10 V) to the control gate and approximately ¹A of the control gate voltage (e.g., > 5 V) to the drain of the flash memory cell. This causes formation of the channel (i.e., conductive path) between the source and drain to enable source-to-drain electrons to flow between the source and the drain. The source-drain voltage is sufficiently high to cause some high energy electrons to jump through an insulating layer surrounding the floating gate onto the floating gate via a process called hot electron injection (or channel hot electrons, CHE) and be trapped therein. To erase a NOR flash cell (resetting it to the "1" state), a large voltage of the opposite polarity is applied between the control gate and the substrate, pulling the electrons off the floating gate through Fowler-Nordheim tunneling. On the other hand NAND flash memory devices use tunneling for both writing and erasing. During a write, electrons tunnel from the substrate onto the floating gate of the NAND flash memory cell. During an erase, electrons tunnel from the floating gate to the substrate of the NAND flash memory cell.

[0006] Floating gate memory cells face challenges as the channel length become shorter and shorter, for example, below 40 nm. Specifically, as the size of the floating gate becomes smaller, short channel effects become poor, adversely affecting the operation of NOR type flash memory cells. Examples of short channel effects include "punch through" and DIBL (Drain Induced Barrier Lowering). "Punch through" may occur when a high drain voltage causes uncontrolled current (current that is not controlled by the floating gate) to flow. DIBL refers to the flash memory cell's effective threshold voltage decreasing due to the small size of the floating gate. In addition, for NAND flash memory cells, unintentional programming of adjacent memory cells ("program disturb") may occur due to capacitive coupling between the control gate and the floating gate of an adjacent memory cells. In addition, the number of electrons stored in the floating gate drops quickly to an unacceptably low level, Also, for NOR type flash memory cells programmed via channel hot electrons (CHE), the write bandwidth becomes poor due to the inefficiency of CHE creation. Some researches show that the height of the floating gate may need to be scaled down (e.g., height scaled down to less than 100 A for floating gate with channel length below 40 nm) in order to minimize capacitive coupling between the control gate and the floating gate of the adjacent cell. However, there are practical limits to how thin the floating gate can be fabricated. Conventional chemical vapor deposition (CVD) techniques typically cannot deposit polysilicon layers for the floating gate thinner than 100 A in order to form a continuous film. Thinner polysilicon layers are not stable and tend to agglomerate into small silicon islands rather than form a continuous film.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The teachings of the embodiments of the present disclosure can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.

[0008] FIG. IA illustrates the structure of a flash memory cell with a floating gate formed in a U-shaped groove, according to one embodiment of the present disclosure.

[0009] FIG. IB illustrates the structure of a flash memory cell with a floating gate formed in a U-shaped groove, according to an alternative embodiment of the present disclosure.

[0010] FIG. 2 illustrates the structure of a SONOS (Silicon/Oxide/Nitride/Oxide/Silicon) type memory cell with a charge storage layer formed in a U-shaped groove, according to one embodiment of the present disclosure.

[0011] FIGS. 3A, 3B, 3C-1, 3C-2, 3D-1, 3D-2, 3E-1, 3E-2, 3F-1, 3F-2, 3G-1, and 3G-2 illustrate the process of fabricating a flash memory cell with a floating gate formed in a U- shaped groove, according to embodiments of the present disclosure as shown in FIGS. IA and IB.

[0012] FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G, and 4H illustrate the process of fabricating a SONOS type memory cell with a charge storage layer formed in a U-shaped groove, according to one embodiment of the present disclosure as shown in FIG. 2.

DETAILED DESCRIPTION OF EMBODIMENTS

[0013] Embodiments of the present disclosure include a non-volatile memory cell with a charge storage layer formed in a groove in a semiconductor substrate, with at least one of a source region and a drain region of the non- volatile memory cell not extending beyond a dielectric layer formed between a control gate and a charge storage layer. More specifically, in one embodiment, the non-volatile memory cell comprises a charge storage layer formed in a groove of the semiconductor substrate, a dielectric layer formed on the charge storage layer with at least a part of the dielectric layer being formed in the groove below a surface of the substrate, a control gate formed on the dielectric layer, a source region formed in the substrate on a first side of the control gate, and a drain region formed in the substrate on a second side of the control gate. At least one of the source region and the drain region does not extend in the substrate beyond the dielectric layer to overlap with the charge storage layer. Thus, in one embodiment, the source region and the drain region do not overlap with the charge storage layer. In another embodiment, the source region does not overlap with the charge storage layer but the drain region overlaps with the charge storage layer. An induced channel is formed between the source region and the drain region along a contour of the groove, when a voltage potential is applied between the control gate and the substrate. The groove may have a substantially U- shape.

[0014] In one embodiment, the non-volatile memory cell is a flash memory cell and the charge storage layer includes a floating gate polysilicon layer. In another embodiment, the non-volatile memory cell is a SONOS type memory cell and the charge storage layer includes a silicon nitride layer formed between a first silicon dioxide layer and a second dioxide layer, where the silicon nitride layer, the second silicon dioxide layer, and at least a part of the first silicon dioxide layer are formed within the groove. The groove may have a substantially U- shape, and the first silicon dioxide layer, the silicon nitride layer, and the second silicon dioxide layer also may have the substantially U-shape. Other types of charge storage layers may be used in alternative embodiments.

[0015] In one embodiment, the control gate includes a control gate polysilicon layer formed above the charge storage layer. At least a part of the control gate polysilicon layer is formed in the groove below the surface of the substrate and extends, in one embodiment, to a depth below the bottom edge of at least one of the source region and the drain region. The control gate polysilicon layer may also extend, in part, above the surface of the substrate.

[0016] The non- volatile memory according to the present disclosure has advantages over conventional non- volatile memory cell structures. First, the short channel behavior of the non-volatile memory cell is improved, because the groove effectively increases the length of the channel between the source and the drain of the non- volatile memory cell. Second, program disturb between adjacent memory cells can be avoided, because the charge storage layer is shielded from the control gate of an adjacent memory cell by the substrate. Third, the number of electrons that can be trapped in the charge storage layer is increased due to the increased surface area of the charge storage layer formed in a U-shaped groove, thereby allowing for a smaller, shorter channel floating gate without reducing the charge storage capacity of the floating gate. Fourth, CHE programming using the induced channel significantly improves the write speed and write bandwidth. [0017] The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims.

[0018] The Figures (FIG.) and the following description relate to preferred embodiments of the present disclosure by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of the disclosure.

[0019] Reference will now be made in detail to several embodiments of the present disclosure(s), examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the disclosure described herein.

[0020] FIG. IA illustrates the structure of a flash memory cell with a floating gate formed in a U-shaped groove, according to one embodiment of the present disclosure. The flash memory cell is fabricated in a p-well substrate (or Silicon substrate) 102 and includes a floating gate 104, a dielectric layer 105, which can be a high-k dielectric layer (with high dielectric constant (k) compared to that Of SiO₂), silicon oxide (SiO₂) layers 116, 118, and a control gate structure comprised of the control gate polysilicon 106, the tungsten suicide (WSi₂) 108, and the silicon nitride (Si₃N₄) layer 110. Although FIG. IA illustrates one flash memory cell, it should be noted that a flash memory device would have a plurality of such flash memory cells of FIG. IA arranged in rows and columns, accessible via word line and bit line circuitry.

[0021] As shown in FIG. IA, the flash memory cell includes a floating gate 104 comprised of polysilicon. Other types of materials may be used for the floating gate 104. For example, the floating gate 104 may be formed with nanocrystals of different conductors such as silicon or Tantalum Nitride (TaN) or other metallic films. The floating gate 104 is used as the charge storage layer for the flash memory. The floating gate 104 is contained entirely within a U-shaped groove (or trench) 120 etched into the silicon substrate (typically p-well substrate) 102. Additionally, in the embodiment of FIG. IA, the floating gate 104 is entrenched deep into the groove 120 of the silicon substrate 102 such that the floating gate 104 does not overlap with the source region 112 and the drain region 114 of the flash memory cell, which improves the write efficiency as will be explained in more detail below. Between the floating gate 104 and the substrate 102 is a thin silicon dioxide layer 116 which provides insulation between the floating gate 104 and the substrate 102 and serves as the tunneling oxide for the flash memory cell.

[0022] The dielectric layer 105 separates the floating gate 104 from the control gate polysilicon 106. The entire dielectric layer 105 is formed in the groove below the surface of the substrate 102. The source region 112 and the drain region 114 are formed such that they do not extend in the substrate 102 beyond the high-k dielectric layer 105. As a result, the floating gate 104 does not overlap with the source region 112 and the drain region 114 of the flash memory cell, meaning that the floating gate 104 is separated from the source region 112 or the drain region 114 by part of the substrate 102 below the source region 112 or the drain region 114, or that an inversion layer or channel that can be induced in the substrate 102 by the floating gate 104 itself would generally not come in contact with the source region 112 or the drain region 114. The control gate polysilicon 106 is formed above the floating gate 104 and the dielectric layer 105, deep into the groove 120 such that it extends beyond the depths of the source region 112 and the drain region 114. In one embodiment, the control gate polysilicon 106 is deposited such that part of the control gate polysilicon 106 extends below the surface of the substrate 102 in the U-shaped groove 120 beyond the depth to which the source 112 and drain 114 regions extend, and another part of the control gate polysilicon 106 extends above the surface of the substrate 102. Other conductive material (e.g., metal) may be used to form the control gate 106. The tungsten suicide 108 is formed on the control gate polysilicon 106 to reduce the resistance of the word line. Other types of metallic material may be used instead of tungsten suicide 108 for the control gate metallic layer 108. For example, other suicide layers such as molybdenum suicide, titanium suicide, cobalt suicide, or nickel suicide could be used for the control gate metallic layer 108. Additionally, metal layers with appropriate barrier, such as tungsten/tungsten nitride layers, could be used. When a high voltage is applied to the control gate structure 108, 106, inversion regions 129 are induced by the voltage on the control gate along the SiO₂ layer 118 near the source and drain regions 112 and 114, respectively, and an inversion region 128 is induced by a voltage coupled to the floating gate along the contours of the groove 120 along the SiO₂ layer 116 near a bottom surface of the groove 120 facing the floating gate. The inversion regions 129 can act as source/drain extensions while the inversion 128 can act as a channel between the source/drain extensions, so that the S/D extensions 129 and the channel 128 together may form a conductive path 117 between the source region 112 and the drain region 114. The silicon nitride layer 110 is formed on the tungsten suicide 108 to protect the tungsten suicide 108. The silicon dioxide layer 118 insulates the control gate polysilicon 106 from the substrate 102.

[0023] To write to the flash memory cell, a high voltage (e.g., 10 V) is applied to the control gate 106, the source 112 is grounded (0 V), a medium voltage (e.g., 5 V) lower than the voltage applied to the control gate 106 is applied to the drain 114, and the p-well or substrate 102 is grounded (0 V). This causes the induced S/D extensions 129 and the induced channel 128 to be created along the contours of the groove 120, and a source-drain current to flow along the conductive path 117 comprising the induced S/D extensions 129 and the induced channel 128. The source-drain current causes some high energy electrons to tunnel through the insulating silicon dioxide layer 116 onto the floating gate 104 via hot electron injection (or channel hot electrons, CHE) or other mechanisms and be trapped therein, thereby programming the flash memory cell with a binary "0" value. The level of the high voltage applied to the control gate 106 in the write mode of the flash memory cell may vary depending upon the thickness of the silicon oxide layers 116 and the high-k dielectric layer 105.

[0024] To erase data from the flash memory cell, the control gate 106 is grounded and a high voltage (e.g., 20 V) is applied to the p-well substrate 102. The source/drain regions 112, 114 are left floating. This causes the electrons trapped in the floating gate 104 to tunnel out through the tunneling silicon dioxide layer 116, thereby erasing the data stored in the flash memory cell.

[0025] To read data from the flash memory cell, the source 112 is grounded (0 V), a medium voltage Vmid (e.g., 5 V) is applied to the control gate 106, a low voltage (e.g., 1 V) is applied to the drain 114, and the p-well substrate 102 is grounded. The voltage Vmid is set to be between the threshold voltage V_tl of the flash memory cell when no electrons are trapped in the floating gate 104 and the threshold voltage V_to of the flash memory cell when electrons are trapped in the floating gate 104, i.e., Vt₁ < Vmid < Vt₀. As a result, current will flow through the induced S/D extensions 129 and the induced channel 128. If high current flows through the induced S/D extensions 129 and the induced channel 128, that indicates that the threshold voltage of the flash memory cell is at its low level Vt₁ with no electrons trapped in the floating gate, and thus the data read from the flash memory cell is binary data "1." If low or no current flows through the induced S/D extensions 129 and the induced channel 128, that indicates that the threshold voltage of the flash memory cell is at its high level Vto with electrons trapped in the floating gate 104, and thus the data read from the flash memory cell is binary data "0." Although in this example, two levels "1" and "0" of data are stored in the flash memory cell, it is also possible to have a multi-level memory cell (e.g., "11," "10," "01," and "00") by determining the current level over multiple levels of electrical charge trapped in the floating gate 104 of the flash memory cell.

[0026] The flash memory cell according to the present disclosure has advantages over conventional flash memory cell structures. First, the short channel behavior of the flash memory cell is improved without increasing the cell size, because the extension of the channel along the perimeter of the U-groove 120 effectively increases the length of the channel between the source 112 and the drain 114 relative to a channel that extends laterally from source to drain. Second, program disturb between adjacent flash memory cells is avoided, because the floating gate 104 is shielded from the control gate of an adjacent memory cell by the substrate 120. Third, the number of electrons that can be trapped in the floating gate 104 is increased due to the increased surface area of the floating gate 104 facing the substrate 102 and separated from the substrate by mostly the thin oxide layer 116, thereby allowing for a smaller, shorter lateral separation between the source and drain without reducing the charge storage capacity of the floating gate 104. The increased surface area of the floating gate 104 increases the capacitance between the floating gate 104 and the substrate 120, thereby allowing more electrons to be stored in the floating gate 104 for a given shift in the threshold voltage V_t. Fourth, CHE programming using the induced S/D extensions 129 significantly improves the write speed and write bandwidth, in the order of approximately 100 - 1000 times compared to that of conventional flash memory cells, since an induced channel 128 is much more efficient for generating hot electrons. That is, when a positive voltage is applied to the control gate 106, S/D extensions 129 are created directly by the control gate, extending the source/drain regions 112, 114 toward top corners 107 of the floating gate 104. This induced S/D extensions 129 lead to a high electric field between the induced source/drain extensions 129 and the floating gate 104, which results in very efficient creation of channel hot electrons.

[0027] FIG. IB illustrates the structure of a flash memory cell formed in a U-shaped groove, according to an alternative embodiment of the present disclosure that may provide a higher capacitive coupling ratio between the control gate 106 and the floating gate 104 than the embodiment of FIG. IA.

[0028] The flash memory cell of FIG. IB is similar to the flash memory cell shown in FIG. IA, except that the floating gate 104', the control gate 106 and the dielectric 105' are shaped differently. For example, as in the embodiment of FIG. IA, the floating gate 104' of the flash memory cell of FIG. IB is formed deep in the U-shaped groove 120 in the region 132 and does not overlap with the source region 112, meaning that the region 132 is separated from the source region 112 by part of the substrate 102 below the source region 112, or that the channel 116 that can be induced in the substrate 102 by the floating gate 104 itself would generally not come in contact with the source region 112. However, the floating gate 104' in the region 130 is formed toward an upper part of the groove 120, thereby overlapping with the drain region 114. As shown in FIB. IB, the channel 128 induced by the floating gate 104' itself can come in contact with the drain region. The high-k dielectric layer 105' is also disposed along the contours of the boundary between the control gate polysilicon 106 and the floating gate 104'. At least a part of the high-k dielectric layer 105' is formed in the groove 120 below the surface of the substrate 102. A S/D extension 129 can be induced directly by a voltage on the control gate near the source region 112 along a surface of the groove facing the control gate 106. The S/D extension 129 and the channel 128 together can form a conductive path 117 between the source and drain regions 112 and 114. Such floating gate structure of FIG. IB increases the surface area between the control gate polysilicon 106 and the floating gate 104'. As a result, the capacitive coupling between the control gate 106 and the floating gate 104' is increased. The shape of the cross-section of the floating gate region 130 or the shape of the floating gate region 130 itself may vary depending upon how much capacitive coupling between the control gate 106 and the floating gate 104' is to be obtained. For example, the shape of the cross-section of the floating gate region 130 may be square, rectangular, circle, elliptical, cylinder, crown, etc. A variety of shapes may be employed for the region 130 of the floating gate 104' with the idea of increasing the surface area between the control gate 106 and the floating gate 104' while keeping at least a portion 132 of the floating gate 104' formed deep in the trench 120 such that the region 132 does not overlap with the source region 112. Also, the regions 132, 130 may be switched, in that the region 132 may be modified to overlap with the source region 112 while the region 130 is modified to reside deep in the trench 120 such that the region 130 does not overlap with the drain 114, meaning that the region 130 is separated from the drain region 114 by part of the substrate 102, or that the channel 128 that can be induced in the substrate 102 by the floating gate 104 itself can come in contact with the source region 112 but would generally not come in contact with the drain region 114.

[0029] FIG. 2 illustrates the structure of a SONOS (Silicon/Oxide/Nitride/Oxide/Silicon) type flash memory cell with a charge storage layer formed in a U-shaped groove, according to one embodiment of the present disclosure. The SONOS memory cell is fabricated in a p- well (or Silicon) substrate 102 and includes a charge storage structure comprised of a silicon dioxide layer 204, a silicon nitride layer 206, and a silicon dioxide layer 208'. The SONOS memory cell additionally includes a control gate structure comprised of the control gate polysilicon 210, the tungsten suicide (WSi₂) 212, and the silicon nitride (Si₃N₄) layer 214. An n+ type source region 216 and an n+ type drain region 218 are also formed for the SONOS memory cell. Although FIG. 2 illustrates one SONOS type memory cell, it should be noted that a SONOS memory device would have a plurality of such SONOS memory cells of FIG. 2 arranged in rows and columns, accessible via word line and bit line circuitry.

[0030] As shown in FIG. 2, the SONOS structure is comprised of the p-type silicon substrate 102, the silicon dioxide layer 204, the silicon nitride layer 206, the silicon dioxide layer 208', and the control gate polysilicon 210. The silicon nitride layer 206 serves as a charge storage (trap) layer, and the silicon dioxide layers 204, 208' insulate the silicon nitride layer 206 from the substrate 102 and the control gate polysilicon 210, respectively. The charge trapping silicon nitride layer 206 is contained entirely within a U-shaped groove (or trench) 120 etched into the silicon substrate (typically p-well) 102, and is entrenched deep into the groove 120 such that it does not overlap with the source region 216 and the drain region 218 of the SONOS memory, meaning that the charge trapping silicon nitride layer 206 is separated from the source region 216 and the drain region 218 by part of the substrate 102 below the source region 216 and part of the substrate 102 below the drain region 218, respectively, or that a channel 220 that can be induced in the substrate 102 by the control gate 210 across the charge trapping silicon nitride layer 206 would generally not come in contact with the source region 216 and the drain region 218. In other words, the source region 216 and the drain region 218 do not extend beyond the silicon dioxide dielectric layer 208' to overlap with the silicon nitride layer 206. This improves the write efficiency as will be explained in more detail below.

[0031] The control gate polysilicon 210 is formed above the charge storage structure, above the silicon dioxide layers 204, 208' and the silicon nitride layer 206. The control gate polysilicon 210 is formed deep into the groove 120 such that it is extends beyond the depths of the source region 216 and the drain region 218. Other types of conductive material (e.g., metal) may be used for the control gate 210. The tungsten suicide tungsten suicide layer 212 is formed on the control gate polysilicon layer 210 to reduce the resistance of the word line (not shown) of the SONOS memory. Other types of metallic material may be used instead of tungsten suicide for the control gate metallic layer 212. For example, other suicide layers such as molybdenum suicide, titanium suicide, cobalt suicide, or nickel suicide could be used. Additionally, metal layers with appropriate barrier, such as tungsten/tungsten nitride layers, could be used. When a high voltage is applied to the control gate structure 212, 210, induced source/drain (S/D) extensions 228, 222 are formed on both sides of the groove 120, and together with the channel 220, they form a conductive path 225 between the source 216 and the drain 218. The silicon nitride layer 214 is formed on the tungsten suicide 212 to protect the tungsten suicide 212. The silicon dioxide layer 204 also insulates the control gate polysilicon 210 from the substrate 102.

[0032] The SONOS memory shown in FIG. 2 is capable of storing 2 bits of binary data in one memory cell. In the example of FIG. 2, charges stored on the drain side 226 is referred to as corresponding to bit 1 of the SONOS memory cell, and charges stored on the source side 224 is referred to as corresponding to bit 2 of the SONOS memory cell. In order to write to the flash memory cell (bit 1, drain side), a high voltage (e.g., 10 V) is applied to the control gate 210, the source 216 is grounded (0 V), a medium voltage (e.g., 5 V) lower than the voltage applied to the control gate 210 is applied to the drain 218, and the p-well or substrate 102 is grounded (0 V). This causes current to flow from the drain 218 to the source 216 along the conductive path 225 and some high energy electrons to jump through the insulating silicon dioxide layer 204 onto a region 226 on the drain side of the charge trapping silicon nitride layer, resulting in hot electrons trapped therein. If hot electrons are not trapped in the region 226 of the silicon nitride layer 206, then bit 1 of the SONOS memory stores "1." On the other hand, if hot electrons are trapped in the region 226 of the silicon nitride layer 206, then bit lof the SONOS memory stores "0."

[0033] In order to write to the flash memory cell (bit 2, source side), a high voltage (e.g., 10 V) is applied to the control gate 212, the drain 218 is grounded (0 V), a medium voltage (e.g., 5 V) lower than the voltage applied to the control gate 212 is applied to the source 216, and the p-well or substrate 102 is grounded. This causes current to flow from the source to the drain along the conductive path 225 and some high energy electrons to jump through the insulating silicon dioxide layer 204 onto a region 224 on the source side of the charge trapping silicon nitride layer 206, resulting in hot electrons 224 trapped therein. If hot electrons 224 are not trapped in the region 224 of the silicon nitride layer 206, then bit 2 of the SONOS memory stores "1." On the other hand, if hot electrons 224 are trapped in the region 224 of the silicon nitride layer 206, then bit 2 of the SONOS memory stores "0."

[0034] In order to erase data from the SONOS memory cell (bit 1, drain side), a high negative voltage (e.g., -6 V) is applied to the control gate 212, 210, the source 216 is floated, a medium voltage (e.g., 5 V) is applied to the drain 218, and the p-well or substrate 102 is set to a more negative voltage (e.g. -8 V). This causes holes to tunnel into the drain side of the silicon nitride layer 206 to erase the trapped electrons in the region 226.

[0035] In order to erase the data from the SONOS memory cell (bit 2, source side), a high negative voltage (e.g., -6 V) is applied to the control gate 212, 210, the drain 218 is floated, a medium voltage (e.g., 5 V) is applied to the source 216, and the p-well or substrate 102 is set to a more negative voltage (e.g. -8 V). This causes holes to tunnel into source side of the silicon nitride layer 206 to erase the trapped electrons in the region 224.

[0036] In order to read data from bit 2 (source side) of the SONOS memory cell, the source 216 is grounded (0 V), a medium voltage Vmid (e.g., 2.5 V) is applied to the control gate 212, a lower voltage (e.g., typically 1.5 V) is applied to the drain 218, and the p-well or substrate 102 is grounded. As a result, current will flow and the amount of current indicates whether electrons are trapped in the region 224 of the silicon nitride layer 206 or whether the data read from bit 2 of the SONOS memory cell is binary data "1" or "0."

[0037] In order to read data from bit 1 (drain side) of the SONOS memory cell, the drain 218 is grounded (0 V), a medium voltage Vmid (e.g., 2.5 V) is applied to the control gate 212, a lower voltage (e.g., typically 1.5 V) is applied to the source 216, and the p-well or substrate 102 is grounded. As a result, current will flow and the amount of current indicates whether electrons are trapped in the region 226 of the silicon nitride layer 206 or whether the data read from bit 1 of the SONOS memory cell is binary data "1" or "0."

[0038] The SONOS memory according to the present disclosure has advantages over conventional SONOS memory cell structures. First, the short channel behavior of the SONOS memory cell is improved, because the conductive path 225 between the source 216 and the drain 218 is extended along the contour of the groove. Second, the effective spacing between the electron trapping regions 224 and 226 is increased in the charge storage layer 206, thereby avoiding potential interference of these two charge trapping regions 224, 226. Third, CHE programming using the induced S/D regions 228, 222 significantly improves the write speed and write bandwidth compared to that of conventional SONOS memory cells, since the induced S/D regions 228, 222 are much more efficient for generating hot electrons.

[0039] FIGS. 3A, 3B, 3C-1, 3C-2, 3D-1, 3D-2, 3E-1, 3E-2, 3F-1, 3F-2, 3G-1, and 3G-2 illustrate the process of fabricating a flash memory cell with a floating gate formed in U- shaped groove, according to embodiments of the present disclosure shown in FIGS. IA and IB. Although specific fabrication techniques are described, numerous other techniques may be used to form or etch trenches, establish wells and doped regions, grow or deposit layers and so forth. The fabrication process for two flash memory cells is illustrated in FIGS. 3 A, 3B, 3C-1, 3C-2, 3D-1, 3D-2, 3E-1, 3E-2, 3F-1, 3F-2, 3G-1, and 3G-2 for simplicity, although there would be a number of such flash memory cells fabricated on a flash memory device. FIGS. 3A, 3B, 3C-1, 3D-1, 3E-1, 3F-1, and 3G-1 correspond to the process of fabricating the flash memory cell according to the embodiment shown in FIG. IA, and FIGS. 3A, 3B, 3C-2, 3D-2, 3E-2, 3F-2, and 3G-2 correspond to the process of fabricating the flash memory cell according to the embodiment shown in FIG. IB.

[0040] Referring to FIG. 3A, a silicon dioxide layer (SiO₂) 302 is formed on a p-type substrate 102. The silicon dioxide layer (SiO₂) 302 may be grown by, for example, thermal oxidation or other types of oxidation techniques. Then, a silicon nitride (Si₃N₄) layer 306 is formed on the silicon dioxide layer (SiO₂) 302, using chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). Referring to FIG. 3B, trenches forming the U-shaped grooves 120 are etched into the substrate 102, using the silicon oxide layer 302 and the silicon nitride layer 306 as a mask. Then, a silicon dioxide layer 116 is grown on the surface of the U-shaped grooves 120, using for example thermal oxidation. The silicon dioxide layer 116 is used as the tunneling oxide layer for the floating gate of the flash memory cell.

[0041] Referring to FIG. 3C- 1, the floating gate polysilicon (polycrystalline silicon) 104 is deposited on the bottom of the U-shaped grooves 120 using, for example and without limitation, CVD, PECVD, or LPCVD (Low-pressure CVD). The floating gate polysilicon 104 may be deposited up to the top of the substrate 102, but is planarized and etched back into the U-shaped groove 120, so that the floating gate polysilicon 104 does not overlap with the source and drain regions of the flash memory cell to be formed later. The structure shown in FIG. 3C- 1 corresponds to the floating gate polysilicon structure 104 shown in FIG. IA. In addition, the silicon dioxide layer 308 is grown on the floating gate polysilicon 104 using thermal oxidation. The old silicon nitride layer 306 is etched away and a new silicon nitride layer 310 is deposited using CVD or PECVD to cover the silicon dioxide layers 302, 308, 116.

[0042] However, referring to FIG. 3C-2, the floating gate polysilicon 104' may have a shape different from the shape of the floating gate polysilicon 104 shown in FIG. 3C-1. The floating gate structure 104' shown in FIG. 3C-2 corresponds to the floating gate polysilicon structure 104' shown in FIG. IB. Referring to FIG. 3C-2, the floating gate polysilicon 104' is deposited on the bottom of the U-shaped grooves 120 using CVD, PECVD, or LPCVD (Low-pressure CVD) to the top of the substrate 102, but is planarized and etched back into the U-shaped groove 120. However, the etch back to recess the floating gate polysilicon 104' is done with a mask, so that the region 130 of the floating gate polysilicon 104' is not etched back but the region 132 of the floating gate polysilicon 104' is etched back into the U-shaped groove 120 so that it does not overlap with the source and drain regions of the flash memory cell to be formed later. As explained above, a variety of shapes of the cross section of the region 130 may be formed using a variety of shapes of masks. In addition, the silicon dioxide layer 308' is grown on the floating gate polysilicon 104 using thermal oxidation. The old silicon nitride layer 306 is etched away and a new silicon nitride layer 310 is deposited using CVD or PECVD to cover the silicon dioxide layers 302, 308', 116.

[0043] Referring to FIGS. 3D-1 and 3D-2, isolation trenches may be etched into the substrate 102, and silicon dioxide 312 is deposited in the isolation trenches using CVD, PECVD, LPCVD, or spin on glass (SOG) to provide isolation between adjacent flash memory cells. Then, referring to FIGS. 3E-1 and 3E-2, the silicon nitride layer 310, the silicon dioxide layer 308, and part of the thin silicon dioxide layer 116 above the floating gate polysilicon 104, 104' are removed, and the isolation trench 312 is also etched back to be planar with the surface of the substrate 102. A dielectric layer 105, which can be a high-k dielectric layer, is deposited on the floating gate polysilicon 104, 104' using directional deposition techniques such as PECVD. Examples of high-k dielectric material 105 may include Aluminum Oxide (AI2O3), hafnium-based high-k dielectrics such as HfSiON, HfO₂, and HfSiO, or oxynitride dielectrics where silicon oxide dielectric is infused with a small amount of nitrogen. The high-k dielectric materials can also be deposited with conformal techniques such as CVD or metal organic CVD (MOCVD) or atomic layer deposition (ALD). In addition, the silicon dioxide layer 118 on the side walls of the groove 120 above the dielectric layer 105 is formed using thermal oxidation.

[0044] Referring to FIGS. 3F- 1 and 3F-2, the control gate polysilicon layer 106 is deposited on the high-K dielectric layer 105, and the tungsten suicide (WSi₂) layer 108 is deposited on the control gate polysilicon layer 106, both by CVD or its variants. The control gate polysilicon layer 106 and the tungsten suicide tungsten suicide layer 108 together form the control gate of the flash memory cell. Then, the silicon nitride layer 110 is deposited on the tungsten suicide tungsten suicide layer 108 as a passivation layer. Referring to FIGS. 3G-1 and 3G-2, the source 112 and the drain 114 regions are formed by n+ doping the regions 112, 114 of the substrate 102 by, for example, ion implantation. The depth of the ion implantation is controlled such that the source region 112 and the drain region 114 do not overlap with at least part of the floating gate polysilicon 104, 104' by extending too deep in the substrate 102. As a result, two flash memory cells 350, 352 are formed as shown in FIG. 3G-1 according to the embodiment shown in FIG. IA, and two flash memory cells 350, 352' are formed as shown in FIG. 3G-2 according to the embodiment shown in FIG. IB. Thereafter, conventional metallization processes to form the word lines and bit lines of the flash memory device and other conventional processes (e.g., formation of spacers on the control gates, etc.) to complete the fabrication of the flash memory device are performed.

[0045] FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G, and 4H illustrate the process of fabricating a SONOS type memory cell with a charge storage layer stored in a U-shaped groove, according to one embodiment of the present disclosure as shown in FIG. 2. Although specific fabrication techniques are described, various other techniques may be used to form or etch trenches, establish wells and doped regions, grow or deposit layers and so forth. The fabrication process for two SONOS cells is illustrated in FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G, and 4H for simplicity, although there would be a number of such SONOS memory cells fabricated on a SONOS memory device.

[0046] Referring to FIG. 4A, a silicon dioxide layer (SiO₂) 302 is formed on a p-type substrate 102. The silicon dioxide layer (SiO₂) 302 may be grown by, for example, thermal oxidation or other types of oxidation techniques. Then, a silicon nitride (S1₃N₄) layer 306 is formed on the silicon dioxide layer (SiO₂) 302, using chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). [0047] Referring to FIG. 4B, trenches forming the U-shaped grooves 120' are etched into the substrate 102, using the silicon oxide layer 302 and the silicon nitride layer 306 as a mask. Then, a silicon dioxide layer 204 is grown on the surface of the U-shaped grooves 120 and on the silicon nitride layer 306, using for example thermal oxidation. The silicon dioxide layer 204 is used as the tunneling oxide layer for the charge storage layer of the SONOS memory cell. The silicon nitride layer 206 is formed on the silicon dioxide layer 204 using CVD or PECVD. The silicon nitride layer 206 stores the charges trapped in the SONOS memory cell. The silicon dioxide layer 208 is formed on the silicon nitride layer 206 using CVD or LPCVD followed by a thermal anneal to densify the deposited SiO₂.

[0048] Referring to FIG. 4C, the NO layers (206, 208) are recessed below the surface of the substrate 102 deep in the U-grooves 120'. Recessing the NO layers (206, 208) is carried out by filling the openings 420 (FIG. 4B) of the U-shaped grooves 120' with organic material such as a photoresist (not shown), and recessing such photoresist in the grooves 120' by isotropic etch back, and etching the NO layers (206, 208) (not covered by the photoresist), and removing the photoresist from the U-shaped grooves 120'. Then, the oxide layers 204, 208 are further etched, followed by re-growing or depositing the silicon dioxide layers 205, 208'.

[0049] Referring to FIG. 4D, the control gate polysilicon 210 is deposited on the ONO layers 204, 206, 208' using CVD or its variants. Referring to FIG. 4E, isolation trenches 312 are etched into the substrate 102, and silicon dioxide 312 is deposited in the isolation trenches 312 using CVD, PECVD, LPCVD, or spin on glass (SOG) to provide isolation between adjacent SONOS memory cells. Then, referring to FIG. 4F, the silicon nitride layer 306 and the silicon dioxide layer 302, and the isolation trench 312 are also etched back to be planar with the surface of the substrate 102. Thereafter, the source 216 and the drain 218 regions are formed by n+ doping the regions 216, 218 of the substrate 102 by, for example, ion implantation. The depth of the ion implantation is controlled such that the source region 216 and the drain region 218 do not overlap with the ONO layers 204, 206, 208' by extending too deep in the substrate 102 beyond the oxide layer 208'.

[0050] Referring to FIG. 4G, conformal silicon dioxide 402 is deposited by CVD or SOG to fill gaps between the control gate polysilicon 210 and etched back to expose the top of the control gate polysilicon 210. In addition, gate oxide layers 424, 422 for support transistors (not shown) for the SONOS memory cells are grown as well. Then, referring to FIG. 4H, the tungsten suicide (WSi₂) layer 212 is deposited on the control gate polysilicon layer 210 by CVD or its variants. The control gate polysilicon layer 210 and the tungsten suicide tungsten suicide layer 212 together form the control gate of the SONOS memory cell. Then, the silicon nitride layer 214 is deposited on the tungsten suicide tungsten suicide layer 212 as a passivation layer. As a result, two SONOS memory cells 450, 452 are formed as shown in FIG. 4H according to the embodiment shown in FIG. 2. Thereafter, conventional metallization processes to form the word lines and bit lines of the SONOS memory device and other conventional processes (e.g., formation of spacers on the control gates, etc.) to complete the fabrication of the SONOS memory device are performed.

[0051] It should be noted that the various circuits disclosed herein may be described using computer aided design tools and expressed (or represented), as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and HLDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media).

[0052] When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

[0053] Upon reading this disclosure, those of ordinary skill in the art will appreciate still additional alternative structural and functional designs for non- volatile memory cells having a charge storage layer formed in a U-shaped groove without overlapping with the source/drain regions of the non- volatile memory cells and methods for operating or fabricating such nonvolatile memory cells, through the disclosed principles of the present disclosure. For example, although a U-shaped groove is used in the examples of FIGS. IA, IB, and 2 in which the charge storage layer is formed, different shape grooves (e.g., V-shape) may be used instead. For another example, there could be variations to the methods for fabricating the non-volatile memory cells as described herein. The non-volatile memory cell may include a flash memory cell, a SONOS type flash memory cell, a TANOS type flash memory cell, or any other type of non- volatile memory cell. Thus, while particular embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the disclosure is not limited to the precise construction and components disclosed herein. Various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present disclosure disclosed herein without departing from the spirit and scope of the disclosure as defined in the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A non- volatile memory cell comprising: a charge storage layer formed in a groove of a semiconductor substrate; a dielectric layer formed over the charge storage layer, at least part of the dielectric layer being formed in the groove below a surface of the substrate; a control gate formed on the dielectric layer, at least part of the control gate being formed in the groove below the surface of the substrate; and a source region and a drain region formed in the substrate on opposite sides of the groove and separated from each other by the groove, wherein at least one of the source region and the drain region does not overlap with the charge storage layer.

2. The non- volatile memory cell of claim 1 , wherein the source region and the drain region do not overlap with the charge storage layer.

3. The non- volatile memory cell of claim 1, wherein one of the source region and the drain region overlaps with the charge storage layer.

4. The non- volatile memory cell of claim 1 , wherein a voltage can be applied to the control gate to cause a conductive path to be formed along a contour of the groove between the source and drain regions, at least part of the conductive path being a source or drain extension induced directly by the control gate.

5. The non- volatile memory cell of claim 1, wherein the groove has a substantially U-shape.

6. The non- volatile memory cell of claim 1 , wherein part of the control gate is above the surface of the substrate.

7. The non- volatile memory cell of claim 1, wherein the entire dielectric layer is formed in the groove below the surface of the substrate.

8. The non- volatile memory cell of claim 1, wherein the dielectric layer has at least one of a non-planer interface with the control gate and a non-planer interface with the charge storage layer.

9. The non- volatile memory cell of claim 1 , wherein the non- volatile memory cell is one of a flash memory cell with the charge storage layer including a floating gate polysilicon layer and a SONOS type memory cell with the charge storage layer including a silicon nitride layer.

10. The non- volatile memory cell of claim 9, wherein the SONOS type memory cell is capable of storing 2 bits of binary data, with charges stored on a first part of the silicon nitride layer near the drain region corresponding to bit 1 of the SONOS type memory cell, and charges stored on a second part of the silicon nitride layer near the drain region corresponding to bit 2 of the SONOS memory cell.

11. A non-volatile memory cell comprising: a floating gate formed in a groove of a semiconductor substrate; a control gate formed over the floating gate and separated from the floating gate by at least one dielectric layer, at least part of the control gate being formed in the groove below the surface of the substrate; and a source region and a drain region formed in the substrate on opposite sides of the groove and separated from each other by the groove; wherein a conductive path can be formed along a contour of the groove between the source and drain regions in response to a voltage applied to the control gate, at least part of the conductive path being a source extension or a drain extension induced directly by the voltage on the control gate.

12. The non- volatile memory cell of claim 11 , wherein another part of the conductive path is a channel region induced by a voltage capacitively coupled to the floating gate, and the channel region does not come in contact with at least one of the source region and the drain region.

13. A method of programming a non- volatile memory cell, comprising: applying a first voltage to a control gate disposed at least partially within a groove in a silicon substrate; applying a second voltage to a source region in the substrate on a first side of the groove; and applying a third voltage to a drain region in the substrate on a second side of the groove; whereby a conductive path is formed along a contour of the groove between the source region and the drain region and whereby electrons are transferred between the conductive path and a floating gate disposed near a bottom of the groove.

14. A method of reading a non- volatile memory cell, comprising: applying a first voltage to a control gate disposed at least partially within a groove in a silicon substrate; applying a second voltage to a source region in the substrate on a first side of the groove; and applying a third voltage to a drain region in the substrate on a second side of the groove; whereby current flows between the source region and the drain region along a contour of the groove, the level of the current being dependent on the amount of electrons stored in a floating gate disposed near a bottom of the groove.

15. A method of programming a SONOS type nonvolatile memory cell, comprising: applying a first voltage to a control gate disposed at least partially within a groove in a silicon substrate; and applying a second voltage to a source region in the substrate on a first side of the groove; whereby a source extension is formed on the first side of the groove adjacent the source region and electrons are transferred between the source extension region and a first part of a charge storage layer near the first side of the groove, the charge storage layer being disposed entirely within the groove and near a bottom of the groove.

16. The method of claim 15 , further comprising : applying a third voltage to the control gate; and applying a fourth voltage to a drain region formed in the substrate on a second side of the groove, the source region and the drain region being separated from each other by the groove; whereby a drain extension is formed on the second side of the groove adjacent the drain region and electrons are transferred between the drain extension and a second part of the charge storage layer near the second side of the groove.

17. A method of fabricating a flash memory cell, the method comprising: forming a groove below a surface of a semiconductor substrate; forming a first dielectric layer on a surface of the groove; forming a charge storage layer within the groove; forming a second dielectric layer over the charge storage layer, at least part of the second dielectric layer being formed in the groove below the surface of the substrate; forming a control gate on the second dielectric layer, at least part of the control gate being formed in the groove below the surface of the substrate; forming a source region and a drain region on opposite sides of the groove such that the source region and the drain region are separated by the groove, at least one of the source region and the drain region being also separated from the charge storage layer by part of the substrate below the at least one of the source region and the drain region.

18. The method of claim 17, wherein the source region and the drain region do not overlap with the charge storage layer.

19. The method of claim 17, wherein the source region does not overlap with the floating gate but the drain region overlaps with the charge storage layer.

20. The method of claim 17, wherein the charge storage layer is one selected from the group consisting of a polysilicon floating gate and a silicon nitride layer.